Integrated circuit and integrated circuit system

Abstract

The invention provides an integrated circuit and an integrated circuit system, and belongs to the technical field of integrated circuits, and the integrated circuit comprises a data unit which is used for storing data; the functional units are connected with the data unit, acquire data from the data unit and process the data acquired from the data unit; the data unit and the function unit respectively work under different clock frequencies. According to the invention, the data unit is used as an independent part, can provide large enough storage capacity, and is connected with a plurality of groups of functional units, so that the data unit and the functional units are located at different clock frequencies, and high and low frequency joint work between the data unit and the functional units is realized; meanwhile, the access speed of the data unit is matched with the calculation speed of the functional unit, so that the application requirements of an artificial intelligence system and a high-performance calculation system are met.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and relates to an integrated circuit centered on a data unit formed based on a core particle architecture, specifically an integrated circuit and an integrated circuit system. Background Art

[0002] Over the past few decades, the semiconductor industry has been developing in accordance with Moore's Law, that is, when the price remains unchanged, the number of transistors that can be accommodated on an integrated circuit will double approximately every 18 months, and the performance will also double. However, when the semiconductor processing technology evolves to the 5nm / 3nm / 1nm node, it becomes increasingly difficult to increase the density of transistors. At the same time, due to the high integration of integrated circuits, the power consumption density is increasing, and power supply and heat dissipation are also facing huge challenges. It is becoming increasingly difficult to obtain high-performance chips through transistor miniaturization technology. In order to improve the performance of the chip, increasing the chip area to integrate more transistors and thus manufacture large chips has become an effective technical implementation solution.

[0003] Among the big chip design solutions, the current mainstream is the system-on-chip, which integrates different types of data units, storage units, and communication units into the same big chip, takes highly integrated measures, and improves chip performance through advanced processes. At the same time, in pursuit of higher performance, the size of transistors used in big chips has reached its limit, and the increase in clock frequency has caused a large increase in power consumption and a large increase in the difficulty of clock management, resulting in the access speed of storage units on big chips lagging behind the computing speed of data units. Therefore, a single big chip can no longer meet the application requirements of artificial intelligence systems and high-performance computing systems. Summary of the invention

[0004] In view of the technical problem described in the above-mentioned prior art that the access speed of the storage unit on the large chip in the prior art lags behind the computing speed of the data unit, resulting in the inability to meet the application requirements of artificial intelligence systems and high-performance computing systems, the present invention proposes an integrated circuit and an integrated circuit system to solve this technical problem.

[0005] The present invention is an integrated circuit centered on a data unit based on a core-grain architecture. The data unit is dedicated to storing data, so that the data unit can match at least one group of functional units. The data unit is used as an independent part to provide a sufficiently large storage capacity. Multiple groups of functional units are connected, and the data unit and the functional unit are at different clock frequencies. The bandwidth of the data unit is fully utilized by the multiple groups of functional units to achieve high and low frequency joint operation between the data unit and the functional unit, and at the same time, the access speed of the data unit is matched with the computing speed of the functional unit to meet the application requirements of artificial intelligence systems and high-performance computing systems.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0007] The present invention provides an integrated circuit, comprising:

[0008] Data unit: used to store data;

[0009] and at least one group of functional units: connected to the data unit, obtaining data from the data unit, and processing the data obtained from the data unit;

[0010] The data unit and the functional unit operate at different clock frequencies respectively.

[0011] It is further defined that the data unit is further used to perform one or a combination of the following operations:

[0012] Provide data transfer, in-memory computing or data interaction between at least one group of the functional units.

[0013] It is further defined that the data unit includes:

[0014] At least one group of storage units: used to provide storage media of different capacities and types;

[0015] Each group of storage units is connected to one or more groups of functional units;

[0016] and / or, multiple groups of storage units correspond to one or more groups of functional units;

[0017] The functional units are connected to corresponding storage units according to the access frequency.

[0018] It is further defined that the data unit further includes: a data processing unit,

[0019] The data processing unit is used to process the data stored in the storage unit and send the processing results to the functional unit.

[0020] It is further defined that the integrated circuit further comprises: a communication interaction unit and a first controller;

[0021] The first controller is connected to the communication interaction unit and transmits data between the communication interaction unit and the data unit; it is also connected to the functional unit and is used to control the operation of the functional unit;

[0022] The functional unit includes FPGA and / or MCU;

[0023] The FPGA is connected to the storage unit and is used to receive customized information from the user;

[0024] The MCU is connected to the storage unit and is used for debugging and monitoring the integrated circuit.

[0025] It is further defined that the integrated circuit further comprises: an interface unit corresponding to at least one group of the functional units,

[0026] The functional unit is connected to the data unit through a corresponding interface unit and stores and accesses data on the data unit.

[0027] It is further defined that the storage units are connected in series via a bus for converting data between multiple groups of the storage units.

[0028] It is further defined that the sum of bandwidths of at least one group of the functional units is less than or equal to the bandwidth of the data unit.

[0029] The present invention provides an integrated circuit system, comprising: a plurality of the above-mentioned integrated circuits and a second controller respectively connected to the plurality of the integrated circuits.

[0030] It is further defined that the second controller is respectively connected to the communication interaction unit in each of the integrated circuits.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] 1. The present invention provides an integrated circuit, which is formed based on the core grain architecture principle with a data unit as the center. The data unit is dedicated to storing data, so that the data unit can match at least one group of functional units. The present invention uses the data unit as an independent part, which can provide a sufficiently large storage capacity; multiple groups of functional units are connected, and the data unit and the functional unit are at different clock frequencies, so that the bandwidth of the data unit is fully utilized by the multiple groups of functional units to realize the high and low frequency joint work between the data unit and the functional unit, and at the same time, the access speed of the data unit is matched with the computing speed of the functional unit to meet the application requirements of artificial intelligence systems and high-performance computing systems.

[0033] 2. The present invention includes at least one group of storage units for providing storage media of different capacities and types, which can be selected and matched according to different capacity densities, different storage speeds and different cost sizes to meet the needs of different application scenarios.

[0034] 3. The functional unit of the present invention may be a functional unit that provides computing power, a functional unit that provides an auxiliary role for an integrated circuit, an FPGA and / or an MCU. Diversified functional units can meet different needs. In practical applications, combining multiple functional units can better coordinate and serve a certain application scenario.

[0035] 4. The integrated circuit of the present invention also includes a communication interaction unit. The communication interaction unit serves as a bridge unit of the integrated circuit system and can provide higher computing power for the expansion of the integrated circuit system.

[0036] 5. The present invention realizes high- and low-frequency joint operation between the data unit and the functional unit. During processing, different process nodes can be independently selected to reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The structure of the integrated circuit of the present invention is schematically shown in FIG. Figure 1 ;

[0038] Figure 2 The structure of the integrated circuit of the present invention is shown in FIG. Figure 2 ;

[0039] Figure 3 FIG. 4 is a schematic diagram of an integrated circuit system of the present invention. DETAILED DESCRIPTION

[0040] In order to make the technical solution of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in combination with the embodiments and drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of protection claimed, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The chiplet architecture divides a large chip into multiple small chips with the same or different functions. The small chips can be manufactured using the same or different process nodes, and then packaged and integrated through cross-chip interconnection and packaging technology, thereby reducing costs while achieving higher integration.

[0042] The focus of the present invention is to form an integrated circuit centered on a data unit based on a core particle architecture, and to adopt a computing architecture centered on a data unit to achieve high and low frequency joint operation of multiple chips.

[0043] The present invention provides an integrated circuit, comprising: a data unit: used to store data; and at least one group of functional units: connected to the data unit, obtaining data from the data unit, and processing the data obtained from the data unit; the data unit and the functional unit respectively operate at different clock frequencies to achieve high- and low-frequency joint operation of the data unit and at least one group of functional units. Among them, at least one group of functional units is connected to the data unit. Specifically, the number of functional units can be two groups, three groups, four groups, five groups, or even more groups.

[0044] An integrated circuit of the present invention also includes: an interface unit corresponding to at least one group of functional units, the functional unit is connected to the data unit through the corresponding interface unit, and data is stored and accessed on the data unit. A sufficiently large bandwidth can be provided through multiple interface units to access more functional units, and the bandwidth of the data unit can also be fully utilized by external functional units.

[0045] See also Figure 1 As a preferred embodiment of the present invention, the number of functional units is 4 groups, the data unit is the core, located in the center, and can provide sufficient storage capacity as an independent core particle; four interface units are arranged outside the data unit, each functional unit is connected to the data unit through the corresponding interface unit, and the four functional units use a clock frequency different from that of the data unit. The functional unit is responsible for processing the data of the data unit, and the clock frequency of each functional unit is mutually related to the clock frequency of the data unit, ensuring that the data flow of the entire integrated circuit is broadband matched between the functional unit and the data unit; the core particle can freely select an independent process node to reduce costs. Preferably, the structural unit is an IO interface.

[0046] In the present invention, the sum of the bandwidths of at least one group of functional units is less than or equal to the bandwidth of the data unit, that is, the bandwidth of the functional unit matches the bandwidth of the data unit.

[0047] In the present invention, the storage units are connected in series via a bus for data conversion between multiple groups of storage units.

[0048] by Figure 1 Take the data unit as an example to explain the relationship of broadband matching: the data unit is represented by the letter O, and the functional units are represented by the letters A, B, C, and D respectively. The number of data that can be transmitted by the functional unit in one clock cycle is called the data bit width, which can be expressed as "bit_width". For example, the data bit width of functional unit A can be expressed as bit_width(A), the data bit width of functional unit B can be expressed as bit_width(B), the data bit width of functional unit C can be expressed as bit_width(C), and the data bit width of functional unit D can be expressed as bit_width(D). The number of clock cycles in 1 second can be expressed as the operating frequency on the data chip, which is expressed by "clock_frequency", abbreviated as "clock_freq". For example, the operating frequency of functional unit A can be expressed as clk_freq(A), the operating frequency of functional unit B can be expressed as clk_freq(B), the operating frequency of functional unit C can be expressed as clk_freq(C), and the operating frequency of functional unit D can be expressed as clk_freq(D). Therefore, the bandwidth matching between functional units and data units can be expressed by the following formula:

[0049] clk_freq(O)×bit_width(O)=clk_freq(A)×bit_width(A)+clk_freq(B)×bit_width(B)+clk_freq(C)×bit_width(C)+clk_freq(D)×bit_width(D)

[0050] The present invention divides a large chip into multiple identical or different small chips based on the core grain architecture, and integrates and packages the core chip (data unit) in the center of multiple identical or different small chips (functional units). The core chip (data unit) is responsible for executing instructions and processing data. The data unit is located in the middle of the circuit, and as an independent part, it can provide sufficient storage capacity. At the same time, it has multiple groups of interfaces with the outside, which can provide a large enough bandwidth and access multiple groups of functional units. The bandwidth of the data unit can be fully utilized by the outside. The functional unit is located around the data unit and can use a clock frequency different from that of the data unit. The functional unit is responsible for processing the data of the data unit. The clock frequency of each functional unit is interrelated with the clock frequency of the data unit, ensuring that the bandwidth of the data flow of the entire computing system matches between the functional unit and the data unit.

[0051] In the present invention, the data unit is also used to provide one or a combination of operations including data transfer, in-memory computing, or data interaction between at least one group of functional units.

[0052] In the present invention, the data unit further includes: a data processing unit, which is used to process the data stored in the storage unit and send the processing results to the functional unit.

[0053] In the present invention, the integrated circuit also includes: a communication interaction unit and a first controller; the first controller is connected to the communication interaction unit, and transmits data between the communication interaction unit and the data unit; it is also connected to the functional unit to control the operation of the functional unit; the functional unit includes FPGA and / or MCU; FPGA is connected to the storage unit to receive customized information from the user; MCU is connected to the storage unit to debug and monitor the integrated circuit. The functional unit can be FPGA, MCU, or FPGA and MCU, that is, on the same chip, it can only include FPGA or only include MCU.

[0054] In the present invention, the data unit includes: at least one group of storage units, at least one group of storage units is used to provide storage media of different capacities and types; each group of storage units is connected to one or more groups of functional units; and / or, multiple groups of storage units correspond to one or more groups of functional units; the functional units are connected to the corresponding storage units according to the access frequency. Specifically, the storage units can be one group, two groups, three groups, four groups, or even more groups, wherein each group of storage units may include multiple storage units, and each group of functional units may include multiple functional units. As a preferred embodiment of the present invention, see Figure 2 The functional unit includes three groups of functional units, one group of FPGA and one group of MCU, wherein the first group of functional units includes two functional units 1, and the second group of functional units includes two functional units 2. The storage unit includes three groups of storage units, wherein the first group of storage units includes three storage units 1, the second group of storage units includes two storage units 2, and the third group of storage units includes three storage units 3.

[0055] See also Figure 2 As an embodiment of the present invention, in an integrated circuit composed of multiple core particles, the data unit is located in the middle as a frequently accessed unit, and undertakes the functions of data storage, data transfer, data exchange between functional units, and partial in-memory calculation. The data unit contains multiple groups of storage units, which can provide storage media of different capacities and types, wherein the third group of storage units (including three storage units 3) refers to SRAM with small capacity but fast access speed, the first group of storage units (including three storage units 1) refers to DRAM with moderate capacity and access speed, and the second group of storage units (including two storage units 2) refers to PCM particles with large capacity but relatively slow read and write speed, which can meet the needs of different application scenarios. The data unit contains a data processing unit and a computing unit 1, which can undertake the in-memory calculation function. The data unit has a bus inside for connecting all storage units in series, and the bus can be used for data exchange between functional units. The data processing unit can complete the work of data exchange scheduling. The storage unit, for example, the storage unit 2 can have a computing unit 1 alone, and a single storage unit can also undertake all the functions of the data unit and be used independently. The data unit is interconnected externally using a unified interface unit to facilitate docking with the functional unit and achieve standardization of the core grain architecture.

[0056] Functional units and data units complete data exchange, using data units as carriers of intermediate data for calculation; data units can also store original data for calculation; or use data units as carriers to transmit data to achieve the purpose of collaborative work between functional units. Figure 2The integrated circuit includes three functional units, a communication interaction unit, an FPGA (field-programmable gate array) and an MCU (micro controller unit), etc. The number of each functional unit may include one or more. In the actual application process, the functional unit 1 can be independently applied to a certain work scenario, or multiple functional units can be used in combination. The number of functional units can be increased or decreased according to actual needs.

[0057] in, Figure 2 The working steps of the integrated circuit in are:

[0058] The first controller establishes a connection with the data processing unit through the communication interaction unit, and stores the original data in the storage unit 1, storage unit 2 and storage unit 3 through this link. The original data will be stored in different storage units according to the access frequency. Data with high access frequency is stored in the storage unit with fast reading speed, and data with low access frequency and infrequent use is stored in the storage unit with slow reading speed. The data transfer is completed through the data bus in the data unit.

[0059] Functional unit 1, functional unit 2, functional unit 3, FPGA and MCU work together. The first controller has a set of data lines connecting each functional unit for downloading the initial program for debugging and programming of the integrated circuit. Different programs are loaded into each functional unit according to different functions for initialization of the functional unit.

[0060] Functional unit 1 initiates calculation, reads data in storage unit 3, and calculates the result including part of the data and the calculation address of the calculation unit in the data processing unit. The calculation unit reads the data in storage unit 1, storage unit 2 and storage unit 3 through bus scheduling according to the initial address, and takes advantage of the high frequency and large data bit width of the data unit. It does not need to exchange data between the functional unit and the data unit, and can complete a large number of calculations. The calculation unit 1 assumes the function of in-memory calculation. In the next step of the work of functional unit 1, the data processing unit undertakes part of the work to transmit the calculation results of functional unit 1 and part of the intermediate data to different blocks of storage unit 1 and storage unit 2. As the data source of functional unit 2 and functional unit 3, the data processing unit, as the scheduler of the data unit, completes the data exchange between functional units. Functional unit 2 assumes the main calculation function and is also the main user of bandwidth.

[0061] Functional unit 3, FPGA and MCU all play auxiliary roles in the entire integrated circuit. Functional unit 3, as a security encryption module in the integrated circuit, provides data protection to ensure that stored data and transmitted data are not accessed by unauthorized persons, and provides user privacy protection and the ability to defend against adversarial attacks. As a programmable module, FPGA allows users to add customized information and enrich the functions of the entire system circuit based on its flexibility. As a low-cost and low-power module, MCU assumes the functions of debugging and monitoring in the entire system circuit.

[0062] The above steps serially describe the functional implementation of each unit. In actual application, each unit is processed in a pipeline and works in parallel. The working efficiency of each unit is maximized, and bandwidth utilization is maximized at the same time.

[0063] The combination of high and low frequencies is reflected in the fact that data units and functional units do not need to work at the same frequency. For example, data units often have lower process nodes and can provide sufficiently large capacity, but cannot work at very high clock frequencies. The provision of high bandwidth is achieved through multiple interface units; Functional unit 2, as the main provider of computing power, often works at the highest clock frequency, and the remaining functional units can choose their own clock frequencies according to actual needs. The clock frequency that can be achieved by the clock is strongly related to the process node, and the purpose of reducing costs can be achieved by selecting different process nodes. Reasonable functional division is carried out according to the performance, power consumption, cost and other requirements of the application, and finally the process nodes of each core particle are optimized. As the core of the entire structure and integrated circuit, the data unit provides the largest capacity and bandwidth. The functional unit is connected to the data unit through different combinations through the interface unit to maximize the use of the bandwidth of the data unit and achieve the purpose of bandwidth matching.

[0064] The communication interaction unit serves as the interface between the integrated circuit and the outside world. It has functions such as network interaction and data transmission. It is the data source channel of the entire data unit and also the result output channel.

[0065] The present invention also provides an integrated circuit system, comprising: a plurality of the above-mentioned integrated circuits and a second controller respectively connected to the plurality of integrated circuits. The second controller is respectively connected to the communication interaction unit in each integrated circuit. Specifically, the number of the second controllers can be two, three, four, or even more.

[0066] See also Figure 3As a preferred embodiment of the present invention, the integrated circuit system includes a second controller and four integrated circuits, each of which can be matched with a communication interaction unit, which can be used to directly interact with the outside through the communication interaction unit. A single integrated circuit is a complete working system. The four integrated circuits can also be connected to the second controller through an interface unit, and the second controller is used as the main control unit to schedule the four integrated circuits to work, providing greater computing power support as an integrated circuit system. The performance of the chip mainly depends on the scale of transistors integrated in the chip. Multiple circuits with specific functions are integrated together to form a high-performance chip. Therefore, the integrated circuit or integrated circuit system of the present invention can better meet the application requirements of artificial intelligence systems and high-performance computing systems.

[0067] It should be noted that the data unit of the present invention may also be composed of one or more data chips; the core storage medium of the data unit may include one or more volatile or non-volatile media sets, including but not limited to (SRAM / MRAM / DRAM / RRAM / PCM / flash, etc.); (SRAM, static random access memory, static random access memory; MRAM, magnetic random access memory, magnetic random access memory; DRAM, dynamic random access memory, dynamic random access memory; RRAM, resistive random access memory, resistive random access memory; PCM, phase change memory, phase change memory; flash, flash memory), etc.

[0068] The types of functional units in the present invention are diverse, and may include data processing and application units such as ASIC, FPGA, and general-purpose chips; the functional units can be applied independently or in combination to a certain work scenario; similarly, the integrated circuit formed by such core particles can serve multiple applications and work simultaneously.

[0069] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An integrated circuit, characterized in that: include: Data unit: used to store data; and at least one group of functional units: connected to the data unit, obtaining data from the data unit, and processing the data obtained from the data unit; The data unit and the functional unit operate at different clock frequencies respectively.

2. The integrated circuit according to claim 1, characterized in that The data unit is further used to perform one or a combination of the following operations: Provide data transfer, in-memory computing or data interaction between at least one group of the functional units.

3. The integrated circuit according to claim 2, characterized in that The data unit includes: At least one group of storage units: used to provide storage media of different capacities and types; Each group of storage units is connected to one or more groups of functional units; and / or, multiple groups of storage units correspond to one or more groups of functional units; The functional units are connected to corresponding storage units according to the access frequency.

4. The integrated circuit according to claim 3, characterized in that The data unit also includes: a data processing unit, The data processing unit is used to process the data stored in the storage unit and send the processing results to the functional unit.

5. The integrated circuit according to claim 4, characterized in that The integrated circuit further comprises: a communication interaction unit and a first controller; The first controller is connected to the communication interaction unit and transmits data between the communication interaction unit and the data unit; it is also connected to the functional unit and is used to control the operation of the functional unit; The functional unit includes FPGA and / or MCU; The FPGA is connected to the storage unit and is used to receive customized information from the user; The MCU is connected to the storage unit and is used for debugging and monitoring the integrated circuit.

6. The integrated circuit according to claim 1, characterized in that The integrated circuit further comprises: an interface unit corresponding to at least one group of the functional units, The functional unit is connected to the data unit through a corresponding interface unit and stores and accesses data on the data unit.

7. The integrated circuit according to claim 3, characterized in that: The storage units are connected in series via a bus for data conversion between multiple groups of the storage units.

8. The integrated circuit according to claim 1, characterized in that The sum of bandwidths of at least one group of the functional units is less than or equal to the bandwidth of the data unit.

9. An integrated circuit system, characterized in that: include: A plurality of integrated circuits as claimed in any one of claims 5 to 8 and a second controller respectively connected to the plurality of said integrated circuits.

10. The integrated circuit system according to claim 9, characterized in that: The second controller is respectively connected to the communication interaction unit in each of the integrated circuits.

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