A method and system for signal compression transmission based on TDM

Abstract

The present invention discloses a method and system for signal compression transmission based on TDM, comprising the following steps: in a parallel clock cycle, a transmitting device converts parallel interconnection signals of several transmitting ends into controllable number of interconnection signals between FPGAs through a TDM parallel-to-serial circuit; a receiving device receives the interconnection signals between FPGAs and restores them into parallel interconnection signals of several receiving ends, thereby realizing compression transmission of interconnection signals. The present invention can not only realize configurable compression ratio, realize conversion of n signal lines between FPGAs into 1+1 signal lines for transmission between FPGAs, but also enable TXFSM / RXFSM circuits to realize parallel-to-serial and serial-to-parallel conversion, and at the same time, it is not targeted at a specific protocol, and compression transmission can be realized as long as the interconnection signals between FPGAs are synchronous signals under the same clock domain.

Description

Technical Field

[0001] The invention relates to a method and system for signal compression transmission based on TDM. Background Art

[0002] As the chip scale becomes larger and larger, one FPGA can no longer accommodate enough circuits in FPGA prototype verification, so the circuits need to be divided into different FPGAs. After division, due to the limited number of IOs of FPGA, it is impossible to support direct transmission of multiple buses (such as CHI bus) and internal interconnection lines (often reaching tens of thousands of interconnection lines), and the FPGA board level cannot directly support so many signal interconnections.

[0003] Signal transmission between multiple FPGA chips can include transmission of AXI, AHB, APB, CHI and ACE signals, such as Figure 1 As shown, when transmitting data between devices, taking the CHI bus as an example, data transmission based on the CHI bus is carried out between RN-F and ICN, and different types of transmission channels are established between RN-F and ICN respectively to realize the interconnection of request / response / data / monitoring. However, since this protocol does not have a ready signal, it is impossible to perform compressed transmission by combining the valid with the ready signal.

[0004] For AXI, AHB and ACE signals, the method of patented disclosure (patent announcement number CN117234995 and patent announcement number CN117009276) can be used for compressed transmission. However, if FPGAs are interconnected not by AXI / AHB bus but by CHI or any non-protocol signal, the above method cannot be used. Summary of the invention

[0005] The purpose of the present invention is to provide a technical solution of a method and system for signal compression transmission based on TDM to address the deficiencies in the prior art. The compression transmission method can not only realize configurable compression ratio and convert n signal lines between FPGAs into 1+1 signal lines for transmission between FPGAs, but also enable the TXFSM / RXFSM circuit to realize parallel-to-serial and serial-to-parallel conversion. At the same time, it is not targeted at a specific protocol, and compression transmission can be realized as long as the signals interconnected between FPGAs are synchronous signals under the same clock domain.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0007] A method for signal compression transmission based on TDM, characterized by comprising the following steps:

[0008] In a parallel clock cycle, the transmitting device converts the parallel interconnection signals of several transmitting ends into a controllable number of interconnection signals between FPGAs through the TDM parallel-to-serial circuit. The parallel clock uses the p-multiplied clock of clk_ser, where p=k+3, k is the compression ratio. The TDM parallel-to-serial circuit includes the tdm_sync circuit and the tdm_mux circuit. The interconnection signals between FPGAs include the tx_sync_ser signal and the tx_data_ser signal.

[0009] The receiving device receives the interconnection signal between FPGAs and restores it into parallel interconnection signals of several receiving ends, thereby realizing compressed transmission of the interconnection signal.

[0010] This compression transmission method can not only realize configurable compression ratio and convert n signal lines between FPGAs into 1+1 signal lines for transmission between FPGAs, but also enable the TXFSM / RXFSM circuit to realize parallel-to-serial and serial-to-parallel conversion. At the same time, it is not targeted at specific protocols and can realize compression transmission as long as the signals interconnected between FPGAs are synchronous signals in the same clock domain.

[0011] A signal compression transmission system based on TDM, characterized in that it includes a sending device and a receiving device, wherein:

[0012] The transmitting device is used to convert the parallel interconnection signals of several transmitting ends into a controllable number of interconnection signals between FPGAs through the TDM parallel-to-serial circuit within a parallel clock cycle. The parallel clock adopts the p-frequency clock of clk_ser, where p=k+3, k is the compression ratio. The TDM parallel-to-serial circuit includes a tdm_sync circuit and a tdm_mux circuit. The interconnection signals between FPGAs include a tx_sync_ser signal and a tx_data_ser signal.

[0013] The receiving device is used to receive the interconnection signal between FPGAs and restore it into parallel interconnection signals of several receiving ends to realize the compressed transmission of the interconnection signal.

[0014] The system can not only realize configurable compression ratio and convert n signal lines between FPGAs into 1+1 signal lines for transmission between FPGAs, but also enable the TXFSM / RXFSM circuit to realize parallel-to-serial and serial-to-parallel conversion. At the same time, it is not targeted at specific protocols, and compressed transmission can be achieved as long as the signals interconnected between FPGAs are synchronous signals in the same clock domain.

[0015] The present invention has the following beneficial effects due to the adoption of the above technical solution:

[0016] The present invention can not only realize configurable compression ratio and convert n signal lines between FPGAs into 1+1 signal lines for transmission between FPGAs, but also enable the TXFSM / RXFSM circuit to realize parallel-to-serial and serial-to-parallel conversion. At the same time, it is not targeted at a specific protocol, and compressed transmission can be realized as long as the signals interconnected between FPGAs are synchronous signals under the same clock domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below in conjunction with the accompanying drawings:

[0018] Figure 1 It is a schematic diagram of CHI bus data between devices in the prior art;

[0019] Figure 2 A schematic diagram of a TDM-based signal compression transmission method and a compressed signal transmission between FPGAs in the system of the present invention;

[0020] Figure 3 A circuit diagram of a tdm_sync circuit generating a tx_sync_ser signal in the present invention;

[0021] Figure 4 It is a schematic diagram of the operation of the TXFSM circuit of the sending device in the present invention;

[0022] Figure 5 It is a schematic diagram of the operation of the RXFSM circuit of the receiving device in the present invention. DETAILED DESCRIPTION

[0023] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0026] Definitions of professional terms used in this invention:

[0027] Abbreviations Chinese ACE AXI Buffer Extension Interface AXI Advanced extension interface Channel aisle FF trigger FIFO FIFO FPGA Field Programmable Gate Array FSM Finite State Machine IP Intellectual Property PARTITION segmentation TDM time-division multiplexing RC Root Complex RX DATA Receiving Data RX FSM Receive state machine SERDES SERializer (serializer) / DESerializer (deserializer) SOC System-on-Chip TX DATA Sending Data TX FSM Sending state machine RX Receiver TX Transmitter clk_paral Parallel clock PLL Phase-locked loop clk_ser Serial clock

[0028] The present invention provides a method for signal compression transmission based on TDM, comprising the following steps:

[0029] In a parallel clock cycle, the sending device converts the parallel interconnection signals of several sending ends into a controllable number of FPGA interconnection signals through the TDM parallel-to-serial circuit. The parallel clock uses the p-multiplied clock of clk_ser, where p=k+3, k is the compression ratio, and p depends on the compression ratio k.

[0030] The compression ratio k is configurable, and is generally configured as 4:1 / 8:1 / 16:1 / 32:1. For example, at 8:1, 8 parallel signals become 1+1 serial signals in the middle; at 16:1, 1 parallel signal becomes 1+1 serial signal in the middle.

[0031] The parallel interconnection signals of the plurality of transmitting ends include ff1tx, ff2tx, ..., ffntx.

[0032] The TDM parallel-to-serial circuit includes a tdm_sync circuit and a tdm_mux circuit.

[0033] The interconnection signals between FPGAs include the tx_sync_ser signal and the tx_data_ser signal.

[0034] The tdm_sync circuit generates a tx_sync_ser signal based on the phase relationship between the parallel clock and the serial clock, which is transmitted from the sending device to the receiving device. The tx_sync_ser signal flips once in each parallel clock cycle and is used to synchronize the serial bits between the sending device and the receiving device.

[0035] The tdm_sync circuit generates a tx_sync_in signal, which is provided to the TXFSM circuit of the transmitting device. The tx_sync_in signal is flipped only once in each parallel clock cycle.

[0036] like Figure 3 As shown, the 2-frequency signal of clk_paral is sampled by clk_ser, and XORed with reg_paral_div2 through reg_div2_sample_ser, and tx_sync_ser is obtained after clk_ser sampling. This signal is a pulse signal with a width of clk_ser period in the clk_ser clock domain; tx_sync_in is obtained after clk_ser inversion sampling. This signal is also a pulse signal with a width of clk_ser period in the clk_ser clock domain.

[0037] The receiving device receives the interconnection signal between FPGAs and restores it into parallel interconnection signals of several receiving ends, thereby realizing compressed transmission of the interconnection signal.

[0038] The parallel interconnection signals of the plurality of receiving ends include ff1rx, ff2rx, ..., ffnrx.

[0039] In the TXFSM circuit in the transmitting device, the clk_ser clock starts the state machine flipping according to the tx_sync_in signal generated by the tdm_sync circuit. Each time the FSM flips, a parallel signal of the FPGA is sent to the tx_data_ser signal.

[0040] like Figure 4 As shown, after power-on reset, FSM is in st_idle state, indicating idle, waiting for the arrival of tx_sync_ser;

[0041] When tx_sync_in is sampled to be high, enter st_ff1tx and assign ff1tx to tx_data_ser;

[0042] In the next cycle, enter st_ff2tx and assign ff2tx to tx_data_ser;

[0043] Similarly, enter st_ffntx and assign ffntx to tx_data_ser;

[0044] After that, it enters the waiting cycle to allow time for RX to recover;

[0045] Then it returns to the st_idle state and waits for the next batch of parallel data to be sent.

[0046] In the RXFSM circuit in the receiving device, the clk_ser clock starts the state machine according to the tx_sync_ser signal sent by the transmitting device. Each time the FSM flips, it takes a tx_data_ser serial signal and restores it to the required parallel clock domain signal.

[0047] like Figure 5 As shown, after power-on reset, FSM is in st_idle state, indicating idle, waiting for the arrival of tx_sync_ser;

[0048] When tx_sync_ser is sampled to be high, it enters st_ff1rx, and tx_data_ser is assigned to ff1rx;

[0049] In the next cycle, st_ff2rx is entered, and tx_data_ser will be assigned to ff2rx;

[0050] Similarly, enter st_ffnrx, ​​and tx_data_ser will be assigned to ffnrx;

[0051] After that, it enters the hold cycle so that all serial bits can present a complete parallel data;

[0052] Then it returns to the st_idle state and waits for the next batch of parallel data to be received.

[0053] This compression transmission method can not only realize configurable compression ratio and convert n signal lines between FPGAs into 1+1 signal lines for transmission between FPGAs, but also enable the TXFSM / RXFSM circuit to realize parallel-to-serial and serial-to-parallel conversion. At the same time, it is not targeted at specific protocols and can realize compression transmission as long as the signals interconnected between FPGAs are synchronous signals in the same clock domain.

[0054] like Figure 2 As shown, a signal compression transmission system based on TDM includes a sending device and a receiving device, wherein:

[0055] The sending device is used to convert the parallel interconnection signals of several sending ends into a controllable number of FPGA interconnection signals through the TDM parallel-to-serial circuit within one parallel clock cycle. The parallel clock uses the p-multiplied clock of clk_ser, where p=k+3, k is the compression ratio, and p depends on the compression ratio k.

[0056] The compression ratio k is configurable, and is generally configured as 4:1 / 8:1 / 16:1 / 32:1. For example, at 8:1, 8 parallel signals become 1+1 serial signals in the middle; at 16:1, 1 parallel signal becomes 1+1 serial signal in the middle.

[0057] The parallel interconnection signals of the plurality of transmitting ends include ff1tx, ff2tx, ..., ffntx.

[0058] The TDM parallel-to-serial circuit includes a tdm_sync circuit and a tdm_mux circuit.

[0059] The interconnection signals between FPGAs include the tx_sync_ser signal and the tx_data_ser signal.

[0060] The tdm_sync circuit generates a tx_sync_ser signal based on the phase relationship between the parallel clock and the serial clock, which is transmitted from the sending device to the receiving device. The tx_sync_ser signal flips once in each parallel clock cycle and is used to synchronize the serial bits between the sending device and the receiving device.

[0061] The tdm_sync circuit generates a tx_sync_in signal, which is provided to the TXFSM circuit of the transmitting device. The tx_sync_in signal is flipped only once in each parallel clock cycle.

[0062] like Figure 3 As shown, the 2-frequency signal of clk_paral is sampled by clk_ser, and XORed with reg_paral_div2 through reg_div2_sample_ser, and tx_sync_ser is obtained after clk_ser sampling. This signal is a pulse signal with a width of clk_ser period in the clk_ser clock domain; tx_sync_in is obtained after clk_ser inversion sampling. This signal is also a pulse signal with a width of clk_ser period in the clk_ser clock domain.

[0063] The receiving device is used to receive the interconnection signal between FPGAs and restore it into parallel interconnection signals of several receiving ends to realize the compressed transmission of the interconnection signal.

[0064] The parallel interconnection signals of the plurality of receiving ends include ff1rx, ff2rx, ..., ffnrx.

[0065] In the TXFSM circuit in the transmitting device, the clk_ser clock starts the state machine flipping according to the tx_sync_in signal generated by the tdm_sync circuit. Each time the FSM flips, a parallel signal of the FPGA is sent to the tx_data_ser signal.

[0066] like Figure 4 As shown, after power-on reset, FSM is in st_idle state, indicating idle, waiting for the arrival of tx_sync_ser;

[0067] When tx_sync_in is sampled to be high, enter st_ff1tx and assign ff1tx to tx_data_ser;

[0068] In the next cycle, enter st_ff2tx and assign ff2tx to tx_data_ser;

[0069] Similarly, enter st_ffntx and assign ffntx to tx_data_ser;

[0070] After that, it enters the waiting cycle to allow time for RX to recover;

[0071] Then it returns to the st_idle state and waits for the next batch of parallel data to be sent.

[0072] In the RXFSM circuit in the receiving device, the clk_ser clock starts the state machine according to the tx_sync_ser signal sent by the transmitting device. Each time the FSM flips, it takes a tx_data_ser serial signal and restores it to the required parallel clock domain signal.

[0073] like Figure 5 As shown, after power-on reset, FSM is in st_idle state, indicating idle, waiting for the arrival of tx_sync_ser;

[0074] When tx_sync_ser is sampled to be high, it enters st_ff1rx, and tx_data_ser is assigned to ff1rx;

[0075] In the next cycle, st_ff2rx is entered, and tx_data_ser will be assigned to ff2rx;

[0076] Similarly, enter st_ffnrx, ​​and tx_data_ser will be assigned to ffnrx;

[0077] After that, it enters the hold cycle so that all serial bits can present a complete parallel data;

[0078] Then it returns to the st_idle state and waits for the next batch of parallel data to be received.

[0079] The system can not only realize configurable compression ratio and convert n signal lines between FPGAs into 1+1 signal lines for transmission between FPGAs, but also enable the TXFSM / RXFSM circuit to realize parallel-to-serial and serial-to-parallel conversion. At the same time, it is not targeted at specific protocols, and compressed transmission can be achieved as long as the signals interconnected between FPGAs are synchronous signals in the same clock domain.

[0080] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent replacements or modifications made based on the present invention to achieve basically the same technical effects are all included in the protection scope of the present invention.

Claims

1. A method for signal compression transmission based on TDM, characterized in that The steps include: In one parallel clock cycle, the transmitting device converts the parallel interconnection signals of several transmitting ends into a controllable number of interconnection signals between FPGAs through the TDM parallel-to-serial circuit. The parallel clock adopts the p-frequency clock of clk_ser. The TDM parallel-to-serial circuit includes a tdm_sync circuit and a tdm_mux circuit. The interconnection signals between FPGAs include a tx_sync_ser signal and a tx_data_ser signal. The tdm_sync circuit generates the tx_sync_ser signal according to the phase relationship between the parallel clock and the serial clock, and transmits the tx_sync_ser signal from the transmitting device to the receiving device. The tx_sync_ser signal flips once in each parallel clock cycle and is used for synchronization of serial bits between the transmitting device and the receiving device. The receiving device receives the interconnection signal between FPGAs and restores it into parallel interconnection signals of several receiving ends to realize the compressed transmission of the interconnection signal; in the receiving device, the clk_ser clock starts the state machine according to the tx_sync_ser signal sent by the sending device. Each time the FSM flips, a tx_data_ser serial signal is restored to the required parallel clock domain signal.

2. The method for signal compression transmission based on TDM according to claim 1, characterized in that: The tdm_sync circuit generates a tx_sync_in signal, which is provided to a TXFSM circuit of a transmitting device for use. The tx_sync_in signal is flipped only once in each parallel clock cycle.

3. The method for signal compression transmission based on TDM according to claim 2, characterized in that: In the transmitting device, the clk_ser clock starts the state machine flipping according to the tx_sync_in signal generated by the tdm_sync circuit. Each time the FSM flips, a parallel signal of the FPGA is taken and sent to the tx_data_ser signal.

4. A signal compression transmission system based on TDM, characterized in that: It includes a sending device and a receiving device, wherein: A transmitting device, used to convert parallel interconnection signals of several transmitting ends into controllable number of FPGA interconnection signals through a TDM parallel-to-serial circuit within a parallel clock cycle, wherein the parallel clock adopts a p-frequency clock of clk_ser, the TDM parallel-to-serial circuit includes a tdm_sync circuit and a tdm_mux circuit, and the FPGA interconnection signal includes a tx_sync_ser signal and a tx_data_ser signal; the tdm_sync circuit generates the tx_sync_ser signal according to the phase relationship between the parallel clock and the serial clock, and transmits the tx_sync_ser signal from the transmitting device to the receiving device, and the tx_sync_ser signal flips once within each parallel clock cycle, and is used for synchronization of serial bits between the transmitting device and the receiving device; The receiving device is used to receive the interconnection signal between FPGAs and restore it into parallel interconnection signals of several receiving ends to realize the compressed transmission of the interconnection signal; in the receiving device, the clk_ser clock starts the state machine according to the tx_sync_ser signal sent by the sending device. Each time the FSM flips, a tx_data_ser serial signal is restored to the required parallel clock domain signal.

5. The system for signal compression transmission based on TDM according to claim 4, characterized in that: The tdm_sync circuit generates a tx_sync_in signal, which is provided to a TXFSM circuit of a transmitting device for use. The tx_sync_in signal is flipped only once in each parallel clock cycle.

6. The TDM-based signal compression transmission system according to claim 5, characterized in that: In the transmitting device, the clk_ser clock starts the state machine flipping according to the tx_sync_in signal generated by the tdm_sync circuit. Each time the FSM flips, a parallel signal of the FPGA is taken and sent to the tx_data_ser signal.

Images