Method for expanding DDR by FPGA device
By independently controlling the storage chip in the expansion cache area in the FPGA device, the problem of insufficient flexibility of DDR capacity and number of channels has been solved, and the efficient utilization of DDR and the diversified application of the product have been achieved, which improves the added value and development efficiency of the product.
Patent Information
- Application Number
- CN202411224554.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-03
- Publication Date
- 2025-01-24
Smart Images
Figure CN119357119A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic information technology, and in particular to a method for extending DDR using an FPGA device that can flexibly divide DDR capacity and flexibly expand the number of DDR channels. Background Art
[0002] FPGA has a wide range of uses due to its flexible pin allocation and interface expansion. Among them, FPGA-based DDR storage technology is also widely used in practical applications, especially in high-speed, large data throughput data communication or data processing business, where DDR expansion is almost indispensable.
[0003] Currently, FPGAs used to expand DDR are generally mid-to-high-end FPGA chips with HP Bank. HP Bank is the first choice for expanding DDR channels. Sometimes, HR Bank can also be used to expand multiple DDR channels.
[0004] The current DDR expansion method is relatively simple. In order to meet the business processing of large amounts of data, designers generally focus on expanding a whole block of DDR as a cache area, such as Figure 4 As shown in the figure, some designers will expand it into two relatively large cache areas to meet the requirements of ping-pong operations. Each large cache area is composed of several small memory chips (also called: memory particles), such as 8 memory chips with a bit width of 8 bits (x8) to form a cache area with a bit width of 64 bits (x64), or 2 memory chips with a bit width of 16 bits (x16) to form a cache area with a bit width of 32 bits (x32), and so on.
[0005] The expansion method in the prior art has the following shortcomings:
[0006] 1. Lack of flexibility. The DDR channels expanded based on the existing method can only be 1 or 2 channels once the product is manufactured and cannot be adjusted.
[0007] 2. Low reuse rate. When other interfaces are compatible but only the number of DDR channels is not met, the product cannot be reused, resulting in a single product use, non-reusability and low added value.
[0008] 3. DDR utilization is low. Generally, during design, the capacity of DDR is designed with certain redundancy based on evaluation. However, in actual application, the cache area used is often much smaller than the evaluation value, resulting in a large part of the capacity being unused, thus reducing the utilization of DDR.
[0009] 4. It is not conducive to cost control. In order to meet the demand for the number of DDR channels in new application scenarios or to make up for the defects in the design, the only way is to redesign the circuits related to DDR expansion. However, when the PCB drawings are redesigned after the design is completed, other parts of the circuit are drawn repeatedly, resulting in a waste of manpower, time and material costs.
[0010] The current expansion technology is the most fundamental and basic expansion method. Its defects are caused by the progress of technology, not its inherent defects. In previous applications, the buffer design often only serves fixed high-speed interfaces, so the single-chip buffer area is large enough and there is no need to consider adjustment.
[0011] However, with the continuous updating of communication technology, current applications have gradually increased requirements for interface types, the number of data channels, and the communication rate. The inherent 1 or 2 large cache areas often seem to be unable to adapt to the development of technology and the ever-changing application scenarios. Summary of the invention
[0012] In view of the above problems, the present invention provides a method for extending DDR by an FPGA device for overcoming the above problems or at least partially solving the above problems, solving the problems of adjusting DDR capacity on demand, changing DDR channels on demand, DDR utilization and cost control.
[0013] The present invention provides the following scheme:
[0014] A method for extending DDR using an FPGA device, comprising:
[0015] Determining the number of extended cache areas, each of which includes at least one memory chip;
[0016] The pins of the control part and the address part of all the storage chips contained in each extended cache area are aggregated and connected to a configurable pin of the FPGA device, so as to realize independent control of all the storage chips contained in each extended cache area, thereby achieving the purpose of multi-channel expansion of the storage chip.
[0017] Preferably: each of the extended buffer areas includes a memory chip; the control part pins and the address part pins of each memory chip are independently connected to the DDR controller generated by the FPGA device.
[0018] Preferably, each of the extended cache areas includes a plurality of the memory chips, and the number of the memory chips is 2. n .
[0019] Preferably: each of the extended cache areas includes two of the memory chips, and the signals with the same name in the control pins corresponding to the two memory chips and the signals with the same name in the address part are connected together respectively, and then aggregated to the pins corresponding to the DDR control generated by the FPGA device.
[0020] Preferably: the DDR generated by the FPGA device controls the internal interconnection of the corresponding pins, thereby replacing the external copper foil method to connect multiple signal pins with the same name.
[0021] Preferably, the pins of the address part, the data part and the control part corresponding to the same memory chip are respectively in the same Bank or in a Bank group with a shared clock.
[0022] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:
[0023] The method for extending DDR by an FPGA device provided in the embodiment of the present application can divide product grades according to capacity to form a series of products. It is also possible to divide product grades according to the number of channels to form a series of products. Excess memory chips can be soldered empty according to the actual demand for the buffer area, thereby reducing material costs. The developed products can be made suitable for application scenarios with different buffer capacities and different channel numbers, thereby improving the reuse rate of the whole machine product, and then improving the added value of the whole machine product. The capacity adjustment brought by this method has the characteristics of short time, high reliability, and strong operability. It can respond to customer needs with reliable physical objects in the shortest time, so it will have an extremely obvious advantage in time effects such as project competition, and then occupy more market share in the shortest time. This method can flexibly divide DDR capacity, flexibly expand the number of DDR channels, improve DDR utilization, enhance the added value of products, and greatly shorten the development cycle.
[0024] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0026] Figure 1 It is a device connection block diagram after the expansion of a method for expanding DDR by an FPGA device provided by an embodiment of the present invention;
[0027] Figure 2 It is a schematic diagram of a technical implementation scheme of two particles forming a DDR channel provided by an embodiment of the present invention;
[0028] Figure 3 It is a schematic diagram of a technical implementation scheme of multiple particles forming a DDR channel provided by an embodiment of the present invention;
[0029] Figure 4 It is a schematic diagram of the existing technical solution of extending DDR based on FPGA. DETAILED DESCRIPTION
[0030] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.
[0031] See also Figure 1 , a method for extending DDR by an FPGA device provided by an embodiment of the present invention, such as Figure 1 As shown, the method may include:
[0032] Determining the number of extended cache areas, each of which includes at least one memory chip;
[0033] The pins of the control part and the address part of all the storage chips contained in each extended cache area are aggregated and connected to a configurable pin of the FPGA device, so as to realize independent control of all the storage chips contained in each extended cache area, thereby achieving the purpose of multi-channel expansion of the storage chip.
[0034] Furthermore, each of the extended cache areas includes a memory chip; the control part pins and address part pins of each memory chip are independently connected to the DDR controller generated by the FPGA device.
[0035] Each of the extended cache areas includes a plurality of the memory chips, and the number of the memory chips is 2 n .
[0036] Each of the extended buffer areas includes two of the memory chips. The signals with the same name in the control pins corresponding to the two memory chips and the signals with the same name in the address part are connected together respectively, and then summarized to the pins corresponding to the DDR control generated by the FPGA device.
[0037] The DDR control pins generated by the FPGA device are internally interconnected, thereby replacing the external copper foil method to connect multiple signal pins with the same name.
[0038] The pins of the address part, data part and control part corresponding to the same memory chip are respectively in the same bank or in a bank group with a shared clock.
[0039] The expansion method provided in the embodiment of the present application is based on the current traditional expansion method, by adding control pins and address pins, so as to achieve the purpose of the present invention.
[0040] The method for extending DDR by an FPGA device provided in the present application is described in detail below using 8 memory chips with a bit width of 8 bits (x8) as an example.
[0041] It is understandable that the method provided in the embodiment of the present application has certain requirements on the resources of the FPGA itself, and is generally suitable for mid-to-high-end or high-end FPGA chips, because such chips are often more suitable for scenarios with higher and more demanding requirements on speed, interface, data throughput, etc., and have relatively more configurable pins, HP Bank and HR Bank, etc.
[0042] The specific implementation method of the method provided in the embodiment of the present application is as follows:
[0043] The pins of DDR memory chips can be simply summarized into the following parts: power part, address part, data part and control part.
[0044] The power supply and data parts are consistent with the traditional design method, so I will not go into details here;
[0045] Control part and address part: The traditional expansion method connects the control parts of all memory chips in a cache area in a daisy chain or T-type manner, and then aggregates them to the DDR controller, making it impossible to independently control each memory chip. For example, a cache area with a bit width of 64 bits (x64) is composed of 8 memory chips with a bit width of 8 bits (x8). The traditional expansion method is to connect the signals with the same name in the control pins of the 8 memory chips and the signals with the same name in the address part, and then aggregate them to the corresponding pins of the DDR control generated by the FPGA.
[0046] The expansion method provided by the embodiment of the application is to connect the pins of the control part and the address part of each or several memory chips in each extended cache area to the configurable pins of the FPGA separately, so as to realize independent control of each or several chips in each extended cache area, thereby realizing the purpose of DDR multi-channel expansion. Figure 1 shown.
[0047] For example, if eight memory chips with a bit width of 8 bits (x8) are used to form a cache area, by appropriately increasing the FPGA pin resources and determining that each extended cache area includes a memory chip, the control part pins and address part pins of each DDR memory chip are independently connected to the DDR controller generated by the FPGA, and eight DDR cache areas with a bit width of 8 (x8) can be generated, that is, eight 8-bit DDR controllers (also called DDR channel number) are generated by using the FPGA, and eight DDR cache areas are expanded.
[0048] After determining that each extended buffer area includes two memory chips, the signals with the same name in the control pins corresponding to the two DDR memory chips and the signals with the same name in the address part are connected together, and then summarized to the pins corresponding to the DDR control generated by the FPGA, so that four buffers with a width of 16 bits (x16) can be generated, that is, four 16-bit DDR controllers (also called DDR channel number) are generated by using FPGA, and four DDR buffer areas are expanded, such as Figure 2 shown.
[0049] When all eight chips are connected together in the traditional way, a cache area with a bit width of 64 (x64) can be generated, that is, a 64-bit DDR controller (also called the number of DDR channels) is generated using FPGA, and a DDR cache area is expanded, such as Figure 3 shown.
[0050] When multiple DDR memory chips are used to expand the bit width, the number of memory chips contained in each extended buffer area is generally 2 n , such as: 2, 4, 8, 16, etc. This is related to the use of binary calculations inside the computer.
[0051] The use of DDR memory chips requires the control part, address part and data part to be of equal length, i.e., a delay problem. Therefore, when using the expansion method provided in this application to combine two or more memory chips of equal number, it is necessary to configure the corresponding pins of the FPGA to interconnect them internally, thereby replacing the external copper foil method to connect multiple signal pins with the same name, thereby reducing the wiring workload and wiring complexity to a certain extent.
[0052] When using the method provided in the embodiment of the present application to expand DDR, it is required that the pins of the address part, data part and control part corresponding to the same DDR memory chip (storage particle) are as far as possible in the same bank or in a bank group with a shared clock, so as to improve reliability.
[0053] In the current economic era, cost control is an unavoidable topic. The research and development of the same product always hopes to adapt to more application scenarios, always hopes to exchange more markets at the lowest cost, always hopes to respond to user needs at the fastest speed, etc., so as to increase the added value of product research and development. The above-mentioned expansion method provided in the embodiment of the present application can achieve the above-mentioned purpose.
[0054] In short, the method for extending DDR by FPGA device provided by the present application can divide product grades according to capacity to form a series of products. It is also possible to divide product grades according to the number of channels to form a series of products. Excess memory chips can be soldered empty according to the actual demand for the buffer area, thereby reducing material costs. The developed products can be made suitable for application scenarios with different buffer capacities and different channel numbers, thereby improving the reuse rate of the whole machine product, and then improving the added value of the whole machine product. The capacity adjustment brought by this method has the characteristics of short time, high reliability, and strong operability. It can respond to customer needs with reliable physical objects in the shortest time, so it will have an extremely obvious advantage in time effects such as project competition, and then occupy more market share in the shortest time. This method can flexibly divide DDR capacity, flexibly expand the number of DDR channels, improve DDR utilization, enhance the added value of products, and greatly shorten the development cycle.
[0055] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0056] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.
[0057] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.
[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A method for extending DDR using an FPGA device, characterized in that: include: Determining the number of extended cache areas, each of which includes at least one memory chip; The pins of the control part and the address part of all the storage chips contained in each extended cache area are aggregated and connected to a configurable pin of the FPGA device, so as to realize independent control of all the storage chips contained in each extended cache area, thereby achieving the purpose of multi-channel expansion of the storage chip.
2. The method for extending DDR by an FPGA device according to claim 1, characterized in that: Each of the extended buffer areas includes a memory chip; the control part pins and address part pins of each memory chip are independently connected to the DDR controller generated by the FPGA device.
3. The method for extending DDR by an FPGA device according to claim 1, characterized in that: Each of the extended cache areas includes a plurality of the memory chips, and the number of the memory chips is 2 n .
4. The method for extending DDR by an FPGA device according to claim 3, characterized in that: Each of the extended buffer areas includes two of the memory chips. The signals with the same name in the control pins corresponding to the two memory chips and the signals with the same name in the address part are connected together respectively, and then summarized to the pins corresponding to the DDR control generated by the FPGA device.
5. The method for extending DDR by an FPGA device according to claim 4, characterized in that: The DDR control pins generated by the FPGA device are internally interconnected, thereby replacing the external copper foil method to connect multiple signal pins with the same name.
6. The method for extending DDR by an FPGA device according to claim 1, characterized in that: The pins of the address part, data part and control part corresponding to the same memory chip are respectively in the same bank or in a bank group with a shared clock.