An analog computer chip

Abstract

The present invention relates to the field of artificial intelligence technology, and discloses an analog computer chip; the analog computer chip includes an input layer, N addition layers and an output layer; each addition layer includes multiple adders; each input interface in the input layer is connected to each adder in the first addition layer through different operation units; in the N addition layers, each adder in the upper addition layer is connected to each adder in the lower addition layer through different operation units; each operation unit has a transfer function corresponding to its node parameter; and multiple adders in the Nth adder layer are connected one-to-one with multiple output interfaces in the output layer; the operation units and adders are both composed of analog devices. In the above scheme, using the analog computer chip as an artificial intelligence chip can reduce the size of the artificial intelligence chip, increase the speed of the artificial intelligence chip, and reduce the power consumption of the artificial intelligence chip.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and particularly relates to an analog computer chip. Background Art

[0002] With the rise of artificial intelligence technology, artificial intelligence chips capable of realizing certain specific functions have received extensive attention and applications.

[0003] However, the artificial intelligence chips in the prior art are usually digital computer chips, which are generally composed of a graphics processing unit, a field programmable gate array, and other module circuits. However, since the arithmetic units of the graphics processing unit in the prior art all adopt digital operations, a single arithmetic unit requires tens of thousands to hundreds of thousands of transistors. Therefore, there are usually only thousands of arithmetic units in a single graphics processing unit in the prior art. At this time, if it is necessary to perform calculations on tens of thousands or even hundreds of millions of data simultaneously, a large number of graphics processing units must be used for parallel processing, which results in the problems of large volume, slow speed, and high power consumption of the digital computer chip as an artificial intelligence chip in the prior art. Summary of the Invention

[0004] In view of this, the present application provides an analog computer chip to solve the problems of large volume, slow speed, and high power consumption of the digital computer chip as an artificial intelligence chip. The technical solution is as follows.

[0005] In a first aspect, an analog computer chip is provided. The analog computer chip includes an input layer, N addition layers, and an output layer;

[0006] The input layer includes a plurality of input interfaces; each addition layer includes a plurality of adders; each input interface in the input layer is connected to each adder in the first addition layer through different arithmetic units; in the N addition layers, each adder in the upper addition layer is connected to each adder in the lower addition layer through different arithmetic units; each arithmetic unit has a transfer function corresponding to its node parameters;

[0007] And a plurality of adders in the Nth addition layer are connected to a plurality of output interfaces in the output layer in one-to-one correspondence; the arithmetic units and adders are all composed of analog devices.

[0008] In a possible implementation manner, the arithmetic unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a first operational amplifier;

[0009] The input end of the arithmetic unit is connected to the non-inverting input end of the first operational amplifier through the second resistor; the non-inverting input end of the first operational amplifier is grounded through the first resistor;

[0010] The inverting input terminal of the first operational amplifier is connected to the first voltage terminal through a third resistor; the inverting input terminal of the first operational amplifier is also connected to the input terminal of the first operational amplifier through a fourth resistor; the output terminal of the first operational amplifier is connected to the output terminal of the arithmetic unit.

[0011] In a possible implementation, the first resistor, the second resistor, the third resistor, and the fourth resistor are all adjustable resistors; alternatively, the first resistor and the fourth resistor are adjustable resistors; or, the second resistor and the third resistor are adjustable resistors.

[0012] In a possible implementation, the resistance value of the first resistor is equal to the resistance value of the fourth resistor; the resistance value of the second resistor is equal to the resistance value of the third resistor.

[0013] In a possible implementation, the transfer function of the arithmetic unit is:

[0014]

[0015] where x is the input value of the transfer function; y is the output value of the transfer function; W is the node parameter, , R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, and A11 is the gain of the first operational amplifier.

[0016] In a possible implementation, the arithmetic unit includes a fifth resistor, a sixth resistor, and a second operational amplifier;

[0017] The non-inverting input terminal of the second operational amplifier is grounded through the fifth resistor; the non-inverting input terminal of the second operational amplifier is also connected to the first voltage terminal through the sixth resistor; the inverting input terminal of the second operational amplifier is connected to the input terminal of the arithmetic unit; the output terminal of the second operational amplifier is connected to the output terminal of the arithmetic unit.

[0018] In a possible implementation, at least one of the fifth resistor and the sixth resistor is an adjustable resistor.

[0019] In a possible implementation, the transfer function of the arithmetic unit is:

[0020]

[0021] where x is the input value of the transfer function; y is the output value of the transfer function; B is the node parameter, , R5 is the resistance value of the fifth resistor, R6 is the resistance value of the sixth resistor, and A22 is the gain of the second operational amplifier.

[0022] Second aspect, a regulation circuit is provided, and the regulation circuit is used to regulate the above-mentioned analog computer chip;

[0023] The regulation circuit includes an input end, a digital-to-analog conversion module, and a decoding module;

[0024] The input end is used to receive model parameters and generate model parameter data through the digital-to-analog conversion module; the model parameter data is used to adjust the node parameters of the arithmetic units of the analog computer chip;

[0025] The decoding module is used to receive the parameter address corresponding to the model parameter and determine the arithmetic unit corresponding to the model parameter data according to the parameter address.

[0026] In a possible implementation manner, the decoding module includes a connection sub-circuit, an execution sub-circuit, and an address sub-circuit;

[0027] The address sub-circuit is used to determine the arithmetic unit to be regulated according to the parameter address and connect the arithmetic unit to be regulated to the execution sub-circuit through the connection sub-circuit;

[0028] The execution sub-circuit is used to adjust the node parameters of the arithmetic unit to be regulated according to the model parameter data.

[0029] In a possible implementation manner, the regulation circuit is arranged outside the analog computer chip to adjust the node parameters of each arithmetic unit during the production process of the analog computer chip.

[0030] In a possible implementation manner, the regulation circuit is arranged inside the analog computer chip to adjust the node parameters of each arithmetic unit in the analog computer chip according to the model parameters when the model parameters are received.

[0031] Third aspect, an arithmetic unit is provided, and the arithmetic unit is arranged in the above-mentioned analog computer chip. Each adjustable resistor in the arithmetic unit is a non-volatile storage unit; the node parameters of the arithmetic unit are related to the stored data of the non-volatile storage unit.

[0032] Fourth aspect, an application circuit is provided, and the application circuit includes a front-end device, a back-end device, and the above-mentioned analog computer chip;

[0033] The front-end device is used to generate an analog electrical signal and transmit it to the analog computer chip; the analog computer chip is used to process the analog electrical signal and transmit it to the back-end device to implement the corresponding function.

[0034] The technical solution provided by this application may include the following beneficial effects:

[0035] The present application provides an analog computer chip and its adjustment circuit. The arithmetic units of the analog computer chip are all composed of analog devices, so that each arithmetic unit of the analog computer chip only requires a very small number of analog devices to achieve arithmetic operations. Usually, each arithmetic unit only requires dozens or even a few transistors. Therefore, a single analog computer chip can perform calculations on tens of thousands or even hundreds of millions of data simultaneously. Therefore, when the analog computer chip is used as an artificial intelligence chip, the volume of the artificial intelligence chip can be reduced, the speed of the artificial intelligence chip can be increased, and the power consumption of the artificial intelligence chip can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 is a schematic structural diagram of an analog computer chip shown according to an exemplary embodiment.

[0038] Figure 2 shows a schematic diagram of an application circuit of the analog computer chip in the present application.

[0039] Figure 3 shows a schematic diagram of the first arithmetic unit circuit structure in the embodiment of the present application.

[0040] Figure 4 shows a schematic diagram of the second arithmetic unit circuit structure in the embodiment of the present application.

[0041] Figure 5 shows the adjustment circuit of the arithmetic unit in the present application and its connection structure.

[0042] Figure 6 shows a schematic diagram of the structure of a decoding module in the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0044] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect corresponding relationship between two entities, may also indicate an associated relationship between them, or may be a relationship such as indication and being indicated, configuration and being configured, etc.

[0045] Figure 1 is a schematic structural diagram of an analog computer chip shown according to an exemplary embodiment. As Figure 1 shown, the analog computer chip includes an input layer, N adder layers, and an output layer;

[0046] The input layer includes a plurality of input interfaces; each adder layer includes a plurality of adders; each input interface in the input layer is connected to each adder in the first adder layer through different arithmetic units; in the N adder layers, each adder in the upper adder layer is connected to each adder in the lower adder layer through different arithmetic units; each of the arithmetic units has a transfer function corresponding to its node parameters;

[0047] and a plurality of adders in the Nth adder layer are connected to a plurality of output interfaces in the output layer in a one-to-one correspondence; both the arithmetic units and the adders are composed of analog devices.

[0048] In the embodiments of the present application, the number of input interfaces, the number of first adder layers, the number of second adder layers, and up to the number of the nth adder layer may be the same or different. At the same time, the number of the nth adder layer is the same as the number of output interfaces.

[0049] As Figure 1 shown, the input layer includes a plurality of input interfaces (including in1, in2, in3...), and external data is input into the analog computer chip through the plurality of input interfaces;

[0050] After that, the external data input by each input interface is then input into each adder in the first layer (each adder in the first layer includes adder 11, adder 12, adder 13...) connected to each arithmetic unit through the arithmetic units connected to each input interface. Among them, the attached Figure 1 arrows in it represent each arithmetic unit;

[0051] Then, the data obtained by the operations of the adders in the first layer are input into the adders in the second layer connected to the respective operation units through the respective operation units connected to the output ends of the adders in the first layer (the second-layer adders include adder 21, adder 22, adder 23...). After connecting in this way successively, the final data obtained by the operations of the adders in the nth layer (the nth-layer adders include adder n1, adder n2, adder n3...) are connected to several output interfaces of the output layer (including out1, out2, out3...). That is, at this time, several output interfaces of the output layer output the final data obtained by the operation of the analog computer chip.

[0052] Figure 2 FIG. shows a schematic diagram of an application circuit of the analog computer chip in the present application, where the analog computer chip is connected to a front-end device and a back-end device. The front-end device is used to generate an analog electrical signal and transmit it into the analog computer chip; the analog computer chip is used to process the analog electrical signal and transmit it to the back-end device to implement corresponding functions.

[0053] For example, the front-end device can be a graphic input device such as a camera or a sound input device such as a recording system. The front-end device converts the graphic signal or the sound signal into an analog electrical signal and directly inputs it into the analog computer chip. After rapid calculation by the analog computer chip, the calculated analog electrical signal is output to the back-end device. The back-end device can be a display device or a control device, etc. After calculating and analyzing the analog electrical signal output by the analog computer chip, the back-end device obtains the output signal required by the application circuit (the required output signal includes but is not limited to specific display signals such as graphics and sounds or abstract control signals such as yes and no).

[0054] Specifically, the embodiment of the present application can use an external computer to perform artificial intelligence model training according to Figure 2 the data signal input by the front-end device therein. Among them, the connection structure of the artificial intelligence model is the same as the structure of the analog computer chip shown in Figure 1 . By using an external computer to perform artificial intelligence model training, the parameters of each node in the model are obtained, and the parameters of each node correspond to the node parameters of the operation units in the analog computer chip. And changing the node parameters of each operation unit will change the transfer function of each operation unit.

[0055] Therefore, after the external computer finishes training the artificial intelligence model, it can modify the node parameters of the operation units in the analog computer chip according to the parameters of each node in the model, that is, it can change the transfer functions of the operation units in the analog computer chip, so that the analog computer chip can implement the same or similar functions as the artificial intelligence model.

[0056] Please refer to Figure 3 , which shows a schematic diagram of the first arithmetic unit circuit structure in the embodiments of the present application. As Figure 3 shown, the arithmetic unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a first operational amplifier A1;

[0057] The input end of the arithmetic unit is connected to the non-inverting input end of the first operational amplifier through the second resistor; the non-inverting input end of the first operational amplifier is grounded through the first resistor;

[0058] The inverting input end of the first operational amplifier A1 is connected to the first voltage end through the third resistor; the inverting input end of the first operational amplifier A1 is also connected to the input end of the first operational amplifier through the fourth resistor; the output end of the first operational amplifier A1 is connected to the output end of the arithmetic unit.

[0059] Optionally, the first resistor, the second resistor, the third resistor, and the fourth resistor are all adjustable resistors;

[0060] Or, the first resistor and the fourth resistor are adjustable resistors; or, the second resistor and the third resistor are adjustable resistors.

[0061] Optionally, the resistance value R1 of the first resistor is equal to the resistance value R4 of the fourth resistor; the resistance value R2 of the second resistor is equal to the resistance value R3 of the third resistor.

[0062] Let the input voltage VIN of the arithmetic unit be the independent variable x of the function, the output voltage VOUT of the arithmetic unit be the dependent variable y of the function, the first voltage end be connected to a fixed voltage VR, and the fixed voltage VR be the constant c of the function. Thus, it can be known that when the resistance value R1 of the first resistor is equal to the resistance value R4 of the fourth resistor, the resistance value R2 of the second resistor is equal to the resistance value R3 of the third resistor, and the gain of the first operational amplifier A1 is represented by A11, Figure 3 in the first arithmetic unit circuit structure shown , where VOUT is the output voltage of the arithmetic unit; VIN is the input voltage of the arithmetic unit; VR is the voltage of the first voltage end; A11 is the gain of the first operational amplifier A1; that is, at this time, after is represented by W, at this time w is the node parameter, and the transfer function is , at this time, x is the input value of the transfer function; y is the output value of the transfer function; .

[0063] Please refer to Figure 4 , which shows a schematic diagram of the second arithmetic unit circuit structure in the embodiments of the present application. As Figure 4 shown, the arithmetic unit includes a fifth resistor, a sixth resistor, and a second operational amplifier A2;

[0064] The non-inverting input terminal of the second operational amplifier A2 is grounded through the fifth resistor; the non-inverting input terminal of the second operational amplifier A2 is also connected to the first voltage terminal through the sixth resistor; the inverting input terminal of the second operational amplifier A2 is connected to the input terminal of the arithmetic unit; the output terminal of the second operational amplifier A2 is connected to the output terminal of the arithmetic unit.

[0065] Optionally, at least one of the fifth resistor and the sixth resistor is an adjustable resistor.

[0066] At this time, Figure 4 In the second arithmetic unit circuit structure shown, , where VOUT is the output terminal voltage of the arithmetic unit; VIN is the input terminal voltage of the arithmetic unit; VR is the voltage of the first voltage terminal; R5 is the resistance value of the fifth resistor; R6 is the resistance value of the sixth resistor; A22 is the gain of the second operational amplifier A2.

[0067] At this time, after is represented by B, at this time B is a node parameter, and the transfer function is ; at this time, x is the input value of the transfer function; y is the output value of the transfer function; .

[0068] At the same time, since both the first arithmetic unit circuit structure and the second arithmetic unit circuit structure are composed of operational amplifiers, therefore, the output terminal voltage VOUT of both the first arithmetic unit circuit structure and the second arithmetic unit circuit structure should be between the positive input power supply and the negative input power supply of the operational amplifier. Generally speaking, the positive input power supply of the operational amplifier is a conventional power supply such as 5V or 3.3V, and the negative input power supply is GND, that is, 0V. At this time, assuming that the positive input power supply is 5V, therefore, it can be further obtained that the accurate transfer function of the first arithmetic unit circuit structure is and the accurate transfer function of the second arithmetic unit circuit structure is ;

[0069] It can be seen from this that a single arithmetic unit of the analog computer chip in this application only needs a very small number of analog devices to achieve arithmetic operations.

[0070] Moreover, in the arithmetic units involved in the embodiments of this application, they are all circuit structures composed of analog devices. Specifically, the operational amplifiers (including the first operational amplifier A1 or the second operational amplifier A2) in the arithmetic unit can use operational amplifiers with non-infinite gain, and the gain of the operational amplifier can be obtained through calculation or measurement.

[0071] Furthermore, the embodiment of the present application further provides an adjustment circuit, which can be used to adjust the node parameters of the arithmetic unit in the analog computer chip. Figure 5 It shows the adjustment circuit of the arithmetic unit in the present application and its connection structure. The adjustment circuit includes an input end, a digital-to-analog (DAC, Digital-to-Analog) module, and a decoding module;

[0072] The input end is used to receive model parameters and generate model parameter data through the digital-to-analog conversion module; the model parameter data is used to adjust the node parameters of the arithmetic unit of the analog computer chip;

[0073] The decoding module is used to receive the parameter address corresponding to the model parameter and determine the arithmetic unit corresponding to the model parameter data according to the parameter address.

[0074] Specifically, the parameter address is input into the decoding module through the input end, and the model parameter is input into the DAC module through the input end. After the decoding module finds each arithmetic unit corresponding to the model parameter according to the parameter address, it then adjusts the corresponding node parameters in each arithmetic unit according to the analog signal output by the DAC module (i.e., the model parameter data);

[0075] The input end inputs the parameter address, and specifically, one of the following two methods can be adopted:

[0076] (1) The input parameter address includes the address data corresponding to the parameters of each node. After the decoding module finds the positions of the parameters of each node according to the address data corresponding to the parameters of each node, it then adjusts the node parameters of the arithmetic unit corresponding to the positions of the parameters of each node to the parameters of each node in the input model parameter;

[0077] (2) Although the error rate of parameter adjustment in the first method is relatively low, it will result in a large amount of input data. Therefore, the input parameter address can be designed as the address of the parameter of the first node in the input model parameter. At this time, after the decoding module adjusts the node parameters of the first arithmetic unit according to this address, the decoding module directly adjusts the node parameters of the arithmetic unit at the first address after this address to the parameters of the second node after the first node in the input model parameter, and so on, adjusting one by one in sequence until the adjustment of the node parameters of the arithmetic unit at the last address is completed;

[0078] From the above analysis, it can be seen that Figure 5 The input end needs to input the parameters of each node of the artificial intelligence model obtained by computer training and the addresses of the parameters of each node;

[0079] At this time, both the model parameters and the parameter addresses in the artificial intelligence model obtained through computer training are digital signals. The decoding module can directly receive digital signals. Therefore, the parameter addresses can be directly input into the decoding module. Since the arithmetic units of the analog computer chip in this application are all composed of analog devices, at this time, it is necessary to convert the digital signal model parameters into analog signal model parameter data through the DAC module. The converted analog signal is input into the decoding module. The decoding module adjusts the node parameters of each arithmetic unit according to the parameter addresses and the model parameter data, so as to obtain the transfer function required by the artificial intelligence model, and finally generate the artificial intelligence model obtained through computer training in the analog computer chip;

[0080] Therefore, at this time, in a possible implementation manner, the adjustment circuit can be arranged inside the analog computer chip to adjust the node parameters of each arithmetic unit in the analog computer chip according to the model parameters when receiving the model parameters. The parameters of the transfer function of the arithmetic units of the artificial intelligence model generated in the analog computer chip can be modified arbitrarily, which makes the application field of the analog computer chip relatively wide, but at the same time, it will also cause the chip to be relatively large in volume.

[0081] In another possible implementation manner, the adjustment circuit can also be arranged outside the analog computer chip to adjust the node parameters of each arithmetic unit during the production process of the analog computer chip.

[0082] For example, during the wafer manufacturing process of the analog computer chip, the node parameters of each arithmetic unit in the analog computer chip are directly adjusted to the required data through an external adjustment circuit. At this time, the node parameters of the arithmetic unit are the parameters of the transfer function required by the artificial intelligence model. Since the analog computer chip does not need to integrate the adjustment circuit, the volume of the analog computer chip is relatively small, but at the same time, it will also cause the artificial intelligence model generated in the analog computer chip to be unable to be modified, and the application field of the chip is single.

[0083] Please refer to Figure 6 , which shows a schematic structural diagram of a decoding module in an embodiment of the present application.

[0084] As Figure 6 shown, the decoding module includes a connection sub-circuit, an execution sub-circuit, and an address sub-circuit;

[0085] The address sub-circuit is used to determine the arithmetic unit to be adjusted according to the parameter address, and connect the arithmetic unit to be adjusted to the execution sub-circuit through the connection sub-circuit;

[0086] The execution sub-circuit is used to adjust the node parameters of the arithmetic unit to be adjusted according to the model parameter data.

[0087] Figure 6 The working principle of the decoding module shown is as follows:

[0088] Each arithmetic unit is arranged in the address sub-circuit in a certain order. The address sub-circuit finds the arithmetic unit to be adjusted corresponding to the input parameter address according to the parameter address. At this time, the address sub-circuit connects the arithmetic unit to be adjusted to the execution sub-circuit through the connection sub-circuit, and the execution sub-circuit adjusts the node parameters in the arithmetic unit according to the model parameter data output by the DAC module;

[0089] In a possible implementation manner of the embodiment of the present application, each adjustable resistor in the arithmetic unit is a non-volatile storage unit; the node parameters of the arithmetic unit are related to the stored data of the non-volatile storage unit.

[0090] At this time, from Figure 3 it can be known that its transfer function is , so at this time, changing the value of W (i.e., the node parameter) can adjust the transfer function. Therefore, changing Figure 3 the resistance values of the first resistor and the fourth resistor in Figure 3 or changing Figure 3 the resistance values of the second resistor and the third resistor in

[0091] Similarly, from Figure 4 it can be known that its transfer function is , so at this time, changing the value of B (i.e., the node parameter) can adjust the transfer function. Therefore, changing Figure 5 the resistance value R5 of the fifth resistor in Figure 5 or changing Figure 5By adjusting the resistance values of all the resistors in the circuit, the adjustment of the transfer function can be achieved. Therefore, at this time, non-volatile memory cells can be used as resistors. That is, both the fifth resistor and the sixth resistor are composed of non-volatile memory cells. At this time, by adjusting the stored data of the non-volatile memory cell (such as the floating gate charge of the MOS transistor in the non-volatile memory cell), its resistance value can be changed. Therefore, the non-volatile memory cell constituting the fifth resistor or the sixth resistor can be connected to the address sub-circuit. When it is necessary to change the parameters of the transfer function corresponding to a certain arithmetic unit, the address sub-circuit will find the non-volatile memory cell corresponding to this arithmetic unit. The execution sub-circuit adjusts the stored data of the non-volatile memory cell according to the model parameter data output by the DAC module (such as charging and discharging the floating gate of the MOS transistor in this non-volatile memory cell to change its resistance value), thereby changing the node parameters corresponding to the arithmetic unit to obtain the transfer function required for this arithmetic unit.

[0092] In summary, the present application provides an analog computer chip and its adjustment circuit. The arithmetic units of this analog computer chip are all composed of analog devices, so that each arithmetic unit of this analog computer chip only needs a very small number of analog devices to achieve arithmetic operations. Usually, each arithmetic unit only needs dozens or even a few transistors. Therefore, this single analog computer chip can perform calculations on tens of thousands or even hundreds of millions of data at the same time. Therefore, when this analog computer chip is used as an artificial intelligence chip, the volume of the artificial intelligence chip can be reduced, the speed of the artificial intelligence chip can be increased, and the power consumption of the artificial intelligence chip can be reduced.

[0093] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present application. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0094] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. An analog computer chip, characterized in that: The analog computer chip includes an input layer, N addition layers and an output layer; The input layer includes a plurality of input interfaces; each addition layer includes a plurality of adders; each input interface in the input layer is connected to each adder in the first addition layer through different operation units; in N addition layers, each adder in the previous addition layer is connected to each adder in the next addition layer through different operation units; each operation unit has a transfer function corresponding to its node parameters; the analog electrical signal is input into the analog computer chip through the plurality of input interfaces; The operation unit includes an adjustable resistor composed of a non-volatile storage unit; the node parameters of the operation unit are related to the storage data of the non-volatile storage unit; the transfer function of the operation unit is obtained by adjusting the storage data of the non-volatile storage unit to adjust the node parameters corresponding to the operation unit; The multiple adders in the Nth layer of adders are connected to the multiple output interfaces in the output layer in a one-to-one correspondence; the operation units and adders are both composed of analog devices; the multiple output interfaces output analog electrical signals obtained by analog computer chip operation; The analog computer chip is internally provided with a regulating circuit so as to adjust the node parameters of each computing unit in the analog computer chip according to the model parameters when receiving the model parameters.

2. The analog computer chip according to claim 1, characterized in that: The operation unit includes a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier; The input end of the operation unit is connected to the non-inverting input end of the first operational amplifier through the second resistor; the non-inverting input end of the first operational amplifier is grounded through the first resistor; The inverting input terminal of the first operational amplifier is connected to the first voltage terminal through a third resistor; the inverting input terminal of the first operational amplifier is also connected to the input terminal of the first operational amplifier through a fourth resistor; the output terminal of the first operational amplifier is connected to the output terminal of the operation unit.

3. The analog computer chip according to claim 2, characterized in that: The first resistor, the second resistor, the third resistor and the fourth resistor are all adjustable resistors; or, the first resistor and the fourth resistor are adjustable resistors; or, the second resistor and the third resistor are adjustable resistors.

4. The analog computer chip according to claim 3, characterized in that: The resistance value of the first resistor is equal to the resistance value of the fourth resistor; the resistance value of the second resistor is equal to the resistance value of the third resistor.

5. The analog computer chip according to claim 4, characterized in that: The transfer function of the arithmetic unit is: Wherein, x is the input value of the transfer function; y is the output value of the transfer function; W is the node parameter, , R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, A11 is the gain of the first operational amplifier; and c is a constant.

6. The analog computer chip according to claim 1, characterized in that: The operation unit includes a fifth resistor, a sixth resistor and a second operational amplifier; The non-inverting input terminal of the second operational amplifier is grounded through the fifth resistor; the non-inverting input terminal of the second operational amplifier is also connected to the first voltage terminal through the sixth resistor; the inverting input terminal of the second operational amplifier is connected to the input terminal of the operation unit; and the output terminal of the second operational amplifier is connected to the output terminal of the operation unit.

7. The analog computer chip according to claim 6, characterized in that: At least one of the fifth resistor and the sixth resistor is an adjustable resistor.

8. The analog computer chip according to claim 7, characterized in that: The transfer function of the arithmetic unit is: Wherein, x is the input value of the transfer function; y is the output value of the transfer function; B is the node parameter, , R5 is the resistance value of the fifth resistor, R6 is the resistance value of the sixth resistor, A22 is the gain of the second operational amplifier; and c is a constant.

9. A regulating circuit, characterized in that: The regulating circuit is used to regulate the analog computer chip as claimed in any one of claims 1 to 8; The regulating circuit includes an input terminal, a digital-to-analog conversion module and a decoding module; The input end is used to receive model parameters, and generate model parameter data from the model parameters through a digital-to-analog conversion module; the model parameter data is used to adjust the node parameters of the computing unit of the analog computer chip; The decoding module is used to receive a parameter address corresponding to a model parameter, and determine a calculation unit corresponding to the model parameter data according to the parameter address.

10. The regulating circuit according to claim 9, characterized in that: The decoding module includes a connection subcircuit, an execution subcircuit and an address subcircuit; The address subcircuit is used to determine the to-be-adjusted operation unit according to the parameter address, and connect the to-be-adjusted operation unit with the execution subcircuit through the connection subcircuit; The execution subcircuit is used to adjust the node parameters of the to-be-adjusted operation unit according to the model parameter data.

11. An application circuit, characterized in that: The application circuit comprises a front-end device, a back-end device and an analog computer chip as claimed in any one of claims 1 to 8; The front-end device is used to generate analog electrical signals and transmit them to the analog computer chip; the analog computer chip is used to process the analog electrical signals and transmit them to the back-end device to realize corresponding functions.

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