Working method for simulating computer chip

Abstract

The invention relates to the technical field of artificial intelligence, and discloses a working method for simulating a computer chip. The method comprises the following steps: receiving training data and a model parameter initial value; the model parameter initial value is used for initializing parameters of the storage arithmetic unit; according to the training data, parameters of the storage arithmetic unit are iteratively updated through the regulator, and when an iteration completion condition is met, a first operation model corresponding to the storage arithmetic unit is generated; and inputting the model input value corresponding to the first target scene into the analog computer chip, and outputting a model output value corresponding to the first target scene through a first operation model in the analog computer chip. According to the scheme, the operation model can be autonomously generated in the analog computer chip, and self-learning updating can be carried out, so that the application range of the working method is enlarged, and the accuracy of the artificial intelligence chip applying the working method is improved.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to a working method for simulating a computer chip. Background Art

[0002] The working method of artificial intelligence chips in the prior art is usually: first, a computing model is generated outside the chip according to the chip design requirements and application scenarios, and then the externally generated computing model is input into the artificial intelligence chip. Since the computing model is trained outside the chip based on data from a specific working scenario, after the computing model is input into the artificial intelligence chip, the artificial intelligence chip can only be applied to a specific working scenario.

[0003] It can be seen from this that the working method of the artificial intelligence chip in the prior art can only be applied to fixed working scenarios, and the calculation model inside the artificial intelligence chip using this working method cannot be self-learned and updated, which leads to a narrow application scope of the working method and low accuracy of the artificial intelligence chip using this working method. Summary of the invention

[0004] In view of this, the present invention provides a working method for simulating a computer chip to increase the applicable scope of the working method of an artificial intelligence chip.

[0005] In a first aspect, the present invention provides a working method of an analog computer chip, the method being executed by the analog computer chip, wherein the analog computer chip is provided with a storage operator and a regulator; the topological structure of the storage operator is the same as the topological structure of a target neural network model, and the method comprises: Receiving training data and initial values ​​of model parameters; the initial values ​​of model parameters are used to initialize parameters of the storage operator; Iteratively updating the parameters of the storage operator through the regulator according to the training data, and generating a first operation model corresponding to the storage operator when an iteration completion condition is met; The model input value corresponding to the first target scene is input into the simulation computer chip, and the model output value corresponding to the first target scene is output through the first computing model in the simulation computer chip.

[0006] In a possible implementation, the iterative updating of the parameters of the storage operator by the regulator according to the training data includes: Processing the sample input values ​​in the training data by the storage operator to obtain actual output values; If the first error value between the actual output value and the expected output value in the training data does not satisfy the iteration completion condition, the parameters of the storage operator are iteratively updated through the regulator according to the actual output value and the expected output value in the training data.

[0007] In a possible implementation, the iteration completion condition is that the first error value is less than an error threshold.

[0008] In a possible implementation, when the number of the actual output values ​​is greater than 1; The method further comprises: Obtain the error between each actual output value and the corresponding expected output value; The average of the errors between the actual output values ​​and the corresponding expected output values ​​is determined as the first error value.

[0009] In a possible implementation, in the storage operator, the input end is connected to the output end through n layers of memory and n layers of operators; two adjacent layers of operators are connected through a layer of memory; the transfer function of the memory corresponds to the parameter of the memory; The iterative updating of the parameters of the storage operator by a regulator according to the actual output value and the expected output value in the training data comprises: According to the actual output value and the expected output value in the training data, the parameters of each memory in the nth layer of the storage operator are adjusted by the regulator; According to the expected output values ​​in the memories and training data of the nth layer after the parameters are updated, the corresponding operation update values ​​of the operators in the n-1th layer are obtained through the regulator, and the operation update values ​​are used as the expected output values ​​of the operators in the n-1th layer; According to the actual output value and expected output value of each operator in the q-1th layer, the parameters of each memory in the q-1th layer of the storage operator are adjusted by the regulator; According to the various memories of the q-1th layer and the various expected output values ​​of the q-1th layer after the updated parameters, the corresponding operation update values ​​of the operators in the q-2th layer are obtained through the regulator, and the operation update values ​​are used as the expected output values ​​of the operators in the q-2th layer, where n≥q≥3.

[0010] In a possible implementation, the method further includes: According to the actual output value and expected output value of the first layer operator, the parameters of each memory of the first layer in the storage operator are adjusted by the regulator.

[0011] In a possible implementation manner, the parameter of the memory is related to the floating gate charge of the MOS tube of the non-volatile memory unit in the memory.

[0012] In a possible implementation, the method further includes: When an expected output value corresponding to the model input value and a model adjustment level signal are received through the expected output value input pin, the first operation model is adjusted according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value and the received model adjustment level signal to obtain a second operation model.

[0013] In a possible implementation, adjusting the first operation model according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal to obtain the second operation model includes: When the model adjustment level signal is received and the target memory is updated, a memory parameter value of the target memory is obtained, and a parameter update value of the target memory is obtained according to an actual output value corresponding to the model input value and an expected output value corresponding to the model input value; If the difference between the memory parameter value and the parameter update value is greater than an update threshold, the parameter of the target memory is updated by the regulator.

[0014] In a possible implementation, the method further includes: When the simulation computer chip is applied to a second target scene, the simulation computer chip obtains the first training set and the first parameter initial value; the first training set is the training data corresponding to the second target scene; the first parameter initial value is the model parameter initial value corresponding to the second target scene; Initialize the parameters of the storage operator according to the first parameter initial value; Iteratively updating the parameters of the storage operator according to the first training set, and generating a third operation model corresponding to the storage operator when an iteration completion condition is met; The model input value corresponding to the second target scene is input into the simulation computer chip, and the model output value corresponding to the second target scene is output through the third computing model in the simulation computer chip.

[0015] In a possible implementation, the method further includes: When the simulation computer chip is applied to a third target scene, the simulation computer chip acquires the second training set; the second training set is training data corresponding to the third target scene; Iteratively updating the parameters of the storage operator in the first operation model according to the second training set, and generating a fourth operation model when an iteration completion condition is met; The model input value corresponding to the third target scene is input into the simulation computer chip, and the model output value corresponding to the third target scene is output through the fourth computing model in the simulation computer chip.

[0016] In another aspect, a working method of an analog computer chip is provided, wherein the analog computer chip is provided with a storage operator and a regulator; the topological structure of the storage operator is the same as the topological structure of a target neural network model; the target neural network model is generated in a computer device; the method comprises: Acquire training data and initial values ​​of model parameters; the initial values ​​of model parameters are used to initialize the target neural network model; Training the target neural network model using the training data; The parameters of each memory in the storage operator are set according to the trained target neural network model to obtain a first operation model in the simulated computer chip; The model input value corresponding to the first target scene is input into the simulation computer chip, and the model output value corresponding to the first target scene is output by the simulation computer chip through the first computing model.

[0017] In a possible implementation, the parameters of each memory in the storage operator are set according to the trained target neural network model to obtain a first operation model in the simulated computer chip, including: The model parameters of the target neural network model are input into the regulator of the analog computer chip through the model parameter initial value input pin of the analog computer chip, so that the regulator adjusts the parameters of the corresponding memories according to the model parameters of the target neural network model.

[0018] In a possible implementation manner, the parameter of the memory is related to the floating gate charge of the MOS tube of the non-volatile memory unit in the memory.

[0019] In a possible implementation, the method further includes: When an expected output value corresponding to the model input value and a model adjustment level signal are received through the expected output value input pin, the first operation model is adjusted according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value and the received model adjustment level signal to obtain a second operation model.

[0020] In a possible implementation, adjusting the first operation model according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal to obtain the second operation model includes: When the model adjustment level signal is received and the target memory is updated, a memory parameter value of the target memory is obtained, and a parameter update value of the target memory is obtained according to an actual output value corresponding to the model input value and an expected output value corresponding to the model input value; If the difference between the memory parameter value and the parameter update value is greater than an update threshold, the parameter of the target memory is updated by the regulator in the analog computer chip.

[0021] In a possible implementation, the method further includes: When the simulation computer chip is applied to a second target scene, the simulation computer chip obtains the first training set and the first parameter initial value; the first training set is the training data corresponding to the second target scene; the first parameter initial value is the model parameter initial value corresponding to the second target scene; Initialize the parameters of the storage operator according to the first parameter initial value; Iteratively updating the parameters of the storage operator according to the first training set, and generating a third operation model corresponding to the storage operator when an iteration completion condition is met; The model input value corresponding to the second target scene is input into the simulation computer chip, and the model output value corresponding to the second target scene is output through the third computing model in the simulation computer chip.

[0022] In a possible implementation, the method further includes: When the simulation computer chip is applied to a third target scene, the simulation computer chip acquires the second training set; the second training set is training data corresponding to the third target scene; Iteratively updating the parameters of the storage operator in the first operation model according to the second training set, and generating a fourth operation model when an iteration completion condition is met; The model input value corresponding to the third target scene is input into the simulation computer chip, and the model output value corresponding to the third target scene is output through the fourth computing model in the simulation computer chip.

[0023] On the other hand, an analog computer chip is provided, wherein a storage operator and a regulator are provided in the analog computer chip; the analog computer chip is used to execute the working method of the analog computer chip mentioned above.

[0024] On the other hand, a computer device is provided, wherein a processing unit and a storage unit are provided on the computer device, wherein the storage unit stores computer instructions, and the processing unit is used to execute the computer instructions to perform the above-mentioned working method of simulating a computer chip.

[0025] In summary, the present application provides two working methods for simulating computer chips. Both of these working methods can autonomously generate a computing model inside the simulated computer chip and can perform self-learning and updating, thereby increasing the application scope of the two working methods and improving the accuracy of the artificial intelligence chip using the two working methods. In the working method of the first analog computer chip provided in the present application, the first operation model is generated by autonomous chip training. Since the internal circuits (regulator and storage operator) of the analog computer chip in the present application are all composed of analog devices, the training performed by using analog devices inside the chip in the present application is faster and consumes less energy than the training performed by using digital operation units such as graphics cards in the host computer. Therefore, this method is suitable for small batch customized analog computer chips; In the second working method of the analog computer chip provided in the present application, according to the application scenario of the analog computer chip, the expected output value and the initial value of the model parameter suitable for the application scenario are input into the host computer, the target neural network model is trained, and then the parameters of each memory in the storage operator are set according to the trained target neural network model, so as to generate a first operation model. At this time, the analog computer chip can be directly used in actual normal operation without first being trained. This method is suitable for analog computer chips that are mass-produced and the initial application scenario of the chip is known; In the working methods of the two analog computer chips provided in the present application, when an operation error occurs in the analog computer chip or the application scenario (target scenario) is changed and the first operation model needs to be adjusted, analog devices are used inside the chip for training to obtain the second operation model, the third operation model and the fourth operation model, thereby speeding up the model adjustment and reducing the energy consumption of the model adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A working method of a simulated computer chip involved in an embodiment of the present application is shown; Figure 2 A network architecture diagram of a simulated computer chip involved in an embodiment of the present application is shown; Figure 3 A specific structural diagram of a storage operator involved in an embodiment of the present application is shown; Figure 4 A specific structural diagram of a memory in a storage operator according to an embodiment of the present application is shown; Figure 5 A schematic diagram of the structure of a first error comparison circuit involved in an embodiment of the present application is shown; Figure 6 A specific structural schematic diagram of a comparison subcircuit involved in an embodiment of the present application is shown; Figure 7 A parameter initial value extraction circuit involved in an embodiment of the present application is shown; Figure 8 The operation update value generating circuit in the embodiment of the present application is shown; Fig. 9 The model adjustment circuit in the embodiment of the present application is shown; Fig.10 Another working method of simulating a computer chip according to an embodiment of the present application is shown; Fig.11 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0029] The present application provides a working method for simulating a computer chip, which can autonomously generate a computing model inside the simulating computer chip and can perform self-learning and updating, thereby expanding the application scope of the working method and improving the accuracy of the artificial intelligence chip using the working method; It should be noted that some of the steps executed by a computer as shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0030] Figure 1 The working method of an analog computer chip involved in the embodiment of the present application is shown, and the method is executed by the analog computer chip, such as Figure 2 As shown, it shows a network architecture diagram of a simulated computer chip involved in an embodiment of the present application. Figure 2As shown, the analog computer chip is provided with a storage operator and a regulator. The analog computer chip can adjust parameters of the storage operator so that the storage operator represents the mapping relationship between specific input data and specific output data. Figure 1 The corresponding working method of the analog computer chip includes: Step 101, receiving training data and initial values ​​of model parameters.

[0031] The model parameter initial values ​​are used to initialize the parameters of the storage operator.

[0032] Specifically, the analog computer chip includes a model parameter initial value input pin, which is connected to a host computer. The host computer inputs the model parameter initial value into the analog computer chip, and the model parameter initial value is input into a regulator of the chip. The model parameter initial value initializes the parameters of the storage operator through the regulator, so that each transfer function in the storage operator is set according to the initial value of each model parameter.

[0033] Optionally, the initial value of the model parameter may be a random value; or, the initial value of the model parameter may be manually set by a research and development personnel according to an application scenario of the simulated computer chip.

[0034] When the analog computer chip is in normal use, the input pin of the model parameter initial value is left floating or connected to a specific voltage value, so that the model parameter initial value does not participate in the normal operation of the analog computer chip.

[0035] Please refer to Figure 3 , which shows a specific structural diagram of a storage operator involved in an embodiment of the present application. Figure 3 As shown, in the storage operator, the input end is connected to the output end through n layers of memory and n layers of operators; two adjacent layers of operators are connected through a layer of memory; and the transfer function of the memory corresponds to the parameters of the memory.

[0036] Specifically, the first layer in the storage operator is the input node (for example, including input 1, input 2, input 3 and other input nodes), and the last layer is the output node (for example, including output 1, output 2, output 3 and other output nodes). Taking the normal working process of the simulated computer chip as an example, the input node is used to receive the model input value. At this time, the model input value passes through several memories in the first layer and reaches several operators in the first layer (for example, including operator 11, operator 12, operator 13), and then passes through several memories in the second layer and reaches several operators in the second layer. And so on, after passing through n layers of memories and operators, the model output value is output through each output node.

[0037] In the embodiments of the present application, Figure 3Each memory in the multi-layer memory is used to fit different transfer functions, so that the storage operator composed of multi-layer memories and multi-layer operators can characterize the mapping relationship between specific input data and specific output data. Figure 3 Each operator in the system is used to accumulate the output voltages of each memory connected thereto and then output them. Optionally, the operator may be an adder composed of analog devices.

[0038] Figure 4 The specific structure diagram of the memory in the storage operator in the embodiment of the present application is shown. Figure 4 As shown, VIN is the input voltage of the memory, the input voltage VIN is the independent variable x of the transfer function corresponding to the memory, VOUT is the output voltage of the memory, the output voltage VOUT is input into the corresponding operator of the same layer, the output voltage VOUT is used as the dependent variable y of the transfer function, VR is the first fixed voltage input to the memory, the first fixed voltage VR is the constant c of the function, the memory is composed of an operational amplifier with a non-infinite gain, and the gain of the operational amplifier can be obtained by calculation or measurement. It can be seen that when the resistance value of the first resistor R1 is equal to the resistance value of the fourth resistor R4, the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3, and when the gain of the first operational amplifier A1 is represented by A11, Figure 3 The memory structure shown in , that is, at this time, After being expressed by W, the transfer function corresponding to the memory is ; Furthermore, a non-volatile memory unit is used as a resistor, that is, the first resistor R1 and the fourth resistor R4, or the second resistor R2 and the third resistor R3 are all composed of non-volatile memory units. At this time, the parameters of the memory are related to the floating gate charge of the MOS tube of the non-volatile memory unit in the memory. By adjusting the storage data of the non-volatile memory unit (such as the floating gate charge of the MOS tube of the non-volatile memory unit), its resistance value can be changed, thereby adjusting the parameters of the memory to obtain the transfer function required by the memory.

[0039] Therefore, when the initial value of the model parameter is input into the regulator, the regulator adjusts the floating gate charge of the MOS tube of the non-volatile storage unit, thereby changing the corresponding resistance value, so that each memory can be represented by the transfer function corresponding to the initial value of the model parameter.

[0040] Step 102, based on the training data, the parameters of the storage operator are iteratively updated by the regulator, and when the iteration completion condition is met, a first operation model corresponding to the storage operator is generated.

[0041] In the embodiment of the present application, the training data includes sample input values ​​and expected output values.

[0042] Furthermore, the analog computer chip includes a model input value input pin and an expected output value input pin. Both the model input value input pin and the expected output value input pin are connected to a host computer; during the parameter update process of the analog computer chip, the host computer inputs a sample input value through the model input value input pin, and the host computer inputs an expected output value through the expected output value input pin; When the analog computer chip is in normal use, the expected output value input pin is left floating or connected to a specific voltage value, so that the expected output value does not participate in the normal operation of the analog computer chip; and the model input value input pin is used to connect the input value during normal operation to perform data processing on the input value during normal operation.

[0043] The following is a detailed description of the parameter update process of the simulated computer chip: The parameter update process of the analog computer chip mainly involves the iterative update of the parameters of the storage operator. Specifically, the analog computer chip processes the sample input value in the training data through the storage operator to obtain the actual output value; if the first error value between the actual output value and the expected output value in the training data does not meet the iteration completion condition (optionally, the iteration completion condition is that the first error value is less than the error threshold), then according to the actual output value and the expected output value in the training data, the parameters of the storage operator are iteratively updated through the regulator.

[0044] That is, during the iterative update process of the storage operator, the analog computer chip will determine whether the iteration meets the iteration completion condition. If the first error value is less than the preset error threshold, it means that the iteration completion condition is met, and the storage operator after parameter update can be implemented as the first operation model. If the first error value is greater than or equal to the error threshold, it is necessary to continue to iterate and update the parameters of the storage operator.

[0045] Specifically, a first error comparison circuit is provided in the regulator, and the first error comparison circuit calculates a first error value between an actual output value and an expected output value.

[0046] When the number of the actual output values ​​is greater than 1, the average of the errors between the actual output values ​​and the corresponding expected output values ​​is determined as the first error value.

[0047] Please refer to Figure 5 , which shows a schematic diagram of the structure of the first error comparison circuit involved in the embodiment of the present application. Figure 5As shown, the first error comparison circuit includes a plurality of comparison sub-circuits and a comparison resistor corresponding to each comparison sub-circuit (for example, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7), and the output end of each comparison sub-circuit is connected to the non-inverting input end of the second operational amplifier A2 through the corresponding comparison resistor; the second operational amplifier A2 forms a follower structure; the output end of the second operational amplifier A2 is connected to the non-inverting input end of the third operational amplifier A3; and the inverting input end of the third operational amplifier is connected to the error threshold voltage VPD.

[0048] Furthermore, the number of comparison subcircuits is the same as the number of output nodes of the storage operator; the first input terminal of each comparison subcircuit is respectively connected to the actual output value of the output node of the storage operator; The expected output value input terminal of the analog computer chip transmits the expected output value to the second input terminal of each comparison subcircuit of the first error comparator respectively, and each expected output value corresponds to the actual output value one by one.

[0049] Please refer to Figure 6 , which shows a specific structural diagram of a comparison subcircuit involved in an embodiment of the present application. Figure 6 As shown, for a comparison sub-circuit, the non-inverting input terminal of the fourth operational amplifier is the second input terminal of the comparison sub-circuit, which is used to access the expected output value; the inverting input terminal of the fourth operational amplifier is the first input terminal of the comparison sub-circuit, which is used to access the actual output value; the output terminal of the fourth operational amplifier is connected to the first terminal of the first switch S1; the output terminal of the fourth operational amplifier is also connected to the second terminal of the second switch S2 through the first inverter F1; and the output terminal of the fourth operational amplifier is also connected to the non-inverting input terminal of the fifth operational amplifier; the inverting input terminal of the fifth operational amplifier is grounded; the output terminal of the fifth operational amplifier is used to control the working state of the first switch S1.

[0050] Specifically, the output value of the fourth operational amplifier A4 is the difference between the expected output value and the actual output value. When the difference is greater than or equal to 0, the fifth operational amplifier A5 outputs a high level, the first switch S1 is directly connected to the output end of the fourth operational amplifier A4, and the comparison subcircuit outputs the difference. When the difference is less than 0, the fifth operational amplifier A5 outputs a low level, the first switch S1 is connected to the output end of the fourth operational amplifier A4 through the first inverter F1, and the comparison subcircuit outputs the opposite value of the difference. Therefore, the output value of the comparison subcircuit is the error between the expected output value and the actual output value. At the same time, the error output by the comparison subcircuit is always a positive voltage value, thereby ensuring the correctness of subsequent logic.

[0051] At this time, the output values ​​of each comparison sub-circuit (for example, VP1, VP2, ..., VPi) obtain the error average value VPS (i.e., the voltage value corresponding to the first error value) between each expected output value and the corresponding actual output value through the first error comparison circuit, and the error average value VPS is a positive voltage value. At this time, the error average value VPS is compared with the error threshold voltage VPD (i.e., the voltage value corresponding to the error threshold). When the error average value VPS is less than the error threshold voltage VPD, the third operational amplifier A3 outputs a low level and the regulator stops working. When the error average value VPS is greater than or equal to the error threshold voltage VPD, the third operational amplifier A3 outputs a high level and the regulator continues to work.

[0052] When the regulator continues to work, that is, according to the actual output value and the expected output value in the training data, the regulator iteratively updates the parameters of the storage operator, for each memory of the nth layer, the regulator can adjust the parameters of each memory of the nth layer in the storage operator according to the actual output value and the expected output value in the training data; Specifically, assume that the expected output values ​​in the training data are , , … , the actual output values ​​of the operators in the nth layer (that is, the actual output values ​​of each output node) are , … , so the error EL between the expected output value and the actual output value can be expressed as: At this time, according to the specific structure of the memory of the present application, the actual output value of the a-th operator in the n-th layer is , so we can get the error , at this time, the parameter of the first memory of the nth layer The following calculation method is explained. Specifically, except The initial values ​​of other parameters except for EL are substituted into the error EL. After that, Substitute the initial value of the parameter into the derived formula, and finally get The corresponding derivative value Similarly, the derivative values ​​corresponding to other W parameters are obtained in turn. At the same time, in order to take into account both training speed and training accuracy, it is also necessary to set the correction coefficient , the correction factor is a constant, so at this time, the parameter of the first memory of the nth layer can be obtained Corresponding correction value ; From the above analysis, we can see that except The initial values ​​of other parameters except for EL are substituted into the error EL. After taking the derivative, we can get , where i is a known fixed value when designing the circuit, for The input of the first memory of the nth layer corresponding to the parameter, is the value of the first fixed voltage VR, is the expected output value of the operator in the nth layer corresponding to the first memory in the nth layer, is the sum of the outputs of all memories connected to the corresponding operator in the nth layer except the first memory in the nth layer, is the initial value of the parameter of the first memory of the nth layer; therefore, the correction value can be obtained ; like Figure 7 As shown, it shows a parameter initial value extraction circuit involved in an embodiment of the present application. In an analog computer chip, each memory corresponds to a parameter initial value extraction circuit, wherein the sixth operational amplifier A6 in the parameter initial value extraction circuit has the same parameters as the first operational amplifier A1 in the memory, and the gain is A11, and the in-phase input terminal of the sixth operational amplifier A6 is connected to the second fixed voltage VR1 through the second resistor R2; the in-phase input terminal of the sixth operational amplifier A6 is grounded through the first resistor R1; the inverting input terminal of the sixth operational amplifier A6 is connected to the first fixed voltage VR through the third resistor R3; the inverting input terminal of the sixth operational amplifier A6 is connected to the output terminal of the sixth operational amplifier A6 through the fourth resistor R4, the resistance parameters and resistance settings in the parameter initial value extraction circuit and the memory and the parameters of the first fixed voltage VR are also the same, and the second fixed voltage VR1 of the parameter initial value extraction circuit is VR+1, so at this time, it can be obtained that the voltage value outputted from the output terminal of the parameter initial value extraction circuit is , it can be seen that the voltage value VW outputted by the output terminal of the parameter initial value extraction circuit is the voltage value corresponding to the parameter initial value W of the memory; Therefore, a correction value generating circuit is provided in the regulator (the correction value generating circuit can generate a correction value according to the correction value The correction value generating circuit obtains the correction value of the transfer function according to the actual output value and the expected output value, and the parameter initial value extracting circuit extracts the parameter initial value of the transfer function. At this time, the regulator subtracts the correction value from the parameter initial value through the subtraction circuit to obtain the parameter update value. The regulator adjusts the floating gate charge of the MOS tube of the corresponding non-volatile storage unit according to the parameter update value, thereby adjusting the parameter of the first memory of the nth layer in the storage operator; Afterwards, the same circuit and method can be used to adjust the parameters of each memory of the nth layer in the storage operator through the regulator; In addition, the regulator will also obtain the corresponding operation update values ​​of each operator in the n-1 layer according to the expected output values ​​in each memory and training data of the n-1 layer after the parameter update, and use the operation update values ​​as the expected output values ​​of the operators in the n-1 layer; Specifically, each operator in the n-1th layer corresponds to m memories (where m is the same as the number of operators in the nth layer). All the operation update values ​​calculated by the m memories need to be added up and then divided by m. The average value obtained is the corresponding operation update value of each operator in the n-1th layer. For example, Figure 3 As shown, assuming that the number of operators in each layer is 3 and there are 2 layers of operators, after the memory parameters of the second layer are updated, the expected output value of operator 21 is , at this time, the ones that have not yet been updated will be and Substitute the value of into the above formula to obtain the first operation update value of the first layer operator 11 Similarly, the second operation update value of the first layer operator 11 is obtained according to the expected output value of the operator 22 and the operator 23. and the third operation update value of the first layer operator 11 Finally, we can get the updated value of the operation of the first layer operator 11 ; Then, the same method is used to obtain the calculation update value of the first layer operator 12 and the calculation update value of the first layer operator 13 , and, and as the expected output values ​​of the first layer operator 11, operator 12 and operator 13 respectively; It can be seen that the calculation method of the expected input voltage of the memory between the operator 11 and the operator 21 (i.e., the voltage value corresponding to the first operation update value of the first layer operator 11) is: first, the expected output value of the operator 21 is subtracted from the output value of the memory after the parameters are updated between the operator 12 and the operator 21, and then the output value of the memory after the parameters are updated between the operator 13 and the operator 21 is subtracted, thereby obtaining the output value of the memory after the parameters are updated between the operator 11 and the operator 21, and then the formula is used. It can be seen that the first operation update value of the first layer operator 11 is That is ,in, is the parameter after the memory between the operator 11 and the operator 21 is updated, and y is the output value of the memory after the parameter between the operator 11 and the operator 21 is updated; therefore, according to this method, the operation update value generating circuit in the present application can be obtained, such as Figure 8 As shown, the divider A9 is included; like Figure 8 As shown, and is the output voltage of the n-th layer memory connected to the n-th layer target operator, but after the parameters of other memories except the n-th layer target memory are updated. At this time, Figure 8 The operation update value generating circuit shown is used to obtain the operation update value corresponding to the n-th layer target operator.

[0053] Likewise Figure 3 For example, suppose the target operator is Figure 3 The target memory is the memory between the operator 11 and the operator 21. Updated parameters for target memory The corresponding voltage value, where the target memory is updated with the parameter The corresponding voltage value The circuit structure of the acquisition circuit reference parameter initial value extraction circuit, the output voltage VY1 of the tenth operational amplifier A10 is the first operation update value of the first layer operator 11 The corresponding voltage value; Similarly, the second operation update value of the first layer operator 11 can be obtained by using the same operation update value generation circuit. The corresponding voltage value and the third operation update value of the first layer operator 11 The corresponding voltage value; Therefore, at this time, m operation update value generating circuits and the addition averaging circuit are used to form an expected output value generating circuit of the n-1th layer, wherein the voltage values ​​obtained by the m operation update value generating circuits are input into the addition averaging circuit, and the addition averaging circuit can obtain the operation update value of an operator in the n-1th layer. For example, the first operation update value of the operator 11 is The corresponding voltage value, the second calculation update value of the operator 11 The corresponding voltage value and the third calculation update value of the operator 11 After the corresponding voltage value is input into the addition averaging circuit, the calculation update value of the operator 11 is ; This operation updates the value It can be used as the expected output value of the operator 11; It can be seen that by setting the same number of expected output value generation circuits as the number of operators in the n-1th layer, the expected output value of each operator in the n-1th layer can be obtained; wherein the number of operation update value generation circuits included in each expected output value generation circuit is the same as the number of operators in the nth layer; Similarly, according to the actual output value and expected output value of each operator in the q-1th layer, the parameters of each memory in the q-1th layer of the storage operator are adjusted by the regulator; According to the various memories of the q-1th layer and the various expected output values ​​of the q-1th layer after the updated parameters, the corresponding operation update values ​​of the operators in the q-2th layer are obtained through the regulator, and the operation update values ​​are used as the expected output values ​​of the operators in the q-2th layer, where n≥q≥3.

[0054] Similarly, for the parameter update process of the first layer memory, the analog computer chip can still adjust the parameters of each memory of the first layer in the storage operator through the regulator according to the actual output value and expected output value of the first layer operator.

[0055] The logic of the above memory parameter adjustment process and the expected output value acquisition process of each operator are similar and will not be repeated here.

[0056] When the regulator adjusts the parameters of each memory in the first layer of the storage operator according to the actual output value and expected output value of the first layer operator, it can be considered that the storage operator completes a self-learning update process of the operation model, that is, completes an iteration process.

[0057] At this time, after completing one iteration process, the simulated computer chip will continue to use sample input values ​​and expected output values ​​that have not been used in the training data for model training until the first error value between the actual output value and the expected output value of the n-th layer operator is less than the preset error threshold, thereby generating a first operation model.

[0058] Step 103: input the model input value corresponding to the first target scene into the simulation computer chip, and output the model output value corresponding to the first target scene through the first computing model in the simulation computer chip.

[0059] After the first computing model is generated, it can be considered that the simulation computer chip has met the conditions for entering a normal working state. At this time, if the model input value that meets the application scenario (that is, the model input value corresponding to the first target scenario) is directly input into the simulation computer chip, the first computing model in the simulation computer chip can calculate the model input value corresponding to the first target scenario, thereby outputting the model output value corresponding to the first target scenario.

[0060] Furthermore, when the actual output value has a large deviation in the current application scenario, the host computer can input the expected output value corresponding to the model input value into the analog computer chip through the expected output value input pin, and input the model adjustment level signal at the same time; Correspondingly, when the analog computer chip receives the expected output value corresponding to the model input value and the model adjustment level signal through the expected output value input pin, the first operation model is adjusted by the regulator according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value and the received model adjustment level signal to obtain the second operation model.

[0061] When the actual output value deviates greatly in the current application scenario, the regulator adjusts the parameters of each memory in each layer of the storage operator according to the actual output value and the expected output value input by the host computer, thereby self-learning and updating to obtain the second operation model.

[0062] Specifically, when the model adjustment level signal is received and the target memory is updated, a memory parameter value of the target memory is obtained, and a parameter update value of the target memory is obtained according to an actual output value corresponding to the model input value and an expected output value corresponding to the model input value; If the difference between the memory parameter value and the parameter update value is greater than the update threshold, the parameter of the target memory is updated by the regulator.

[0063] Specifically, the regulator also includes Fig. 9 The steps of obtaining the second operation model in the model adjustment circuit shown are basically the same as the steps of obtaining the first operation model. However, the difference between the two is that when obtaining the second operation model, the host computer also inputs a model adjustment level signal into the analog computer chip through the expected output value input pin, and the model adjustment level signal is input into the control end of the second switch S2 of the model adjustment circuit, and the second switch S2 is turned on, and Fig. 9 VW in is the memory parameter value of the target memory, and is the parameter update value of the target memory. When the difference between the memory parameter value and the parameter update value is greater than the update threshold value VT, the output voltage VL of the model adjustment circuit is at a high level. At this time, the regulator updates the parameters of the target memory. If the difference between the memory parameter value and the parameter update value is less than the update threshold value VT, the regulator does not update the parameters of the target memory, and the target memory still retains the initial parameters.

[0064] From the above analysis, it can be seen that after the model adjustment circuit is set in the regulator, when the first operation model is generated, the second switch S2 is in the off state, and the model adjustment circuit does not affect the generation of the first operation model; when the second operation model is generated, the second switch S2 is in the on state, and the model adjustment circuit starts to work. At this time, if the difference between the parameter update value and the corresponding memory parameter value is small, it means that the memory parameter value of the target memory is within an acceptable error range, and when the difference between the parameter update value and the corresponding memory parameter value is large, it means that the memory parameter value of the target memory is outside the error range and needs to be adjusted. It can be seen that when generating the second operation model, the first operation model should be modified as little as possible, because the first operation model is trained by a number of data, and the entire first operation model cannot be adjusted on a large scale because of the current model input value, thereby improving the stability and reliability of the operation model.

[0065] When the analog computer chip is applied to other application scenarios, the expected output value and the initial value of the model parameter suitable for the application scenario are input through the expected output value input pin and the model parameter initial value input pin according to the new application scenario of the analog computer chip, and the third operation model is obtained by retraining or further training according to the above training steps.

[0066] Specifically, when the simulated computer chip is applied to the second target scene, and the similarity between the second target scene and the first target scene is small (for example, less than a similarity threshold), a first training set and a first parameter initial value are obtained; the first training set is training data corresponding to the second target scene; the first parameter initial value is an initial value of a model parameter corresponding to the second target scene; Initialize the parameters of the storage operator according to the first parameter initial value; Iteratively update the parameters of the storage operator according to the first training set, and when an iteration completion condition is met, generate a third operation model corresponding to the storage operator; Then, the model input value corresponding to the second target scene can be input into the simulation computer chip, and the model output value corresponding to the second target scene can be output through the third computing model in the simulation computer chip.

[0067] Among them, the initialization process and iterative update process of the storage operator are similar to the generation process of the first operation model, and will not be repeated here.

[0068] Through the above scheme, when the simulated computer chip needs to be applied in a second target scenario that is significantly different from the first target scenario, the third operation model can be retrained.

[0069] Specifically, when the simulated computer chip is applied to the third target scene, and the third target scene has a large similarity to the first target scene (for example, greater than or equal to a similarity threshold), the second training set is obtained; the second training set is training data corresponding to the third target scene; Iteratively update the parameters of the storage operator in the first operation model according to the second training set, and generate a fourth operation model corresponding to the storage operator when an iteration completion condition is met; At this time, the model input value corresponding to the third target scene is input into the simulation computer chip, that is, the model output value corresponding to the third target scene can be output through the fourth computing model in the simulation computer chip.

[0070] Among them, the iterative update process of the storage operator is similar to the iterative update process of the second operation model, and will not be repeated here.

[0071] Through the above scheme, when the simulated computer chip needs to be applied in a scenario that is similar to the first target scenario but different (such as the third target scenario), the fourth computing model can be obtained by directly training with the second training set of the third target scenario based on the first computing model. The fourth computing model can be directly applied to data processing of the third target scenario.

[0072] In summary, in the working method of the analog computer chip provided in the present application, the chip is used for autonomous training to generate a first computing model. Since the internal circuits (regulators and storage operators) of the analog computer chip in the present application are all composed of analog devices, the training performed by analog devices inside the chip in the present application is faster and consumes less energy than the training performed by digital computing units such as graphics cards in the host computer. Therefore, this method is suitable for small batch customized analog computer chips. When an analog computer chip has a computing error or changes the application scenario, and the first computing model needs to be adjusted, analog devices are used inside the chip for training to obtain the second computing model, the third computing model, and the fourth computing model, thereby speeding up the model adjustment and reducing the energy consumption of the model adjustment.

[0073] Fig.10 Another working method of an analog computer chip involved in an embodiment of the present application is shown, in which a storage operator and a regulator are provided; the topological structure of the storage operator is the same as the topological structure of the target neural network model, and some steps in the method are executed by a computer device, for example, the target neural network model can be generated in the computer device, and the analog computer chip can also have the following structure: Figure 2 The network architecture shown. Fig.10 The corresponding working method of the analog computer chip includes: Step 1001, obtain training data and initial values ​​of model parameters; the initial values ​​of model parameters are used to initialize the target neural network model.

[0074] Specifically, in an embodiment of the present application, the computer device first obtains the training data and initial values ​​of the model parameters required by the target neural network model. The initial values ​​of the model parameters are used to initialize the target neural network model, and the training data is used to train the initialized target neural network model.

[0075] Step 1002: training the target neural network model using the training data.

[0076] In an embodiment of the present application, the computer device can directly input the sample input value in the training data into the target neural network model, and then compare the actual output value of the target neural network model with the expected output value in the training data to obtain a first error value between the actual output value and the expected output value in the training data; when the first error value is less than the error threshold, the training is completed; if the first error value is greater than or equal to the error threshold, the target neural network model is updated according to the first error value.

[0077] Step 1003, setting the parameters of each memory in the storage operator according to the trained target neural network model to obtain the first operation model in the simulated computer chip.

[0078] Optionally, after the training of the target neural network model is completed, the model parameters of the target neural network model can be input into the regulator of the analog computer chip through the model parameter initial value input pin of the analog computer chip, so that the regulator adjusts the parameters of each corresponding memory according to the model parameters of the target neural network model, thereby obtaining the first computing model in the analog computer chip.

[0079] Optionally, in an embodiment of the present application, the parameters of the memory are related to the floating gate charge of the MOS tube of the non-volatile storage unit in the memory, so the regulator can adjust the floating gate charge of the MOS tube of the corresponding non-volatile storage unit according to various parameters, thereby adjusting the parameters of each memory in each layer of the storage operator.

[0080] Step 1004: input the model input value corresponding to the first target scene into the simulation computer chip, and obtain the model output value corresponding to the first target scene output by the simulation computer chip through the first computing model.

[0081] Furthermore, when an expected output value corresponding to the model input value and a model adjustment level signal are received through the expected output value input pin, the first operation model is adjusted according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value and the received model adjustment level signal to obtain a second operation model.

[0082] Optionally, when the model adjustment level signal is received and the target memory is updated, the memory parameter value of the target memory is obtained, and the parameter update value of the target memory is obtained based on the actual output value corresponding to the model input value and the expected output value corresponding to the model input value.

[0083] and Figure 1 The corresponding embodiments are similar. When the actual output value deviates greatly in the current application scenario, the upper computer can input the expected output value corresponding to the model input value into the analog computer chip through the expected output value input pin, and input the model adjustment level signal at the same time, so as to adjust the parameters of each memory in each layer of the storage operator, so that the first operation model can be self-learned and updated to the second operation model.

[0084] Likewise with Figure 1 The corresponding embodiment is similar. During the self-learning update process of the first operation model, when the difference between the memory parameter value and the parameter update value is less than or equal to the update threshold, the parameter of the target memory is within an acceptable error range and is not updated as much as possible. If the difference between the memory parameter value and the parameter update value is greater than the update threshold, the parameter of the target memory is outside the error range and needs to be adjusted.

[0085] When the analog computer chip is applied to other application scenarios, the expected output value and the model parameter initial value suitable for the application scenario are input through the expected output value input pin and the model parameter initial value input pin according to the new application scenario of the analog computer chip. Figure 1 The training step of the corresponding embodiment retrains or further trains to obtain the third operation model or the fourth operation model.

[0086] and Figure 1 The corresponding embodiments are similar. Specifically, when the simulated computer chip is applied to the second target scene, and the similarity between the second target scene and the first target scene is small (for example, less than a similarity threshold), a first training set and a first parameter initial value are obtained; the first training set is training data corresponding to the second target scene; the first parameter initial value is a model parameter initial value corresponding to the second target scene; Initialize the parameters of the storage operator in the first operation model according to the initial values ​​of the model parameters; Iteratively updating the parameters of the storage operator according to the first training set, and generating a third operation model when an iteration completion condition is met; At this time, the model input value corresponding to the second target scene is input into the simulation computer chip, and the model output value corresponding to the second target scene can be output through the third computing model in the simulation computer chip.

[0087] Through the above scheme, when the simulated computer chip needs to be applied in a second target scenario that is significantly different from the first target scenario, the third operation model can be directly obtained by retraining the analog devices inside the simulated computer chip.

[0088] Specifically, when the simulated computer chip is applied to the third target scene, and the third target scene has a large similarity to the first target scene (for example, greater than or equal to a similarity threshold), the second training set is obtained; the second training set is training data corresponding to the third target scene; Iteratively update the parameters of the storage operator in the first operation model according to the second training set, and generate a fourth operation model when an iteration completion condition is met; At this time, the model input value corresponding to the third target scene is input into the simulation computer chip, and the model output value corresponding to the third target scene is output through the fourth computing model in the simulation computer chip.

[0089] Among them, the iterative update process of the storage operator is similar to the iterative update process of the first operation model, which will not be repeated here. Through the above scheme, when the simulated computer chip needs to be applied to a scene similar to the first target scene but different, it can be based on the first operation model, through the second training set of the third target scene, directly trained in the simulated device inside the simulated computer chip, and the fourth operation model can be obtained. The fourth operation model can be directly applied to the data processing of the third target scene.

[0090] To summarize, the working method of the analog computer chip provided in the present application, according to the application scenario of the analog computer chip, inputs the expected output value and the initial value of the model parameter suitable for the application scenario into the upper computer, trains the target neural network model, and then sets the parameters of each memory in the storage operator according to the trained target neural network model, thereby generating a first operation model in the analog computer chip. At this time, the analog computer chip can be directly used in actual normal work without first being trained. This method is suitable for analog computer chips that are mass-produced and have known initial application scenarios of the chip. When an operation error occurs in the analog computer chip or the application scenario is changed, and the first operation model needs to be adjusted, analog devices are used inside the chip for training to obtain the second operation model, the third operation model and the fourth operation model, thereby speeding up the model adjustment and reducing the energy consumption of the model adjustment.

[0091] See also Fig.11 , Fig.11 is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, and the computer device can be used to execute the training steps of the artificial intelligence model involved in the above embodiment, such as Fig.11 As shown, the computer device includes: one or more processing units 10, storage unit 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processing unit can process the instructions executed in the computer device, including instructions stored in or on the storage unit to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processing units and / or multiple buses can be used together with multiple storage units and multiple storage units. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processing unit system). Fig. 9 A processing unit 10 is taken as an example.

[0092] The processing unit 10 may be a central processing unit, a network processing unit or a combination thereof. The processing unit 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0093] The storage unit 20 stores instructions that can be executed by at least one processing unit 10, so that the at least one processing unit 10 executes the method shown in the above embodiment.

[0094] The storage unit 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the storage unit 20 may include a high-speed random access storage unit, and may also include a non-transient storage unit, such as at least one disk storage unit component, a flash memory device, or other non-transient solid-state storage unit components. In some optional embodiments, the storage unit 20 may optionally include a storage unit remotely arranged relative to the processing unit 10, and these remote storage units may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0095] The storage unit 20 may include a volatile storage unit, such as a random access storage unit; the storage unit may also include a non-volatile storage unit, such as a flash storage unit, a hard disk or a solid state drive; the storage unit 20 may also include a combination of the above types of storage units.

[0096] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processing unit, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory unit, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above-mentioned types of storage units. It can be understood that a computer, a processing unit, a microprocessor unit controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processing unit, or hardware, the method shown in the above embodiment is implemented.

[0097] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0098] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for simulating the operation of a computer chip, characterized in that: The method is performed by an analog computer chip, wherein a storage operator and a regulator are provided in the analog computer chip; the topological structure of the storage operator is the same as the topological structure of the target neural network model, and the method comprises: Receiving training data and initial values ​​of model parameters; the initial values ​​of model parameters are used to initialize parameters of the storage operator; Iteratively updating the parameters of the storage operator through the regulator according to the training data, and generating a first operation model corresponding to the storage operator when an iteration completion condition is met; The model input value corresponding to the first target scene is input into the simulation computer chip, and the model output value corresponding to the first target scene is output through the first computing model in the simulation computer chip.

2. The method according to claim 1, characterized in that The iterative updating of the parameters of the storage operator by the regulator according to the training data comprises: Processing the sample input values ​​in the training data by the storage operator to obtain actual output values; If the first error value between the actual output value and the expected output value in the training data does not satisfy the iteration completion condition, the parameters of the storage operator are iteratively updated through the regulator according to the actual output value and the expected output value in the training data.

3. The method according to claim 2, characterized in that The iteration completion condition is that the first error value is less than an error threshold.

4. The method according to claim 3, characterized in that When the number of the actual output values ​​is greater than 1; The method further comprises: Obtain the error between each actual output value and the corresponding expected output value; The average of the errors between the actual output values ​​and the corresponding expected output values ​​is determined as the first error value.

5. The method according to claim 3, characterized in that: In the storage operator, the input end is connected to the output end through n layers of memory and n layers of operators; two adjacent layers of operators are connected through one layer of memory; the transfer function of the memory corresponds to the parameters of the memory; The iterative updating of the parameters of the storage operator by a regulator according to the actual output value and the expected output value in the training data comprises: According to the actual output value and the expected output value in the training data, the parameters of each memory in the nth layer of the storage operator are adjusted by the regulator; According to the expected output values ​​in the memories and training data of the nth layer after the parameters are updated, the corresponding operation update values ​​of the operators in the n-1th layer are obtained through the regulator, and the operation update values ​​are used as the expected output values ​​of the operators in the n-1th layer; According to the actual output value and expected output value of each operator in the q-1th layer, the parameters of each memory in the q-1th layer of the storage operator are adjusted by the regulator; According to the various memories of the q-1th layer and the various expected output values ​​of the q-1th layer after the updated parameters, the corresponding operation update values ​​of the operators in the q-2th layer are obtained through the regulator, and the operation update values ​​are used as the expected output values ​​of the operators in the q-2th layer, where n≥q≥3.

6. The method according to claim 5, characterized in that The method further comprises: According to the actual output value and expected output value of the first layer operator, the parameters of each memory of the first layer in the storage operator are adjusted by the regulator.

7. The method according to claim 5, characterized in that The parameters of the memory are related to the floating gate charge of the MOS tube of the non-volatile memory unit in the memory.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: When an expected output value corresponding to the model input value and a model adjustment level signal are received through the expected output value input pin, the first operation model is adjusted according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value and the received model adjustment level signal to obtain a second operation model.

9. The method according to claim 8, characterized in that The step of adjusting the first operation model according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal to obtain the second operation model includes: When the model adjustment level signal is received and the target memory is updated, a memory parameter value of the target memory is obtained, and a parameter update value of the target memory is obtained according to an actual output value corresponding to the model input value and an expected output value corresponding to the model input value; If the difference between the memory parameter value and the parameter update value is greater than an update threshold, the parameter of the target memory is updated by the regulator.

10. The method according to claim 1, characterized in that The method further comprises: When the simulation computer chip is applied to a second target scene, the simulation computer chip obtains a first training set and a first parameter initial value; the first training set is training data corresponding to the second target scene; the first parameter initial value is a model parameter initial value corresponding to the second target scene; Initialize the parameters of the storage operator according to the first parameter initial value; Iteratively updating the parameters of the storage operator according to the first training set, and generating a third operation model corresponding to the storage operator when an iteration completion condition is met; The model input value corresponding to the second target scene is input into the simulation computer chip, and the model output value corresponding to the second target scene is output through the third computing model in the simulation computer chip.

11. The method according to claim 1, characterized in that: The method further comprises: When the simulation computer chip is applied to a third target scene, the simulation computer chip obtains a second training set; the second training set is training data corresponding to the third target scene; Iteratively updating the parameters of the storage operator in the first operation model according to the second training set, and generating a fourth operation model when an iteration completion condition is met; The model input value corresponding to the third target scene is input into the simulation computer chip, and the model output value corresponding to the third target scene is output through the fourth computing model in the simulation computer chip.

12. A method for simulating the operation of a computer chip, characterized in that: The analog computer chip is provided with a storage operator and a regulator; the topological structure of the storage operator is the same as the topological structure of the target neural network model; The target neural network model is generated in a computer device; the method comprises: Acquire training data and initial values ​​of model parameters; the initial values ​​of model parameters are used to initialize the target neural network model; Training the target neural network model using the training data; The parameters of each memory in the storage operator are set according to the trained target neural network model to obtain a first operation model in the simulated computer chip; The model input value corresponding to the first target scene is input into the simulation computer chip, and the model output value corresponding to the first target scene is output by the simulation computer chip through the first computing model.

13. The method according to claim 12, characterized in that The method of setting the parameters of each memory in the storage operator according to the trained target neural network model to obtain a first operation model in the simulated computer chip includes: The model parameters of the target neural network model are input into the regulator of the analog computer chip through the model parameter initial value input pin of the analog computer chip, so that the regulator adjusts the parameters of the corresponding memories according to the model parameters of the target neural network model.

14. The method according to claim 13, characterized in that The parameters of the memory are related to the floating gate charge of the MOS tube of the non-volatile memory unit in the memory.

15. The method according to any one of claims 12 to 14, characterized in that: The method further comprises: When an expected output value corresponding to the model input value and a model adjustment level signal are received through the expected output value input pin, the first operation model is adjusted according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value and the received model adjustment level signal to obtain a second operation model.

16. The method according to claim 15, characterized in that The step of adjusting the first operation model according to the actual output value corresponding to the model input value, the expected output value corresponding to the model input value, and the received model adjustment level signal to obtain the second operation model includes: When the model adjustment level signal is received and the target memory is updated, a memory parameter value of the target memory is obtained, and a parameter update value of the target memory is obtained according to an actual output value corresponding to the model input value and an expected output value corresponding to the model input value; If the difference between the memory parameter value and the parameter update value is greater than an update threshold, the parameter of the target memory is updated by the regulator in the analog computer chip.

17. The method according to any one of claims 12 to 14, characterized in that: The method further comprises: When the simulation computer chip is applied to a second target scene, the simulation computer chip obtains a first training set and a first parameter initial value; the first training set is training data corresponding to the second target scene; the first parameter initial value is a model parameter initial value corresponding to the second target scene; Initialize the parameters of the storage operator according to the first parameter initial value; Iteratively updating the parameters of the storage operator according to the first training set, and generating a third operation model corresponding to the storage operator when an iteration completion condition is met; The model input value corresponding to the second target scene is input into the simulation computer chip, and the model output value corresponding to the second target scene is output through the third computing model in the simulation computer chip.

18. The method according to any one of claims 12 to 14, characterized in that: The method further comprises: When the simulation computer chip is applied to a third target scene, the simulation computer chip obtains a second training set; the second training set is training data corresponding to the third target scene; Iteratively updating the parameters of the storage operator in the first operation model according to the second training set, and generating a fourth operation model when an iteration completion condition is met; The model input value corresponding to the third target scene is input into the simulation computer chip, and the model output value corresponding to the third target scene is output through the fourth computing model in the simulation computer chip.

19. An analog computer chip, characterized in that: The analog computer chip is provided with a storage operator and a regulator; the analog computer chip is used to execute the working method of the analog computer chip as described in any one of claims 1 to 11.

20. A computer device, characterized in that: The computer device is provided with a processing unit and a storage unit, the storage unit stores computer instructions, and the processing unit is used to execute the computer instructions to perform the working method of simulating a computer chip as claimed in any one of claims 12 to 18.

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