Display device and display driving chip and method thereof

Abstract

The invention discloses a display device and a display driving chip and method thereof. A display area of the display panel comprises a high-refresh-rate display area and a low-refresh-rate display area which are adjacent to each other. And in the whole refresh frame period, the high-refresh-rate display area and the low-refresh-rate display area refresh data. In the local refresh frame period, the high-refresh-rate display area refreshes data, and the low-refresh-rate display area does not refresh data. The controller controls the gate driver such that a boundary of the high refresh rate display area and the low refresh rate display area in the first partial refresh frame period is different from a boundary of the high refresh rate display area and the low refresh rate display area in the second partial refresh frame period.

Description

Technical Field

[0001] The present invention relates to an electronic device, and in particular to a display device and a display driving chip and a display driving method thereof. Background Art

[0002] On a traditional display panel, all display panels display one or more images at a certain same frame rate (frame rate). In some applications, such as in mobile phone applications, all display panels may be divided into multiple partitions, but different partitions display images at the same frame rate. In many usage scenarios, often only one partition needs to refresh the screen frequently (for example, play animations), while the other partition is a static screen and does not need to refresh the screen frequently. When all display areas (all partitions) of a traditional display panel operate at a high frame rate, the display panel consumes high power. At this time, for partitions that do not need to refresh the screen frequently, a high frame rate is a waste of power. When all display areas (all partitions) of a traditional display panel operate at a low frame rate, although the display panel consumes low power, the refresh rate (frame rate) is too low for partitions that need to refresh the screen frequently. Summary of the invention

[0003] The present invention provides a display device and a display driving chip and a display driving method thereof, so that different display areas (partitions) in the same display panel can adaptively have different frame rates (refresh rates).

[0004] In an embodiment according to the present invention, the above-mentioned display driver chip includes a controller. The controller is used to control the gate driver of the display panel to be driven by the display driver chip. The gate driver is used to drive multiple scan lines of the display panel, wherein the display area of ​​the display panel includes adjacent high refresh rate display areas and low refresh rate display areas. The display panel displays data in multiple frame periods, wherein the multiple frame periods include at least one full refresh frame period and at least one partial refresh frame period. The high refresh rate display area and the low refresh rate display area both refresh data in the full refresh frame period. In the partial refresh frame period, the high refresh rate display area refreshes data and the low refresh rate display area does not refresh data. The controller controls the gate driver so that in multiple frame periods, the boundary between the high refresh rate display area and the low refresh rate display area in the first partial refresh frame period and the boundary between the high refresh rate display area and the low refresh rate display area in the second partial refresh frame period are different.

[0005] In an embodiment according to the present invention, the above-mentioned display driving method includes: controlling the display panel and the gate driver by the display driver chip so that the display panel displays data in multiple frame cycles, wherein the display area of ​​the display panel includes adjacent high refresh rate display areas and low refresh rate display areas, and the multiple frame cycles include at least one full refresh frame cycle and at least one partial refresh frame cycle; controlling the gate driver by the controller of the display driver chip so that both the high refresh rate display area and the low refresh rate display area refresh data in all refresh frame cycles, and the high refresh rate display area refreshes data and the low refresh rate display area does not refresh data in the partial refresh frame cycle; and controlling the gate driver by the controller so that in the multiple frame cycles, the boundary between the high refresh rate display area and the low refresh rate display area in the first partial refresh frame cycle and the boundary between the high refresh rate display area and the low refresh rate display area in the second partial refresh frame cycle are different.

[0006] In an embodiment of the present invention, the above-mentioned display device includes a display panel, a gate driver and a display driver chip. The display area of ​​the display panel includes adjacent high refresh rate display areas and low refresh rate display areas. The display panel displays data in multiple frame periods. The multiple frame periods include at least one full refresh frame period and at least one partial refresh frame period. The gate driver is coupled to and drives multiple scan lines of the liquid crystal display panel. The display driver chip is coupled to the gate driver. The display driver chip controls the gate driver to refresh data in both the high refresh rate display area and the low refresh rate display area in all refresh frame periods, and refresh data in the high refresh rate display area and do not refresh data in the low refresh rate display area in the partial refresh frame period. The display driver chip controls the gate driver so that in multiple frame periods, the boundary between the high refresh rate display area and the low refresh rate display area in the first partial refresh frame period and the boundary between the high refresh rate display area and the low refresh rate display area in the second partial refresh frame period are different.

[0007] Based on the above, the display driver chip described in the embodiments of the present invention can refresh data in both the high refresh rate display area and the low refresh rate display area in all refresh frame cycles. In the local refresh frame cycle, the high refresh rate display area refreshes data and the low refresh rate display area does not refresh data. Therefore, the low refresh rate display area of ​​the display area of ​​the display panel is not refreshed in each local refresh frame cycle, so that the refresh rate of the low refresh rate display area of ​​the display panel can be different from the high refresh rate display area of ​​the display panel. Based on the control of the gate driver by the display driver chip, the display device can make different display partitions in the same display panel have different refresh rates adaptively. In addition, the display driver chip can dynamically change the boundary position between adjacent high refresh rate display areas and low refresh rate display areas to blur the visual effect difference of the partition boundary, thereby improving the visual effect. By dynamically changing the partition boundary position, the display driver chip can also reduce the aging difference of the display panel on both sides of the partition boundary position.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a circuit block of a display device according to an embodiment of the present invention;

[0010] Figure 2 is a flow chart of a display driving method according to an embodiment of the present invention;

[0011] Figure 3 A circuit block diagram of a gate driver according to an embodiment of the present invention is shown;

[0012] Figure 4 A schematic diagram of the signal timing of a gate driver according to an embodiment of the present invention;

[0013] Figure 5 A schematic diagram of the signal timing sequence of a gate driver is shown in another embodiment of the present invention;

[0014] Figure 6 A schematic diagram of the signal timing of a gate driver is shown in accordance with another embodiment of the present invention;

[0015] Figure 7 A schematic diagram of the signal timing of a gate driver is shown in accordance with another embodiment of the present invention;

[0016] Figure 8 A circuit block diagram of a display device according to another embodiment of the present invention;

[0017] Fig. 9 A schematic diagram of the signal timing of a gate driver is shown in accordance with another embodiment of the present invention;

[0018] Fig.10 A schematic diagram of the signal timing of a gate driver is shown in accordance with another embodiment of the present invention;

[0019] Fig.11 A schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to an embodiment of the present invention;

[0020] Fig.12 A schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to another embodiment of the present invention;

[0021] Fig.13 A schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to another embodiment of the present invention;

[0022] Fig.14 A schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to another embodiment of the present invention;

[0023] Fig.15 A schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to another embodiment of the present invention;

[0024] Fig.16 This is a schematic diagram illustrating a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to yet another embodiment of the present invention.

[0025] Description of Reference Numerals

[0026] 100, 800: Display device

[0027] 110, 810: Display driver chip

[0028] 111: Controller

[0029] 112: Source driver

[0030] 120, 821, 822: Gate driver

[0031] 121, 122, 123: Shift register

[0032] 130, 830: Display panel

[0033] 831, 833: High refresh rate display area

[0034] 832, 834: Low refresh rate display area

[0035] +: Positive polarity drive

[0036] -: Negative polarity drive

[0037] CLR: Reset pulse

[0038] F1, F2, F3: frame period

[0039] F11_1, F11_2, F11_3, F11_4, F11_5, F11_6, F11_7, F11_8, F11_9, F11_10, F11_11, F11_ 12. F12_1, F12_2, F12_3, F12_4, F12_5, F12_6, F12_7, F12_8, F12_9, F12_10, F12_11, F 12_12, F13_1, F13_2, F13_3, F13_4, F13_5, F13_6, F13_7, F13_8, F13_9, F13_10, F13_1 1. F13_12, F14_1, F14_2, F14_3, F14_4, F14_5, F14_6, F14_7, F14_8, F14_9, F14_10, F14 _11, F14_12, F14_13, F14_14, F14_15, F14_16, F14_17, F14_18, F14_19, F14_20, F14_2 1. F14_22, F14_23, F14_24, F15_1, F15_2, F15_3, F15_4, F15_5, F15_6, F15_7, F15_8, F1 5_9, F15_10, F15_11, F15_12, F16_1, F16_2, F16_3, F16_4, F16_5, F16_6, F16_7, F16_8, F16_9, F16_10, F16_11, F16_12, F16_13, F16_14, F16_15, F16_16, F16_17, F16_18: frame period

[0040] GCK1, GCK2, GCK3, GCK4: gate clock signals

[0041] GL1, GL2, GL3: Scan lines

[0042] GL11_1, GL11_2, GL11_3, GL11_4, GL11_5, GL11_6, GL11_7, GL11_8, GL11_9, GL11_10, GL12_1, GL12_2, GL12_3, GL12_4, GL12_5, G L12_6, GL12_7, GL12_8, GL12_9, GL12_10, GL13_1, GL13_2, GL13_3, GL13_4, GL13_5, GL13_6, GL13_7, GL13_8, GL13_9, GL13_10, GL 14_1, GL14_2, GL14_3, GL14_4, GL14_5, GL14_6, GL14_7, GL14_8, GL14_9, GL14_10, GL15_1, GL15_2, GL15_3, GL15_4, GL15_5, GL15_6, GL15_7, GL15_8, GL15_9, GL15_10, GL16_1, GL16_2, GL16_3, GL16_4, GL16_5, GL16_6, GL16_7, GL16_8, GL16_9, GL16_10: horizontal display line

[0043] PU: Node

[0044] S210, S220, S230: Steps

[0045] STV: Start Vertical Pulse

[0046] t1: first time point

[0047] t2: second time point

[0048] t3: The third time point

[0049] VGH: power supply voltage

[0050] VGL: reference voltage DETAILED DESCRIPTION

[0051] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0052] The term "coupled (or connected)" used in the entire specification of the present invention (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned in the entire specification of the present invention (including the claims) are used to name the components (element) or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of components, nor to limit the order of components. In addition, wherever possible, components / components / steps with the same number in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same number or the same terminology in different embodiments can refer to the relevant descriptions of each other.

[0053] Figure 1 is a circuit block diagram of a display device 100 according to an embodiment of the present invention. Figure 1 The display device 100 shown includes a display driver chip 110, a gate driver 120, and a display panel 130. Based on actual design, the display panel 130 may include various types of display panels, such as a liquid crystal display (LCD) panel or other display panels. The display driver chip 110 is coupled to multiple data lines (data lines, or source lines, source lines) of the display panel 130 to drive multiple data lines of the display panel 130. The display driver chip 110 is coupled to the gate driver 120. The gate driver 120 is coupled to multiple scan lines (scan lines, or gate lines, gate lines) of the display panel 130. The gate driver 120 can scan multiple scan lines of the display panel 130 to display data row by row on horizontal display lines (i.e., pixel rows). According to actual design, the gate driver 120 may include a gate driver on array (Gate Driver on Array, GOA) or other gate driving circuits. In coordination with the scanning timing of the gate driver 120 on the display panel 130 , the display driver chip 110 can drive a plurality of data lines of the display panel 130 , so that the display panel 130 displays corresponding data (image) in each frame period.

[0054] The display panel 130 is a display panel that can achieve different refresh rates in different partitions. The display area of ​​the display panel includes at least two partitions with different refresh rates, such as adjacent first display partitions and second display partitions. The one with a relatively high refresh rate (e.g., 120Hz) among the two display partitions is a high refresh rate display area, and the one with a relatively low refresh rate (e.g., 60Hz) among the two display partitions is a low refresh rate display area. For example, taking the screen of a mobile phone as an illustrative example of the display device 100 and the display panel 130, when the mobile phone opens a streaming multimedia application, the upper part of the screen is a video playback area (a high refresh rate display area) and the area below the screen is a message board area (a low refresh rate display area). The display device 100 can reduce the refresh rate of the low refresh rate display area to reduce power consumption while maintaining a high refresh rate in the high refresh rate display area.

[0055] The multiple frame periods of the display panel 130 displaying the image screen include two types of frame periods, one is a full refresh frame period, and the other is a partial refresh frame period. In the full refresh frame period, both the high refresh rate display area and the low refresh rate display area refresh data. In the partial refresh frame period, only the high refresh rate display area refreshes data, while the low refresh rate display area does not refresh data. The full refresh frame period and the partial refresh frame period are configured at intervals in time. For example, assuming that the input frame rate is 120Hz and a full refresh frame period and a subsequent partial refresh frame period are collectively regarded as a global refresh period for repeated configuration, the refresh rate of the high refresh rate display area is 120Hz and the refresh rate of the low refresh rate display area is 60Hz. For another example, assuming that the input frame rate is 120Hz and a full refresh frame period and two subsequent partial refresh frame periods are collectively regarded as a global refresh period for repeated configuration, the refresh rate of the high refresh rate display area is 120Hz and the refresh rate of the low refresh rate display area is 40Hz (because the low refresh rate display area refreshes data once every three frame periods).

[0056] For the display panel 130, when the boundary position of two display partitions with different refresh rates remains unchanged for a long time, if the refresh rate difference between the two partitions is large, the boundary is easy to see after long-term use. Furthermore, the panel aging phenomenon of the high refresh rate display area is more serious than that of the low refresh rate display area, making it easier for viewers to see the boundary of the two display partitions (because the refresh rate difference causes the two partitions to age at different speeds), which is not good for visual effects. In an embodiment of the present invention, the display driver chip 110 dynamically changes the boundary position of the display partitions with different refresh rates, so that the boundary of the two display partitions dynamically changes position within a limited range, thereby blurring the visual effect difference of the display area boundary.

[0057] For example (but not limited to), suppose Figure 1The display panel 130 shown includes 1612 scan lines. Based on the actual operation scenario, the display driver chip 110 can make the first display partition controlled by the multiple scan lines (e.g., the 1st to 540th scan lines) on the upper part of the display panel 130 as a high refresh rate display area, and make the second display partition controlled by the multiple scan lines (e.g., the 541st to 1612th scan lines) on the lower part of the display panel 130 as a low refresh rate display area. In a full refresh frame cycle, the display driver chip 110 controls the gate driver 120 and the display panel 130 so that both the high refresh rate display area (e.g., the 1st to 540th horizontal display lines) and the low refresh rate display area (e.g., the 541st to 1612th horizontal display lines) refresh data. In a first partial refresh frame period, the display driver chip 110 controls the gate driver 120 and the display panel 130 to refresh data only for the high refresh rate display area (e.g., the 1st to 540th horizontal display lines), and does not refresh data for the low refresh rate display area (e.g., the 541st to 1612th horizontal display lines). In a second partial refresh frame period, the display driver chip 110 controls the gate driver 120 to change the boundary position of the high refresh rate display area and the low refresh rate display area, for example, from the original boundary between the 540th horizontal display line and the 541st horizontal display line to a new boundary between the 541st horizontal display line and the 542nd horizontal display line (or to a new boundary between the 539th horizontal display line and the 540th horizontal display line). In the second partial refresh frame period, only the high refresh rate display area (eg, the 1st to 541st horizontal display lines) refreshes data while the low refresh rate display area (eg, the 542nd to 1612th horizontal display lines) does not refresh data.

[0058] At the beginning of each frame period (or at the end of each frame period), whether it is a full refresh frame period or a partial refresh frame period, the display driver chip 110 sends a reset pulse (native reset pulse) to the gate driver 120, so as to clear the scan pulse of the gate driver 120 before scanning the display panel 130, that is, to clear the scan pulse latched inside the gate driver 120, so as to prepare for the next frame display. After the native reset pulse occurs, the gate driver 120 can start to transfer the scan pulse step by step based on the vertical start pulse STV provided by the display driver chip 110 and output the scan pulse to the scan line of the scan display panel 130. If the current frame cycle is a full refresh frame cycle, the display driver chip 110 only sends a single reset pulse to the gate driver 120 at the beginning or end of the current frame cycle (such as the first time point t1 in the attached figure of the embodiment described later), so that the shift register circuit in the gate driver 120 starts to transfer the scan pulse step by step, and then the gate driver 120 can sequentially output scan signals to all scan lines of the display panel 130, including the scan lines corresponding to the high refresh rate display area and the scan lines corresponding to the low refresh rate display area.

[0059] On the other hand, if the current frame period is a partial refresh frame period, the display driver chip 110 not only sends a native reset pulse to the gate driver 120 at the beginning or end of the current frame period (such as the first time point t1 in the attached figure of the embodiment described later) to make the shift register circuit in the gate driver 120 start to transfer the scan pulse step by step, but also sends an additional reset pulse (i.e., the second reset pulse in the frame period) to the gate driver 120 after the high refresh rate display area displayed previously is finished (such as the second time point t2 in the attached figure of the embodiment described later), that is, after the gate driver 120 outputs the scan pulse of the last (latest in time) scan line corresponding to the high refresh rate display area. The additional reset pulse will clear the scan pulse latched in the gate driver 120. That is, after the high refresh rate display area is finished, since the low refresh rate display area does not need to refresh data in the partial refresh frame period, the gate driver 120 does not need to output a scan pulse to the scan line corresponding to the low refresh rate display area.

[0060] exist Figure 1In the illustrated embodiment, the display driver chip 110 includes a controller 111 and a source driver 112. The source driver 112 is coupled to a plurality of data lines of the display panel 130. The controller 111 is coupled to the source driver 112 and the gate driver 120. The controller 111 controls the gate driver 120 of the display panel 130. The gate driver 120 is used to drive a plurality of scan lines of the display panel 130. According to different designs, in some embodiments, the controller 111 may be implemented as a hardware circuit. In other embodiments, the controller 111 may be implemented as firmware, software, or a combination of the two. In still other embodiments, the controller 111 may be implemented as a combination of hardware, firmware, and software.

[0061] In terms of hardware, the display driver chip 110 and / or the controller 111 may be implemented as a logic circuit on an integrated circuit. For example, the functions of the display driver chip 110 and / or the controller 111 may be implemented in various logic blocks, modules and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs) and / or other processing units. The functions of the display driver chip 110 and / or the controller 111 may be implemented as hardware circuits, such as various logic blocks, modules and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0062] In terms of software and / or firmware, the related functions of the display driver chip 110 and / or the controller 111 can be implemented as programming codes. For example, the display driver chip 110 and / or the controller 111 are implemented using general programming languages ​​(such as C, C++ or assembly language) or other suitable programming languages. The programming code can be recorded / stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory and / or a storage device. The semiconductor memory includes a memory card, a read-only memory (ROM), a flash memory (FLASH memory), a programmable logic circuit or other semiconductor memory. The storage device includes a tape, a disk, a hard disk drive (HDD), a solid-state drive (SSD) or other storage devices. An electronic device (such as a computer, a CPU, a controller, a microcontroller or a microprocessor) can read and execute the programming code from the non-temporary machine-readable storage medium to implement the relevant functions of the display driver chip 110 and (or) the controller 111.

[0063] Figure 2 A schematic flow chart of a display driving method according to an embodiment of the present invention. Figure 2 The embodiment of the present invention takes the global refresh cycle including one full refresh frame cycle and two local refresh frame cycles as an example, but the configuration of the global refresh cycle is not limited to this. Please refer to Figure 1 and Figure 2 , the display driver chip 110 controls the display panel 130 and the gate driver 120 so that the display panel 130 displays data in multiple frame periods (step S210). In step S220, the controller 111 controls the gate driver 120 to refresh the data in both the high refresh rate display area and the low refresh rate display area in all refresh frame periods, and refresh the data in the high refresh rate display area and do not refresh the data in the low refresh rate display area in the partial refresh frame period. In detail, the controller 111 sends a native reset pulse to the gate driver 120 at the start time or end time of all refresh frame periods (such as the first time point t1 in the attached figure of the embodiment described later), so that the shift register in the gate driver 120 starts to transfer the scan pulse step by step, and then the gate driver 120 can sequentially output the scan signal to all scan lines of the display panel 130, including the scan lines corresponding to the high refresh rate display area and the scan lines corresponding to the low refresh rate display area.

[0064] The first partial refresh frame period follows the full refresh frame period. The controller 111 sends a native reset pulse to the gate driver 120 at the start or end time of the first partial refresh frame period (such as the first time point t1 in the attached figure of the embodiment described later), so that the shift register circuit in the gate driver 120 starts to transfer the scan pulse step by step. In addition, the controller 111 also sends an additional reset pulse (i.e., the second reset pulse in the first partial refresh frame period) to the gate driver 120 after the high refresh rate display area displayed first is completed (such as the second time point t2 in the attached figure of the embodiment described later), that is, after the gate driver 120 outputs the scan pulse of the last (latest in time) scan line corresponding to the high refresh rate display area, so as to clear the scan pulse latched in the gate driver 120. After the high refresh rate display area is completed, since the low refresh rate display area does not need to refresh data in the first partial refresh frame period, the gate driver 120 does not need to output a scan pulse to the scan line corresponding to the low refresh rate display area.

[0065] The first local refresh frame period is followed by a second local refresh frame period. The controller 111 sends a native reset pulse to the gate driver 120 at the start time or end time of the second local refresh frame period (such as the first time point t1 in the attached figure of the embodiment described later), so that the shift register circuit in the gate driver 120 starts to transfer the scan pulse step by step. It is worth noting that in step S230, the controller 111 controls the gate driver 120, so that in multiple frame periods, the boundary between the high refresh rate display area and the low refresh rate display area in the first local refresh frame period is different from the boundary between the high refresh rate display area and the low refresh rate display area in the second local refresh frame period. In detail, the number of horizontal display lines (scan lines) corresponding to the high refresh rate display area in the second local refresh frame period is different from the number of horizontal display lines (scan lines) corresponding to the high refresh rate display area in the first local refresh frame period. For example (but not limited to this), the high refresh rate display area in the first partial refresh frame period includes the 1st to 540th horizontal display lines of the display panel, and the high refresh rate display area in the second partial refresh frame period includes the 1st to 541st horizontal display lines of the display panel, that is, the boundary between the high refresh rate display area and the low refresh rate display area has changed. After the high refresh rate display area displayed first is finished (such as the third time point t3 in the attached figure of the embodiment described later), that is, after the gate driver 120 outputs the scan pulse corresponding to the last (latest in time) scan line of the high refresh rate display area, the controller 111 sends an additional reset pulse (that is, the second reset pulse in the second partial refresh frame period) to the gate driver 120 to clear the scan pulse latched in the gate driver 120. The third time point t3 and the second time point t2 correspond to different boundaries between the high refresh rate display area and the low refresh rate display area. After the high refresh rate display area has finished displaying, since the low refresh rate display area does not need to refresh data in the second partial refresh frame period, the gate driver 120 does not need to output scan pulses to the scan lines corresponding to the low refresh rate display area.

[0066] In summary, the controller 111 of the display driver chip 110 described in this embodiment can send a single reset pulse (native reset pulse) to the gate driver 120 in each full refresh frame period of the display frame stream to refresh the entire display area (all display partitions) of the display panel 130. In each partial refresh frame period of the display frame stream, the controller 111 can send multiple reset pulses (such as native reset pulses and additional reset pulses) to the gate driver 120, and the gate driver 120 can sequentially output scan pulses based on the vertical start pulse provided by the display driver chip 110 to scan the scan lines of the display panel 130, so that the high refresh rate display area of ​​the display panel 130 can be refreshed in each partial refresh frame period, and after the controller 111 sends the additional reset pulse, the scan pulse in the gate driver 120 has been cleared, so that the gate driver 120 does not scan the scan lines in the low refresh rate display area of ​​the display panel 130. Even if the number or range of horizontal display lines and the corresponding number or range of scan lines in the low refresh rate display area are changed in different local refresh frame periods, the low refresh rate display area does not need to refresh data through the control of the additional reset pulse. Based on the control of the gate driver 120 by the controller 111 of the display driver chip 110, different display partitions in the display panel 130 are adaptively provided with different refresh rates.

[0067] Figure 3 FIG. 1 is a circuit block diagram of a gate driver 120 according to an embodiment of the present invention. Figure 3 In the illustrated embodiment, the gate driver 120 includes a plurality of shift registers, such as Figure 3 The shift registers 121, 122 and 123 are shown. Each of the shift registers 121, 122 and 123 is coupled to a corresponding scan line of the display panel 130, for example Figure 3 Scan lines GL1, GL2 and GL3 are shown. Figure 3 The shift registers 121-123 are triggered by the vertical start pulse STV and the gate clock signals GCK1 and GCK2 to transfer the scan pulses step by step. Figure 3The voltages VGH and VGL are respectively the power supply voltage and the reference voltage (high voltage and low voltage). In addition to sending a reset pulse CLR (native reset pulse) to each shift register of the gate driver 120 at the start time (or end time) of each partial refresh frame period, the display driver chip 110 also sends another reset pulse CLR (extra reset pulse) to each shift register at other time points in each partial refresh frame period. Based on the extra reset pulse CLR, the latched contents of the entire string of shift registers 121-123 will be pulled down to the reference voltage VGL (i.e., the scan pulse latched in the gate driver 120 is cleared), so that the entire string of shift registers 121-123 cannot continue to transmit the scan pulse.

[0068] According to the actual design, the display driver chip 110 may send an additional reset pulse CLR to each shift register 121-123 in each partial refresh frame period, and (or) stop supplying the gate clock signal GCK during a portion of each partial refresh frame period (e.g. Figure 3 By stopping the gate clock signal GCK (e.g. Figure 3 The switching behavior of GCK1 and GCK2 shown in the figure, and / or by applying multiple reset pulses CLR in the same local refresh frame period, the gate driver 120 stops the scanning operation of the display panel 130 after the high refresh rate display area of ​​the display panel 130 is refreshed.

[0069] The present invention can dynamically change the boundary between the high refresh rate display area and the low refresh rate display area, thereby blurring the visual effect difference of the display area boundary. For example, by stopping the switching (Toggle) behavior of the gate clock signal GCK in the low refresh rate display area, the voltage (latch content) of the node PU of each shift register 121-123 is pulled down to close to the reference voltage VGL due to leakage (that is, clearing the scan pulse latched in the gate driver 120), so that the stage transfer operation (scanning operation) of these shift registers 121-123 of the gate driver 120 is stopped. Based on stopping the supply of gate clock signals GCK1 and GCK2 to the gate driver 120, the low refresh rate display area of ​​the display panel 130 is not refreshed in each local refresh frame cycle, so that the refresh rate of the low refresh rate display area of ​​the display panel 130 can be different from the high refresh rate display area of ​​the display panel 130. Therefore, the display device 100 can make different display partitions in the same display panel 130 adaptively have different refresh rates.

[0070] Alternatively, the display driver chip 110 can use an additional reset pulse CLR in the low refresh rate display area, so that the voltage (latch content) of the node PU of each shift register 121-123 can be quickly pulled down to close to the reference voltage VGL (that is, clearing the scan pulse latched in the gate driver 120), thereby stopping the stage transfer operation (scanning operation) of the gate driver 120. Based on the application of the additional reset pulse CLR, the low refresh rate display area of ​​the display panel 130 is not refreshed in each partial refresh frame period, so that the refresh rate of the low refresh rate display area of ​​the display panel 130 can be different from that of the high refresh rate display area of ​​the display panel 130. Therefore, the display device 100 can make different display partitions in the same display panel 130 adaptively have different refresh rates.

[0071] The source driver 112 of the display driver chip 110 can drive multiple data lines of the display panel 130 based on the control of the controller 111. In some embodiments, in conjunction with the scanning timing of the gate driver 120 on the display panel 130, the controller 111 enables the source driver 112 before the second time point in each partial refresh frame period, and the controller 111 disables the analog domain circuit and (or) digital domain circuit of the source driver 112 after the second time point in each partial refresh frame period. For example, the source driver 112 can stop or reduce the source voltage change behavior (such as maintaining a DC level, Hi-Z or other methods) for the second partition (low refresh rate display area) to save power consumption.

[0072] The controller 111 can dynamically adjust the stop position of the gate clock signal and (or) dynamically determine the timing of the additional reset pulse so that the shift register of the gate driver 120 stops the stage transfer at a certain target time point. Therefore, in the partial refresh frame period, only the pixel data of the high refresh rate display area of ​​the display panel 130 is refreshed, while the pixel data of the low refresh rate display area of ​​the display panel 130 remains unchanged (not refreshed).

[0073] Figure 4 FIG. 1 is a schematic diagram of a signal timing sequence of a gate driver 120 according to an embodiment of the present invention. Figure 4 The horizontal axis represents time. The vertical start pulse STV and the shift register may not be limited to one set. Figure 4 The gate clock signals GCK1 , GCK2 , GCK3 , and GCK4 are used to trigger a plurality of shift registers of the gate driver 120 . Figure 4The frame period F1 shown on the left is a full refresh frame period (normal display frame). In the frame period F1, the reset pulse CLR first clears the scan pulses of all shift registers of the gate driver 120 at the first time point t1 in the frame period F1, and then the controller 111 can provide the vertical start pulse STV and the gate clock signals GCK1-GCK4 to the gate driver 120. Based on the vertical start pulse STV and the gate clock signals GCK1-GCK4, the gate driver 120 and the source driver 112 can completely refresh the high refresh rate display area and the low refresh rate display area. Therefore, in the frame period F1, the entire display area of ​​the display panel 130 can be refreshed normally.

[0074] Figure 4 The frame period F2 shown in the middle is the first partial refresh frame period. In the frame period F2, the gate driver 120 partially scans the high refresh rate display area, but does not scan the low refresh rate display area. The controller 111 sends a native reset pulse CLR to the gate driver 120 at the first time point t1 in the frame period F2 to start generating a plurality of scan pulses corresponding to the high refresh rate display area. After the data in the high refresh rate display area is refreshed in the first partial refresh frame period, the controller 111 also sends an additional reset pulse CLR to the gate driver 120 at the second time point t2 in the frame period F2 (the corresponding time point of the boundary position between the high refresh rate display area and the low refresh rate display area of ​​the display panel 130) to clear the charge of the node PU of all the shift registers of the gate driver 120 (clear the scan pulse in the gate driver 120). Therefore, the scan pulse transmission of all the shift registers of the gate driver 120 is suspended, so that the low refresh rate display area will not be refreshed in the frame period F2. In the frame period F2 , the controller 111 continues to supply the gate clock signals GCK1 ˜ GCK4 to the gate driver 120 before the second time point t2 .

[0075] The source driver 112 drives multiple data lines of the display panel 130 based on the control of the controller 111. The controller 111 enables the source driver 112 before the first time point t1 in the frame period F2. In accordance with the operation timing of the gate driver 120, before the second time point t2, the source driver 112 can refresh the data of the high refresh rate display area. After the data in the high refresh rate display area is refreshed, the controller 111 stops the switching behavior of the gate clock signals GCK1~GCK4 output to the gate driver 120 from the second time point t2 when the additional reset pulse is transmitted. In accordance with the operation timing of the gate driver 120, after the second time point t2, the source driver 112 can stop refreshing the pixel data in the low refresh rate display area. The controller 111 disables the analog domain circuit or the digital domain circuit of the source driver 112 after the second time point t2 in the frame period F2. For example, when the shift registers of the gate driver 120 stop transmitting, the source driver 112 can maintain the black grayscale voltage (or other DC voltage level) to the data line of the display panel 130, or maintain the hi-Z resistance state of the data line, or reduce the frequency of the change of the data line. Alternatively, the digital data path (digital domain circuit) inside the source driver 112 can enter a power saving mode.

[0076] Figure 4The frame period F3 shown on the right is the second partial refresh frame period. In the frame period F3, the gate driver 120 partially scans the high refresh rate display area, but does not scan the low refresh rate display area. After the data in the high refresh rate display area is refreshed in the frame period F3, the controller 111 transmits an additional reset pulse to the gate driver 120 at the third time point t3 to clear the scan pulse in the gate driver. The frame period F3 and the third time point t3 can refer to the relevant description of the frame period F2 and the second time point t2 and be analogized, so they are not repeated. It is worth noting that in the frame period F3, the controller 111 controls the gate driver 120 so that the boundary between the high refresh rate display area and the low refresh rate display area in the frame period F2 (the first partial refresh frame period) is different from the boundary between the high refresh rate display area and the low refresh rate display area in the frame period F3 (the second partial refresh frame period). In detail, the number of horizontal display lines (scan lines) corresponding to the high refresh rate display area in the frame period F3 is different from the number of horizontal display lines (scan lines) corresponding to the high refresh rate display area in the frame period F2. For example (but not limited thereto), the high refresh rate display area in the frame period F2 includes the 1st to 540th horizontal display lines of the display panel, and the high refresh rate display area in the frame period F3 includes the 1st to 541st horizontal display lines of the display panel, that is, the boundary between the high refresh rate display area and the low refresh rate display area has changed. The controller 111 sends an additional reset pulse to the gate driver 120 at the third time point t3, that is, after the gate driver 120 outputs the scan pulse corresponding to the last (latest in time) scan line of the high refresh rate display area, to clear the scan pulse latched in the gate driver 120. The position of the third time point t3 in the frame period F2 is different from the position of the second time point t2 in the frame period F2.

[0077] Figure 5 FIG. 1 is a schematic diagram of a signal timing sequence of a gate driver 120 according to another embodiment of the present invention. Figure 5 The horizontal axis represents time. Figure 5 The frame period F1 shown on the left is a full refresh frame period (normal display frame). In the frame period F1, the entire display area of ​​the display panel 130 is refreshed normally. Figure 5The frame period F2 shown in the middle is a partial refresh frame period. In the frame period F2, based on the control of the controller 111, the gate driver 120 only partially scans the high refresh rate display area of ​​the display panel 130. After the gate driver 120 refreshes the high refresh rate display area, the controller 111 can stop the switching (Toggle) behavior of the gate clock signals GCK1~GCK4, that is, the controller 111 stops supplying the gate clock signals GCK1~GCK4 to the gate driver 120 after the second time point t2, so that all the shift registers of the gate driver 120 stop the stage transmission. During the period when these shift registers stop the stage transmission, the voltage of the node PU of these shift registers decreases due to leakage (clearing the scan pulse latched in the gate driver 120). When the reset pulse CLR of the next frame period comes, the scan pulses of all the shift registers of the gate driver 120 will be cleared (resetting the node PU voltage). When the vertical start pulse STV of the next frame period comes, the source driver 112 and the gate driver 120 can refresh the screen from the beginning. When the shift registers of the gate driver 120 stop transmitting, the source driver 112 can maintain the black grayscale voltage (or other DC voltage level) to the data lines of the display panel 130, or maintain the data lines in a hi-Z impedance state, or reduce the frequency of changes to the data lines. Alternatively, the digital data path (digital domain circuit) inside the source driver 112 can enter a power saving mode.

[0078] Figure 5 The frame period F1, frame period F2 and frame period F3 shown can refer to Figure 4 The related descriptions of the frame period F1, frame period F2 and frame period F3 are similar and can be deduced by analogy, so they will not be repeated here. Figure 4 The embodiment shown is that the controller 111 Figure 5 As shown, no additional reset pulse CLR is sent to the gate driver 120 after the second time point t2 and the third time point t3.

[0079] Figure 6 FIG. 1 is a schematic diagram of signal timing of the gate driver 120 according to yet another embodiment of the present invention. Figure 6 The horizontal axis represents time. Figure 6 The frame period F1 shown on the left is a full refresh frame period (normal display frame). In the frame period F1, the entire display area of ​​the display panel 130 is refreshed normally. Figure 6The frame period F2 shown in the middle is a partial refresh frame period. In the frame period F2, based on the control of the controller 111, the gate driver 120 only partially scans the high refresh rate display area of ​​the display panel 130. After the gate driver 120 refreshes the high refresh rate display area, the controller 111 can stop the switching (Toggle) behavior of the gate clock signals GCK1~GCK4 to stop all the shift registers of the gate driver 120 from transmitting. During the period when these shift registers stop transmitting, the voltage of the node PU of these shift registers decreases due to leakage, thereby causing the scan pulse latched in the gate driver 120 to disappear (clear the scan pulse). When the vertical start pulse STV of the next frame period comes, the source driver 112 and the gate driver 120 can refresh the screen from the beginning. When these shift registers of the gate driver 120 stop transmitting, the source driver 112 can maintain the black grayscale voltage (or other DC level) to the data line of the display panel 130, or maintain the hi-Z resistance state for the data line, or reduce the change frequency of the data line. Alternatively, the digital data path (digital domain circuit) inside the source driver 112 may enter a power saving mode.

[0080] Figure 6 The frame period F1, frame period F2 and frame period F3 shown can refer to Figure 4 The related descriptions of the frame period F1, frame period F2 and frame period F3 are similar and can be deduced by analogy, so they will not be repeated here. Figure 4 The embodiment shown is that Figure 6 As shown, after the second time point t2 and the third time point t3 , the controller 111 does not send an additional reset pulse CLR to the gate driver 120 .

[0081] Figure 7 FIG. 1 is a schematic diagram of signal timing of the gate driver 120 according to yet another embodiment of the present invention. Figure 7 The horizontal axis represents time. Figure 7 The frame period F1 shown on the left is a full refresh frame period (normal display frame). In the frame period F1, the entire display area of ​​the display panel 130 is refreshed normally. Figure 7 The frame period F2 shown in the middle is the first partial refresh frame period. Figure 7 The frame period F3 shown on the right is the second partial refresh frame period. Figure 7 The frame period F1, frame period F2 and frame period F3 shown can refer to Figure 4 The related descriptions of the frame period F1, frame period F2 and frame period F3 are similar and can be deduced by analogy, so they will not be repeated here. Figure 4The embodiment shown is that after the gate driver 120 refreshes the high refresh rate display area, the controller 111 transmits an additional reset pulse but does not stop the toggle behavior of the gate clock signal GCK. That is, after the second time point t2 of the frame cycle F2 and after the third time point t3 of the frame cycle F3, the controller 111 continues to supply the gate clock signals GCK1-GCK4 to the gate driver 120.

[0082] Figure 8 FIG. 8 is a circuit block diagram of a display device 800 according to another embodiment of the present invention. Figure 8 The display device 800 shown includes a display driving chip 810 , a gate driver 821 , a gate driver 822 , and a display panel 830 . Figure 8 The display device 800, the display driver chip 810 and the display panel 830 shown in FIG. Figure 1 The display device 100, the display driver chip 110 and the display panel 130 are described in detail and can be deduced by analogy. Figure 8 The gate driver 821 and the gate driver 822 shown can refer to Figure 1 The related descriptions of the gate driver 120 are also applicable.

[0083] exist Figure 8 In the illustrated embodiment, the display panel 830 is divided into a left half region and a right half region, wherein the scan lines in the left half region are not electrically connected to the scan lines in the right half region. The gate driver 821 is disposed on the left side of the display panel 830, and the gate driver 822 is disposed on the right side of the display panel 830. The gate driver 821 is coupled to a plurality of first scan lines of the display panel 830, and the gate driver 822 is coupled to a plurality of second scan lines of the display panel 830, such as Figure 8 The display driver chip 810 is coupled to the gate drivers 821 and 822. When the left and right sides of the display panel 830 use different gate drivers 821 and 822, the gate drivers 821 and 822 can independently perform scanning operations on the display panel 830. The scanning operation performed by either of the gate drivers 821 and 822 on the display panel 830 can refer to Figures 3 to 7 The relevant instructions are given above and can be deduced by analogy, so I will not go into details here.

[0084] The gate driver 821 drives the first scan lines of the display panel 830, and the gate driver 822 drives the second scan lines of the display panel 830. The display driver chip 810 sends a single reset pulse to the gate driver 821 in each full refresh frame period to clear the scan pulses in the gate driver 821. The display driver chip 810 sends multiple reset pulses to the gate driver 821 in each partial refresh frame period to clear the scan pulses in the gate driver 821 at different time points. Therefore, in each partial refresh frame period, only the pixel data of the high refresh rate display area 831 of the display panel 830 is refreshed, while the pixel data of the low refresh rate display area 832 of the display panel 830 remains unchanged (not refreshed). Based on the control of the gate driver 821 by the display driver chip 810, the high refresh rate display area 831 of the display panel 830 has a high frame rate (e.g., 120 Hz), while the low refresh rate display area 832 of the display panel 830 has a low frame rate (e.g., 40 Hz). Therefore, the display device 800 can reduce the refresh rate of the low refresh rate display area 832 to reduce power consumption while maintaining a high refresh rate in the high refresh rate display area 831 .

[0085] Similarly, the display driver chip 810 sends a single reset pulse to the gate driver 822 in each full refresh frame period to clear the scan pulse in the gate driver 822. The display driver chip 810 sends multiple reset pulses to the gate driver 822 in each partial refresh frame period to clear the scan pulse in the gate driver 822 at different time points. Therefore, in each partial refresh frame period, only the pixel data of the high refresh rate display area 833 of the display panel 830 is refreshed, while the pixel data of the low refresh rate display area 83 of the display panel 830 remains unchanged (not refreshed). Based on the control of the gate driver 822 by the display driver chip 810, the high refresh rate display area 833 of the display panel 830 has a high frame rate (e.g., 120 Hz), while the low refresh rate display area 834 of the display panel 830 has a low frame rate (e.g., 80 Hz). Therefore, the display device 800 can reduce the refresh rate of the low refresh rate display area 834 to reduce power consumption while maintaining the high refresh rate display area 833 at a high refresh rate.

[0086] Fig. 9 FIG. 1 is a schematic diagram of signal timing of the gate driver 120 according to yet another embodiment of the present invention. Fig. 9 The horizontal axis represents time. Fig. 9 In the illustrated embodiment, the number of reset pulses in each full refresh frame period is 0, and the number of reset pulses in each partial refresh frame period is 1. Fig. 9The frame period F1 shown on the left is a full refresh frame period (normal display frame). In the frame period F1, in the absence of the reset pulse CLR, all display areas (all sub-areas) of the display panel 130 are refreshed normally. Fig. 9 The frame period F2 shown in the middle is the first partial refresh frame period. In the frame period F2, the gate driver 120 only partially scans the high refresh rate display area of ​​the display panel 130. After the gate driver 120 refreshes the high refresh rate display area in the frame period F2, the controller 111 stops the switching (Toggle) behavior of the gate clock signal GCK. After the gate driver 120 refreshes the high refresh rate display area in the frame period F2, the controller 111 sends a reset pulse CLR to the gate driver 120 to reset all shift registers of the gate driver 120 (reset the voltage of the node PU of these shift registers).

[0087] Fig. 9 The frame period F3 shown on the right is the second local refresh frame period. In the frame period F3, the gate driver 120 partially scans the high refresh rate display area, but does not scan the low refresh rate display area. The frame period F3 and the third time point t3 can refer to the relevant description of the frame period F2 and the second time point t2 and be analogized, so they are not repeated. In the frame period F3, the controller 111 controls the gate driver 120, so that the boundary between the high refresh rate display area and the low refresh rate display area in the frame period F2 (the first local refresh frame period) is different from the boundary between the high refresh rate display area and the low refresh rate display area in the frame period F3 (the second local refresh frame period).

[0088] Fig.10 FIG. 1 is a schematic diagram of signal timing of the gate driver 120 according to yet another embodiment of the present invention. Fig.10 The horizontal axis represents time. Fig.10 In the illustrated embodiment, the number of reset pulses in each full refresh frame period is 0, and the number of reset pulses in each partial refresh frame period is 1. Fig.10 The frame period F1 shown on the left is a full refresh frame period (normal display frame). In the frame period F1, in the absence of the reset pulse CLR, the entire display area of ​​the display panel 130 is refreshed normally. Fig.10 The frame period F2 shown in the middle is the first partial refresh frame period. In the frame period F2, the gate driver 120 only partially scans the high refresh rate display area of ​​the display panel 130. After refreshing the high refresh rate display area in the frame period F2, the controller 111 does not stop the switching (Toggle) behavior of the gate clock signal GCK. After refreshing the high refresh rate display area in the frame period F2, the controller 111 sends a reset pulse CLR to the gate driver 120 to reset all shift registers of the gate driver 120 (reset the voltage of the node PU of these shift registers).

[0089] Fig.10 The frame period F3 shown on the right is the second partial refresh frame period. In the frame period F3, the gate driver 120 partially scans the high refresh rate display area, but does not scan the low refresh rate display area. The frame period F3 can refer to the relevant description of the frame period F2 and be inferred by analogy, so it is not repeated here. In the frame period F3, the controller 111 controls the gate driver 120 so that the boundary between the high refresh rate display area and the low refresh rate display area in the frame period F2 (the first partial refresh frame period) is different from the boundary between the high refresh rate display area and the low refresh rate display area in the frame period F3 (the second partial refresh frame period).

[0090] Fig.11 It is a schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to an embodiment of the present invention. Fig.11 The horizontal axis represents time. Fig.11 In the figure, “+” indicates positive polarity drive, and “-” indicates negative polarity drive. Fig.11 GL11_1, GL11_2, GL11_3, GL11_4, GL11_5, GL11_6, GL11_7, GL11_8, GL11_9 and GL11_10 represent different horizontal display lines (scanning lines, see Figure 3 The related descriptions of the scan lines GL1, GL2 and GL3 are shown and the same can be applied). Fig.11 A plurality of frame periods F11_1, F11_2, F11_3, F11_4, F11_5, F11_6, F11_7, F11_8, F11_9, F11_10, F11_11 and F11_12 are shown, wherein the frame periods F11_1, F11_4, F11_7 and F11_10 are all refresh frame periods (refer to Figure 4 1 and the like), frame periods F11_2, F11_5, F11_8 and F11_11 are first partial refresh frame periods (refer to Figure 4 The frame periods F11_3, F11_6, F11_9 and F11_12 are second partial refresh frame periods (refer to Figure 4 The relevant description of the frame period F3 shown and the same can be applied).

[0091] The local refresh frame period between the last (or only) full refresh frame period in a global refresh period and the first full refresh frame period in the next global refresh period is regarded as a local refresh cycle. For example, frame periods F11_2 and F11_3 between frame periods F11_1 and F11_4 are the first local refresh cycle, frame periods F11_5 and F11_6 between frame periods F11_4 and F11_7 are the second local refresh cycle, and frame periods F11_8 and F11_9 between frame periods F11_7 and F11_10 are the third local refresh cycle. Adjacent full refresh frame periods and local refresh cycles are a global refresh cycle. For example, frame periods F11_1 to F11_3 are the first global refresh cycle, frame periods F11_4 to F11_6 are the second global refresh cycle, frame periods F11_7 to F11_9 are the third global refresh cycle, and frame periods F11_10 to F11_12 are the fourth global refresh cycle. A plurality of global refresh cycles that complete the positive and negative polarity changes constitute a global refresh cycle. For example, frame cycles F11_1 to F11_6 are the first global refresh cycle, and frame cycles F11_7 to F11_12 are the second global refresh cycle.

[0092] In each partial refresh cycle, the boundary between the high refresh rate display area and the low refresh rate display area in the first partial refresh frame period is different from the boundary between the high refresh rate display area and the low refresh rate display area in the second partial refresh frame period. For example, the boundary between the high refresh rate display area (horizontal display lines GL11_1 to GL11_6) and the low refresh rate display area (horizontal display lines GL11_7 to GL11_10) in frame period F11_2 is different from the boundary between the high refresh rate display area (horizontal display lines GL11_1 to GL11_7) and the low refresh rate display area (horizontal display lines GL11_8 to GL11_10) in frame period F11_3. Other partial refresh cycles can refer to the relevant descriptions of frame periods F11_2 and F11_3 and be inferred by analogy, so they will not be repeated.

[0093] In the application example where the display panel 130 is a liquid crystal display panel, the liquid crystal display panel needs to maintain polarity balance so that there will be no charge residue problem caused by polarity imbalance, which will cause the panel to flicker. By controlling the timing of the additional reset pulse or the timing when the gate clock signal stops switching, the controller 111 can dynamically change the boundary between the high refresh rate display area and the low refresh rate display area in the local refresh frame cycle, and balance the positive and negative polarity of the data voltage of each horizontal display line of the display panel 130 in a global refresh cycle. The global refresh cycle includes at least two full refresh frame cycles (for example, frame cycles F11_1 and F11_4), and the positive and negative polarity changes of the data voltage of a whole frame are completed once in these two full refresh frame cycles.

[0094] Each global refresh cycle includes N total refresh frame cycles and M subsequent partial refresh frame cycles, where N≥1, M≥1. When the number of boundaries between the high refresh rate display area and the low refresh rate display area is not greater than the number of partial refresh frame cycles M in the global refresh cycle, the controller 111 can control the gate driver 120 so that the boundary transformation order in each global refresh cycle is the same. Fig.11 In the illustrated embodiment, N is 1 and M is 2, and the set number of boundaries is 2 (the boundaries dynamically change between two different positions). Fig.11 The order of boundary changes in each global brush cycle is shown to be the same.

[0095] When the boundary position changes dynamically, Fig.11 The embodiment shown can maintain the polarity balance of the data voltage of each pixel row in each global refresh cycle. For example, the horizontal display line GL11_1 has a total of 6 positive polarity drives and 6 negative polarity drives in the frame cycles F11_1 to F11_12, so it is polarity balanced. For another example, the horizontal display line GL11_7 has a total of 6 positive polarity drives and 6 negative polarity drives in the frame cycles F11_1 to F11_12, so it is also polarity balanced.

[0096] Fig.12 FIG. 4 is a schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to another embodiment of the present invention. Fig.12 The horizontal axis represents time. Fig.12 In the figure, “+” indicates positive polarity drive, and “-” indicates negative polarity drive. Fig.12 GL12_1, GL12_2, GL12_3, GL12_4, GL12_5, GL12_6, GL12_7, GL12_8, GL12_9 and GL12_10 represent different horizontal display lines (scanning lines, see Figure 3 The related descriptions of the scan lines GL1, GL2 and GL3 are shown and the same can be applied). Fig.12 A plurality of frame periods F12_1, F12_2, F12_3, F12_4, F12_5, F12_6, F12_7, F12_8, F12_9, F12_10, F12_11 and F12_12 are shown, wherein the frame periods F12_1, F12_4, F12_7 and F12_10 are all refresh frame periods (refer to Figure 4 The frame periods F12_2, F12_5, F12_8 and F12_11 are first partial refresh frame periods (refer to Figure 4The frame periods F12_3, F12_6, F12_9 and F12_12 are the second partial refresh frame periods (refer to Figure 4 The relevant description of the frame period F3 shown and the same can be applied).

[0097] Fig.12 The illustrated embodiment can be referred to Fig.11 The relevant description of the embodiment shown in the figure can be inferred by analogy. Fig.11 The set number of boundaries in the illustrated embodiment is 2, Fig.12 The number of boundaries set in the illustrated embodiment is 4 (the boundaries are dynamically changed at four different positions), wherein the first boundary position is between the horizontal display lines GL12_6 and GL12_7, the second boundary position is between the horizontal display lines GL12_7 and GL12_8, the third boundary position is between the horizontal display lines GL12_8 and GL12_9, and the fourth boundary position is between the horizontal display lines GL12_9 and GL12_10.

[0098] Each global refresh cycle includes N total refresh frame cycles and M subsequent partial refresh frame cycles, where N≥1, M≥1. When the set number of boundaries between the high refresh rate display area and the low refresh rate display area is greater than the number of partial refresh frame cycles M in the global refresh cycle, the controller 111 controls the gate driver 120 to make the boundary change order in the first global refresh cycle different from the boundary change order in the second global refresh cycle, where each of the first global refresh cycle and the second global refresh cycle includes at least one global refresh cycle. Fig.12 In the illustrated embodiment, N is 1 and M is 2, and the set number of boundaries is 4 (the boundaries are dynamically changed at four different positions). Therefore, the controller 111 controls the gate driver 120 so that the boundary change order in the first global brush cycle (frame periods F12_1 to F12_6) is different from the boundary change order in the second global brush cycle (frame periods F12_7 to F12_12).

[0099] Fig.13 FIG. 4 is a schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to yet another embodiment of the present invention. Fig.13 The horizontal axis represents time. Fig.13 In the figure, “+” indicates positive polarity drive, and “-” indicates negative polarity drive. Fig.13 GL13_1, GL13_2, GL13_3, GL13_4, GL13_5, GL13_6, GL13_7, GL13_8, GL13_9 and GL13_10 represent different horizontal display lines (scanning lines, see Figure 3The related descriptions of the scan lines GL1, GL2 and GL3 are shown and the same can be applied). Fig.13 A plurality of frame periods F13_1, F13_2, F13_3, F13_4, F13_5, F13_6, F13_7, F13_8, F13_9, F13_10, F13_11 and F13_12 are shown, wherein the frame periods F13_1, F13_6 and F13_14 are all refresh frame periods (refer to Figure 4 The frame periods F13_2, F13_7 and F13_12 are first partial refresh frame periods (refer to Figure 4 The frame periods F13_3 and F13_8 are the second partial refresh frame periods (refer to Figure 4 The frame periods F13_4 and F13_9 are third partial refresh frame periods, and the frame periods F13_5 and F13_10 are fourth partial refresh frame periods.

[0100] Fig.13 The illustrated embodiment can be referred to Fig.11 The relevant description of the embodiment shown in the figure can be inferred by analogy. Fig.13 In the illustrated embodiment, the number of boundaries is set to 4 and one local refresh cycle has 4 local refresh frame periods. The first boundary position is between the horizontal display lines GL13_6 and GL13_7, the second boundary position is between the horizontal display lines GL13_7 and GL13_8, the third boundary position is between the horizontal display lines GL13_8 and GL13_9, and the fourth boundary position is between the horizontal display lines GL13_9 and GL13_10. Fig.13 In the illustrated embodiment, the total number of refresh frame periods N in each global refresh cycle is 1, the number of partial refresh frame periods M in each global refresh cycle is 4, and the number of boundaries is 4 (the boundaries are dynamically changed at four different positions). Because the number of boundaries between the high refresh rate display area and the low refresh rate display area is not greater than the number of partial refresh frame periods M in the global refresh cycle, Fig.13 The order of boundary changes in each global brush cycle is shown to be the same.

[0101] Fig.14 A schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to yet another embodiment of the present invention. Fig.14 The horizontal axis represents time. Fig.12 In the figure, “+” indicates positive polarity drive, and “-” indicates negative polarity drive. Fig.14GL14_1, GL14_2, GL14_3, GL14_4, GL14_5, GL14_6, GL14_7, GL14_8, GL14_9 and GL14_10 represent different horizontal display lines (scanning lines, see Figure 3 The related descriptions of the scan lines GL1, GL2 and GL3 are shown and the same can be applied). Fig.14 A plurality of frame periods F14_1, F14_2, F14_3, F14_4, F14_5, F14_6, F14_7, F14_8, F14_9, F14_10, F14_11, F14_12, F14_13, F14_14, F14_15, F14_16, F14_17, F14_18, F14_19, F14_20, F14_21 are shown , F14_22, F14_23 and F14_24, wherein the frame periods F14_1, F14_2, F14_4, F14_5, F14_7, F14_8, F14_10, F14_11, F14_13, F14_14, F14_16, F14_17, F14_19, F14_20, F14_22 and F14_23 are all refresh frame periods (refer to Figure 4 The frame periods F14_3, F14_6, F14_9, F14_12, F14_15, F14_18, F14_21 and F14_24 are partial refresh frame periods (refer to Figure 4 The relevant description of the frame period F2 shown and the same can be applied).

[0102] Fig.14 The illustrated embodiment can be referred to Fig.11 The relevant description of the embodiment shown in the figure can be inferred by analogy. Fig.14 In the illustrated embodiment, the number of boundaries is set to 4 and one local refresh cycle has one local refresh frame period. The first boundary position is between the horizontal display lines GL14_6 and GL14_7, the second boundary position is between the horizontal display lines GL14_7 and GL14_8, the third boundary position is between the horizontal display lines GL14_8 and GL14_9, and the fourth boundary position is between the horizontal display lines GL14_9 and GL14_10. Fig.14 In the illustrated embodiment, the total number of refresh frame periods N in each global refresh cycle is 2, the number of partial refresh frame periods M in each global refresh cycle is 1, and the set number of boundaries is 4 (the boundaries are dynamically transformed at four different positions). Because the set number of boundaries between the high refresh rate display area and the low refresh rate display area is greater than the number of partial refresh frame periods M in the global refresh cycle, the controller 111 controls the gate driver 120 so that different global refresh cycles have different boundary transformation orders.

[0103] Fig.15 A schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to another embodiment of the present invention. Fig.15 The horizontal axis represents time. Fig.15 In the figure, “+” indicates positive polarity drive, and “-” indicates negative polarity drive. Fig.15 GL15_1, GL15_2, GL15_3, GL15_4, GL15_5, GL15_6, GL15_7, GL15_8, GL15_9 and GL15_10 represent different horizontal display lines (scanning lines, see Figure 3 The related descriptions of the scan lines GL1, GL2 and GL3 are shown and the same can be applied). Fig.15 A plurality of frame periods F15_1, F15_2, F15_3, F15_4, F15_5, F15_6, F15_7, F15_8, F15_9, F15_10, F15_11 and F15_12 are shown, wherein the frame periods F15_1, F15_4, F15_7 and F15_10 are all refresh frame periods (refer to Figure 4 The frame periods F15_2, F15_5, F15_8 and F15_11 are first partial refresh frame periods (refer to Figure 4 The frame periods F15_3, F15_6, F15_9 and F15_12 are the second partial refresh frame periods (refer to Figure 4 The relevant description of the frame period F3 shown and the same can be applied).

[0104] Fig.15 The number and location of the boundary settings of the illustrated embodiment are similar Fig.12 As shown, the total refresh frame period number N of each global refresh cycle is 1, the local refresh frame period number M of each global refresh cycle is 2, and the set number of boundaries is 4, and the boundaries are dynamically changed at four different positions, wherein the first boundary position is between the horizontal display lines GL15_6 and GL15_7, the second boundary position is between the horizontal display lines GL15_7 and GL15_8, the third boundary position is between the horizontal display lines GL15_8 and GL15_9, and the fourth boundary position is between the horizontal display lines GL15_9 and GL15_10. However, as Fig.15 In the embodiment shown, the controller 111 does not have Fig.12Instead of controlling the gate driver 120 to change the boundary transformation order according to the global refresh cycle, different boundary transformation orders are applied in different global refresh cycles, resulting in a polarity imbalance. For example, it can be seen that the number of frames in which the horizontal display lines GL15_7 and GL15_8 are maintained at positive polarity is greater than the number of frames in which they are maintained at negative polarity in the global refresh cycle (F15_1 to F15_6) or the next global refresh cycle (F15_7 to F15_14).

[0105] Fig.16 A schematic diagram showing a dynamic change in the boundary position between a high refresh rate display area and a low refresh rate display area according to yet another embodiment of the present invention. Fig.16 The horizontal axis represents time. Fig.16 In the figure, “+” indicates positive polarity drive, and “-” indicates negative polarity drive. Fig.16 GL16_1, GL16_2, GL16_3, GL16_4, GL16_5, GL16_6, GL16_7, GL16_8, GL16_9 and GL16_10 represent different horizontal display lines (scanning lines, see Figure 3 The related descriptions of the scan lines GL1, GL2 and GL3 are shown and the same can be applied). Fig.16 A plurality of frame periods F16_1, F16_2, F16_3, F16_4, F16_5, F16_6, F16_7, F16_8, F16_9, F16_10, F16_11, F16_12, F16_13, F16_14, F16_15, F16_16, F16_17 and F16_18 are shown, wherein the frame periods F16_1, F16_3, F16_5, F16_7, F16_9, F16_11, F16_13, F16_15 and F16_17 are all refresh frame periods (refer to Figure 4 The frame periods F16_2, F16_4, F16_6, F16_8, F16_10, F16_12, F16_14, F16_16 and F16_18 are partial refresh frame periods (refer to Figure 4 The relevant description of the frame period F2 shown and the same can be applied).

[0106] Fig.16 The illustrated embodiment can be referred to Fig.11 The relevant description of the embodiment shown in the figure can be inferred by analogy. Fig.11 ,exist Fig.16In the illustrated embodiment, the display driver chip 110 changes the positive and negative polarity of the output data voltage every two frame periods, the total refresh frame period number N of each global refresh period is 1, the local refresh frame period number M of each global refresh period is 1, and the set number of boundaries is 5 (the boundaries are dynamically changed at five different positions). Among them, the first boundary position is between the horizontal display lines GL15_4 and GL15_5, the second boundary position is between the horizontal display lines GL15_6 and GL15_7, the third boundary position is between the horizontal display lines GL15_7 and GL15_8, the fourth boundary position is between the horizontal display lines GL15_8 and GL15_9, and the fifth boundary position is between the horizontal display lines GL15_9 and GL15_10. The number 5 is a limited description of the drawing, and can actually be any value that does not exceed the maximum number of boundary positions. When the display driver chip 110 switches the polarity of the output data voltage every two frame periods, the controller 111 controls the gate driver 120 to allow the boundary between the high refresh rate display area and the low refresh rate display area to be arbitrarily changed.

[0107] In summary, the display driver chip 110 can refresh data in both the high refresh rate display area and the low refresh rate display area in all refresh frame cycles. In the local refresh frame cycle, the high refresh rate display area refreshes data and the low refresh rate display area does not refresh data. Therefore, the low refresh rate display area of ​​the display area of ​​the display panel 130 is not refreshed in each local refresh frame cycle, so that the refresh rate of the low refresh rate display area of ​​the display panel 130 can be different from the high refresh rate display area of ​​the display panel. Based on the control of the gate driver 120 by the display driver chip 110, the display device 100 can make different display partitions in the same display panel have different refresh rates adaptively. In addition, the display driver chip 110 can dynamically change the boundary position between the adjacent high refresh rate display area and the low refresh rate display area to blur the visual effect difference of the partition boundary, thereby improving the visual effect. By dynamically changing the partition boundary position, the display driver chip 110 can also reduce the aging difference of the display panel 130 on both sides of the partition boundary position.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display driver chip, characterized in that: The display driver chip comprises: A controller, used to control a gate driver of a display panel to be driven by the display driver chip, wherein the gate driver is used to drive a plurality of scan lines of the display panel, wherein a display area of ​​the display panel includes adjacent high refresh rate display areas and low refresh rate display areas, and the display panel displays data in a plurality of frame periods, wherein the plurality of frame periods include at least one full refresh frame period and at least one partial refresh frame period, wherein the high refresh rate display area and the low refresh rate display area both refresh data in the full refresh frame period, and wherein the high refresh rate display area refreshes data and the low refresh rate display area does not refresh data in the partial refresh frame period; The controller controls the gate driver so that in the multiple frame periods, the boundary between the high refresh rate display area and the low refresh rate display area in the first partial refresh frame period and the boundary between the high refresh rate display area and the low refresh rate display area in the second partial refresh frame period are different.

2. The display driver chip according to claim 1, characterized in that: In the first local refresh frame period and the second local refresh frame period, the controller transmits a reset pulse to the gate driver at a first time point to start generating multiple scan pulses corresponding to the high refresh rate display area, after the data in the high refresh rate display area is refreshed in the first local refresh frame period, the controller transmits an additional reset pulse to the gate driver at a second time point to clear the scan pulse in the gate driver, and, after the data in the high refresh rate display area is refreshed in the second local refresh frame period, the controller transmits the additional reset pulse to the gate driver at a third time point to clear the scan pulse in the gate driver.

3. The display driver chip according to claim 2, characterized in that: After the data in the high refresh rate display area is refreshed in the first partial refresh frame period or the second partial refresh frame period, the controller stops switching the multiple gate clock signals output by the controller to the gate driver from the point of transmitting the additional reset pulse.

4. The display driver chip according to claim 1, characterized in that: In the first local refresh frame period and the second local refresh frame period, the controller transmits a reset pulse to the gate driver at a first time point to start generating multiple scan pulses corresponding to the high refresh rate display area, and after the data in the high frame rate display area is refreshed, the controller stops the switching behavior of the multiple gate clock signals output by the controller to the gate driver from a second time point and does not transmit an additional reset pulse to the gate driver.

5. The display driver chip according to claim 1, characterized in that: The display driver chip also includes: a source driver coupled to the controller, for driving a plurality of data lines of the display panel based on control of the controller, wherein the controller enables the source driver before a first time point in the first partial refresh frame period and the second partial refresh frame period, and the controller disables an analog domain circuit or a digital domain circuit of the source driver after at least one of a second time point in the first partial refresh frame period and a third time point in the second partial refresh frame period, Among them, the first time point is the time point when the controller transmits a reset pulse, the second time point or the third time point is the time point when the controller transmits an additional reset pulse or the time point when the controller stops outputting switching behavior of multiple gate clock signals to the gate driver, the additional reset pulse and the reset pulse are in the same frame cycle and later than the reset pulse, and the second time point and the third time point are both after the high refresh rate display area has completed display.

6. The display driver chip according to claim 1, characterized in that: The display panel is a liquid crystal display panel, and the controller changes the boundary between the high refresh rate display area and the low refresh rate display area in a local refresh frame period by controlling the timing of an additional reset pulse or the timing when a gate clock signal stops switching, and balances the positive and negative polarities of the data voltage of each horizontal display line of the display panel within a global refresh cycle.

7. The display driver chip according to claim 6, characterized in that: The global refresh cycle includes at least two full refresh frame periods, and the positive and negative polarity changes of the data voltage of a whole frame are completed once in the two full refresh frame periods.

8. The display driver chip according to claim 6, characterized in that: The multiple frame cycles include multiple global refresh cycles, each global refresh cycle includes N total refresh frame cycles and M subsequent local refresh frame cycles, N≥1, M≥1, when the set number of boundaries between the high refresh rate display area and the low refresh rate display area is not greater than the number of local refresh frame cycles (M) in the global refresh cycle, the controller controls the gate driver so that the boundary change order in each global refresh cycle is the same.

9. The display driver chip according to claim 6, characterized in that: The multiple frame cycles include multiple global brush cycles, each global brush cycle includes N total refresh frame cycles and M subsequent local refresh frame cycles, N≥1, M≥1, when the set number of boundaries between the high refresh rate display area and the low refresh rate display area is greater than the number of local refresh frame cycles (M) in the global brush cycle, the controller controls the gate driver so that the boundary change order in the first global brush cycle and the boundary change order in the second global brush cycle are different, wherein each of the first global brush cycle and the second global brush cycle includes at least one global brush cycle.

10. The display driver chip according to claim 6, characterized in that: When the display driver chip switches the positive and negative polarities of the output data voltage every two frame periods, the controller controls the gate driver to cause the boundary between the high refresh rate display area and the low refresh rate display area to change positions arbitrarily.

11. A display driving method, characterized in that: The display driving method comprises: The display panel and the gate driver are controlled by a display driver chip so that the display panel displays data in a plurality of frame periods, wherein the display area of ​​the display panel includes adjacent high refresh rate display areas and low refresh rate display areas, and the plurality of frame periods include at least one full refresh frame period and at least one partial refresh frame period; The gate driver is controlled by a controller of the display driver chip so that the high refresh rate display area and the low refresh rate display area both refresh data in the entire refresh frame period, and the high refresh rate display area refreshes data and the low refresh rate display area does not refresh data in the partial refresh frame period; and The gate driver is controlled by the controller so that in the multiple frame periods, the boundary between the high refresh rate display area and the low refresh rate display area in the first partial refresh frame period and the boundary between the high refresh rate display area and the low refresh rate display area in the second partial refresh frame period are different.

12. The display driving method according to claim 11, characterized in that: The display driving method further includes: In the first local refresh frame period and the second local refresh frame period, the controller transmits a reset pulse to the gate driver at a first time point to start generating multiple scan pulses corresponding to the high refresh rate display area, and after the data in the high refresh rate display area is refreshed in the first local refresh frame period, the controller transmits an additional reset pulse to the gate driver at a second time point to clear the scan pulse in the gate driver, and after the data in the high refresh rate display area is refreshed in the second local refresh frame period, the controller transmits the additional reset pulse to the gate driver at a third time point to clear the scan pulse in the gate driver.

13. The display driving method according to claim 12, characterized in that: The display driving method further includes: In the first local refresh frame period or the second local refresh frame period, after the data in the high refresh rate display area is refreshed, the controller stops switching multiple gate clock signals output by the controller to the gate driver from the point of time when the additional reset pulse is transmitted.

14. The display driving method according to claim 11, characterized in that: The display driving method further includes: In the first local refresh frame period and the second local refresh frame period, the controller transmits a reset pulse to the gate driver at a first time point to start generating a plurality of scan pulses corresponding to the high refresh rate display area, and after the data in the high frame rate display area is refreshed, the controller stops the switching of a plurality of gate clock signals output by the controller to the gate driver from a second time point and does not transmit an additional reset pulse to the gate driver.

15. The display driving method according to claim 11, characterized in that: The display driving method further includes: The source driver of the display driver chip drives a plurality of data lines of the display panel based on the control of the controller. The controller enables the source driver before a first time point in the first partial refresh frame period and the second partial refresh frame period, and The controller disables the analog domain circuit or the digital domain circuit of the source driver after at least one of a second time point in the first partial refresh frame period and a third time point in the second partial refresh frame period, Among them, the first time point is the time point when the controller transmits a reset pulse, the second time point or the third time point is the time point when the controller transmits an additional reset pulse or the time point when the controller stops outputting switching behavior of multiple gate clock signals to the gate driver, the additional reset pulse and the reset pulse are in the same frame cycle and later than the reset pulse, and the second time point and the third time point are both after the high refresh rate display area has completed display.

16. The display driving method according to claim 11, characterized in that: The display panel is a liquid crystal display panel, and the display driving method further includes: The controller changes the boundary between the high refresh rate display area and the low refresh rate display area in a local refresh frame period by controlling the timing of an additional reset pulse or the timing when the gate clock signal stops switching, and balances the positive and negative polarities of the data voltage of each horizontal display line of the display panel within a global refresh cycle.

17. The display driving method according to claim 16, characterized in that: The global refresh cycle includes at least two full refresh frame periods, and the positive and negative polarity changes of the data voltage of a whole frame are completed once in the two full refresh frame periods.

18. The display driving method according to claim 16, characterized in that: The plurality of frame periods include a plurality of global refresh periods, each global refresh period includes N total refresh frame periods and M subsequent local refresh frame periods, N≥1, M≥1, and the display driving method further includes: When the set number of boundaries between the high refresh rate display area and the low refresh rate display area is not greater than the number of local refresh frame cycles (M) in the global refresh cycle, the controller controls the gate driver so that the boundary change order in each global refresh cycle is the same.

19. The display driving method according to claim 16, characterized in that: The plurality of frame periods include a plurality of global refresh periods, each global refresh period includes N total refresh frame periods and M subsequent local refresh frame periods, N≥1, M≥1, and the display driving method further includes: When the set number of boundaries between the high refresh rate display area and the low refresh rate display area is greater than the number of local refresh frame cycles (M) in the global brush cycle, the controller controls the gate driver to cause a boundary change order in a first global brush cycle and a boundary change order in a second global brush cycle to be different, wherein each of the first global brush cycle and the second global brush cycle includes at least one global brush cycle.

20. The display driving method according to claim 16, characterized in that: The display driving method further includes: When the display driver chip switches the positive and negative polarities of the output data voltage every two frame periods, the controller controls the gate driver to cause the boundary between the high refresh rate display area and the low refresh rate display area to change positions arbitrarily.

21. A display device, characterized in that: The display device comprises: A display panel, wherein a display area of ​​the display panel includes adjacent high refresh rate display areas and low refresh rate display areas, and the display panel displays data in a plurality of frame periods, wherein the plurality of frame periods include at least one full refresh frame period and at least one partial refresh frame period; a gate driver coupled to a plurality of scan lines of the liquid crystal display panel, wherein the gate driver is used to drive the plurality of scan lines of the display panel; and a display driver chip coupled to the gate driver, wherein the display driver chip controls the gate driver so that the high refresh rate display area and the low refresh rate display area both refresh data in the entire refresh frame period, and the high refresh rate display area refreshes data and the low refresh rate display area does not refresh data in the partial refresh frame period; The display driver chip controls the gate driver so that in the multiple frame periods, the boundary between the high refresh rate display area and the low refresh rate display area in the first partial refresh frame period is different from the boundary between the high refresh rate display area and the low refresh rate display area in the second partial refresh frame period.

22. The display device according to claim 21, characterized in that The display driver chip comprises: A controller for controlling the gate driver, wherein the controller controls the gate driver so that in the multiple frame periods, a boundary between the high refresh rate display area and the low refresh rate display area in the first partial refresh frame period and a boundary between the high refresh rate display area and the low refresh rate display area in the second partial refresh frame period are different.

23. The display device according to claim 22, characterized in that In the first local refresh frame period and the second local refresh frame period, the controller transmits a reset pulse to the gate driver at a first time point to start generating multiple scan pulses corresponding to the high refresh rate display area, after the data in the high refresh rate display area is refreshed in the first local refresh frame period, the controller transmits an additional reset pulse to the gate driver at a second time point to clear the scan pulse in the gate driver, and, after the data in the high refresh rate display area is refreshed in the second local refresh frame period, the controller transmits the additional reset pulse to the gate driver at a third time point to clear the scan pulse in the gate driver.

24. The display device according to claim 23, characterized in that After the data in the high refresh rate display area is refreshed in the first partial refresh frame period or the second partial refresh frame period, the controller stops switching the multiple gate clock signals output by the controller to the gate driver from the point of transmitting the additional reset pulse.

25. The display device according to claim 22, characterized in that In the first local refresh frame period and the second local refresh frame period, the controller transmits a reset pulse to the gate driver at a first time point to start generating multiple scan pulses corresponding to the high refresh rate display area, and after the data in the high frame rate display area is refreshed, the controller stops the switching behavior of the multiple gate clock signals output by the controller to the gate driver from a second time point and does not transmit an additional reset pulse to the gate driver.

26. The display device according to claim 22, characterized in that The display driver chip also includes: a source driver coupled to the controller, for driving a plurality of data lines of the display panel based on control of the controller, wherein the controller enables the source driver before a first time point in the first partial refresh frame period and the second partial refresh frame period, and the controller disables an analog domain circuit or a digital domain circuit of the source driver after at least one of a second time point in the first partial refresh frame period and a third time point in the second partial refresh frame period, Among them, the first time point is the time point when the controller transmits a reset pulse, the second time point or the third time point is the time point when the controller transmits an additional reset pulse or the time point when the controller stops outputting switching behavior of multiple gate clock signals to the gate driver, the additional reset pulse and the reset pulse are in the same frame cycle and later than the reset pulse, and the second time point and the third time point are both after the high refresh rate display area has completed display.

27. The display device according to claim 22, characterized in that The display panel is a liquid crystal display panel, and the controller changes the boundary between the high refresh rate display area and the low refresh rate display area in a local refresh frame period by controlling the timing of an additional reset pulse or the timing when a gate clock signal stops switching, and balances the positive and negative polarities of the data voltage of each horizontal display line of the display panel within a global refresh cycle.

28. The display device according to claim 27, characterized in that The global refresh cycle includes at least two full refresh frame periods, and the positive and negative polarity changes of the data voltage of a whole frame are completed once in the two full refresh frame periods.

29. The display device according to claim 27, characterized in that The multiple frame cycles include multiple global refresh cycles, each global refresh cycle includes N total refresh frame cycles and M subsequent local refresh frame cycles, N≥1, M≥1, when the set number of boundaries between the high refresh rate display area and the low refresh rate display area is not greater than the number of local refresh frame cycles (M) in the global refresh cycle, the controller controls the gate driver so that the boundary change order in each global refresh cycle is the same.

30. The display device according to claim 27, characterized in that The multiple frame cycles include multiple global brush cycles, each global brush cycle includes N total refresh frame cycles and M subsequent local refresh frame cycles, N≥1, M≥1, when the set number of boundaries between the high refresh rate display area and the low refresh rate display area is greater than the number of local refresh frame cycles (M) in the global brush cycle, the controller controls the gate driver so that the boundary change order in the first global brush cycle and the boundary change order in the second global brush cycle are different, wherein each of the first global brush cycle and the second global brush cycle includes at least one global brush cycle.

31. The display device according to claim 27, characterized in that When the display driver chip switches the positive and negative polarities of the output data voltage every two frame periods, the controller controls the gate driver to cause the boundary between the high refresh rate display area and the low refresh rate display area to change positions arbitrarily.

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