Refreshing method, device and equipment for high-bandwidth memory HBM

Abstract

The invention discloses a method, a device and equipment for refreshing a high-bandwidth memory HBM, and the method comprises the steps: dividing storage regions of different storage chips in advance, and carrying out the statistics of the number of errors that storage data cannot be correctly recognized in each storage region; according to the number of errors corresponding to different storage areas, determining the danger level of data loss corresponding to each storage area; and determining the refreshing frequency of the storage area according to the danger level of each storage area, and only refreshing the storage area when the corresponding refreshing time is reached. Therefore, the problems that a DRAM storage array still has a large data failure risk due to an existing ECC error correction mechanism, the self-refresh frequency is increased, and the Dram power consumption can be improved are solved.

Description

Background Art

[0002] DRAM (Dynamic Random Access Memory) uses capacitors to store data. Even if the power is on, the information will be lost as time and temperature change. Therefore, it must be refreshed at regular intervals, which is called a refresh cycle.

[0003] The charge retention time of storage cells in DRAM storage arrays is strongly correlated with temperature, and leakage current is more likely to cause storage failure at high temperatures. Therefore, high temperatures can easily lead to increased leakage current, and DRAM storage arrays are more likely to have retention problems, bringing risks to the reliability and stability of the on-chip system (Session Initialization Protocol, SIP). Especially for HBM (High Bandwidth Memory), the multi-layer stacked chips on the chip lead to complex on-chip thermal distribution and thermal characteristics, and the retention problem caused by temperature is more significant.

[0004] At present, the common solution to the retention problem of DRAM storage arrays is to detect and correct data storage errors through on-chip ECC (Error Checking and Correcting), but the ECC error correction capability is limited. When there are many retention failures, it cannot be corrected, resulting in a large risk of data failure in the DRAM storage array. Increasing the self-refresh frequency will increase the power consumption of DRAM. Summary of the invention

[0005] The purpose of the present application is to provide a refresh method, device and equipment for a high bandwidth memory HBM, which is used to solve the problem that the existing ECC error correction mechanism still has a large risk of data failure in the DRAM storage array, and increasing the self-refresh frequency will increase the power consumption of DRAM.

[0006] In a first aspect, an embodiment of the present application provides a method for refreshing a high bandwidth memory HBM, the method comprising:

[0007] According to the pre-division of storage areas of different storage chips, the number of errors in each storage area that cannot correctly identify the stored data is counted;

[0008] According to the number of errors corresponding to different storage areas, the risk level of data loss corresponding to each storage area is determined;

[0009] The refresh frequency of each storage area is determined according to the danger level of the storage area, and when the corresponding refresh time is reached, only the storage area is refreshed.

[0010] In some possible embodiments, the method further includes:

[0011] Use temperature sensors to obtain the temperature of different storage areas;

[0012] The refresh frequency of each storage area is determined according to the danger level of the storage area, including:

[0013] The refresh frequency of each storage area is determined according to the danger level and temperature of the storage area.

[0014] Determine the refresh frequency of each storage area based on the danger level and temperature of the storage area, including:

[0015] Determine the initial refresh frequency corresponding to the danger level of each storage area according to the preset refresh frequencies corresponding to different danger levels;

[0016] According to different preset temperature ranges, and according to the temperature range corresponding to each storage area, the initial refresh frequency of the storage area is adjusted accordingly.

[0017] In some possible embodiments, according to the temperature range corresponding to each storage area, the initial refresh frequency of the storage area is adjusted accordingly, including:

[0018] According to the preset gear refresh frequencies corresponding to different temperature ranges and according to the gear refresh frequencies corresponding to each storage area, the initial refresh frequency of the storage area is adjusted.

[0019] In some possible embodiments, adjusting the initial refresh frequency of each storage area according to the gear refresh frequency corresponding to the storage area includes:

[0020] Determine that the gear refresh frequency corresponding to any storage area is greater than the initial refresh frequency setting degree corresponding to the storage area, increase the initial refresh frequency of the storage area, and obtain the refresh frequency of the storage area;

[0021] Otherwise, the initial refresh frequency of the storage area is determined as the refresh frequency of the storage area.

[0022] In some possible embodiments, counting the number of errors in each storage area that cannot correctly identify stored data includes:

[0023] Different memory chips are refreshed using a default refresh frequency, and the number of errors at different storage locations on different memory chips is counted.

[0024] In some possible embodiments, the danger level includes a low danger level and a high danger level, and the refresh frequency of each storage area is determined according to the danger level of the storage area, including:

[0025] When it is determined that the danger level of any storage area reaches a high danger level, a self-refresh of the storage area is triggered once based on the default refresh frequency;

[0026] After the storage area is refreshed, the number of errors is reset to zero, and the number of errors in the storage area that cannot correctly identify the stored data begins to be counted again.

[0027] In some possible embodiments, refreshing different memory chips using a default refresh frequency includes:

[0028] Use temperature sensors to obtain the temperature of different storage areas;

[0029] Determine the target gear refresh frequency corresponding to the temperature range where the current temperature of any storage area is located according to the preset gear refresh frequencies corresponding to different temperature ranges;

[0030] The target gear refresh frequency of the storage area is used as the default refresh frequency of the storage area, and the storage chip is refreshed using the default refresh frequency.

[0031] In some possible embodiments, determining the risk level of data loss corresponding to each storage area according to the number of errors corresponding to different storage areas includes:

[0032] The number of errors in the storage area is compared with the thresholds set for different risk levels to determine the risk level of data loss corresponding to each storage area.

[0033] In some possible embodiments, the method is applied to a logic processing chip to count the number of errors in each storage area that cannot correctly identify stored data, including:

[0034] Obtaining, from the error checking and correction control unit of each memory chip, the number of errors in each memory area that cannot correctly identify the stored data;

[0035] When the corresponding refresh time arrives, only the storage area is refreshed, including:

[0036] When the corresponding refresh time arrives, the sub-word line driver SWD of the corresponding memory chip is controlled to refresh only the memory area.

[0037] In a second aspect, an embodiment of the present application provides a refresh device for a high bandwidth memory HBM, the device comprising:

[0038] The error count module is used to count the number of errors in each storage area that cannot correctly identify the stored data according to the pre-division of storage areas of different storage chips;

[0039] A risk level determination module, used to determine the risk level of data loss corresponding to each storage area according to the number of errors corresponding to different storage areas;

[0040] The partition refresh module is used to determine the refresh frequency of each storage area according to the danger level of the storage area, and refresh only the storage area when the corresponding refresh time arrives.

[0041] In the third aspect, another embodiment of the present application also provides a device of a high-bandwidth memory HBM, comprising at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any refresh method of the high-bandwidth memory HBM provided in the embodiment of the present application.

[0042] In a fourth aspect, another embodiment of the present application further provides a computer storage medium, wherein the computer storage medium stores a computer program, and the computer program is used to enable a computer to execute any high bandwidth memory HBM refresh method provided in the embodiments of the present application.

[0043] The refresh method, device and equipment of the high-bandwidth memory HBM provided in the embodiment of the present application perform partition management on the storage chip, determine the corresponding danger level by counting the number of errors in each storage area respectively; determine the refresh frequency of each storage area according to the danger level, and refresh each storage according to its own refresh frequency. In this way, when the refresh time of a certain storage area is reached, only the storage area is refreshed, and other storage areas that have not reached the refresh time are not refreshed. In this way, error correction of some areas can be implemented in a targeted manner, and the error correction frequencies of different storages are different, which can reduce the risk of data loss within the error correction capability, reduce the self-refresh frequency, and reduce the power consumption of DRAM.

[0044] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings introduced below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A schematic diagram of charge disappearance of a DRAM in the related art;

[0047] Figure 2 A schematic diagram of an application scenario according to an embodiment of the present disclosure;

[0048] Figure 3 A schematic diagram of a refresh method for a high bandwidth memory HBM according to an embodiment of the present disclosure;

[0049] Figure 4 A schematic diagram of the HBM structure according to an embodiment of the present disclosure;

[0050] Figure 5 A schematic diagram of a refresh device for a high bandwidth memory HBM according to an embodiment of the present disclosure;

[0051] Figure 6 The figure is a structural diagram of a refresh device of a high bandwidth memory HBM according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] To further illustrate the technical solution provided by the embodiment of the present application, this is described in detail below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiment of the present application provides the method operation steps as shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on routine or no creative labor. In the steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided by the embodiment of the present application. The method can be executed in the order of the method shown in the embodiment or drawings or in parallel during the actual processing process or when the control device is executed.

[0053] The 1T1C (transistor and capacitor) unit has a complex leakage current mechanism in the MOS (Metal-Oxide-Semiconductor) transistor. When saving data, the MOS transistor cannot be completely turned off, which will cause the charge on the capacitor to gradually lose. The leakage current mainly includes the reverse saturation current of the pn junction, the subthreshold current and the gate leakage current. The leakage current is also affected by temperature, so the DRAM storage array is more prone to retention problems. Figure 1The figure shows the relationship between the number of failed nodes and time, with time as the horizontal axis. Currently, the ECC error correction capability is limited. When there are many retention failures, it cannot be corrected, resulting in a high risk of data failure in the DRAM storage array. Increasing the self-refresh refresh frequency will increase the DRAM power consumption (IDD6).

[0054] In view of the fact that the DRAM storage array still has a large risk of data failure due to the ECC error correction mechanism in the related art, increasing the self-refresh frequency will increase the power consumption of DRAM. The present application proposes a refresh method, device and equipment for a high bandwidth memory HBM.

[0055] In view of this, the invention concept of the present application is as follows: partition management of the storage chip, determine the corresponding danger level by counting the number of errors in each storage area respectively; determine the refresh frequency of each storage area according to the danger level, and refresh each storage according to its own refresh frequency.

[0056] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings.

[0057] The refresh method of the high bandwidth memory HBM in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0058] See also Figure 2 , is a schematic diagram of an application environment according to an embodiment of the present application.

[0059] HBM is a high-bandwidth, high-speed DRAM memory composed of 3D stacking. Its DRAM chips (DRAM Dies) are connected by silicon through vias. Through 3D stacking, HBM breaks through the bottleneck of memory capacity and bandwidth. Figure 2 As shown, the application environment may include, for example, different memory chips, specifically, HBM DRAM Die 10 , a logic processing chip (Logic Die) 20 , a silicon interposer (Interposer) 30 , and a package substrate (Package Substrate) 40 .

[0060] Figure 3 A schematic flow chart of a refresh method for a high bandwidth memory HBM provided by an embodiment of the present application is shown, including:

[0061] Step 301, based on the pre-division of storage areas of different storage chips, count the number of errors in each storage area that cannot correctly identify the stored data.

[0062] The memory chip in the embodiment of the present application is a HDM DRAM Die, and each HDM DRAM Die can be divided into regions to obtain different storage regions, each storage region including multiple storage locations. The specific storage region division method can be determined by those skilled in the art as needed.

[0063] After the HDM DRAM Die is divided into multiple corresponding storage areas, the storage locations in the storage areas are monitored for errors that cannot correctly identify the stored data. As mentioned above, the leakage of the basic storage units in the storage area will cause the charge on the capacitor to gradually lose. For data storage, if the charge on the capacitor is higher than the set threshold, it is considered to be the first bit, and if it is lower than the set threshold, it is considered to be the second bit value. Therefore, when the data is initially stored or refreshed, the charge at the storage location corresponding to the first bit is higher than the set threshold, and the charge at the storage location of the second bit is lower than the set threshold. However, as the charge is lost, the charge at the storage location corresponding to the first bit is lower than the set threshold, resulting in an identification error of the first bit as the second bit.

[0064] Step 302, determining the risk level of data loss corresponding to each storage area according to the number of errors corresponding to different storage areas.

[0065] In the embodiment of the present application, a corresponding counter can be set for each storage area, and the number of errors in each storage area can be counted respectively. Specifically, the number of errors in each storage area within a period of time can be counted, and storage areas with different numbers of errors can be distinguished. The correspondence between different error number ranges and danger levels can be pre-set, and the danger level of each storage area can be determined based on the number of errors in each storage area counted. In the embodiment of the present application, the more errors there are, the more serious the leakage of the storage area is, and the greater the risk of losing data is. The higher the corresponding danger level is, the fewer errors there are, which means that the leakage of the storage area is not serious, the risk of losing data is not great, and the corresponding danger level is lower.

[0066] Step 303: determine the refresh frequency of each storage area according to the danger level of the storage area, and refresh only the storage area when the corresponding refresh time arrives.

[0067] The embodiments of the present application can perform refreshes at different frequencies for different storage areas according to the risk of data loss in the storage areas. When the refresh time of a certain storage area is reached, only the storage area is refreshed, while other storage areas that have not reached the refresh time are not refreshed. On the one hand, this can achieve targeted error correction for some areas to avoid performing error correction on multiple storage chips at the same time and exceeding the error correction capability. On the other hand, it can also reduce the overall self-refresh frequency and reduce DRAM power consumption.

[0068] In one or more possible embodiments, the method further includes:

[0069] Use temperature sensors to obtain the temperature of different storage areas;

[0070] The refresh frequency of each storage area is determined according to the danger level of the storage area, including:

[0071] The refresh frequency of each storage area is determined according to the danger level and temperature of the storage area.

[0072] As mentioned above, high temperature can easily lead to increased leakage, and DRAM storage arrays are more prone to retention problems. In order to avoid the impact of temperature on the risk of data loss in the storage area, the embodiment of the present application can set at least one temperature sensor in each storage area to monitor the temperature of each storage area. The embodiment of the present application determines the refresh frequency of the storage area according to the danger level and temperature of each storage area. The higher the risk level, the higher the refresh frequency of the storage area, and the higher the temperature, the higher the refresh frequency of the storage area. Therefore, these two factors can be comprehensively considered to determine the refresh frequency of each storage area. One possible implementation method is to determine the refresh frequency corresponding to each storage area based on the danger level, and then adjust it based on the temperature of the storage area; another possible implementation method is to set different influence weights for the danger level and temperature, quantify the danger level and temperature, multiply the quantized value by the corresponding weight, obtain the corresponding comprehensive value, and determine the corresponding refresh frequency according to the comprehensive value.

[0073] In one or more possible embodiments, determining the refresh frequency of each storage area according to the danger level and temperature of the storage area includes:

[0074] Determine the initial refresh frequency corresponding to the danger level of each storage area according to the preset refresh frequencies corresponding to different danger levels;

[0075] According to different preset temperature ranges, and according to the temperature range corresponding to each storage area, the initial refresh frequency of the storage area is adjusted accordingly.

[0076] One possible frequency adjustment is to increase the initial refresh frequency of the storage area if the temperature range is higher than a corresponding threshold value, and the frequency increase is greater if the temperature range is higher.

[0077] In one or more possible embodiments, according to the temperature range corresponding to each storage area, the initial refresh frequency of the storage area is adjusted accordingly, including:

[0078] According to the preset gear refresh frequencies corresponding to different temperature ranges and according to the gear refresh frequencies corresponding to each storage area, the initial refresh frequency of the storage area is adjusted.

[0079] If the temperature range is larger, the corresponding gear refresh frequency is higher, and the temperature range is smaller, the corresponding gear refresh frequency is lower.

[0080] In one or more possible embodiments, adjusting the initial refresh frequency of each storage area according to the gear refresh frequency corresponding to each storage area includes:

[0081] Determine that the gear refresh frequency corresponding to any storage area is greater than the initial refresh frequency setting degree corresponding to the storage area, increase the initial refresh frequency of the storage area, and obtain the refresh frequency of the storage area;

[0082] Otherwise, the initial refresh frequency of the storage area is determined as the refresh frequency of the storage area.

[0083] Of course, there may be other ways to adjust the initial refresh frequency according to the gear refresh frequency.

[0084] In one or more possible embodiments, counting the number of errors in each storage area that cannot correctly identify stored data includes:

[0085] Different memory chips are refreshed using a default refresh frequency, and the number of errors at different storage locations on different memory chips is counted.

[0086] The present application can use the default refresh frequency for refresh, and count the number of errors in different storage areas under the default refresh frequency. One possible method is to determine whether to adjust the default refresh frequency used by the storage area based on the error count results after a period of statistics. For example, if the total number of errors is higher than a certain value, the default refresh frequency can be increased as the refresh frequency of the storage area. The higher the number of errors, the greater the increase in the refresh frequency. Another possible method is to trigger an additional refresh of the storage area when the number of errors in a certain storage area reaches a certain threshold based on the default refresh frequency, and clear the counter to re-count the number of errors.

[0087] In one or more possible embodiments, determining the risk level of data loss corresponding to each storage area according to the number of errors corresponding to different storage areas includes:

[0088] The number of errors in the storage area is compared with the thresholds set for different risk levels to determine the risk level of data loss corresponding to each storage area.

[0089] The thresholds for setting the above different danger levels can be determined through empirical values ​​or based on experiments.

[0090] In one or more possible embodiments, the danger level includes a low danger level and a high danger level, and determining the refresh frequency of each storage area according to the danger level of the storage area includes:

[0091] When it is determined that the danger level of any storage area reaches a high danger level, a self-refresh of the storage area is triggered once based on the default refresh frequency;

[0092] After the storage area is refreshed, the number of errors is reset to zero, and the number of errors in the storage area that cannot correctly identify the stored data begins to be counted again.

[0093] When the above-mentioned method of refreshing the storage area based on the default refresh frequency is adopted, the influence of temperature on leakage can be further considered. In one or more possible embodiments, refreshing different storage chips using the default refresh frequency includes:

[0094] Use temperature sensors to obtain the temperature of different storage areas;

[0095] Determine the target gear refresh frequency corresponding to the temperature range where the current temperature of any storage area is located according to the preset gear refresh frequencies corresponding to different temperature ranges;

[0096] The target gear refresh frequency of the storage area is used as the default refresh frequency of the storage area, and the storage chip is refreshed using the default refresh frequency.

[0097] In this way, by monitoring the temperature of each storage area, different default refresh frequencies can be adjusted adaptively according to the temperature.

[0098] In the embodiment of the present application, it is necessary to perform error detection on different positions of each storage area through an error checking and correction ECC control unit in the storage chip, and the ECC control unit will send the number of errors collected by a counter to the logic processing chip.

[0099] In one or more possible embodiments, the method is applied to a logic processing chip to count the number of errors in each storage area that cannot correctly identify stored data, including:

[0100] Obtaining the number of errors in each storage area that cannot correctly identify stored data from the error checking and correction ECC control unit of each storage chip;

[0101] When the corresponding refresh time arrives, only the storage area is refreshed, including:

[0102] When the corresponding refresh time arrives, the sub-word line driver SWD of the corresponding memory chip is controlled to refresh only the memory area.

[0103] In conjunction with the structure of HBM, a detailed embodiment of the HBM refresh method of the present application is given below.

[0104] like Figure 4 As shown, HBM includes a logic processing chip 401 (Logic Die) and multiple storage chips 402 (DRAM Die), each DRAM Die includes multiple storage cell arrays Cell array, SWD (Sub-wordline driver, sub-wordline driver), error checking and error correction ECC control unit ECC control, temperature sensor temperature sensor, wherein the Cell array is divided into different storage areas, and each storage is provided with at least one temperature sensor temperature sensor. ECC control can be integrated into the corresponding DRAM Die, or it can also be set outside the corresponding DRAM Die, for detecting and correcting data errors in the corresponding storage area, and generating an error signal. It should be noted that the generation of an error signal does not affect the error correction work of the ECC itself.

[0105] Logic Die includes self-refresh control unit, error information collection unit and counter unit. The specific process is as follows:

[0106] The self-refresh control determines the default refresh frequency and notifies the ECC control unit to refresh different storage areas using the default refresh frequency.

[0107] The retention time is greatly affected by temperature, in an exponential relationship. This is mainly because as the temperature rises, the subthreshold leakage current will increase, causing the current in the capacitor to leak faster and cause erroneous information.

[0108] Through the temperature sensors on different DRAM Dies, the temperature of different storage areas can be accurately understood. In this embodiment, different temperature threshold intervals can be set through self-refresh control, and the default self-refresh frequency of each storage area can be adaptively adjusted according to the temperature sensor detecting the temperature of different storage areas.

[0109] Therefore, self-refresh control can adapt to different default refresh rates based on temperature.

[0110] For example, the DRAM Die is tested to a temperature of 25°C, and the first refresh frequency is 60us. The DRAM Die temperature is 30°C due to the impact of packaging, and the second refresh frequency is 55us. . . .

[0111] The check and error correction ECC control unit is used to check whether errors occur in different storage areas and storage locations in the corresponding HBM DRAM Die, and send the error information to the Error information collection when an error occurs. The Error information collection collects the error information of identification errors in different storage areas in each DRAM Die and sends the error information to the Counter; Counter: Receives the error information sent from the Error information collection and accumulates the number of errors in different storage areas.

[0112] Because temperature has a significant impact on retention, and HBM uses TSV (Through Silicon Via) stacking, affected by packaging and heat dissipation, the retention time capability of each DRAM Die is different. The embodiment of the present application performs error statistics on each DRAM Die, and can obtain n*k (n is the DRAM Die number, k is the number of storage areas of each memory chip) statistical results, which can reflect the risk of data loss.

[0113] These error messages can not only reflect the number of errors that occur in different storage areas of different DRAM Dies, but also the degree of the errors. For example, if there are multiple errors at different addresses in a storage area, it means that the error degree of the storage area is high.

[0114] Counter accumulates the errors in the same storage area (storage area division is determined according to different products); Sum = S+1, and detects whether the error level of the area exceeds the threshold corresponding to the high-risk level, and determines the area exceeding the threshold as a high-risk area.

[0115] When any one or more high-risk areas are detected, the data in the storage area will be at risk of loss. LogicDie controls SWD (Sub-wordline driver) to refresh the storage area, and other storage areas do not need to be refreshed, which greatly reduces the refresh times of the full chip and reduces the operating power consumption of DRAM. (Other locations maintain the default refresh frequency, and this refresh refers to additional refresh) After the refresh, the counter is cleared and counted again.

[0116] For example, if DRAM Die1 / 4 is determined to be a high-risk area, only DRAM Die1 / 4 needs to be refreshed, and DRAM Die3 / 4 does not need to be refreshed to waste unnecessary power consumption.

[0117] That is to say, if a certain storage area in DRAM Die 1 is determined to be a high-risk area, only this part needs to be refreshed, and other locations do not need to be refreshed.

[0118] Based on the same inventive concept, the present application also provides a refresh device 500 for a high bandwidth memory HBM, such as Figure 5 As shown, the device comprises:

[0119] The error count module 501 is used to count the number of errors in each storage area that cannot correctly identify the stored data according to the pre-division of storage areas of different storage chips;

[0120] The risk level determination module 502 is used to determine the risk level of data loss corresponding to each storage area according to the number of errors corresponding to different storage areas;

[0121] The partition refresh module 503 is used to determine the refresh frequency of each storage area according to the danger level of the storage area, and refresh only the storage area when the corresponding refresh time arrives.

[0122] In one or more possible embodiments, it further includes:

[0123] A temperature sensing module is used to obtain the temperature of different storage areas using a temperature sensor;

[0124] The partition refresh module determines the refresh frequency of each storage area according to the danger level of the storage area, including:

[0125] The refresh frequency of each storage area is determined according to the danger level and temperature of the storage area.

[0126] In one or more possible embodiments, the partition refresh module determines the refresh frequency of each storage area according to the danger level and temperature of the storage area, including:

[0127] Determine the initial refresh frequency corresponding to the danger level of each storage area according to the preset refresh frequencies corresponding to different danger levels;

[0128] According to different preset temperature ranges, and according to the temperature range corresponding to each storage area, the initial refresh frequency of the storage area is adjusted accordingly.

[0129] In one or more possible embodiments, the partition refresh module adjusts the initial refresh frequency of each storage area according to the temperature range corresponding to each storage area, including:

[0130] According to the preset gear refresh frequencies corresponding to different temperature ranges and according to the gear refresh frequencies corresponding to each storage area, the initial refresh frequency of the storage area is adjusted.

[0131] In one or more possible embodiments, the partition refresh module adjusts the initial refresh frequency of each storage area according to the gear refresh frequency corresponding to each storage area, including:

[0132] Determine that the gear refresh frequency corresponding to any storage area is greater than the initial refresh frequency setting degree corresponding to the storage area, increase the initial refresh frequency of the storage area, and obtain the refresh frequency of the storage area;

[0133] Otherwise, the initial refresh frequency of the storage area is determined as the refresh frequency of the storage area.

[0134] In one or more possible embodiments, the error count module counts the number of errors in each storage area that cannot correctly identify the stored data, including:

[0135] Different memory chips are refreshed using a default refresh frequency, and the number of errors at different storage locations on different memory chips is counted.

[0136] In one or more possible embodiments, the danger level includes a low danger level and a high danger level, and the danger level determination module determines the refresh frequency of each storage area according to the danger level of the storage area, including:

[0137] When it is determined that the danger level of any storage area reaches a high danger level, a self-refresh of the storage area is triggered once based on the default refresh frequency;

[0138] After the storage area is refreshed, the number of errors is reset to zero, and the number of errors in the storage area that cannot correctly identify the stored data begins to be counted again.

[0139] In one or more possible embodiments, the risk level determination module uses a default refresh frequency to refresh different storage chips, including:

[0140] Use temperature sensors to obtain the temperature of different storage areas;

[0141] Determine the target gear refresh frequency corresponding to the temperature range where the current temperature of any storage area is located according to the preset gear refresh frequencies corresponding to different temperature ranges;

[0142] The target gear refresh frequency of the storage area is used as the default refresh frequency of the storage area, and the storage chip is refreshed using the default refresh frequency.

[0143] In one or more possible embodiments, the risk level determination module determines the risk level of data loss corresponding to each storage area according to the number of errors corresponding to different storage areas, including:

[0144] The number of errors in the storage area is compared with the thresholds set for different risk levels to determine the risk level of data loss corresponding to each storage area.

[0145] In one or more possible embodiments, the method is applied to a logic processing chip, and the error count module counts the number of errors in each storage area that cannot correctly identify the stored data, including:

[0146] Obtaining the number of errors in each storage area that cannot correctly identify stored data from the error checking and correction ECC control unit of each storage chip;

[0147] When the corresponding refresh time is reached, the partition refresh module only refreshes the storage area, including:

[0148] When the corresponding refresh time arrives, the sub-word line driver SWD of the corresponding memory chip is controlled to refresh only the memory area.

[0149] After introducing the refresh method and apparatus of the high bandwidth memory HBM according to the exemplary embodiment of the present application, next, a refresh device of the high bandwidth memory HBM according to another exemplary embodiment of the present application is introduced.

[0150] Those skilled in the art will appreciate that various aspects of the present application may be implemented as a system, method or program product. Therefore, various aspects of the present application may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to as "circuit", "module" or "system" herein.

[0151] In some possible implementations, a refresh device of a high bandwidth memory HBM according to the present application is as follows: Figure 6 As shown, it may include at least one processor 601 and at least one memory 602. The memory stores program codes, and when the program codes are executed by the processor, the processor executes the following steps:

[0152] According to the pre-division of storage areas of different storage chips, the number of errors in each storage area that cannot correctly identify the stored data is counted;

[0153] According to the number of errors corresponding to different storage areas, the risk level of data loss corresponding to each storage area is determined;

[0154] The refresh frequency of each storage area is determined according to the danger level of the storage area, and when the corresponding refresh time is reached, only the storage area is refreshed.

[0155] In one or more possible embodiments, the processor is further configured to:

[0156] Use temperature sensors to obtain the temperature of different storage areas;

[0157] The refresh frequency of each storage area is determined according to the danger level of the storage area, including:

[0158] The refresh frequency of each storage area is determined according to the danger level and temperature of the storage area.

[0159] In one or more possible embodiments, the processor determines the refresh frequency of each storage area according to the danger level and temperature of the storage area, including:

[0160] Determine the initial refresh frequency corresponding to the danger level of each storage area according to the preset refresh frequencies corresponding to different danger levels;

[0161] According to different preset temperature ranges, and according to the temperature range corresponding to each storage area, the initial refresh frequency of the storage area is adjusted accordingly.

[0162] In one or more possible embodiments, the processor adjusts the initial refresh frequency of each storage area according to the temperature range corresponding to each storage area, including:

[0163] According to the preset gear refresh frequencies corresponding to different temperature ranges and according to the gear refresh frequencies corresponding to each storage area, the initial refresh frequency of the storage area is adjusted.

[0164] In one or more possible embodiments, the processor adjusts the initial refresh frequency of each storage area according to the gear refresh frequency corresponding to each storage area, including:

[0165] Determine that the gear refresh frequency corresponding to any storage area is greater than the initial refresh frequency setting degree corresponding to the storage area, increase the initial refresh frequency of the storage area, and obtain the refresh frequency of the storage area;

[0166] Otherwise, the initial refresh frequency of the storage area is determined as the refresh frequency of the storage area.

[0167] In one or more possible embodiments, the processor counts the number of errors in each storage area that cannot correctly identify the stored data, including:

[0168] Different memory chips are refreshed using a default refresh frequency, and the number of errors at different storage locations on different memory chips is counted.

[0169] In one or more possible embodiments, the danger level includes a low danger level and a high danger level, and the processor determines the refresh frequency of each storage area according to the danger level of the storage area, including:

[0170] When it is determined that the danger level of any storage area reaches a high danger level, a self-refresh of the storage area is triggered once based on the default refresh frequency;

[0171] After the storage area is refreshed, the number of errors is reset to zero, and the number of errors in the storage area that cannot correctly identify the stored data begins to be counted again.

[0172] In one or more possible embodiments, the processor uses a default refresh frequency to refresh different memory chips, including:

[0173] Use temperature sensors to obtain the temperature of different storage areas;

[0174] Determine the target gear refresh frequency corresponding to the temperature range where the current temperature of any storage area is located according to the preset gear refresh frequencies corresponding to different temperature ranges;

[0175] The target gear refresh frequency of the storage area is used as the default refresh frequency of the storage area, and the storage chip is refreshed using the default refresh frequency.

[0176] In one or more possible embodiments, the processor determines the risk level of data loss corresponding to each storage area according to the number of errors corresponding to different storage areas, including:

[0177] The number of errors in the storage area is compared with the thresholds set for different risk levels to determine the risk level of data loss corresponding to each storage area.

[0178] In one or more possible embodiments, the method is applied to a logic processing chip, and the processor counts the number of errors in each storage area that cannot correctly identify the stored data, including:

[0179] Obtaining the number of errors in each storage area that cannot correctly identify stored data from the error checking and correction ECC control unit of each storage chip;

[0180] The processor refreshes only the storage area when the corresponding refresh time is reached, including:

[0181] When the corresponding refresh time arrives, the sub-word line driver SWD of the corresponding memory chip is controlled to refresh only the memory area.

[0182] In some possible implementations, various aspects of a refresh method for a high-bandwidth memory HBM provided in the present application may also be implemented in the form of a program product, which includes program code. When the program product is run on a computer device, the program code is used to enable the computer device to execute the steps of a refresh method for a high-bandwidth memory HBM according to various exemplary implementations of the present application described above in this specification.

[0183] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0184] The program product for refreshing the high bandwidth memory HBM of the embodiment of the present application can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on an electronic device. However, the program product of the present application is not limited to this. In this document, the readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

[0185] The readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, wherein the readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable signal medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0186] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0187] The program code for performing the operations of the present application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and also conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code can be executed entirely on the user electronic device, partially on the user device, as an independent software package, partially on the user electronic device and partially on the remote electronic device, or entirely on the remote electronic device or server. In the case of a remote electronic device, the remote electronic device can be connected to the user electronic device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external electronic device (for example, using an Internet service provider to connect through the Internet).

[0188] It should be noted that, although several units or subunits of the device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided into multiple units to be embodied.

[0189] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0190] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0191] The present application is described with reference to the flowcharts and block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and block diagram, as well as the combination of the processes and boxes in the flowchart and block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and block diagram. Figure 1 Process or multiple processes and boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0192] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 Process or multiple processes and boxes Figure 1 A function specified in one or more boxes.

[0193] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 Process or multiple processes and boxes Figure 1 The steps for the functions specified in one or more boxes.

[0194] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0195] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for refreshing a high bandwidth memory, characterized in that: The method comprises: According to the pre-division of storage areas of different storage chips, the number of errors in each storage area that cannot correctly identify the stored data is counted; According to the number of errors corresponding to different storage areas, the risk level of data loss corresponding to each storage area is determined; The refresh frequency of each storage area is determined according to the danger level of the storage area, and when the corresponding refresh time is reached, only the storage area is refreshed.

2. The method according to claim 1, characterized in that Also includes: Use temperature sensors to obtain the temperature of different storage areas; The refresh frequency of each storage area is determined according to the danger level of the storage area, including: The refresh frequency of each storage area is determined according to the danger level and temperature of the storage area.

3. The method according to claim 2, characterized in that Determine the refresh frequency of each storage area based on the danger level and temperature of the storage area, including: Determine the initial refresh frequency corresponding to the danger level of each storage area according to the preset refresh frequencies corresponding to different danger levels; According to different preset temperature ranges, and according to the temperature range corresponding to each storage area, the initial refresh frequency of the storage area is adjusted accordingly.

4. The method according to claim 3, characterized in that According to the temperature range corresponding to each storage area, the initial refresh frequency of the storage area is adjusted accordingly, including: According to the preset gear refresh frequencies corresponding to different temperature ranges and according to the gear refresh frequencies corresponding to each storage area, the initial refresh frequency of the storage area is adjusted.

5. The method according to claim 4, characterized in that According to the gear refresh frequency corresponding to each storage area, the initial refresh frequency of the storage area is adjusted, including: Determine that the gear refresh frequency corresponding to any storage area is greater than the initial refresh frequency setting degree corresponding to the storage area, increase the initial refresh frequency of the storage area, and obtain the refresh frequency of the storage area; Otherwise, the initial refresh frequency of the storage area is determined as the refresh frequency of the storage area.

6. The method according to claim 1, characterized in that Count the number of errors in each storage area that cannot correctly identify the stored data, including: Different memory chips are refreshed using a default refresh frequency, and the number of errors at different storage locations on different memory chips is counted.

7. The method according to claim 6, characterized in that The danger level includes a low danger level and a high danger level. The refresh frequency of each storage area is determined according to the danger level of the storage area, including: When it is determined that the danger level of any storage area reaches a high danger level, a self-refresh of the storage area is triggered once based on the default refresh frequency; After the storage area is refreshed, the number of errors is reset to zero, and the number of errors in the storage area that cannot correctly identify the stored data begins to be counted again.

8. The method according to claim 6, characterized in that Use the default refresh rate to refresh different memory chips, including: Use temperature sensors to obtain the temperature of different storage areas; Determine the target gear refresh frequency corresponding to the temperature range where the current temperature of any storage area is located according to the preset gear refresh frequencies corresponding to different temperature ranges; The target gear refresh frequency of the storage area is used as the default refresh frequency of the storage area, and the storage chip is refreshed using the default refresh frequency.

9. The method according to claim 1, characterized in that: According to the number of errors corresponding to different storage areas, determine the risk level of data loss corresponding to each storage area, including: The number of errors in the storage area is compared with the thresholds set for different risk levels to determine the risk level of data loss corresponding to each storage area.

10. The method according to claim 1, characterized in that The method is applied to a logic processing chip to count the number of errors in each storage area that cannot correctly identify the stored data, including: Obtaining, from the error checking and correction control unit of each memory chip, the number of errors in each memory area that cannot correctly identify the stored data; When the corresponding refresh time arrives, only the storage area is refreshed, including: When the corresponding refresh time arrives, the sub-word line driver of the corresponding memory chip is controlled to refresh only the storage area.

11. A refresh device for a high bandwidth memory, characterized in that: The device comprises: The error count module is used to count the number of errors in each storage area that cannot correctly identify the stored data according to the pre-division of storage areas of different storage chips; A risk level determination module, used to determine the risk level of data loss corresponding to each storage area according to the number of errors corresponding to different storage areas; The partition refresh module is used to determine the refresh frequency of each storage area according to the danger level of the storage area, and refresh only the storage area when the corresponding refresh time arrives.

12. A high bandwidth memory device, characterized in that: It comprises at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method as described in any one of claims 1-10.

13. A computer storage medium, characterized in that: The computer storage medium stores a computer program, and the computer program is used to enable a computer to execute the method according to any one of claims 1 to 10.

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