Method for improving uniformity of ion implantation barrier layer

Abstract

This invention provides a method for improving the uniformity of an ion implantation barrier layer. The method includes a substrate comprising a cell region for a power device and an ESD device region. A gate structure is formed on the cell region of the power device. A first oxide layer is formed on the substrate and the gate structure. An etch stop layer is formed on the first oxide layer, followed by the formation of a second oxide layer on the etch stop layer. A polysilicon layer is formed on the second oxide layer. Ion implantation is performed on the polysilicon layer. An ESD structure on the ESD device region is formed using photolithography and etching methods, followed by annealing of the ESD device region. The exposed second oxide layer and the etch stop layer below it are removed. The exposed first oxide layer is etched to reduce its thickness, such that the first oxide layer retained on the upper surface of the gate structure serves as a protective layer, and the first oxide layer retained on the substrate serves as an ion implantation barrier layer. Ion implantation is used to form the body region of the cell region of the power device. The thickness uniformity of the ion implantation barrier layer of this invention is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the uniformity of ion implantation barrier layers. Background Technology

[0002] Existing ion implantation barrier layer processes for ESD-protected structure products include:

[0003] Step 1: Provide a substrate 201, which includes a cell region for a power device and an ESD device region. A gate structure is formed on the cell region of the power device. The gate structure includes: a gate trench formed on the substrate; a gate dielectric layer 203 formed on the gate trench; and a polysilicon gate layer 204 filling the remaining gate trench.

[0004] Step 2: An oxide layer 202 is formed on the substrate 201 and the gate structure. The oxide layer 202 is an NSG (non-permeable silicate glass) layer formed by atmospheric pressure chemical vapor deposition. A polysilicon layer is formed on the oxide layer 202. Ion implantation is performed on the ESD device region. The ESD structure 205 on the ESD device region is formed using photolithography and etching methods, forming as shown. Figure 1 The structure shown is followed by annealing of the ESD device region.

[0005] Step 3: Thin the exposed oxide layer 202 using wet etching. The thinned oxide layer 202 serves as an ion implantation barrier layer, forming a layer as shown in the figure. Figure 2 The structure shown; the bulk region of the cell region of the power device formed by ion implantation.

[0006] Because the NSG (non-permeable silicate glass) layer formed by atmospheric pressure chemical vapor deposition is not dense enough, the etching rate varies greatly in different areas of the wafer during wet etching, which can easily cause uneven distribution of the ion implantation barrier layer on the wafer surface. In addition to causing poor thickness uniformity, it will also have a certain impact on the uniformity of CP (yield) parameters, especially VTH (threshold voltage).

[0007] To address the aforementioned issues, a novel method for improving the uniformity of the ion implantation barrier layer is needed. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the uniformity of the ion implantation barrier layer, so as to solve the problem of uneven distribution of the ion implantation barrier layer within the wafer surface in the prior art.

[0009] To achieve the above and other related objectives, the present invention provides a method for improving the uniformity of an ion implantation barrier layer, comprising:

[0010] Step 1: Provide a substrate, the substrate including a cell region for power devices and an ESD device region, and form a gate structure on the cell region for power devices;

[0011] Step 2: A first oxide layer is formed on the substrate and the gate structure, an etch stop layer is formed on the first oxide layer, and then a second oxide layer is formed on the etch stop layer;

[0012] Step 3: Form a polysilicon layer on the second oxide layer, perform ion implantation on the polysilicon layer, and form an ESD structure on the ESD device region using photolithography and etching methods, followed by annealing of the ESD device region.

[0013] Step 4: Remove the exposed second oxide layer and the etching stop layer beneath it;

[0014] Step 5: Etch the exposed first oxide layer to reduce its thickness, so that the first oxide layer remaining on the upper surface of the gate structure serves as a protective layer, and the first oxide layer remaining on the substrate serves as an ion implantation barrier layer.

[0015] Step 6: Use ion implantation to form the bulk region of the cell region of the power device.

[0016] Preferably, the gate structure in step one is a trench gate structure.

[0017] Preferably, the gate structure in step one includes: a gate trench formed on the substrate; a gate dielectric layer formed on the gate trench; and a polysilicon gate layer filling the remaining gate trench.

[0018] Preferably, the first oxide layer is formed in step two using a thermal oxidation method.

[0019] Preferably, the thickness of the first oxide layer in step two is 130 to 170 angstroms.

[0020] Preferably, the temperature of the thermal oxidation in step two is 900 to 950 degrees Celsius.

[0021] Preferably, the material of the etching stop layer in step two is silicon nitride.

[0022] Preferably, the thickness of the etching stop layer in step two is 50 to 70 angstroms.

[0023] Preferably, the etching stop layer is formed in step two using a low-pressure chemical vapor deposition method.

[0024] Preferably, the second oxide layer in step two is an NSG (non-permeable silicate glass) layer formed by atmospheric pressure chemical vapor deposition.

[0025] Preferably, the thickness of the second oxide layer in step two is 1800 to 2200 angstroms.

[0026] Preferably, in step four, a wet etching method is used to remove the exposed second oxide layer and the etching stop layer below it.

[0027] Preferably, in step four, the exposed etching stop layer is removed using an H3PO4 solution.

[0028] Preferably, in step five, the first oxide layer is thinned using a wet etching method.

[0029] As described above, the method for improving the uniformity of the ion implantation barrier layer of the present invention has the following beneficial effects:

[0030] The thickness uniformity of the ion implantation barrier layer of the present invention is improved, and the uniformity of the device threshold voltage is also improved. Attached Figure Description

[0031] Figure 1 The diagram shows a schematic representation of the ESD structure formed using existing technology.

[0032] Figure 2 The diagram shows a schematic representation of the formation of an ion implantation barrier layer using existing technology.

[0033] Figure 3 The diagram shown is a schematic representation of the process flow of the present invention.

[0034] Figure 4 The diagram shown illustrates the formation of the gate structure according to the present invention.

[0035] Figure 5 The diagram shown illustrates the formation of the first oxide layer according to the present invention.

[0036] Figure 6 The diagram shown illustrates the formation of the etch stop layer according to the present invention.

[0037] Figure 7 The diagram shown illustrates the formation of the second oxide layer according to the present invention.

[0038] Figure 8 The diagram shown illustrates the formation of the ESD structure according to the present invention.

[0039] Figure 9 The diagram shows the second oxide layer and the etching stop layer exposed by etching according to the present invention.

[0040] Figure 10 The diagram shown illustrates the formation of the ion implantation barrier layer according to the present invention. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Please see Figure 3 The present invention provides a method for improving the uniformity of an ion implantation barrier layer, comprising:

[0043] Step 1: Provide a substrate 101, which includes a cell region for power devices and an ESD device region. A gate structure is formed on the cell region of the power devices, forming a structure as shown below. Figure 4 The structure shown;

[0044] In some embodiments, please refer to Figure 4 In step one, the gate structure can be a trench gate structure, including: a gate trench formed on the substrate 101, which is formed using photolithography and etching methods; a gate dielectric layer 103 formed on the gate trench, the material of which can be an oxide layer or other known dielectric material; and a polysilicon gate layer 104 filling the remaining gate trench, which can be formed using deposition and polysilicon etch-back methods. In other examples, the gate structure can be a planar gate structure.

[0045] Step 2: Form a first oxide layer 102 on the substrate 101 and the gate structure, forming as shown in the figure. Figure 5 The structure shown has an etch stop layer 105 formed on the first oxide layer 102, forming a structure as shown. Figure 6 The structure shown is followed by the formation of a second oxide layer 106 on the etch stop layer 105, forming a structure as shown. Figure 7 The structure shown; the introduction of an etch stop layer 105 as a stop layer for wet etching of the subsequent ion implantation barrier layer can effectively improve the problem of poor uniformity of the ion implantation barrier layer caused by the unevenness of the second oxide layer 106; in order to avoid stress problems caused by direct contact between the etch stop layer 105 and the surface of the polysilicon gate layer 104 in the trench, a first oxide layer 102 is first formed as a transitional intermediate layer.

[0046] In some embodiments, the first oxide layer 102 is formed in step two using a thermal oxidation method.

[0047] In some embodiments, the thickness of the first oxide layer 102 in step two is 130 angstroms to 170 angstroms, for example 150 angstroms.

[0048] In some embodiments, the temperature of thermal oxidation in step two is 900 to 950 degrees Celsius, for example, 925 degrees Celsius.

[0049] In some embodiments, the material of the etch stop layer 105 in step two is silicon nitride.

[0050] In some embodiments, the thickness of the etch stop layer 105 in step two is 50 to 70 angstroms, for example, 60 angstroms.

[0051] In some embodiments, step two involves forming an etch stop layer 105 using a low-pressure chemical vapor deposition method.

[0052] In some embodiments, the second oxide layer 106 in step two is an NSG (non-permeable silicate glass) layer formed by atmospheric pressure chemical vapor deposition.

[0053] In some embodiments, the thickness of the second oxide layer 106 in step two is 1800 to 2200 angstroms, for example 2000 angstroms.

[0054] Step 3: A polysilicon layer is formed on the second oxide layer 106. Ion implantation is performed on the polysilicon layer, and the polysilicon layer is patterned using photolithography and etching to form the ESD structure 107 on the ESD device region, which functions as a diode. Figure 8 The structure shown is followed by annealing of the ESD device region.

[0055] Step 4: Remove the exposed second oxide layer 106 and the etching stop layer 105 below it, after etching to form... Figure 9 The structure shown;

[0056] In some embodiments, step four involves using a wet etching method to remove the exposed second oxide layer 106 and the etching stop layer 105 below it.

[0057] In some embodiments, step four involves using an H3PO4 solution to remove the exposed etch stop layer 105.

[0058] Step 5: Etch the exposed first oxide layer 102 to reduce its thickness, so that the first oxide layer 102 remaining on the upper surface of the gate structure serves as a protective layer, and the first oxide layer 102 remaining on the substrate 101 serves as an ion implantation barrier layer, forming a structure as shown in the figure. Figure 10 The structure shown also includes an oxide protective layer of approximately 200 angstroms on the surface of the polysilicon gate layer 104, which can prevent the polysilicon gate layer 104 from being damaged by the charge accumulation effect introduced by subsequent front-layer dry etching and subsequent ion implantation processes.

[0059] In some embodiments, step five involves using a wet etching method to thin the first oxide layer 102.

[0060] Step 6: Use ion implantation to form the bulk region of the cell region of the power device.

[0061] The thickness uniformity of the ion implantation barrier layer of the present invention is improved by 80% compared with the prior art, and the uniformity of the device threshold voltage is also improved by about 50%.

[0062] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0063] In summary, the thickness uniformity of the ion implantation barrier layer of the present invention is improved, and the uniformity of the device threshold voltage is also enhanced. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the uniformity of an ion implantation barrier layer, characterized in that, At least including: Step 1: Provide a substrate, the substrate including a cell region for power devices and an ESD device region, and form a gate structure on the cell region for power devices; Step 2: A first oxide layer is formed on the substrate and the gate structure using thermal oxidation, an etch stop layer is formed on the first oxide layer, and then a second oxide layer is formed on the etch stop layer; Step 3: Form a polysilicon layer on the second oxide layer, perform ion implantation on the polysilicon layer, and form an ESD structure on the ESD device region using photolithography and etching methods, followed by annealing of the ESD device region. Step 4: Remove the exposed second oxide layer and the etching stop layer beneath it; Step 5: Etch the exposed first oxide layer to reduce its thickness, so that the first oxide layer remaining on the upper surface of the gate structure serves as a protective layer, and the first oxide layer remaining on the substrate serves as an ion implantation barrier layer. Step 6: Use ion implantation to form the bulk region of the cell region of the power device.

2. The method for improving the uniformity of the ion implantation barrier layer according to claim 1, characterized in that: The gate structure mentioned in step one is a trench gate structure.

3. The method for improving the uniformity of the ion implantation barrier layer according to claim 2, characterized in that: The gate structure in step one includes: a gate trench formed on the substrate; a gate dielectric layer formed on the gate trench; and a polysilicon gate layer filling the remaining gate trench.

4. The method for improving the uniformity of the ion implantation barrier layer according to claim 1, characterized in that: The thickness of the first oxide layer in step two is 130 to 170 angstroms.

5. The method for improving the uniformity of the ion implantation barrier layer according to claim 1, characterized in that: The temperature of the thermal oxidation in step two is 900 to 950 degrees Celsius.

6. The method for improving the uniformity of the ion implantation barrier layer according to claim 1, characterized in that: The material of the etching stop layer in step two is silicon nitride.

7. The method for improving the uniformity of the ion implantation barrier layer according to claim 6, characterized in that: The thickness of the etching stop layer in step two is 50 to 70 angstroms.

8. The method for improving the uniformity of the ion implantation barrier layer according to claim 6, characterized in that: In step two, the etching stop layer is formed using low-pressure chemical vapor deposition.

9. The method for improving the uniformity of the ion implantation barrier layer according to claim 1, characterized in that: The second oxide layer in step two is an NSG (non-permeable silicate glass) layer formed by atmospheric pressure chemical vapor deposition.

10. The method for improving the uniformity of the ion implantation barrier layer according to claim 1, characterized in that: The thickness of the second oxide layer in step two is 1800 to 2200 angstroms.

11. The method for improving the uniformity of the ion implantation barrier layer according to claim 1, characterized in that: In step four, a wet etching method is used to remove the exposed second oxide layer and the etching stop layer below it.

12. The method for improving the uniformity of the ion implantation barrier layer according to claim 6, characterized in that: In step four, the exposed etching stop layer is removed using an H3PO4 solution.

13. The method for improving the uniformity of the ion implantation barrier layer according to claim 1, characterized in that: In step five, the first oxide layer is thinned using a wet etching method.

Images