Glass panel level embedded packaging process for reducing chip offset

Abstract

The invention discloses a glass panel level embedded packaging process for reducing chip offset, and belongs to the technical field of semiconductor devices. The process comprises the following manufacturing processes: forming a glass cavity on a glass substrate; bonding the glass substrate with the cavity with another glass substrate by using a bonding agent; placing a chip in the cavity by using a chip bonding film; and carrying out RDL lamination and curing on two sides of the whole package substrate on which the chip is placed. The process solves the problem that the position of the chip in the packaging of the glass panel level embedded chip deviates greatly, and has practical value.

Description

Technical Field

[0001] The invention relates to an embedded chip packaging manufacturing process, in particular to a glass panel level embedded packaging process for reducing chip offset, belonging to the technical field of semiconductor devices. Background Art

[0002] With the continuous advancement of semiconductor technology, the integration level is getting higher and higher, and the number of components inside the chip is showing a trend of increasing, which puts higher requirements on packaging technology. Fan-out wafer-level packaging has great advantages in size, cost, performance and reliability compared with traditional flip-chip and wire-bonded packaging. A major trend of fan-out wafer-level packaging is to turn to panel-level embedded chip packaging. Panel-level embedded chip packaging is based on panel processing and can significantly reduce production costs.

[0003] The chip offset problem refers to the displacement of the chip relative to the packaging substrate during the placement and fixing process of the embedded chip package, which leads to problems in the connection or packaging process, and may cause electrical connection errors, insufficient mechanical strength and other quality problems. In the embedded chip packaging process, chip offset mainly occurs during the curing process of the FO-WLP molding material. The typical chip offset size exceeds tens of microns, which is a serious problem in embedded packaging and will cause inevitable misalignment errors in the subsequent lithography process of forming the fine pitch RDL layer.

[0004] With the growing demand for panel-level embedded chip packaging, improving I / O port density, high-frequency performance and output, reducing costs and ensuring reliability have become urgent needs of panel-level embedded chip packaging technology. Under this urgent need, glass, as a material with many advantages including low dielectric constant and low loss tangent, high output, low cost, adjustable thermal expansion coefficient and high stability, has become an ideal panel-level embedded chip packaging material. The glass panel-level embedded packaging process (Glass Panel Embedded Packaging, GPE) using glass as the packaging material has become the current advanced panel-level embedded chip packaging technology.

[0005] In the GPE packaging process, a cavity is first formed on a glass substrate, and then the chip is embedded in the groove by bonding the metal on the non-functional surface of the chip to the metal layer at the bottom of the cavity, and then the dielectric material is processed to form a redistribution layer. However, the size of the cavity formed on the glass substrate by the existing glass cavity formation process is not easy to accurately control, and the displacement of the chip embedded in the cavity by metal bonding relative to the glass substrate is affected by the cavity accuracy, and the chip is prone to shifting during the process of processing the dielectric material.

[0006] Therefore, how to improve the chip offset problem in glass panel-level embedded chip packaging is an issue that needs to be solved urgently. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned background technology and provide a process for reducing chip offset in embedded chip packaging, so as to solve the technical problem of large chip offset in glass panel level embedded chip packaging process through precise and rapid chip placement and RDL lamination and curing methods.

[0008] The present invention adopts the following technical solutions to achieve the above-mentioned invention object: A glass panel level embedded packaging process for reducing chip offset, the production process comprising the following steps: Step 1, forming a cavity penetrating the glass substrate on the glass substrate; Step 2: using an adhesive to bond the glass substrate with the cavity to another glass substrate to form a packaging substrate with the cavity; Step 3, bonding a chip bonding film to the non-functional surface of the chip, and placing the chip into the cavity with the functional surface facing upward; Step 4: RDL lamination and curing are performed on both sides of the entire package substrate after the chip bonding cavity.

[0009] As a further optimization solution for the glass panel level embedded packaging process to reduce chip offset, the cavity formation on the glass substrate in step 1 uses a method combining laser ablation and mechanical scribing.

[0010] As a further optimization solution for the glass panel level embedded packaging process to reduce chip offset, the type of adhesive in step 2 is benzocyclobutene dry film adhesive.

[0011] As a further optimization solution for the glass panel-level embedded packaging process to reduce chip offset, a 10μm thick chip bonding film needs to be added to the non-functional surface of the chip before chip placement in step three, and cured at 130°C for 4 hours. The chip bonding film is a product of Nitto Denko.

[0012] As a further optimization solution for the glass panel-level embedded packaging process to reduce chip offset, a high-speed placement machine is used for chip placement in step three. The pressure applied during placement is 1 MPa, the duration is 5 seconds, and the temperature of the placement tool head is set to 150°C.

[0013] As a further optimization solution for the glass panel-level embedded packaging process to reduce chip offset, in step 4, a vacuum laminator is used to perform RDL lamination and curing on both sides of the entire packaging substrate after the chip bonding cavity, with a pressure of 0.7 MPa and a temperature of 100°C.

[0014] The present invention adopts the above technical solution and has the following beneficial effects: (1) The glass panel-level embedded chip packaging manufacturing process proposed in the present invention firstly bonds a glass substrate with a cavity to another glass substrate to form a packaging substrate with a cavity, which can accurately control the size of the cavity and limit the offset of the chip after embedding; then, a layer of chip adhesive film is added to the non-functional surface of the chip, and the chip is embedded in the cavity with high precision by using a high-speed placement tool; finally, after the chip is placed, the dielectric material is laminated and cured on both sides of the packaging substrate, and the lamination and curing process parameters are optimized to achieve higher packaging surface flatness, more stable chip embedding, and smaller chip offset. Experimental measurements show that the average chip offset of the embedded chip packaging manufacturing process proposed in the present invention is less than 2μm, while the average chip offset of other processes is generally above 7μm, and the chip offset has been significantly reduced.

[0015] (2) Compared with the embedded chip packaging of silicon substrate, the glass panel-level embedded chip packaging manufacturing process proposed in the present invention uses a glass substrate as the packaging substrate, taking advantage of the low loss tangent, adjustable thermal expansion coefficient and low price of glass, and can achieve higher I / O port density and lower production cost.

[0016] (3) Compared with the embedded chip packaging of silicon substrate, the glass panel level embedded chip packaging manufacturing process proposed in the present invention uses a glass substrate as the packaging substrate. By taking advantage of the smooth surface and high stability of the glass, it can achieve capabilities similar to silicon RDL on a large substrate, thereby reducing the number of RDL layers required for signal transmission.

[0017] (4) Compared with other types of fan-out packages, the glass panel-level embedded chip package proposed in the present invention has a lower thickness and does not require additional organic packaging to connect to a large-size circuit board. It can be directly connected to the circuit board through surface mounting. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a structural diagram of a glass substrate after a cavity is formed on the glass substrate in the packaging process of the present invention.

[0019] Figure 2 This is a structural diagram of a glass substrate with a cavity bonded to another glass substrate using an adhesive in the packaging process of the present invention.

[0020] Figure 3 This is a structural diagram after the chip is placed in the cavity of the glass substrate in the packaging process of the present invention.

[0021] Figure 4 This is a structural diagram of the packaging process proposed by the present invention after dielectric materials are laminated and cured on both sides of the glass substrate.

[0022] Figure 5 The figure is a flow chart of the packaging process proposed by the present invention.

[0023] Explanation of the numbers in the figure: 1. glass substrate with cavity, 2. adhesive, 3. chip, 4. chip adhesive film, 5. RDL layer. DETAILED DESCRIPTION

[0024] The technical solution of the invention is described in detail below with reference to the accompanying drawings.

[0025] In order to solve the problem that chip placement may be offset in glass panel-level embedded chip packaging, the present invention proposes an improved chip packaging process. In this process, a glass cavity is first formed on a glass substrate; then, the glass substrate with the cavity is bonded to another glass substrate using an adhesive to form a packaging substrate with a cavity; then, a chip bonded with a chip bonding film is placed in the cavity; finally, RDL lamination and curing are performed on both sides of the packaging substrate.

[0026] like Figure 5 As shown, a glass panel level embedded packaging process for reducing chip offset proposed by the present invention includes the following four steps.

[0027] Step 1: Forming a glass cavity on a glass substrate like Figure 1 As shown, a cavity penetrating the glass substrate is formed on the glass substrate by combining laser ablation and mechanical scribing to obtain a glass substrate with a cavity 1. The glass substrate has a thickness of 70 μm and a size of 300 mm x 300 mm.

[0028] Step 2: Use an adhesive to bond the glass substrate with the cavity to another glass substrate. like Figure 2 As shown, the glass substrate 1 with the cavity is bonded to another glass substrate using an adhesive 2 to form a packaging substrate with the cavity. The thickness of the other glass substrate is 50 μm. The adhesive is a benzocyclobutene dry film adhesive from Dow. In this process for forming a packaging substrate with a cavity, the size of the cavity can be precisely controlled by adjusting the size of the cavity that passes through the glass substrate 1, thereby limiting the chip offset that may occur in subsequent process steps.

[0029] Step 3: Place the chip in the cavity like Figure 3As shown, a 10μm thick chip bonding film 4 is added to the non-functional surface of the chip 3, and cured at 130°C for 4 hours. Then, the chip 3 with the laminated chip bonding film is placed in the cavity with the functional surface facing up using a high-speed placement machine from KULICKE&SOFFA. The pressure applied during placement is 1Mpa, the duration is 5 seconds, and the placement tool head is set to a temperature of 150°C, so that the chip can be embedded in the cavity with high precision. The chip bonding film is a product of Nitto Denko with a thickness of 10μm.

[0030] Step 4: Laminating and curing the dielectric material on both sides of the entire package substrate processed in step 3 For the tiny chip offset introduced by high-precision embedded chips, the present invention forms a flat packaging surface while reducing chip offset by laminating and curing the dielectric material on both sides of the entire packaging substrate after step 3. Figure 4 As shown, a Meiki MVLP300 / 300-S vacuum laminator is used to laminate dielectric materials on the upper and lower sides of the entire package substrate after step 3 and then cure to form an RDL layer 5. The vacuum laminator performs lamination and curing at a pressure of 0.7 MPa and a temperature of 100°C.

[0031] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above specific embodiments. The above specific embodiments and the description in the specification are only for further illustrating the principles and preparation effects of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements. For example, different adhesives and RDL lamination equipment and rapid placement equipment may be used to implement the chip packaging process of the present invention. These changes and improvements fall within the scope of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A glass panel level embedded packaging process for reducing chip offset, characterized in that: The steps include: Step 1, forming a cavity penetrating the glass substrate; Step 2, using an adhesive to bond the glass substrate with the cavity to another glass substrate to form a packaging substrate with the cavity; Step 3, bonding a chip bonding film to the non-functional surface of the chip, and placing the chip into the cavity with the functional surface facing upward; Step 4: laminating dielectric material on the upper and lower sides of the package substrate after the chip is placed and curing.

2. A glass panel level embedded packaging process for reducing chip offset according to claim 1, characterized in that: In the step 1, a cavity penetrating the glass substrate is formed by combining laser ablation and mechanical scribing.

3. A glass panel level embedded packaging process for reducing chip offset according to claim 2, characterized in that: The second step is to bond the glass substrate with the cavity to another glass substrate by using a benzocyclobutene dry film adhesive.

4. A glass panel level embedded packaging process for reducing chip offset according to claim 3, characterized in that: The specific method of bonding the chip bonding film to the non-functional surface of the chip in step three is: adding a layer of chip bonding film to the non-functional surface of the chip and performing a curing treatment at 130° C. for 4 hours.

5. A glass panel level embedded packaging process for reducing chip offset according to claim 4, characterized in that: In the step three, the chip functional surface of the chip laminated with the chip adhesive film is placed upward into the cavity by a high-speed placement machine.

6. A glass panel level embedded packaging process for reducing chip offset according to claim 5, characterized in that: The fourth step is to laminate and solidify the dielectric material on the upper and lower sides of the packaging substrate after the chip is placed therein by a vacuum laminator.

7. A glass panel level embedded packaging process for reducing chip offset according to claim 5, characterized in that: When the high-speed placement machine places the chip laminated with the chip adhesive film into the cavity, the pressure applied is 1 MPa, the duration is 5 seconds, and the setting temperature of the placement tool head is 150°C.

8. A glass panel level embedded packaging process for reducing chip offset according to claim 6, characterized in that: When the vacuum laminator laminates and solidifies the dielectric material on the upper and lower sides of the packaging substrate after the chip is placed, the pressure is 0.7 MPa and the temperature is 100° C.

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