Metal wiring, manufacturing method thereof and integrated circuit

Abstract

The invention provides a metal wiring and a manufacturing method thereof, and an integrated circuit, and the manufacturing method comprises the steps: after an interlayer dielectric layer is etched under the masking effect of a graphical photomask layer to form a through hole, keeping a part, which covers the side wall or bottom corner of a first groove around the through hole, of the graphical photomask layer when the graphical photomask layer is removed; further, the interlayer dielectric layer can be etched under the masking action of the hard mask layer and the remaining patterned photomask layer to form a second groove, so that the formed second groove is narrowed close to the through hole relative to other areas (i.e., the necking effect of the second groove when the through hole and the second groove are close on a plane is enhanced); therefore, the thickness of the interlayer dielectric layer formed between the adjacent metal wires is ensured, and the reliability of the metal wires is improved. According to the method, the effect similar to complete self-alignment of the through hole and the groove can be achieved, and the effect of increasing the offset latitude of the overlay precision between the through hole and the groove can be achieved for a specific metal wiring structure.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a metal wiring and a manufacturing method thereof, and an integrated circuit. Background Art

[0002] In the current advanced logic circuit process nodes, in the back-end metal wiring process, low-K materials (i.e., Low-K materials, whose dielectric constant K value is less than that of silicon oxide) or ultra-low-K materials (i.e., Ultra Low-K, whose dielectric constant K value is less than 3) are usually used to replace traditional silicon oxide as the interlayer dielectric layer between metal wirings to reduce the capacitance between metal lines and thus improve the RC delay effect. And the metal wiring is usually made using a dual damascene process, such as Figure 1 As shown, the metal wiring 103 includes a metal material filled in a trench 102 and a via 101 through which the trench passes.

[0003] Since low-K and ultra-low-K materials have low breakdown field strength, they pose reliability challenges. Figure 1 In (A), in the prior art, the through hole 101 and the trench 102 are usually fully aligned by strictly controlling specific process parameters such as the critical dimension (CD) and overlay accuracy in the process, that is, a fully self-aligned via (SAV) structure is realized, thereby strictly controlling the thickness of the interlayer dielectric layer 100 between the metal wirings 103 (that is, the distance D1 between the side walls of two adjacent trenches 102).

[0004] The above method has the following defects: on the one hand, it has high process requirements and will sacrifice contact resistance; on the other hand, Figure 1 As shown in (B) in FIG. 1 , once the critical dimension (CD) and the stacking alignment (Overlay) accuracy are offset, the through hole 101 and the groove 102 cannot be fully aligned. Figure 1 The through hole passing through the right groove in (B) is connected to another groove adjacent to the groove (such as Figure 1 The spacing between the left grooves in (B) becomes smaller, which will cause the thickness of the interlayer dielectric layer 100 between the metal wirings 103 to decrease (that is, it is reduced to the spacing D2 between the side walls of the groove 102 and the through hole 101 at the adjacent groove), thereby causing reliability problems of the metal wiring. Summary of the invention

[0005] The object of the present invention is to provide a metal wiring and a manufacturing method thereof, and an integrated circuit, which can ensure the thickness of the interlayer dielectric layer between the metal wirings and improve the reliability of the metal wirings.

[0006] To achieve the above object, the present invention provides a method for manufacturing a metal wiring, which comprises the following steps:

[0007] S1, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a hard mask layer having a first trench on the interlayer dielectric layer;

[0008] S2, forming a patterned photomask layer by a photolithography process to cover the hard mask layer and fill the first groove, wherein the patterned photomask layer is formed with an opening at least partially aligned with the first groove, and the aperture of the opening is smaller than the line width of the first groove;

[0009] S3, etching the interlayer dielectric layer under the masking effect of the patterned photomask layer and the hard mask layer to form a through hole in the interlayer dielectric layer;

[0010] S4, retaining the patterned photomask layer covering the sidewall or bottom corner of the first trench near the through hole, and removing the rest of the patterned photomask layer;

[0011] S5, under the masking effect of the hard mask layer and the remaining patterned photomask layer, etching the interlayer dielectric layer, deepening the through hole downward and forming a second trench connected to the through hole in the interlayer dielectric layer, wherein the bottom depth of the second trench is less than the bottom depth of the through hole and is relatively narrowed near the through hole;

[0012] S6, filling metal into the second trench and the through hole to form metal wiring.

[0013] Optionally, the material of the interlayer dielectric layer formed in step S1 includes a low-K dielectric having a dielectric constant K less than that of silicon oxide or an ultra-low-K dielectric having a dielectric constant K less than 3.

[0014] Optionally, in the process of forming the patterned photomask layer in step S2, the patterned photomask layer covering the sidewalls or bottom corners of the first groove near the through hole is hardened; or, after executing step S3 and before executing step S4, step S7 is also included: at least the patterned photomask layer covering the sidewalls or bottom corners of the first groove near the through hole is hardened; or, in step S4, the process conditions for removing the patterned mask layer are controlled to remove most of the patterned mask layer, and the patterned photomask layer covering the bottom corners or sidewalls of the first groove near the through hole is retained, and the remaining patterned photomask layer is further hardened.

[0015] Optionally, the patterned photomask layer formed in step S2 includes at least one of a bottom anti-reflection layer, a spin-on carbon layer and a photoresist layer.

[0016] Optionally, in step S2 or step S7, the bottom anti-reflection layer and / or the spin-on carbon layer in the patterned photomask layer covering the sidewall of the first trench near the through hole is hardened.

[0017] Optionally, step S7 is completed in the same device as step S3 and / or step S4.

[0018] Optionally, at least one of the following hardening processes is used in step S2, step S4 or step S7 to harden the patterned photomask layer covering the sidewall or bottom corner of the first trench near the through hole:

[0019] (1) heating, baking, annealing or irradiating the patterned photomask layer to harden the patterned photomask layer;

[0020] (2) performing surface hardening treatment on corresponding areas of the patterned photomask layer using corresponding etching-resistant gas or plasma or electron beam;

[0021] (3) performing corresponding ion implantation into corresponding regions of the patterned photomask layer to harden corresponding regions of the patterned photomask layer;

[0022] (4) depositing a hardened film on the surface of the patterned photomask layer;

[0023] (5) Forming hardened film sidewalls on the sidewalls of the opening by material deposition and etching.

[0024] Optionally, the etching-resistant gas includes a carbon-containing gas, and the plasma or the corresponding ions include carbon ions and / or hydrogen ions.

[0025] Optionally, the carbon-containing gas further contains hydrogen and / or fluorine elements.

[0026] Optionally, after forming a through hole in the interlayer dielectric layer in step S3, or after removing the remaining patterned photomask layers in step S4, the lateral thickness of the patterned photomask layer retained near a single side of the through hole and covering the bottom corner or sidewall of the first groove is approximately 30% to 40% of the radius of the through hole.

[0027] Based on the same inventive concept, the present invention also provides a metal wiring, which is filled in the grooves and through holes of the corresponding interlayer dielectric layer, the through holes are formed below the grooves and connected to the grooves, the through holes are at least partially aligned with the grooves, and the grooves are narrowed near the through holes relative to other areas.

[0028] Based on the same inventive concept, the present invention also provides an integrated circuit, which includes the metal wiring as described in the present invention.

[0029] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0030] 1. After etching the interlayer dielectric layer to form a through hole under the masking effect of the patterned photomask layer, the portion around the through hole and covering the side wall or bottom corner of the first groove is retained when removing the patterned photomask layer, and then the interlayer dielectric layer can be etched under the masking effect of the hard mask layer and the remaining patterned photomask layer to form a second groove, so that the formed second groove is narrowed near the through hole relative to other areas (that is, the necking effect of the second groove is enhanced when the through hole and the second groove are adjacent to each other on the plane), thereby ensuring the thickness of the interlayer dielectric layer between adjacent metal wirings and improving the reliability of the metal wiring.

[0031] 2. Because before forming the second groove, at least the bottom corner or sidewall portion of the first groove around the through hole is retained, that is, a hardened portion is formed on at least one side of the through hole, and this portion will be more retained when the interlayer dielectric layer that protects this portion is formed when the second groove is formed, forming a portion that is narrower than other areas of the second groove, so an effect similar to complete self-alignment of the through hole and the groove is achieved, and for a specific metal wiring structure, the effect of increasing the offset tolerance of the stacking alignment (overlay) accuracy between the through hole and the groove can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0033] Figure 1 It is a schematic diagram of the cross-sectional structure when the existing metal wiring manufacturing method is fully aligned and offset.

[0034] Figure 2 It is a schematic flow chart of a method for manufacturing metal wiring according to a specific embodiment of the present invention.

[0035] Figures 3 to 9 It is a schematic diagram of the top view and cross-sectional structure of the metal wiring manufacturing method in a specific embodiment of the present invention.

[0036] Fig.10It is a schematic diagram of the cross-sectional structure when the metal wiring manufacturing method is fully aligned and offset in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0037] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0039] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a metal wiring, which comprises the following steps:

[0040] S1, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a hard mask layer having a first trench on the interlayer dielectric layer;

[0041] S2, forming a patterned photomask layer by a photolithography process to cover the hard mask layer and fill the first groove, wherein the patterned photomask layer is formed with an opening at least partially aligned with the first groove, and the aperture of the opening is smaller than the line width of the first groove;

[0042] S3, etching the interlayer dielectric layer under the masking effect of the patterned photomask layer and the hard mask layer to form a through hole in the interlayer dielectric layer;

[0043] S4, retaining the patterned photomask layer covering the sidewall or bottom corner of the first trench near the through hole, and removing the rest of the patterned photomask layer;

[0044] S5, under the masking effect of the hard mask layer and the remaining patterned photomask layer, etching the interlayer dielectric layer, deepening the through hole downward and forming a second trench connected to the through hole in the interlayer dielectric layer, wherein the bottom depth of the second trench is less than the bottom depth of the through hole and is relatively narrowed near the through hole;

[0045] S6, filling metal into the second trench and the through hole to form metal wiring.

[0046] Please refer to Figure 3 An exemplary process of step S1 of this embodiment includes:

[0047] First, a substrate 200 is provided, which can be made of any known semiconductor material, such as silicon, silicon-germanium, silicon on insulator or silicon on sapphire substrate, etc. The substrate 200 can be a substrate that has been processed by the front-end process of integrated circuit (such as manufacturing transistors, capacitors, resistors, diodes and other electronic components) and part of the back-end process (such as bottom contact holes and bottom metal wiring, etc.).

[0048] Next, an etch stop layer (not shown), an interlayer dielectric layer 201 and a hard mask layer 202 are sequentially formed from bottom to top on the substrate 200 using any material and a film forming process such as a chemical vapor deposition process. As an example, the material of the etch stop layer is, for example, silicon oxynitride (SiON) or silicon oxide; the material of the interlayer dielectric layer 201 can be a low-K dielectric material or an ultra-low-K dielectric material (K is less than 3) whose dielectric constant K is less than that of silicon dioxide, and can be a single-layer film structure or a structure formed by stacking multiple films; the material of the hard mask layer 202 is, for example, titanium nitride, tantalum nitride, etc.

[0049] Then, a series of photolithography processes such as photoresist coating, exposure and development are performed on the hard mask layer 202 to form a patterned photoresist layer (not shown) for defining the grooves. In this step, a photomask for manufacturing grooves is required to realize photoresist exposure.

[0050] Next, the hard mask layer 202 is etched using the patterned photoresist layer as a mask until the surface of the etch stop layer is exposed, so as to form a first trench 203 in the hard mask layer 202 .

[0051] Thereafter, the patterned photoresist layer is removed.

[0052] Please refer to Figure 4 An exemplary process of step S2 of this embodiment includes:

[0053] First, a bottom anti-reflective coating (BARC) 204a, a spin-on carbon (SOC) layer 204b and a photoresist layer 204c are sequentially formed on the surface of the hard mask layer 202 and the surface of the first groove 203 from bottom to top by any suitable material and process. The bottom anti-reflective layer 204a can be conformally formed on the surface of the hard mask layer 202 and the first groove 203, and the thickness is relatively thin. The bottom anti-reflective layer 204a can improve the effect of photolithography to form a patterned photomask layer 204 on the one hand, and can improve the filling effect of the spin-on carbon 204b in the first groove 203 on the other hand. The spin-on carbon 204b fills the first groove 203 and provides a flat process surface above the top surface of the hard mask layer 202, so as to facilitate the coating of the photoresist layer 204c and make the photoresist layer 204c have a flat upper surface after coating.

[0054] Then, the photoresist layer 204c is patterned through a series of photolithography processes such as exposure and development to form a photoresist pattern with openings. It is worth mentioning that the position and shape of the openings of the photoresist pattern correspond to the position and shape of the through holes to be formed in the interlayer dielectric layer 201, and the openings are at least partially aligned with the first groove 203.

[0055] Next, the SOC layer 204b and the bottom anti-reflective layer 204a can be etched from top to bottom using the photoresist pattern as a mask until the etching stop layer at the bottom of the first trench 203 is exposed, thereby forming a patterned photomask layer 204 having an opening 205. In order to ensure that the desired hardened patterned photomask layer 204 (i.e., the hardened layer 204) remains on the sidewall or bottom corner of the first trench 203 in the subsequent process of removing the patterned photomask layer 204, Figure 7 204d in the figure, to avoid the problem that the necking effect of the groove cannot be formed after etching in the subsequent step S5 due to the patterned photomask layer 204 retained near the top of the through hole 206 being too thin, and to avoid the problem that the necking is too much due to the patterned photomask layer 204 retained near the top of the through hole 206 being too thick, resulting in defects in the formed metal wiring. On the basis that the aperture of the opening 205 (i.e., the critical dimension of the through hole 206 formed subsequently) is smaller than the line width of the first groove 203 (i.e., the critical dimension of the first groove 203), the distance between the side wall of the opening 205 and the side wall of the first groove 203 needs to be close to a certain extent. For example, d is 30% to 40% of r.

[0056] It should be understood that in other embodiments of the present invention, the patterned photomask layer 204 may be a single-layer film, or a double-layer film including a bottom anti-reflection layer 204a and a photoresist layer 204c, etc., and the present invention does not make any specific limitation on this.

[0057] Please refer to Figure 5 In step S3 of this embodiment, under the masking effect of the patterned photomask layer 204 (i.e., using the patterned photomask layer 204 as a mask), a conventional dry etching process (e.g., anisotropic dry etching) is used to perform etching from top to bottom, thereby etching a partial thickness of the interlayer dielectric layer 201 (i.e., a Partial-Via etching) to form a through hole 206. At this time, the bottom of the through hole 206 does not reach the surface of the substrate 200. The aperture of the through hole 206 (i.e., the critical dimension of the through hole 206) is smaller than the line width of the first trench 203 (i.e., the critical dimension of the first trench 203). At this time, the hard mask layer 202 around the top of the through hole 206 forms a step (not marked) with the interlayer dielectric layer 201. As an example, after the through hole 206 is formed, the lateral thickness of the patterned photomask layer 204 remaining on the side wall of the first groove 203 above the top of the through hole 206 is equal to d, or slightly less than d. The lateral thickness can be 30% to 40% of the radius r of the through hole 206. This can avoid the problem of the necking effect of the groove cannot be formed after etching in the subsequent step S5 due to the patterned photomask layer 204 retained near the top of the through hole 206 after step S4 being too thin. At the same time, it can also avoid the problem of excessive necking due to the patterned photomask layer 204 retained near the top of the through hole 206 after step S4 being too thick, resulting in defective metal wiring.

[0058] It should be understood that in other embodiments of the present invention, when a sufficiently thick or hard-to-etch etch stop layer is formed between the interlayer dielectric layer 201 and the substrate 200, the etching depth may be increased in step S2 until the through hole 206 penetrates the interlayer dielectric layer 201. The present invention does not specifically limit this.

[0059] In an example of this embodiment, step S7 is performed after step S3: by any suitable process, only the patterned photomask layer 204 covering the sidewall or bottom corner of the first trench 203 near the through hole 206 (i.e., covering the sidewall or bottom corner of the hard mask layer 202 facing the through hole 206) is hardened, such as Fig. 6A Alternatively, the surface of the entire patterned photomask layer 204 covering the first trench 203 and the surface of the hard mask layer 202 is hardened to a hardening depth of d, as shown in FIG. Figure 6BAs shown. Thus, the patterned photomask layer 204 covering the sidewall or bottom corner of the first trench 203 near the top corner of the through hole 206 is more resistant to etching in the subsequent steps S4 and S5, that is, the hardening process makes the patterned photomask layer 204 covering the sidewall or bottom corner of the first trench 203 near the top corner of the through hole 206 more difficult to remove in the subsequent steps S4 and S5. When the patterned photomask layer 204 formed in step S2 includes a bottom anti-reflection layer 204a, a spin-coated carbon layer 204b, and a photoresist layer 204c, at least one of the bottom anti-reflection layer 204a, the spin-coated carbon layer 204b, and the photoresist layer 204c on the sidewall of the through hole 206 (for example, the bottom anti-reflection layer 204a that is close to the sidewall of the first trench 203) can be hardened, thereby hardening at least one of the patterned photomask layers 204 on the sidewall or bottom corner or on the sidewall of the first trench 203 (i.e., at least one of the bottom anti-reflection layer 204a, the spin-coated carbon layer 204b, and the photoresist layer 204c) to form a hardened film sidewall 204d. Optionally, at least one of the following hardening processes is used in step S7 to harden the patterned photomask layer 204 covering the sidewall or bottom corner or on the sidewall of the first trench 203 near the through hole 206:

[0060] (1) After the through hole is formed in step S3 and before executing step S4, the patterned photomask layer 204 can be heated from the back side of the substrate 200 (i.e., the bottom surface of the substrate 200), or the patterned photomask layer 204 can be baked, annealed, or illuminated from the front side (i.e., the top surface) of the substrate 200 to harden the patterned photomask layer 204 as a whole, thereby not only hardening the patterned photomask layer 204 covering the bottom corner or side wall of the first groove 203 near the through hole 206, but also hardening the surface layer of the patterned photomask layer 204 with a thickness of about d in other areas. However, due to the small distance between the through hole 206 and the hard mask layer 202, under the influence of the proximity effect, in the subsequent step S4, the patterned photomask layer 204 covering the bottom corner or side wall of the first groove 203 near the top of the through hole 206 is more difficult to remove than the patterned photomask layer 204 in other areas.

[0061] (2) After forming the through hole in step S3 and before executing step S4, a carbon-containing C gas (e.g., CH 4 , CH 3 F, CH 2 F 2 The corresponding areas of the patterned photomask layer 204 (such as the parts covering the side walls of the through holes 206) are surface hardened by using corresponding etching-resistant gases such as etch-resistant gases or plasma or electron beams obtained by these carbon-containing gases to form hardened film side walls 204d on the side walls of the openings 203.

[0062] (3) After forming the through hole in step S3 and before executing step S4, the corresponding area of ​​the patterned photomask layer 204 (e.g., the surface layer covering the portion around the side wall of the through hole 206) is implanted with any suitable one or more ions including carbon C, hydrogen H, nitrite N, fluorine F, etc., so as to harden the patterned photomask layer 204 on the side wall of the through hole 206. The hardening depth and hardening area of ​​the patterned photomask layer 204 depend on the implantation conditions such as the energy, dose and implantation range of the ion implantation.

[0063] (4) After forming the through hole in step S3 and before executing step S4 , a hardening film (not shown) is deposited on the surface of the patterned photomask layer 204 .

[0064] (5) After forming the through hole in step S3 and before executing step S4, a hardened film sidewall 204d is formed on the sidewall of the opening 203 by material deposition and etching.

[0065] It should be understood that the above methods (1) to (5) are merely examples of several methods for implementing the hardening treatment, which can also be replaced by any suitable process in the art, and the present invention does not specifically limit this. Moreover, according to the selection of the hardening treatment process in step S7, it can be implemented in the same device as the previous step S3 and / or the subsequent step S4, or it can be implemented in other devices independently of the previous step S3 and the subsequent step S4.

[0066] Please refer to Figure 7In step S4, the patterned photomask layer 204 can be removed by a conventional debonding process such as an ashing process or a wet debonding process. In this step, since the patterned photomask layer 204 covering the sidewall or bottom corner of the first trench 203 near the top of the through hole 206 has been hardened in advance, when the sidewall of the first trench 203 and the sidewall of the through hole 206 are adjacent to a certain extent (i.e., d is small), under the step shielding effect of the hard mask layer 202, the patterned photomask layer 204 on the sidewall or bottom corner of the first trench 203 (i.e., a part of the hardened film sidewall 204d) is more difficult to remove and has more stable performance than the prior art, and can be retained and used as a part of the mask in the process of etching the interlayer dielectric layer 201 to form the second trench in the subsequent step S5. As an example, the patterned photomask layer 204 (i.e., a portion of the hardened film sidewall 204d) retained on the sidewall or bottom corner of the first groove 203 has a lateral thickness less than or equal to d, and is 30% to 40% of the radius of the through hole 206, thereby avoiding the problem that the patterned photomask layer 204 retained near the top of the through hole 206 is too thin and is directly removed in the subsequent etching step S5, thereby failing to achieve the necking effect of the second groove. At the same time, it also avoids the problem that the patterned photomask layer 204 retained near the top of the through hole 206 is too thick, resulting in excessive necking of the formed second groove, causing defects in the metal wiring filled in the second groove.

[0067] Please refer to Figure 8 In step S5, the interlayer dielectric layer 201 can be etched under the masking effect of the hard mask layer 202 and the remaining patterned photomask layer (i.e., a portion of the hardened film sidewall 204d) to form a second trench 207 whose bottom is connected to the through hole 206. At this time, the through hole 206 penetrates the interlayer dielectric layer 201, the bottom depth of the second trench 207 is less than the bottom depth of the through hole 206, and the second trench 207 passes above the through hole 206. Moreover, for the interlayer dielectric layer 201 in the first trench 203 region, the remaining patterned photomask layer (i.e., a portion of the hardened film sidewall 204d) masks the vicinity of the top of the through hole 206 relative to other regions, so the formed second trench 207 is automatically narrowed near the top of the through hole 206 relative to other regions.

[0068] It should be understood that in step S5, during the process of etching the interlayer dielectric layer 201 to form the second trench 207, the remaining patterned photomask layer (i.e., the remaining portion of the hardened film sidewall 204d) can be gradually removed simultaneously, or can be partially or completely retained and removed simultaneously when the hard mask layer 202 is subsequently removed. In this embodiment, in step S5, the loss of the remaining patterned photomask layer during the process of forming the second trench 207 can be ignored, so that most of the patterned photomask layer is retained and removed simultaneously when the hard mask layer 202 is subsequently removed. Please further combine Fig.10 As shown, for two adjacent second grooves 207, if the through hole 206 is completely aligned with the second grooves 207, the spacing D3 of the second grooves 207 near the through hole 206 becomes larger than the spacing D1 of the second grooves 207 in other areas, that is, D3>D1; if the through hole 206 is not aligned with the second grooves 207, the spacing D4 of the second grooves 207 near the through hole 206 can be equivalent to the spacing D1 of the second grooves 207 in other areas. At this time, D4 ​​is equal to or slightly smaller than or slightly larger than D1, achieving an effect similar to that of the through hole 206 and the second groove 207 being completely aligned (i.e., self-aligned).

[0069] from Fig.10 It can be seen that the morphological consistency of the second grooves 207 formed on the entire substrate 200 is improved, and the thickness uniformity of the interlayer dielectric layer 201 between adjacent second grooves 207 is improved. Even if the through hole 206 and the second groove 207 are not completely aligned, the interlayer dielectric layer 201 between two adjacent second grooves 207 will not be too thin near the through hole 206, which improves the offset tolerance of the stacking alignment (overlay) accuracy of the through hole 206 and the second groove 207, thereby achieving the effect of improving the TDDB performance of the dielectric layer, which is more conducive to improving the reliability of metal wiring.

[0070] Please refer to Fig. 9 In step S6, a metal diffusion barrier layer (not shown, such as at least one of Ta, TaN, Ti and TiN) and a metal seed layer (not shown, such as Ti or Cu) and other thin films can be conformally formed in the through hole 206 and the second trench 207 by any suitable process in the art such as sputtering or deposition, and then any suitable process in the art such as electroplating can be used to fill the through hole 206 and the second trench 207 with metal until the through hole 206 and the second trench 207 are filled, and then the filled metal is chemically and mechanically planarized to remove the hard mask layer 202 and the remaining patterned photomask layer 204 (i.e., a part of the hardened film sidewall 204d), exposing the top surface of the interlayer dielectric layer 201, and then forming a metal wiring 208. The metal wiring 208 is a dual damascene structure, the part filled in the through hole 206 is used as a plug, and the part filled in the second trench 207 is used as an interconnection line.

[0071] It should be understood that in the above embodiment, after step S3 (i.e., the Partial Via etching step in the conventional method) and before step S4 (i.e., the conventional step of removing the patterned photomask layer 204), and also before the Trench etching step in the conventional method, a hardening process is added (i.e., step S7 for hardening the patterned photomask layer 204), so that the patterned photomask layer 204 at the side wall or bottom corner of the hard mask layer 202 near the through hole 206 is more resistant to etching in the subsequent step of removing the patterned photomask layer 204 (i.e., step S4) and the Trench etching step (i.e., step S5). This is merely an example of the technical solution of the present invention, and does not mean that the technical solution of the present invention is limited thereto. In other embodiments of the present invention, the hardness of the patterned photomask layer 204 at the sidewalls or bottom corners of the hard mask layer 202 near the through hole 206 can be enhanced at any suitable process node before the trench etching step in the conventional method. This can also achieve the effect of hardening the patterned photomask layer 204 at the sidewalls or bottom corners of the hard mask layer 202 near the through hole 206 and making it more resistant to etching and preserved in the subsequent step of removing the patterned photomask layer 204 (i.e., step S4) and the trench etching step (i.e., step S5).

[0072] For example, in the above-mentioned step S2, when any one of the bottom anti-reflection layer 204a and the spin-coated carbon layer 204b is covered on the surface of the hard mask layer 202 and the first groove 203, the bottom anti-reflection layer 204a is hardened or the bottom anti-reflection layer 204a and the spin-coated carbon layer 204b are hardened together by directly depositing a special material as the bottom anti-reflection layer 204a and / or the spin-coated carbon layer 204b, or by depositing the bottom anti-reflection layer 204a and / or the spin-coated carbon layer 204b and then performing ion implantation or surface hardening treatment or further depositing a hardened film or any other suitable hardening process.

[0073] For another example, in the above-mentioned step S2, after forming a patterned mask layer 204 with an opening through a photolithography process, and before executing step S3, at least one of the processes (1) to (5) used in the above-mentioned step S7 is first used to harden the patterned mask layer 204 on the side wall or bottom corner of the opening 205.

[0074] For another example, in the above-mentioned step S4, the process conditions for removing the patterned mask layer 204 are controlled, so as to remove most of the patterned mask layer 204, and retain the patterned photomask layer 204 at the side wall or bottom corner of the hard mask layer 202 near the through hole 206, and further harden the retained patterned photomask layer 204 so that it can be more resistant to etching and retained in the subsequent trench etching step (i.e., step S5).

[0075] In summary, the manufacturing method of the metal wiring of the present invention, after etching the interlayer dielectric layer under the masking effect of the patterned photomask layer to form a through hole, retains the portion of the patterned photomask layer covering the sidewall or bottom corner of the first groove when removing the patterned photomask layer, and then etches the interlayer dielectric layer under the masking effect of the hard mask layer and the remaining patterned photomask layer to form a second groove, so that the formed second groove is narrowed relative to other areas near the through hole (that is, the necking effect of the groove is enhanced when the through hole and the second groove are adjacent on the plane), thereby ensuring the thickness of the interlayer dielectric layer between the adjacent metal wirings formed, and improving the reliability of the metal wiring. Moreover, it can achieve an effect similar to the complete self-alignment of the through hole and the groove, and for a specific metal wiring structure, it can achieve the effect of increasing the offset tolerance of the stacking alignment (overlay) accuracy between the through hole and the groove.

[0076] Based on the same invention concept, please refer to Figures 9 and 10 An embodiment of the present invention further provides a metal wiring 208, which can be formed by the manufacturing method of the metal wiring of the present invention. The metal wiring 208 is filled in the corresponding groove (i.e., the second groove 207) and the through hole 206 of the interlayer dielectric layer 201, the through hole 206 is formed below the second groove 207 and connected to the second groove 207, the through hole 206 is at least partially aligned with the second groove 207, and the second groove 207 is narrowed near the through hole 206 relative to other areas.

[0077] Please refer to Fig.10For two adjacent metal wirings 208, if the through hole 206 is completely aligned with the second groove 207, the spacing D3 of the second grooves 207 near the through hole 206 becomes larger than the spacing D1 of the second grooves 207 in other areas, that is, D3>D1; if the through hole 206 is not aligned with the second groove 207, the spacing D4 of the second grooves 207 near the through hole 206 can be equivalent to the spacing D1 of the second grooves 207 in other areas. At this time, D4 ​​is equal to or slightly smaller than or slightly larger than D1, achieving an effect similar to that of the through hole 206 and the second groove 207 being completely aligned (i.e., self-aligned). Moreover, the morphological consistency of the second grooves 207 formed on the entire substrate 200 is improved, and the thickness uniformity of the interlayer dielectric layer 201 between adjacent second grooves 207 is improved. Even if the through hole 206 and the second groove 207 are not completely aligned, the interlayer dielectric layer 201 between two adjacent second grooves 207 will not be too thin near the through hole 206, thereby improving the offset tolerance of the stacking alignment (overlay) accuracy of the through hole 206 and the second groove 207, thereby achieving the effect of improving the TDDB performance of the dielectric layer, which is more conducive to improving the reliability of metal wiring.

[0078] Based on the same invention concept, please refer to Figures 9 and 10 An embodiment of the present invention further provides an integrated circuit, which includes at least one metal wiring 208 as described in the present invention.

[0079] The metal wiring and integrated circuit of the present invention have an interlayer dielectric layer between the metal wirings of sufficient thickness, which improves the performance of the interlayer dielectric layer TDDB, and ultimately improves the reliability of the metal wiring and the integrated circuit.

[0080] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a metal wiring, characterized in that: The following steps are involved: S1, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a hard mask layer having a first trench on the interlayer dielectric layer; S2, forming a patterned photomask layer by a photolithography process to cover the hard mask layer and fill the first groove, wherein the patterned photomask layer is formed with an opening at least partially aligned with the first groove, and the aperture of the opening is smaller than the line width of the first groove; S3, etching the interlayer dielectric layer under the masking effect of the patterned photomask layer and the hard mask layer to form a through hole in the interlayer dielectric layer; S4, retaining the patterned photomask layer covering the bottom corner or the sidewall of the first trench near the through hole, and removing the rest of the patterned photomask layer; S5, under the masking effect of the hard mask layer and the remaining patterned photomask layer, etching the interlayer dielectric layer, deepening the through hole downward and forming a second trench connected to the through hole in the interlayer dielectric layer, wherein the bottom depth of the second trench is less than the bottom depth of the through hole and is relatively narrowed near the through hole; S6, filling metal into the second trench and the through hole to form metal wiring.

2. The manufacturing method according to claim 1, characterized in that The material of the interlayer dielectric layer formed in step S1 includes a low-K dielectric having a dielectric constant K less than that of silicon oxide or an ultra-low-K dielectric having a dielectric constant K less than 3.

3. The manufacturing method according to claim 1, characterized in that: In the process of forming the patterned photomask layer in step S2, the patterned photomask layer covering the sidewalls or bottom corners of the first groove near the opening is hardened; or, after executing step S3 and before executing step S4, step S7 is also included: hardening the patterned photomask layer covering the sidewalls or bottom corners of the first groove near the through hole; or, in step S4, the process conditions for removing the patterned mask layer are controlled to remove most of the patterned mask layer, and the patterned photomask layer covering the bottom corners or sidewalls of the first groove near the through hole is retained, and the remaining patterned photomask layer is further hardened.

4. The manufacturing method according to claim 3, characterized in that: The patterned photomask layer formed in step S2 includes at least one of a bottom anti-reflection layer, a spin-coated carbon layer and a photoresist layer; in step S2 or step S7, the bottom anti-reflection layer and / or the spin-coated carbon layer in the patterned photomask layer covering the side wall of the first groove near the through hole are hardened.

5. The manufacturing method according to claim 3, characterized in that: The step S7 is completed in the same device as the step S3 and / or the step S4.

6. The manufacturing method according to claim 3, characterized in that: In step S2, step S4 or step S7, at least one of the following hardening processes is used to harden the patterned photomask layer covering the sidewall or bottom corner of the first trench near the through hole: (1) heating, baking, annealing or irradiating the patterned photomask layer to harden the patterned photomask layer; (2) performing surface hardening treatment on corresponding areas of the patterned photomask layer using corresponding etching-resistant gas or plasma or electron beam; (3) performing corresponding ion implantation into corresponding regions of the patterned photomask layer to harden corresponding regions of the patterned photomask layer; (4) depositing a hardened film on the surface of the patterned photomask layer; (5) Forming hardened film sidewalls on the sidewalls of the opening by material deposition and etching.

7. The manufacturing method according to claim 6, characterized in that: The etch-resistant gas includes a carbon-containing gas, and the plasma or the corresponding ions include carbon ions and / or hydrogen ions.

8. The manufacturing method according to claim 1, characterized in that: After forming a through hole in the interlayer dielectric layer in step S3, or after removing the remaining patterned photomask layers in step S4, the lateral thickness of the patterned photomask layer retained near a single side of the through hole and covering the bottom corner or sidewall of the first groove is approximately 30% to 40% of the radius of the through hole.

9. A metal wiring, characterized in that: The metal wiring is filled in the groove and through hole of the corresponding interlayer dielectric layer. The through hole is formed below the groove and connected to the groove. The through hole is at least partially aligned with the groove, and the groove is narrowed near the through hole relative to other areas.

10. An integrated circuit, characterized in that: Comprising the metal wiring as claimed in claim 9.

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