Formation method of semiconductor device

Abstract

The invention relates to a method for forming a semiconductor device. In the forming method, a metal hard mask layer, a consumption layer and a graphical first photomask layer are sequentially stacked on an interlayer dielectric layer, and the first photomask layer is used as an etching mask to form a graphical groove penetrating through the consumption layer and the metal hard mask layer; and then, when the patterned second photomask layer is used as an etching mask to etch the interlayer dielectric layer, the consumption layer and the metal hard mask layer are used for blocking at the same time, so that the hole formed in the interlayer dielectric layer is limited by the width of the patterned groove, displacement is avoided, and in the etching process, the thickness of the patterned groove is reduced. The consumption layer can protect the metal hard mask layer, the side wall of the metal hard mask layer of the pattern groove is prevented from being etched, and the position precision of the hole and the through hole formed by further etching the interlayer dielectric layer along the hole can be improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for forming a semiconductor device. Background Art

[0002] In the semiconductor manufacturing process, metal interconnection technology is usually used to connect electronic components such as transistors formed on the surface area of ​​the substrate to form a circuit, and to form ports for connecting to external electrical signals to achieve the sending and receiving of power and signals, thereby obtaining a chip with certain functions.

[0003] In the metal interconnection process, an interlayer dielectric layer is used to isolate adjacent patterned metal layers, and a connection channel is formed in the interlayer dielectric layer. Since metal materials such as titanium nitride have a large etching selectivity with interlayer dielectric materials, a metal hard mask is often used to etch the interlayer dielectric layer to form a through hole therein. However, when a through hole is formed in the interlayer dielectric layer using a metal hard mask, the position accuracy of the through hole is not high and it is easy to shift, resulting in a decrease in device reliability. The low accuracy of the through hole position also makes it difficult to meet the requirements of advanced processes. Summary of the invention

[0004] In order to solve the problem that the position of a through hole is easily offset when a metal hard mask is used to form a through hole in an interlayer dielectric layer in the prior art, the present invention provides a method for forming a semiconductor device.

[0005] The method for forming a semiconductor device provided by the present invention comprises:

[0006] forming a first metal interconnect structure and an interlayer dielectric layer covering the first metal interconnect structure on a substrate;

[0007] stacking a metal hard mask layer, a sacrificial layer and a patterned first photomask layer in sequence on the interlayer dielectric layer;

[0008] Using the first photomask layer as an etching mask, etching the sacrificial layer and the metal hard mask layer to form a pattern groove penetrating the sacrificial layer and the metal hard mask layer, and then removing the first photomask layer;

[0009] forming a patterned second photomask layer on the sacrificial layer, wherein an opening in the second photomask layer spans across the patterned grooves;

[0010] Using the second photomask layer as an etching mask, and using the sacrificial layer and the metal hard mask layer for blocking, etching the interlayer dielectric layer to form a hole extending from the bottom surface of the pattern groove into the interlayer dielectric layer, and then removing the second photomask layer; and

[0011] The pattern of the graphic groove is transferred to the interlayer dielectric layer, a dielectric groove is formed on the upper part of the interlayer dielectric layer, and the interlayer dielectric layer is etched downward along the hole to form a through hole penetrating the interlayer dielectric layer at the bottom of the dielectric groove.

[0012] Optionally, the interlayer dielectric layer includes an etch stop layer covering a surface of the first metal interconnect structure and a low-k dielectric layer covering a surface of the etch stop layer.

[0013] Optionally, transferring the pattern of the pattern groove into the interlayer dielectric layer, and etching the interlayer dielectric layer downward along the hole comprises:

[0014] Using the sacrificial layer and the metal hard mask layer as etching masks, a dry etching process is performed to form the dielectric trench on the upper portion of the low-k dielectric layer, and a dielectric through hole penetrating the low-k dielectric layer is formed corresponding to the hole, wherein the dielectric through hole exposes the etching stop layer;

[0015] A wet etching process is performed to etch the etch stop layer exposed by the dielectric through hole, so that the dielectric through hole extends downward to form the through hole, and the through hole exposes the corresponding electrical connection in the first metal interconnection structure.

[0016] Optionally, after forming the through hole, the forming method further includes:

[0017] removing the consumable layer;

[0018] Depositing a metal material, wherein the metal material fills the graphic grooves, the dielectric grooves and the through holes and covers the metal hard mask layer;

[0019] A planarization process is performed to remove the metal hard mask layer and the metal material located on the interlayer dielectric layer.

[0020] Optionally, before forming a patterned second photomask layer on the sacrificial layer, the forming method further comprises:

[0021] A leveling layer is formed, the leveling layer fills the pattern grooves and covers the sacrificial layer; wherein the second photomask layer is formed on the surface of the leveling layer, and before the interlayer dielectric layer is etched using the second photomask layer as an etching mask, the leveling layer is etched using the second photomask layer as an etching mask, while the sacrificial layer and the metal hard mask layer are blocked.

[0022] Optionally, a width of the opening in the second photomask layer is greater than a width of the graphic groove located below the opening.

[0023] Optionally, the forming method further comprises:

[0024] A hard mask buffer layer is formed between the interlayer dielectric layer and the metal hard mask layer.

[0025] Optionally, the forming method further comprises:

[0026] A hard mask protection layer is formed between the sacrificial layer and the metal hard mask layer.

[0027] Optionally, the consumption layer includes SiCN, SiC and Si 3 N 4 At least one of .

[0028] Optionally, the metal hard mask layer includes at least one of titanium nitride and titanium oxide.

[0029] In the method for forming a semiconductor device provided by the present invention, a metal hard mask layer, a sacrificial layer and a patterned first photomask layer are stacked in sequence on an interlayer dielectric layer, and the first photomask layer is first used as an etching mask to form a pattern groove that penetrates the sacrificial layer and the metal hard mask layer. Then, when the interlayer dielectric layer is etched using the patterned second photomask layer as an etching mask, the sacrificial layer and the metal hard mask layer are simultaneously used for blocking, so that the hole formed in the interlayer dielectric layer is limited to the width of the pattern groove to avoid displacement. Moreover, during the etching process, the sacrificial layer can protect the metal hard mask layer to avoid etching the sidewalls of the metal hard mask layer of the pattern groove, which can improve the position accuracy of the hole and the through hole formed by further etching the interlayer dielectric layer along the hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present invention.

[0031] Figures 2A to 2K is a schematic cross-sectional view of a method for forming a semiconductor device according to an embodiment of the present invention.

[0032] Figure 3 The diagram is a plan view of a method for forming a semiconductor device according to an embodiment of the present invention, showing a patterned trench, an opening in a second photomask layer, and a hole formed in an interlayer dielectric layer. DETAILED DESCRIPTION

[0033] The following is a further detailed description of the method for forming a semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the figure is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0034] With the development of technology, the characteristic size of semiconductor devices is reduced, the design size of the through hole formed in the interlayer dielectric layer is getting smaller and smaller, and the allowable alignment deviation of the through hole is also getting smaller and smaller. Research has found that when a patterned titanium nitride layer is used as a metal hard mask to etch the interlayer dielectric layer to form a through hole therein, while the interlayer dielectric layer is being etched, the titanium nitride will also be etched and reduced (TiN pullback), so that the opening in the titanium nitride layer is enlarged, which causes the position of the through hole formed in the interlayer dielectric layer to shift, resulting in a decrease in device reliability. For semiconductor devices designed with advanced processes, it is easy to cause device failure. The method for forming a semiconductor device described in an embodiment of the present invention can improve the position accuracy of the through hole formed in the interlayer dielectric layer. The following is combined with Figures 1 to 2K The method for forming a semiconductor device described in the embodiment of the present invention is specifically described.

[0035] Figure 2A The substrate 100 is shown after the first metal interconnection structure 10 and the interlayer dielectric layer 110 are formed. Figure 1 and Figure 2A According to a method for forming a semiconductor device according to an embodiment of the present invention, step S1 is first performed to form a first metal interconnection structure 10 and an interlayer dielectric layer 110 covering the first metal interconnection structure 10 on a substrate 100 .

[0036] The substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or may be other substrates known to those skilled in the art for carrying electronic components. As an example, the substrate 100 is a silicon wafer. The surface area of ​​the substrate 100 may be formed with electronic components (not shown), and the electronic components may include active or passive circuit elements, such as memory cells and / or logic circuits.

[0037] The first metal interconnection structure 10 is formed on the substrate 100. The first metal interconnection structure 10 includes, for example, electrical connectors formed in a dielectric material, at least a portion of the top surface of the electrical connectors being exposed. The electrical connectors may include a patterned conductive layer and / or a conductive plug.

[0038] The interlayer dielectric layer 110 is formed on the first metal interconnect structure 10. Optionally, the interlayer dielectric layer 110 includes an etch stop layer 111 covering the surface of the first metal interconnect structure 10 and a low-k dielectric layer 112 covering the surface of the etch stop layer 111. The etch stop layer 111 and the low-k dielectric layer 112 have etching selectivity. The etch stop layer 111 may include SiCN, SiC, and Si 3 N 4 The low-k dielectric layer 112 may include an ultra-low-k dielectric material or a low-k dielectric material, and may also include other dielectric materials, such as an organic silicon compound (such as SiLK).

[0039] Reference Figure 1 , Figure 2A and Figure 2B , executing step S2 , stacking a metal hard mask layer MHM, a sacrificial layer 120 and a patterned first photomask layer 130 in sequence on the interlayer dielectric layer 110 .

[0040] like Figure 2A As shown, before stacking the metal hard mask layer MHM on the interlayer dielectric layer 110, a hard mask buffer layer 101 may be formed on the surface of the interlayer dielectric layer 110. The hard mask buffer layer 101 may include SiO 2 The hard mask buffer layer 101 can be used to prevent the metal in the metal hard mask layer MHM from diffusing into the interlayer dielectric layer 110 and improve the adhesion between the interlayer dielectric layer 110 and the metal hard mask layer MHM.

[0041] The metal hard mask layer MHM covers the hard mask buffer layer 101. The metal hard mask layer MHM may include at least one of titanium nitride (TiN) and titanium oxide (TiO), or the metal hard mask layer MHM may include other suitable metal materials. As an example, the metal hard mask layer MHM is a titanium nitride film. Optionally, after forming the metal hard mask layer MHM, a hard mask protection layer 102 may be formed on the surface of the metal hard mask layer MHM, and the hard mask protection layer 102 may be made of, for example, silicon oxide. The hard mask protection layer 102 may be used to protect the metal hard mask layer MHM and form a buffer between the metal hard mask layer MHM and the sacrificial layer 120.

[0042] The sacrificial layer 120 is formed on the hard mask protective layer 102. In the present embodiment, the sacrificial layer 120 is used to consume the incident plasma during the process of etching the interlayer dielectric layer 110, so as to protect the metal hard mask layer MHM from being substantially etched. The sacrificial layer 120 may be made of a material having a greater etching selectivity with the interlayer dielectric layer 110, so as to reduce the loss of the sacrificial layer 120 during the process of etching the interlayer dielectric layer 110. As an example, the interlayer dielectric layer 110 and the hard mask protective layer 102 both include silicon oxide, and the sacrificial layer 120 is made of a material having a greater etching selectivity with silicon oxide, for example, the sacrificial layer 120 includes SiCN, SiC and Si 3 N 4 Here, as an example, the sacrificial layer 120 is a SiCN film.

[0043] Figure 2B FIG. 1 shows a first photomask layer 130 formed on the sacrificial layer 120. Figure 2B As shown, after forming the sacrificial layer 120, a patterned first photomask layer 130 is formed on the surface of the sacrificial layer 120, and the first photomask layer 130 has a pattern for defining a pattern groove to be formed in the sacrificial layer 120 and the metal hard mask layer MHM. As an example, the first photomask layer 130 includes a first bottom anti-reflective layer BARC1 formed on the surface of the sacrificial layer 120 and a first photoresist layer PR1 formed on the surface of the first bottom anti-reflective layer BARC1.

[0044] Figure 2C FIG. 2 shows a pattern trench 20 formed in the sacrificial layer 120 and the metal hard mask layer MHM. Figure 1 and Figure 2C , perform step S3, use the first photomask layer 130 as an etching mask, etch the sacrificial layer 120 and the metal hard mask layer MHM, form a graphic groove 20 penetrating the sacrificial layer 120 and the metal hard mask layer MHM, and then remove the first photomask layer 130.

[0045] The anisotropic dry etching process may be used to etch the sacrificial layer 120 and the metal hard mask layer MHM. In this embodiment, since a hard mask protective layer 102 is formed between the sacrificial layer 120 and the metal hard mask layer MHM, the hard mask protective layer 102 is also etched during the dry etching, and the graphic groove 20 penetrates the sacrificial layer 120, the hard mask protective layer 102 and the metal hard mask layer MHM in the depth direction. The graphic groove 20 may extend in a plane parallel to the upper surface of the interlayer dielectric layer 110 and form a pattern. Figure 2C Three cross sections of a patterned groove 20 perpendicular to the extension direction are shown.

[0046] Figure 2D The planarization layer 103 and the second photomask layer 140 formed in the pattern groove 20 and on the sacrificial layer 120 are shown. Figure 1 and Figure 2D Then, step S4 is performed to form a patterned second photomask layer 140 on the sacrificial layer 120 , wherein the opening 140 a in the second photomask layer 140 crosses the patterned groove 20 .

[0047] The second photomask layer 140 can be directly formed in the above-mentioned graphic grooves 20 and on the sacrificial layer 120. For example, in one embodiment, when forming the second photomask layer 140, a second bottom anti-reflection layer can be first formed in the graphic grooves 20 and on the sacrificial layer 120, so that the second bottom anti-reflection layer fills the graphic grooves 20 and covers the surface of the sacrificial layer 120 outside the graphic grooves 20, and the second bottom anti-reflection layer has a relatively flat upper surface. Then, a second photoresist layer is formed on the second bottom anti-reflection layer, and the stack of the second bottom anti-reflection layer and the second photoresist layer is patterned by a photolithography process to obtain a patterned second photomask layer 140.

[0048] In this embodiment, the second photomask layer 140 is not formed directly in the above-mentioned pattern grooves 20 and on the sacrificial layer 120. Instead, before forming the second photomask layer 140, a leveling layer 103 with a leveling property is first formed, the leveling layer 103 fills the above-mentioned pattern grooves 20 and covers the sacrificial layer 120, and the leveling layer 103 has a flat upper surface. After the leveling layer 103 is formed, a second bottom anti-reflection layer BARC2 and a second photoresist layer PR2 are sequentially stacked on the surface of the leveling layer 103, and the stack of the second bottom anti-reflection layer BARC2 and the second photoresist layer PR2 is patterned by a photolithography process to obtain a patterned second photomask layer 140.

[0049] The second photomask layer 140 is used to define the position of the hole to be formed in the interlayer dielectric layer 110. In this embodiment, part of the boundary of the hole is defined by the second photomask layer 140, and the other part of the boundary is self-aligned using the side wall of the graphic groove 20 (that is, defined by the boundary of the graphic groove). The purpose is, on the one hand, to limit the position of the hole to the width of the graphic groove 20, which helps to avoid the displacement of the hole. On the other hand, due to the smaller feature size under advanced process nodes, the hole size is small, and it is difficult to directly use photomask materials to make the hole pattern. By using the graphic groove 20 to self-align part of the boundary of the hole, the difficulty of patterning the photomask material can be reduced while the size of the hole meets the design requirements of advanced process nodes. Figure 3 The positional relationship between the pattern groove 20 and the opening 140a in the second photomask layer 140 is shown. Figure 2D and Figure 3 In this embodiment, the opening 140a in the second photomask layer 140 spans the pattern groove 20, that is, the opening 140a in the second photomask layer 140 is in the width direction of the pattern groove 20 (eg Figure 3 The two opposite side walls on the AA' direction in the figure are both located at the periphery of the side walls of the pattern groove 20 (correspondingly, the two opposite side walls of part of the pattern groove 20 are located at the inner side of the opening 140a). In the width direction of the pattern groove 20, the width W1 of the opening 140a is, for example, greater than the width W2 of the pattern groove 20 below. It should be noted that Figure 3 Only a portion of the pattern groove 20 is shown. Figure 3 The three sections of the graphic groove 20 shown are different sections of the same graphic groove 20. Figure 3 connected outside the area shown.

[0050] Reference Figure 1 and Figure 2E , execute step S5, use the second photomask layer 140 as an etching mask, and use the sacrificial layer 120 and the metal hard mask layer MHM for blocking, etch the interlayer dielectric layer 110 to form a hole 110a extending from the bottom surface of the graphic groove 20 to the interlayer dielectric layer 110, and then remove the second photomask layer 140.

[0051] Step S5 may adopt an anisotropic dry etching process. In this embodiment, a leveling layer 103 is formed between the second photomask layer 140 and the sacrificial layer 120 and in the pattern groove 20. During the etching process of step S5, the leveling layer 103 is etched before the interlayer dielectric layer 110. Figure 2EAs shown, by etching, the pattern of the second photomask layer 140 is transferred to the planarization layer 103 above the pattern groove 20, so that a through hole of the same size as the opening 140a is formed in the planarization layer 103 above the pattern groove 20, and the through hole exposes a portion of the top surface of the sacrificial layer 120 at the opening of the pattern groove 20. When the planarization layer 103 in the pattern groove 20 is further etched downward, due to the obstruction of the side wall of the pattern groove 20, a through hole surrounded by the side wall of the pattern groove 20 and the planarization layer 103 is formed in the pattern groove 20, and the hard mask protection layer 102 at the bottom of the pattern groove is exposed. As the etching proceeds, the hard mask protection layer 102 and the interlayer dielectric layer 110 thereunder are etched, forming a hole 110a extending from the bottom surface of the pattern groove 20 to the inside of the interlayer dielectric layer 110, and the side wall of the hole 110a in the width direction of the pattern groove 20 is aligned with the side wall of the pattern groove 20, as shown in FIG. Figure 3 shown.

[0052] In the present embodiment, a sacrificial layer 120 is formed on the metal hard mask layer MHM. During the etching process of step S5, part of the sacrificial layer 120 can be etched. By setting a suitable thickness, it can be ensured that after the hole 110a is formed, it still covers the metal hard mask layer MHM to protect the metal hard mask layer MHM. Thus, it can be ensured that the width of the graphic groove 20 in the metal hard mask layer MHM does not change substantially during the etching process, so that the position accuracy of the hole 110a limited by the width of the graphic groove 20 is high to avoid displacement.

[0053] Reference Figure 2F Then, the second photomask layer 140 is removed. In this embodiment, the planarization layer 103 is also removed.

[0054] Through the above process, a graphic groove 20 is formed in the metal hard mask layer MHM on the interlayer dielectric layer 110 and the sacrificial layer 120, and a hole 110a connected to the graphic groove 20 is formed in the interlayer dielectric layer 110. In the width direction of the graphic groove 20, the side wall of the hole 110a is limited by the side wall of the graphic groove 20 in the metal hard mask layer MHM, and the width of the hole 110a is equal to the width of the graphic groove 20 in the metal hard mask layer MHM.

[0055] Reference Figure 1 , execute step S6, transfer the pattern of the graphic groove 20 to the interlayer dielectric layer 110, form a dielectric groove 110b on the upper part of the interlayer dielectric layer 110, and etch the interlayer dielectric layer 110 downward along the hole 110a, and form a through hole 110c penetrating the interlayer dielectric layer 110 at the bottom of the dielectric groove 110b.

[0056] Step S6 may specifically include the following process:

[0057] First, if Figure 2G As shown, a dry etching process is performed using the sacrificial layer 120 and the metal hard mask layer MHM as etching masks to etch the hard mask buffer layer 101 and the interlayer dielectric layer 110, and a dielectric trench 110b is formed on the upper portion of the low-k dielectric layer 112 in the interlayer dielectric layer 110 corresponding to the pattern trench 20, and a dielectric through hole 112a penetrating the low-k dielectric layer 112 is formed corresponding to the hole 110a, and the dielectric through hole 112a exposes the etching stop layer 111;

[0058] Then, if Figure 2H As shown, a wet etching process is performed to etch the etch stop layer 111 exposed by the dielectric via 112 a so that the dielectric via 112 a extends downward to form a through hole 110 c , and the through hole 110 c exposes the corresponding electrical connection in the first metal interconnection structure 10 .

[0059] After the above process, a dielectric trench 110b located at the upper part and a through hole 110c located at the lower part are formed in the interlayer dielectric layer 110, the dielectric trench 110b is connected with the through hole 110c, and the through hole 110c exposes the electrical connection member in the first metal interconnection structure 10, so that an interconnection structure connected to the first metal interconnection structure 10 can be formed by filling the through hole 110c and the dielectric trench 110b with a conductive material, which may specifically include the following process:

[0060] like Fig.2I As shown, the sacrificial layer 120 is removed, and the hard mask protection layer 102 is also removed in this embodiment to expose the top surface of the metal hard mask layer MHM;

[0061] Then, if Figure 2J As shown, a metal material 150 is deposited, and the metal material 150 fills the pattern groove 20 in the metal hard mask layer MHM, the dielectric groove 110b and the through hole 110c in the interlayer dielectric layer 110, and covers the metal hard mask layer MHM;

[0062] Afterwards, if Figure 2KAs shown, a planarization process (such as CMP) is performed to remove the metal hard mask layer MHM and the metal material 150 located on the interlayer dielectric layer 110. The remaining metal material 150 is filled in the dielectric trench 110b and the through hole 110c and is in contact with the electrical connection in the first metal interconnection structure 10. The metal material filled in the dielectric trench 110b and the through hole 110c constitutes a second metal interconnection structure, which is located on the first metal interconnection structure 10 and is electrically connected to the first metal interconnection structure 10. In the second metal interconnection structure, the metal material 150 filled in the dielectric trench 110b, for example, constitutes a metal interconnection layer, and the metal material 150 filled in the through hole 110c constitutes a connection channel between the metal interconnection layer and the first metal interconnection structure 10.

[0063] In the method for forming a semiconductor device described in the above embodiment, a metal hard mask layer MHM, a sacrificial layer 120 and a patterned first photomask layer 130 are stacked in sequence on the interlayer dielectric layer 110, and the first photomask layer 130 is first used as an etching mask to form a pattern groove 20 that penetrates the sacrificial layer 120 and the metal hard mask layer MHM. Then, when the interlayer dielectric layer 110 is etched using the patterned second photomask layer 140 as an etching mask, the sacrificial layer 120 and the metal hard mask layer MHM are used for blocking at the same time, so that the hole 110a formed in the interlayer dielectric layer 110 is limited by the width of the pattern groove 20 to avoid displacement. Moreover, during the etching process, the sacrificial layer 120 can protect the metal hard mask layer MHM to avoid the side wall of the metal hard mask layer MHM of the pattern groove 20 from being etched, which can improve the position accuracy of the hole 110a and the through hole 110c.

[0064] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: include: forming a first metal interconnect structure and an interlayer dielectric layer covering the first metal interconnect structure on a substrate; stacking a metal hard mask layer, a sacrificial layer and a patterned first photomask layer in sequence on the interlayer dielectric layer; Using the first photomask layer as an etching mask, etching the sacrificial layer and the metal hard mask layer to form a pattern groove penetrating the sacrificial layer and the metal hard mask layer, and then removing the first photomask layer; forming a patterned second photomask layer on the sacrificial layer, wherein an opening in the second photomask layer spans across the patterned grooves; Using the second photomask layer as an etching mask, and using the sacrificial layer and the metal hard mask layer for blocking, etching the interlayer dielectric layer to form a hole extending from the bottom surface of the pattern groove into the interlayer dielectric layer, and then removing the second photomask layer; as well as The pattern of the graphic groove is transferred to the interlayer dielectric layer, a dielectric groove is formed on the upper part of the interlayer dielectric layer, and the interlayer dielectric layer is etched downward along the hole to form a through hole penetrating the interlayer dielectric layer at the bottom of the dielectric groove.

2. The forming method according to claim 1, characterized in that: The interlayer dielectric layer includes an etch stop layer covering a surface of the first metal interconnect structure and a low-k dielectric layer covering a surface of the etch stop layer.

3. The forming method according to claim 1, characterized in that: Transferring the pattern of the pattern groove to the interlayer dielectric layer, and etching the interlayer dielectric layer downward along the hole comprises: Using the sacrificial layer and the metal hard mask layer as etching masks, a dry etching process is performed to form the dielectric trench on the upper portion of the low-k dielectric layer, and a dielectric through hole is formed corresponding to the hole to penetrate the low-k dielectric layer, wherein the dielectric through hole exposes the etching stop layer; and A wet etching process is performed to etch the etch stop layer exposed by the dielectric through hole, so that the dielectric through hole extends downward to form the through hole, and the through hole exposes the corresponding electrical connection in the first metal interconnection structure.

4. The forming method according to claim 1, characterized in that: After forming the through hole, the method further includes: removing the consumable layer; Depositing a metal material, wherein the metal material fills the pattern trench, the dielectric trench, and the through hole and covers the metal hard mask layer; and A planarization process is performed to remove the metal hard mask layer and the metal material located on the interlayer dielectric layer.

5. The forming method according to claim 1, characterized in that: Before forming a patterned second photomask layer on the sacrificial layer, the forming method further includes: forming a leveling layer, wherein the leveling layer fills the pattern grooves and covers the sacrificial layer; The second photomask layer is formed on the surface of the planarization layer. Before the interlayer dielectric layer is etched using the second photomask layer as an etching mask, the planarization layer is etched using the second photomask layer as an etching mask while the sacrificial layer and the metal hard mask layer are blocked.

6. The forming method according to claim 1, characterized in that: The width of the opening in the second photomask layer is greater than the width of the pattern groove located below the opening.

7. The forming method according to any one of claims 1 to 6, characterized in that: Also includes: A hard mask buffer layer is formed between the interlayer dielectric layer and the metal hard mask layer.

8. The forming method according to any one of claims 1 to 6, characterized in that: Also includes: A hard mask protection layer is formed between the sacrificial layer and the metal hard mask layer.

9. The forming method according to any one of claims 1 to 6, characterized in that: The consumption layer includes at least one of SiCN, SiC and Si3N4.

10. The forming method according to any one of claims 1 to 6, characterized in that: The metal hard mask layer includes at least one of titanium nitride and titanium oxide.

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