Interconnection process between copper column type I / O and glass embedded packaging body

Abstract

The invention discloses an interconnection process between a copper column type I / O and a glass embedded packaging body in glass panel level embedded advanced packaging, and belongs to the field of semiconductor devices. The interconnection method comprises the following manufacturing processes: preparing a glass embedded packaging body; the RDL polymer dielectric layer is laminated on the surface of the glass embedded packaging body and solidified; carrying out surface leveling treatment on the RDL polymer dielectric layer to expose copper columns on the chip; and manufacturing the RDL layer by using a standard semi-additive process. According to the technology, copper-copper interconnection from the chip to the glass panel level embedded packaging body is formed on the active surface of the chip, and compared with a common interconnection technology from the chip to the packaging body, the technology has the advantages that the interconnection path is shorter, the interconnection loss is lower, and the practical value is achieved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices, and in particular discloses an interconnection process between a copper column type I / O and a glass embedded package. Background Art

[0002] With the rapid development of technologies such as mobile devices, high-performance computing, and network communications, traditional wire bonding packaging methods have gradually shown their limitations, including low interconnection density, slow signal transmission speed, and large package size. Flip chip packaging technology has become one of the preferred packaging solutions in these fields due to its advantages of high-density integration and miniaturization. Flip chip packaging is an advanced semiconductor packaging technology that allows the active side of the chip, i.e. the side containing the circuit, to face down and be directly connected to the packaging substrate. This connection is achieved by forming bumps on the chip's pads, usually using solder such as tin-lead alloy.

[0003] However, flip-chip packaging technology also has some disadvantages. The solder balls of flip-chip packaging may have various welding defects, such as cold solder joints, bridging, pinholes, etc. In high-frequency and high-precision application scenarios, these defects will significantly affect the mechanical and electrical properties of the package. The solder used in flip-chip packaging may contain harmful substances such as lead, which has potential impacts on the environment.

[0004] Patent CN117525028A proposes a multi-chip stacking packaging structure and its formation method. The packaging structure of the invention also includes a heat dissipation cover and solder balls. The heat dissipation cover is arranged on the front of the substrate and surrounds the chip stacking module and the main chip. The solder balls are arranged on the back of the substrate. This process has a high processing cost. Under the premise of using solder, it will affect the electrical transmission performance between the chip and the substrate to a certain extent, and the use scenario is limited.

[0005] Glass Panel Embedded Packaging (GPE), which uses glass as the core packaging material, has become a hot technology for advanced packaging due to the excellent mechanical and electrical properties of glass itself (matching of thermal expansion coefficients, high Young's modulus, and low loss factor). It can be used for next-generation high-density and high-performance digital, analog, power, RF, and millimeter-wave applications. However, in the existing glass substrate advanced packaging process, the implementation method of electrical connection limits the further reduction of interconnection loss, which restricts its application in high-frequency and high-precision scenarios.

[0006] In summary, how to achieve low-loss, low-cost direct interconnection from chip to package under high-frequency, high-precision application requirements is an urgent problem to be solved. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned background technology and to provide an interconnection process between a copper pillar type I / O and a glass embedded package. By making an RDL directly connected to the copper pillar on the chip, the copper-copper interconnection between the chip and the glass embedded package is achieved, thereby solving the technical problem of high electrical signal loss under high-frequency and high-precision application requirements in traditional processes at a relatively low cost.

[0008] The present invention adopts the following technical solutions to achieve the above-mentioned invention object: A process for interconnecting a copper pillar I / O with a glass embedded package, the process comprising the following steps: Step 1, preparing a glass embedded package, which includes: a glass panel with a cavity, a glass substrate and a test chip, the glass panel with a cavity and the glass substrate are bonded to form a package substrate with a glass blind cavity, the active surface of the test chip is bonded with a copper pillar, the passive surface of the test chip is bonded with an adhesive film layer, and the active surface of the test chip is placed upward in the glass blind cavity; Step 2: Laminating the RDL polymer dielectric layer on the surface of the glass embedded package and curing it to form an RDL polymer dielectric layer covering the surface of the glass embedded package and filling the gap between the glass blind cavity and the test chip; Step 3: performing surface planarization on the RDL polymer dielectric layer to expose the copper pillars on the active surface of the test chip; Step 4: Fabricate an RDL layer connected to the copper pillar on the surface of the RDL polymer dielectric layer.

[0009] As a further optimization solution for the interconnection process between the copper pillar I / O and the glass embedded package, the test chip height is higher than the glass blind cavity depth.

[0010] As a further optimization solution for the interconnection process between the copper pillar I / O and the glass embedded package, step two uses a vacuum laminator to laminate the RDL polymer dielectric onto the surface of the glass embedded package.

[0011] As a further optimization scheme for the interconnection process between the copper pillar type I / O and the glass embedded package, the RDL polymer dielectric layer formed after curing in step 2 completely covers the active surface of the test chip, the copper pillars bonded on the active surface of the test chip, and the upper surface of the glass substrate with the cavity.

[0012] As a further optimization scheme for the interconnection process between the copper pillar I / O and the glass embedded package, the specific method of step three for surface planarization of the RDL polymer dielectric layer is: using chemical mechanical polishing or fly cutting process to remove excess RDL polymer dielectric and part of the copper.

[0013] As a further optimization scheme for the interconnection process between a copper pillar type I / O and a glass embedded package, in step 4, an RDL layer fabricated on the surface of an RDL polymer dielectric layer using a semi-additive process is connected to the copper pillar.

[0014] As a further optimization scheme for the interconnection process between copper pillar I / O and glass embedded package, in step 4, the thickness of the RDL layer made by the semi-additive process is 1-3 μm, and the copper wiring line width is 1.5-5 μm.

[0015] The present invention adopts the above technical solution and has the following beneficial effects: (1) Compared with the flip-chip packaging technology, the interconnection process between the copper pillar type I / O and the glass embedded package proposed in the present invention realizes the copper-copper interconnection between the chip and the glass embedded package by making an RDL directly connected to the copper pillar on the chip. The resistivity of copper is better than that of solder. Therefore, the interconnection realized by the present invention has lower interconnection loss in high-frequency applications.

[0016] (2) Compared with the copper-copper interconnection formed by hot pressing in a vacuum environment, the interconnection process between the copper pillar type I / O and the glass embedded package proposed in the present invention uses a standard semi-additive process to make RDL and form a copper-copper interconnection with the copper pillar bonded on the active surface of the chip. The process conditions are simpler, the technology is more mature, and the process cost is lower.

[0017] (3) Compared with the solder ball interconnection process, the interconnection process between the copper pillar type I / O and the glass embedded package proposed in the present invention can achieve a higher interconnection density and improve the precision and accuracy of the interconnection.

[0018] (4) Compared with the solder ball interconnection process, the interconnection process between the copper pillar I / O and the glass embedded package proposed in the present invention improves the flatness of the package and reduces mechanical stress concentration through fly cutting. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a structural diagram of the glass embedded package proposed by the present invention.

[0020] Figure 2 This is a structural diagram of the RDL polymer dielectric after lamination in the interconnection process proposed by the present invention.

[0021] Figure 3 This is a structural diagram of the RDL polymer dielectric layer after surface planarization treatment according to the interconnection process proposed in the present invention.

[0022] Figure 4 This is a structural diagram of the interconnection process proposed in the present invention after the RDL layer is manufactured using a standard semi-additive process.

[0023] Figure 5The figure is a flow chart of the interconnection process proposed by the present invention.

[0024] Explanation of the numbers in the figure: 1. Glass panel with cavity; 2. Dry film adhesive; 3. Test chip; 4. Copper pillar; 5. RDL polymer dielectric layer; 6. RDL layer. DETAILED DESCRIPTION

[0025] The technical solution of the invention is described in detail below with reference to the accompanying drawings.

[0026] In order to improve the problem that the chip and the package body in the embedded package are greatly affected by the solder during the high-frequency signal transmission and the interconnection loss of the existing GPE process is large, the present invention proposes an improved interconnection process for the glass panel-level embedded advanced packaging technology. The process, first, prepares a glass embedded package body, the package body includes: a glass panel with a cavity, a glass substrate and a test chip, the glass panel with a cavity and the glass substrate are bonded to form a package substrate with a glass blind cavity, the active surface of the test chip is bonded with a copper column, the passive surface of the test chip is bonded with an adhesive film layer, and the active surface of the test chip is placed in the glass blind cavity upward; then, the RDL polymer dielectric layer is laminated on the surface of the glass embedded package body and cured to reduce the warping of the package body; then, the RDL polymer dielectric layer is subjected to surface flattening treatment to expose the copper column on the chip; finally, the RDL directly connected to the copper column is made using a standard semi-additive process to achieve copper-copper interconnection between the chip and the glass embedded package body.

[0027] like Figure 5 As shown, the interconnection process between a copper pillar type I / O and a glass embedded package provided by the present invention includes the following four steps.

[0028] Step 1: Prepare glass embedded package like Figure 1 As shown, the total thickness of the glass embedded package is 213.8μm, including a 50μm thick glass substrate, a 70μm thick glass panel 1 with a cavity, a dry film adhesive 2, and a 75μm thick test chip 3 embedded in a glass blind cavity. The cavity opened on the glass panel runs through the panel body, and the glass panel 1 with a cavity is bonded to the glass substrate by the dry film adhesive 2 to form a package substrate with a glass blind cavity. An adhesive film layer is bonded to the passive surface of the test chip 3, and a copper column 4 is bonded to the active surface of the test chip. The active surface of the test chip 3 is facing up and then placed in the glass blind cavity. The key features of the test chip are: size 6.469mm×5.902mm, thickness 75μm, pin pitch 65μm, copper pillar thickness 20μm, the copper pillar is formed on the original pad using standard WLCSP UBM pad forming technology. This process is performed on a silicon wafer and the test chip is assembled with a dry film adhesive layer on a 50μm thick glass substrate using Kulicke and Soffa's high-speed placement tool.

[0029] preparation Figure 1 The method of the glass embedded package is as follows: forming a cavity penetrating the panel body on a glass panel; bonding the glass panel with the cavity to another glass substrate by dry film adhesive to form a package substrate with a glass blind cavity; bonding a copper column to the active surface of a test chip; bonding an adhesive film layer to the passive surface of the test chip, and placing the test chip in the glass blind cavity with the active surface facing upward.

[0030] Step 2: Laminating the RDL polymer dielectric onto the surface of the glass embedded package and curing it like Figure 2 As shown, the RDL polymer dielectric layer is laminated on the surface of the glass embedded package using Meiki's MVLP300 / 300-S vacuum laminator to adhere and cure the RDL to form an RDL polymer dielectric layer 5 that covers the surface of the glass embedded package and fills the gap between the glass blind cavity and the test chip 3.

[0031] Step 3: Surface planarization of the RDL polymer dielectric layer to expose the copper pillars on the active surface of the test chip In this embodiment, the fly-cut process is used to remove the excess RDL polymer dielectric and part of the copper to complete the fly-cut package structure. Figure 3 shown.

[0032] Step 4: Use standard semi-additive process to make RDL layer.

[0033] like Figure 4 As shown, copper is used as a seed layer, and an RDL layer 6 with a copper line width of 3 μm is made on the surface of the RDL polymer dielectric layer. The copper pillars 4 are directly connected to the RDL layer 6, and a copper-copper interconnection from the chip to the glass panel level embedded package is formed on the active surface of the test chip 3.

[0034] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above specific embodiments. The above specific embodiments and the description in the specification are only for further illustrating the principles and preparation effects of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, for example, the method for making the RDL layer, and these changes and improvements fall within the scope of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A process for interconnecting a copper pillar I / O with a glass embedded package, characterized in that: The steps include: Step 1, preparing a glass embedded package, the package comprising: a glass panel with a cavity, a glass substrate and a test chip, the glass panel with a cavity and the glass substrate are bonded to form a package substrate with a glass blind cavity, the active surface of the test chip is bonded with a copper pillar, the passive surface of the test chip is bonded with an adhesive film layer, and the active surface of the test chip is placed upward into the glass blind cavity; Step 2: Laminating the RDL polymer dielectric layer on the surface of the glass embedded package and curing it to form an RDL polymer dielectric layer covering the surface of the glass embedded package and filling the gap between the glass blind cavity and the test chip; Step 3, planarizing the RDL polymer dielectric layer to expose the copper pillars; Step 4: fabricate an RDL layer connected to the copper pillar on the surface of the RDL polymer dielectric layer.

2. The interconnection process between a copper pillar type I / O and a glass embedded package according to claim 1, characterized in that: The specific method for preparing the glass embedded package body in step 1 is: forming a cavity penetrating the panel body on the glass panel; bonding the glass panel with the cavity to another glass substrate by dry film adhesive to form a package substrate with a glass blind cavity; bonding a copper column to the active surface of the test chip, bonding an adhesive film layer to the passive surface of the test chip, and placing the test chip in the glass blind cavity with the active surface facing upward.

3. The interconnection process between a copper pillar I / O and a glass embedded package according to claim 2, characterized in that: The specific method for bonding copper pillars on the active surface of the test chip is: forming copper pillars on a silicon wafer; bonding the copper pillars to the active surface of the test chip on a glass substrate: a dry film adhesive is coated on the active surface of the test chip, and the copper pillars are picked up by a high-speed placement tool and placed on the active surface of the test chip.

4. The interconnection process between a copper pillar type I / O and a glass embedded package according to claim 3, characterized in that: The height of the test chip is greater than the depth of the glass blind cavity.

5. The interconnection process between a copper pillar type I / O and a glass embedded package according to any one of claims 1 to 4, characterized in that: The second step is to laminate the RDL polymer dielectric on the surface of the glass embedded package using a vacuum laminator.

6. The interconnection process between a copper pillar type I / O and a glass embedded package according to any one of claims 1 to 4, characterized in that: Step 3: The specific method of planarizing the RDL polymer dielectric layer is: using chemical mechanical polishing or fly cutting process to remove excess RDL polymer dielectric and part of copper.

7. The interconnection process between a copper pillar type I / O and a glass embedded package according to any one of claims 1 to 4, characterized in that: In step 4, a standard semi-additive process is used to form an RDL layer connected to the copper pillars on the surface of the RDL polymer dielectric layer.

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