Semiconductor device

Abstract

Embodiments provide a semiconductor device that improves heat dissipation performance. According to one embodiment, a semiconductor device includes a first substrate, a second substrate, a chip, and a spacer. The second substrate is provided so as to face the first substrate. The chip is arranged on the first substrate and between the first substrate and the second substrate. The spacer is arranged on the chip and connects the chip with the second substrate. The area of the second part, connected with the second substrate, of the spacer is larger than that of the first part, connected with the chip, of the spacer.

Description

[0001] Reference to related applications

[0002] This application claims the priority of Japanese Patent Application No. 2023-120015 (filing date: July 24, 2023) as a basic application. The present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] A power module is known as a semiconductor device. A power module is known that has a structure in which heat is dissipated from both the upper and lower surfaces of the module. Summary of the invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device with improved heat dissipation performance.

[0006] A semiconductor device of an embodiment includes a first substrate, a second substrate, a chip, and a spacer. The second substrate is disposed opposite to the first substrate. The chip is disposed on the first substrate and between the first substrate and the second substrate. The spacer is disposed on the chip to connect the chip to the second substrate. The area of ​​the second portion of the spacer in contact with the second substrate is larger than the area of ​​the first portion of the spacer in contact with the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a circuit diagram showing a configuration example of a semiconductor device according to an embodiment.

[0008] Figure 2 It is a perspective view showing an example of the appearance of a semiconductor device according to an embodiment.

[0009] Figure 3 It is a perspective view showing an example of the internal structure of the semiconductor device according to the embodiment.

[0010] Figure 4 It is a plan view showing an example of the internal structure of the semiconductor device according to the embodiment.

[0011] Figure 5 It is a plan view showing an example of the internal structure of the semiconductor device according to the embodiment.

[0012] Figure 6 This is a cross-sectional view showing an example of the internal structure of the semiconductor device according to the embodiment.

[0013] Figure 7 This is a cross-sectional view showing an example of the internal structure of the semiconductor device according to the embodiment.

[0014] Figure 8It is a plan view showing an example of the internal structure of the semiconductor device according to the first modification.

[0015] Fig. 9 This is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a first modification.

[0016] Fig.10 This is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a second modification.

[0017] Fig.11 This is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a third modification.

[0018] Fig.12 is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a fourth modification.

[0019] Fig.13 It is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a fifth modification.

[0020] Fig.14 It is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a sixth modification.

[0021] Fig.15 This is a cross-sectional view showing an example of the internal structure of a semiconductor device according to the seventh modification.

[0022] Fig.16 It is a cross-sectional view showing an example of the internal structure of a semiconductor device according to an eighth modification.

[0023] Description of Reference Numerals

[0024] 1 ... semiconductor device, 11, 12 ... substrate, 11a, 11b, 12a, 12b, 12c, 12d, 12e, 12f, 12g ... circuit pattern, 21, 22 ... chip, 31, 31a, 31b, 32, 32a, 32b, 33, 33a, 33b, 34, 34a, 34b, 35, 35a, 35b, 36, 37, 37a, 37b, 37c, 38 , 39…spacer, 41, 42…substrate spacer, 50…sealant, 60…bonding layer, BW1, BW2, BW3, BW4…bonding wire, NM1, NM2…transistor, PD1…drain electrode, PG1, PG2, PSL1, PSL2, PSS1, PSS2…pad, TD1, TD2, TG1, TG2, TN, TOUT, TP, TS1, TS2…terminal. DETAILED DESCRIPTION

[0025] The following describes the implementation mode with reference to the accompanying drawings. When describing, the same reference numerals are used to mark the components having substantially the same function and structure. In addition, the implementation mode shown below is used to illustrate the technical idea. The implementation mode does not determine the material, shape, structure, configuration, etc. of the components. Various changes can be added to the implementation mode.

[0026] <Implementation Method>

[0027] A semiconductor device according to an embodiment will be described. A semiconductor device 1 according to an embodiment is a power module. The semiconductor device 1 is used in a power conversion device of an electric vehicle, for example.

[0028] <1>Composition

[0029] <1-1> Circuit Configuration of Semiconductor Device

[0030] Figure 1 1 is a circuit diagram showing a configuration example of a semiconductor device according to an embodiment. The semiconductor device 1 according to the embodiment includes, for example, a half-bridge circuit. Figure 1 As shown, the semiconductor device 1 includes terminals TP, TN, TOUT, TG1, TG2, TD1, TD2, TS1, and TS2, and transistors NM1 and NM2.

[0031] Terminals TP and TN are power supply terminals of the semiconductor device 1. A positive power supply voltage is applied to the terminal TP, and a negative power supply voltage is applied to the terminal TN.

[0032] The terminal TOUT is an output terminal of the semiconductor device 1 .

[0033] The terminals TG1 and TG2 are control terminals of the semiconductor device 1 , respectively.

[0034] The terminals TD1 , TD2 , TS1 , and TS2 are terminals for monitoring the operation of the semiconductor device 1 .

[0035] The transistors NM1 and NM2 are, for example, N-type MOS transistors. The drain of the transistor NM1 is connected to the terminal TP. The source of the transistor NM1 is connected to the terminal TOUT. The gate of the transistor NM1 is connected to the terminal TG1. The drain of the transistor NM2 is connected to the terminal TOUT. The source of the transistor NM2 is connected to the terminal TN. The gate of the transistor NM2 is connected to the terminal TG2.

[0036] The drain of the transistor NM1 is connected to the terminal TD1. The source of the transistor NM1 is connected to the terminal TS1. The drain of the transistor NM2 is connected to the terminal TD2. The source of the transistor NM2 is connected to the terminal TS2.

[0037] <1-2>Semiconductor device package structure

[0038] Figure 2 1 is a perspective view showing an example of the appearance of a semiconductor device according to an embodiment. The semiconductor device 1 has, for example, a thin cubic shape. Hereinafter, the thickness direction of the semiconductor device 1 is referred to as the up-down direction. In addition, when a component of the semiconductor device 1 has two surfaces facing each other in the up-down direction, the two surfaces are referred to as the upper surface and the lower surface, respectively.

[0039] The semiconductor device 1 further includes substrates 11 and 12 and a sealing member 50. The terminals TP, TN, TOUT, TG1, TG2, TD1, TD2, TS1, and TS2 are terminals responsible for electrical connection with the outside, and have portions exposed to the outside of the sealing member 50. The substrates 11 and 12 each have a portion exposed to the outside of the sealing member 50. Hereinafter, the exposed surface of the substrate 11 is referred to as the upper surface, and the exposed surface of the substrate 12 is referred to as the lower surface.

[0040] The substrates 11 and 12 are insulating circuit substrates in which a conductor is attached to both surfaces of a plate-shaped insulator. The insulator is, for example, aluminum oxide. The conductor is, for example, copper. The substrates 11 and 12 are disposed opposite to each other. The substrates 11 and 12 are provided with circuit patterns on the surfaces facing the inner side of the semiconductor device 1, respectively. The substrate 11 is configured to be partially exposed on the upper surface of the sealing member 50. The substrate 12 is configured to be partially exposed on the lower surface of the sealing member 50. The substrate 11 exposed on the upper surface of the sealing member 50 and the substrate 12 exposed on the lower surface of the sealing member 50 each also function as a heat sink that releases heat generated inside the semiconductor device 1 to the outside of the semiconductor device 1.

[0041] The terminals TP, TN, and TOUT are provided to be exposed on the side surface of the seal 50. For example, the terminals TP and TN protrude from the side surface, that is, the first surface, of the seal 50. For example, the terminal TOUT protrudes from the approximate center of the second surface of the side surface of the seal 50 that is opposite to the first surface from which the terminals TP and TN protrude. The terminals TP, TN, and TOUT are respectively bent in an L-shape at the protruding front end, and have a circular opening at the L-shaped bent front end.

[0042] The terminals TG1, TD1 and TS1 are exposed on the side of the seal 50. For example, the terminals TG1, TD1 and TS1 are arranged on the second surface of the side of the seal 50 and the terminal TOUT, and are arranged between the terminal TOUT and the end of the second surface. The terminals TG1, TD1 and TS1 protrude from the side of the seal 50.

[0043] The terminals TG2, TD2, and TS2 are provided to be exposed on the side surface of the seal 50. For example, the terminals TG2, TD2, and TS2 are arranged with the terminal TOUT on the second surface of the side surface of the seal 50, and are provided between the terminal TOUT and the end of the second surface on the side opposite to the portion where the terminals TG1, TD1, and TS1 are provided. The terminals TG2, TD2, and TS2 protrude from the side surface of the seal 50.

[0044] The sealing member 50 is an insulating member that physically and electrically protects the internal structure of the semiconductor device 1 from the outside. The sealing member 50 forms the outer shape of the semiconductor device 1 .

[0045] <1-3> Internal structure of semiconductor devices

[0046] Reference Figure 3 as well as Figure 4 , the internal structure of the semiconductor device 1 is described. Figure 3 It is a perspective view showing an example of the internal structure of the semiconductor device according to the embodiment. Figure 4 FIG. 1 is a top view showing an example of the internal structure of a semiconductor device according to an embodiment. Figure 3 as well as Figure 4 , the substrate 11 and the sealing member 50 are omitted. The semiconductor device 1 further includes chips 21 and 22, spacers 31 and 32, and substrate spacers 41 and 42 as internal structures. In addition, the substrate 12 includes circuit patterns 12a, 12b, 12c, 12d, 12e, 12f, and 12g.

[0047] The circuit patterns 12a, 12b, 12c, 12d, 12e, 12f, and 12g are conductors provided on the substrate 12, such as copper. The circuit pattern 12a is connected to the terminals TP and TD1. The circuit pattern 12b is connected to the terminals TOUT and TD2. The circuit pattern 12c is connected to the terminal TN. The circuit pattern 12d is connected to the terminal TS1. The circuit pattern 12e is connected to the terminal TG1. The circuit pattern 12f is connected to the terminal TS2. The circuit pattern 12g is connected to the terminal TG2.

[0048] Chips 21 and 22 are power semiconductor chips. Specifically, for example, chips 21 and 22 each include an N-type MOS transistor. The transistors included in chip 21 are used Figure 1 The transistors included in chip 22 correspond to the transistor NM1 described above. Figure 1 The chips 21 and 22 correspond to the transistor NM2 described above. Each of the chips 21 and 22 has a rectangular plate shape, for example. The lower surface of each of the chips 21 and 22 is used as an electrode corresponding to a drain.

[0049] Pads PSL1 and PSS1 corresponding to the source and pad PG1 corresponding to the gate are provided on the upper surface of the chip 21. Pad PSL1 is a large pad occupying most of the upper surface of the chip 21. Pad PSL1 is provided in the central part of the upper surface of the chip 21. Pads PSS1 and PG1 are small pads. Pads PSS1 and PG1 are arranged along one side on the upper surface of the chip 21.

[0050] The upper surface of chip 22 is the same as the upper surface of chip 21. That is, pads PSL2 and PSS2 corresponding to the source and pad PG2 corresponding to the gate are provided on the upper surface of chip 22. Pad PSL2 is a large pad that occupies most of the upper surface of chip 22. Pad PSL2 is provided in the central portion of the upper surface of chip 22. Pads PSS2 and PG2 are small pads. Pads PSS2 and PG2 are arranged along one side on the upper surface of chip 22.

[0051] A chip 21 is provided on the circuit pattern 12a. Specifically, the chip 21 is provided so that pads PSS1 and PG1 are arranged so that the sides along which the pads PSS1 and PG1 are arranged face the direction in which the terminals TG1, TD1 and TS1 are provided. The drain electrode provided on the lower surface of the chip 21 is electrically connected to the circuit pattern 12a. Thus, the drain electrode provided on the lower surface of the chip 21 is electrically connected to the terminals TP and TD1. The pad PSS1 provided on the upper surface of the chip 21 is electrically connected to the circuit pattern 12d by the bonding wire BW1. Thus, the pad PSS1 is electrically connected to the terminal TS1. The pad PG1 provided on the upper surface of the chip 21 is electrically connected to the circuit pattern 12e by the bonding wire BW2. Thus, the pad PG1 is electrically connected to the terminal TG1.

[0052] A chip 22 is provided on the circuit pattern 12b. Specifically, the chip 22 is provided so that pads PSS2 and PG2 are arranged so that the edges along which the pads PSS2 and PG2 are arranged face the direction in which the terminals TG2, TD2 and TS2 are provided. The drain electrode provided on the lower surface of the chip 22 is electrically connected to the circuit pattern 12b. Thus, the drain electrode provided on the lower surface of the chip 22 is electrically connected to the terminals TOUT and TD2. The pad PSS2 provided on the upper surface of the chip 22 is electrically connected to the circuit pattern 12f using the bonding wire BW3. Thus, the pad PSS2 is electrically connected to the terminal TS2. The pad PG2 provided on the upper surface of the chip 22 is electrically connected to the circuit pattern 12g using the bonding wire BW4. Thus, the pad PG2 is electrically connected to the terminal TG2.

[0053] A spacer 31 is provided on a pad PSL1 provided on the upper surface of the chip 21. A spacer 32 is provided on a pad PSL2 provided on the upper surface of the chip 22. The spacers 31 and 32 are respectively conductive. The spacers 31 and 32 are respectively composite materials such as aluminum and silicon carbide. The spacers 31 and 32 each have a structure in which the area of ​​the upper surface is larger than the area of ​​the lower surface. The area of ​​the lower surface of the spacer 31 is smaller than the area of ​​the upper surface of the chip 21. The area of ​​the lower surface of the spacer 32 is smaller than the area of ​​the upper surface of the chip 22.

[0054] For example, the spacer 31 includes spacers 31a and 31b. The spacers 31a and 31b are rectangular flat plates with the area of ​​the upper surface and the area of ​​the lower surface being approximately equal. The spacer 31a has an upper surface and a lower surface that can be included in the upper surface of the chip 21 when viewed from above. The long sides of the upper surface and the lower surface of the spacer 31b are respectively longer than the long sides of the upper surface and the lower surface of the spacer 31a. The short sides of the upper surface and the lower surface of the spacer 31b are respectively longer than the short sides of the upper surface and the lower surface of the spacer 31a. The spacer 31 has a structure in which the spacer 31b overlaps on the spacer 31a in an aligned manner. The spacer 31 is set so that the side where the spacers 31a and 31b overlap in an aligned manner is arranged toward the chip 21, and the pads PSS1 and PG1 are arranged along the side along which the pads PSS1 and PG1 are arranged. The spacer 31 is electrically connected to the pad PSL1.

[0055] The same is true for the spacer 32. That is, the spacer 32 includes spacers 32a and 32b. The spacers 32a and 32b are rectangular flat plates with the area of ​​the upper surface and the area of ​​the lower surface being approximately equal, respectively. The spacer 32a has an upper surface and a lower surface that can be included in the upper surface of the chip 22 when viewed from above. The long sides of the upper surface and the lower surface of the spacer 32b are respectively longer than the long sides of the upper surface and the lower surface of the spacer 32a. The short sides of the upper surface and the lower surface of the spacer 32b are respectively longer than the short sides of the upper surface and the lower surface of the spacer 32a. The spacer 32 has a structure in which the spacer 32b overlaps on the spacer 32a in an aligned manner. The spacer 32 is set to the side along which the pads PSS2 and PG2 are arranged toward the chip 22. The spacer 32 is electrically connected to the pad PSL2.

[0056] A substrate spacer 41 is provided on the circuit pattern 12c and between the chips 21 and 22. A substrate spacer 42 is provided on the circuit pattern 12b and between the chips 21 and 22. The substrate spacers 41 and 42 are respectively conductive. The substrate spacers 41 and 42 are respectively composite materials such as aluminum and silicon carbide. The substrate spacers 41 and 42 have, for example, a cylindrical shape. The lower surface of the substrate spacer 41 is electrically connected to the circuit pattern 12c. Thus, the substrate spacer 41 is electrically connected to the terminal TN. The lower surface of the substrate spacer 42 is electrically connected to the circuit pattern 12b. Thus, the substrate spacer 42 is electrically connected to the terminals TOUT and TD2 and the drain electrode provided on the lower surface of the chip 22. The height of the upper surface of each of the substrate spacers 41 and 42 is substantially equal to the height of the upper surface of each of the spacers 31 and 32.

[0057] Figure 5 FIG. 1 is a top view showing an example of the internal structure of a semiconductor device according to an embodiment. Figure 5 In the figure, the seal 50 is omitted. Figure 5 As shown, the circuit pattern 11a provided on the lower surface of the substrate 11 electrically connects the upper surface of the spacer 31 with the upper surface of the substrate spacer 42. Thus, the pad PSL1 of the chip 21 is electrically connected to the terminal TOUT and TD2 and the drain electrode provided on the lower surface of the chip 22. The circuit pattern 11b provided on the lower surface of the substrate 11 electrically connects the upper surface of the spacer 32 with the upper surface of the substrate spacer 41. Thus, the pad PSL2 of the chip 22 is electrically connected to the terminal TN.

[0058] Figure 6 This is a cross-sectional view showing an example of the internal structure of the semiconductor device according to the embodiment. Figure 6 Shown with Figure 5 The cross section corresponding to the VI-VI line. Figure 6 , the sealing member 50 is omitted from the illustration. The circuit pattern 12a on the substrate 12 is bonded to the drain electrode PD1 provided on the lower surface of the chip 21 by means of a bonding layer 60. The pad PSL1 provided on the upper surface of the chip 21 is bonded to the lower surface of the spacer 31 by means of a bonding layer 60. The upper surface of the spacer 31a is bonded to the lower surface of the spacer 31b by means of a bonding layer 60. The upper surface of the spacer 31 is bonded to the circuit pattern 11a provided on the substrate 11 by means of a bonding layer 60. The lower surface of the substrate spacer 42 is bonded to the circuit pattern 12b on the substrate 12 by means of a bonding layer 60. The upper surface of the substrate spacer 42 is bonded to the circuit pattern 11a provided on the substrate 11 by means of a bonding layer 60. The bonding layer 60 is, for example, solder.

[0059] The same is true for the chip 22, the spacer 32, and the substrate spacer 41. That is, the circuit pattern 12b on the substrate 12 is bonded to the drain electrode provided on the lower surface of the chip 22 by a bonding layer. The pad PSL2 provided on the upper surface of the chip 22 is bonded to the lower surface of the spacer 32 by a bonding layer. The upper surface of the spacer 32a is bonded to the lower surface of the spacer 32b by a bonding layer. The upper surface of the spacer 32 is bonded to the circuit pattern 11b provided on the substrate 11 by a bonding layer. The lower surface of the substrate spacer 41 is bonded to the circuit pattern 12c on the substrate 12 by a bonding layer. The upper surface of the substrate spacer 41 is bonded to the circuit pattern 11b provided on the substrate 11 by a bonding layer. The bonding layer is, for example, solder.

[0060] Figure 7 This is a cross-sectional view showing an example of the internal structure of the semiconductor device according to the embodiment. Figure 7 Shown with Figure 5 The section corresponding to the VII-VII line. Figure 7 In the figure, the sealing member 50 is omitted. The pad PG1 provided on the upper surface of the chip 21 is electrically connected to the circuit pattern 12e by the bonding wire BW2. In the semiconductor device 1 of the embodiment, the spacer 31 is not provided above the pad PG1.

[0061] Similarly, the spacer 31 is not provided above the pad PSS1. As described above, in the semiconductor device 1 of the embodiment, the pad for wire bonding and the spacer are arranged so as not to overlap in a plan view.

[0062] The thermal expansion coefficients of the elements used in the semiconductor device 1 of the embodiment are as follows. The chips 21 and 22 mainly made of silicon are, for example, 2×10 －6 / K~5×10 －6 / K. The copper of the circuit pattern of the substrates 11 and 12 is, for example, 17×10 －6 / K. The aluminum-silicon carbide composite material contained in the spacers 31 and 32 and the substrate spacers 41 and 42 is, for example, 10×10 －6 / K. Thus, the thermal expansion coefficient of the aluminum-silicon carbide composite material included in the spacers 31 and 32 is larger than that of the chips 21 and 22 , and smaller than that of the copper included in the substrates 11 and 12 .

[0063] According to the semiconductor device 1 of the embodiment, it is possible to improve heat dissipation performance.

[0064] The spacer provided on the chip is a part of a current path connecting the source of the transistor included in the chip to the external connection terminal, and is also one of the heat dissipation paths for transferring the heat generated in the chip to the substrate 11 .

[0065] According to an embodiment, the spacer provided on the chip is configured so that the area of ​​the upper surface bonded to the substrate is larger than the area of ​​the lower surface bonded to the chip. Thus, when heat is transferred from the chip to the substrate via the spacer, the heat is diffused to a larger area, which can improve heat dissipation performance.

[0066] In addition, in the semiconductor device 1 of the embodiment, the thermal expansion coefficient of the spacer provided on the chip is larger than the thermal expansion coefficient of the chip and smaller than the thermal expansion coefficient of copper contained in the substrate. Therefore, even if the temperature of the semiconductor device 1 of the embodiment repeatedly rises and falls, the bonding between the chip and the spacer and between the spacer and the substrate can be prevented from being peeled off.

[0067] [2] Modifications, etc.

[0068] In the above embodiment, a structure in which a flat plate with a smaller area and a flat plate with a larger area are overlapped and arranged so that one side is aligned is shown as an example of the spacers 31 and 32. The spacers 31 and 32 are not limited to this. A plurality of modified examples will be described below.

[0069] Figure 8 It is a plan view showing an example of the internal structure of the semiconductor device according to the first modification. Figure 8 With the above-mentioned embodiment Figure 4 Corresponding. Figure 8 , the illustration of the substrate 11 and the sealing member 50 is omitted. In the first variant, relative to the above-mentioned embodiment, the spacer 31 is replaced by the spacer 33, and the spacer 32 is replaced by the spacer 34. The spacer 33 includes spacers 33a and 33b. The spacers 33a and 33b are respectively quadrilateral flat plates with the area of ​​the upper surface and the area of ​​the lower surface being approximately equal. The spacer 33a has an upper surface and a lower surface that can be included in the upper surface of the chip 21 when viewed from above. The spacer 33b has an upper surface and a lower surface that can include the upper surface of the spacer 33a when viewed from above. The spacer 33 has a structure in which the spacer 33b is overlapped on the spacer 33a. More specifically, the spacers 33a and 33b are overlapped in such a manner that the upper surface of the spacer 33a is included in the lower surface of the spacer 33b, and the lower surface of the spacer 33b protrudes from the four sides of the upper surface of the spacer 33a.

[0070] The spacer 34 also has the same structure as the spacer 33. That is, the spacer 34 includes spacers 34a and 34b. The spacers 34a and 34b are respectively quadrilateral flat plates whose upper surface area and lower surface area are approximately equal. The spacer 34a has an upper surface and a lower surface that can be included in the upper surface of the chip 22 when viewed from above. The spacer 34b has an upper surface and a lower surface that can include the upper surface of the spacer 34a when viewed from above. The spacer 34 has a structure in which the spacer 34b is overlapped on the spacer 34a. More specifically, the spacers 34a and 34b are overlapped in a manner such that the upper surface of the spacer 34a is included in the lower surface of the spacer 34b and the lower surface of the spacer 34b protrudes from the four sides of the upper surface of the spacer 34a.

[0071] Fig. 9 This is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a first modification. Fig. 9 With the above-mentioned embodiment Figure 7 Corresponding. Fig. 9 In the figure, the seal 50 is omitted. Fig. 9 As shown, in the semiconductor device according to the first modification, the spacer 33b protrudes above the pad PG1.

[0072] The spacers 33 and 34 thus constructed have a shape in which the spacer 33b protrudes all four sides from the upper part of the spacer 33a, and the spacer 34b protrudes all four sides from the upper part of the spacer 34a. The spacer may also be constructed in this way. In addition, when the spacer is constructed as in the first modified example, the spacers 33 and 34 are respectively arranged on the chips 21 and 22 after the wire bonding process is completed. In addition, each bonding wire is set not to contact each spacer.

[0073] Fig.10 This is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a second modification. Fig.10 With the above-mentioned embodiment Figure 6 Corresponding. Fig.10, the illustration of the sealing member 50 is omitted. In the second variant, relative to the above-mentioned embodiment, the spacer 31 is replaced by the spacer 35. The spacer 35 includes spacers 35a and 35b. The spacer 35a is a quadrangular pyramid whose upper surface and lower surface are respectively quadrilateral and parallel, and the area of ​​the upper surface is larger than the area of ​​the lower surface. The lower surface of the spacer 35a can be included in the upper surface of the chip 21. The spacer 35b is a quadrilateral flat plate whose upper surface area is substantially equal to the area of ​​the lower surface. The lower surface of the spacer 35b can include the upper surface of the spacer 35a. The spacer 35 has a structure in which the spacer 35b is overlapped on the spacer 35a. More specifically, the spacers 35a and 35b are overlapped in such a way that the upper surface of the spacer 35a is included in the lower surface of the spacer 35b. In addition, the spacer 35a and the spacer 35b are joined by a bonding layer 60. The bonding layer 60 is, for example, solder.

[0074] The spacer 35 thus constructed has a side wall of the spacer that is inclined so as to widen from the bottom to the top. The spacer may be constructed in such a manner that the side wall of the spacer is inclined.

[0075] Fig.11 This is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a third modification. Fig.11 With the above-mentioned embodiment Figure 6 correspond. Fig.11 In the third modification, the seal 50 is omitted. In the third modification, the spacer 31 is replaced by a spacer 36 relative to the above embodiment. The spacer 36 is a quadrangular pyramid whose upper and lower surfaces are respectively quadrilateral and parallel, and the area of ​​the upper surface is larger than that of the lower surface. The lower surface of the spacer 36 can be included in the upper surface of the chip 21.

[0076] In this way, the spacer can also be composed of only a member with inclined side walls. In addition, the spacer can also be composed of a single member.

[0077] Alternatively, the spacer 36 may be configured such that the cross-sectional area of ​​the spacer 36 on a surface parallel to the substrates 11 and 12 continuously increases from the lower surface toward the upper surface.

[0078] Fig.12 is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a fourth modification. Fig.12 With the above-mentioned embodiment Figure 6 Corresponding. Fig.12, the illustration of the sealing member 50 is omitted. In the fourth variant, relative to the above-mentioned embodiment, the spacer 31 is replaced by the spacer 37. The spacer 37 includes spacers 37a, 37b and 37c. The spacers 37a, 37b and 37c are respectively quadrilateral flat plates with the area of ​​the upper surface and the area of ​​the lower surface being approximately equal. The spacer 37a has an upper surface and a lower surface that can be included in the upper surface of the chip 21 when viewed from above. The spacer 37b has an upper surface and a lower surface that can include the upper surface of the spacer 37a when viewed from above. The spacer 37c has an upper surface and a lower surface that can include the upper surface of the spacer 37b when viewed from above. The spacer 37 has a structure in which the spacer 37b is overlapped on the spacer 37a, and the spacer 37c is overlapped on the spacer 37b. More specifically, the spacers 37a, 37b, and 37c are overlapped so that the upper surface of the spacer 37a is included in the lower surface of the spacer 37b, and the upper surface of the spacer 37b is included in the lower surface of the spacer 37c. In addition, the spacers 37a and 37b, and the spacers 37b and 37c are joined by the joining layer 60. The joining layer 60 is, for example, solder.

[0079] Thus, the number of components constituting the spacer may be one or more, and is not limited to one or two. The spacer may be constituted by any number of components.

[0080] Fig.13 It is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a fifth modification. Fig.13 With the above-mentioned embodiment Figure 7 Corresponding. Fig.13 In the fifth modification, the seal 50 is omitted. In the fifth modification, the spacer 33 composed of multiple components is replaced with a spacer 38 composed of a single component relative to the first modification. The spacer 38 has the same shape as the structure of the overlapping spacers 33a and 33b in the first modification.

[0081] Fig.14 It is a cross-sectional view showing an example of the internal structure of a semiconductor device according to a sixth modification. Fig.14 With the above-mentioned embodiment Figure 6 Corresponding. Fig.14 In the sixth modification, the seal 50 is omitted. In the sixth modification, the spacer 35 composed of multiple components is replaced with a spacer 39 composed of a single component relative to the second modification. The spacer 39 has the same shape as the structure of the overlapping spacers 35a and 35b in the second modification.

[0082] In this way, the spacers composed of a plurality of members described in the above-mentioned embodiment and modified examples may be composed of a single member in the same shape.

[0083] Fig.15This is a cross-sectional view showing an example of the internal structure of a semiconductor device according to the seventh modification. Fig.15 With the above-mentioned embodiment Figure 7 Corresponding. Fig.15 In the figure, the seal 50 is omitted. The seventh modification example is different from the first modification example in that the spacer 33 a and the spacer 33 b constituting the spacer 33 are directly connected without the intermediary of the bonding layer 60 .

[0084] Fig.16 It is a cross-sectional view showing an example of the internal structure of a semiconductor device according to an eighth modification. Fig.16 With the above-mentioned embodiment Figure 6 Corresponding. Fig.16 In the figure, the seal 50 is omitted. The eighth modification example is different from the second modification example in that the spacer 35 a and the spacer 35 b constituting the spacer 35 are directly connected without the bonding layer 60 interposed therebetween.

[0085] In this way, the spacer composed of a plurality of members described in the above-mentioned embodiment and modified examples may be configured so that the members of the spacer are directly connected to each other.

[0086] In the above embodiments and variations, when the spacer includes a plurality of components, solder is cited as an example of a bonding layer for bonding the components of the spacer to each other. The bonding layer for bonding the components of the spacer to each other may be, for example, a sintered silver material.

[0087] In the above-mentioned embodiments and variations, a case where two transistors are included is used as an example of a power module. The number of transistors included in the power module is not limited to two. The number of transistors included in the power module may be one, four, or six, for example.

[0088] In this specification, “one end of the current path of the transistor” corresponds to the source or drain of the MOS transistor. “The other end of the current path of the transistor” corresponds to the drain or source of the MOS transistor.

[0089] The term "connected" in this specification means electrically connected, and does not exclude the case where, for example, other elements are interposed therebetween. In addition, "electrically connected" may be connected via an insulator as long as the same operation as in the case of electrical connection is possible.

[0090] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device, characterized in that: Include: a first substrate; a second substrate, disposed opposite to the first substrate; A chip, disposed on the first substrate and between the first substrate and the second substrate; as well as a spacer, disposed on the chip, connecting the chip to the second substrate, An area of ​​a second portion of the spacer in contact with the second substrate is larger than an area of ​​a first portion of the spacer in contact with the chip.

2. The semiconductor device according to claim 1, wherein: The first portion of the spacer may be included in a surface of the chip that is in contact with the spacer.

3. The semiconductor device according to claim 1, wherein: The thermal expansion coefficient of the spacer is larger than the thermal expansion coefficient of the chip, and smaller than the thermal expansion coefficient of copper included in the first substrate and the second substrate.

4. The semiconductor device according to claim 1, wherein: The chip includes transistors, The spacer electrically connects one end of a current path of the transistor to the second substrate.

5. The semiconductor device according to claim 1, wherein: The partition has a portion whose side wall is inclined from the first portion toward the second portion.

6. The semiconductor device according to claim 1, wherein: A cross-sectional area of ​​the spacer on a surface parallel to the first substrate continuously increases from the first portion toward the second portion.

7. The semiconductor device according to claim 1, wherein: The spacer has a first part including the first portion and a second part including the second portion, The first member and the second member are bonded together via a bonding layer.

8. The semiconductor device according to claim 7, wherein: The bonding layer includes solder.

9. The semiconductor device according to claim 1, wherein: The spacer has a first part including the first portion and a second part including the second portion, The spacer has a shape in which a second member protrudes from all four sides on an upper portion of the first member.

10. The semiconductor device according to claim 1, wherein: The spacer includes a first component including the first portion, a second component including the second portion, and a third component provided between the first component and the second component. The first component has an upper surface that can be included in the upper surface of the chip and a lower surface, The third component has an upper surface and a lower surface that can include the upper surface of the first component, The second member has an upper surface capable of including an upper surface of the third member and a lower surface.

11. The semiconductor device according to claim 10, wherein: The first component and the third component are bonded via a bonding layer. The third member and the second member are bonded together via a bonding layer.

12. The semiconductor device according to claim 1, wherein: The spacer has a first part including the first portion and a second part including the second portion, The first component and the second component are directly connected without a bonding layer.

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