Cell architecture of semiconductor device including semiconductor cells

Abstract

A semiconductor device based on a cell architecture is provided, the cell architecture comprising: a first semiconductor cell; and a second semiconductor unit connected to the first semiconductor unit in a first direction such that an output pin of the first semiconductor unit is connected to an input pin of the second semiconductor unit, in which the second semiconductor unit is in a form in which the first semiconductor unit is inverted.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims priority to U.S. Provisional Application No. 63 / 527,957 filed in the U.S. Patent and Trademark Office on July 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Apparatus consistent with example embodiments of the present disclosure relates to a semiconductor unit architecture including a backside power distribution network. Background Art

[0004] An integrated circuit includes a plurality of logic circuits (or logic gates) that implement one or more logic operations or functions, such as AND, OR, NOT (inverter), NAND, NOR, XOR, XNOR, AOI, multiplexers, and combinations thereof, but not limited thereto. These logic circuits are the building blocks of an integrated circuit.

[0005] In an integrated circuit, a logic circuit is usually arranged repeatedly to realize a desired circuit. Therefore, when designing a unit structure of a semiconductor device, the semiconductor unit that realizes the logic circuit is usually arranged repeatedly. For example, two semiconductor units that each realize the same inverter circuit can be arranged adjacent to each other in the unit length direction and connected to each other, so that the output signal from the output pin of one semiconductor unit is input to the input pin of another semiconductor unit as its input signal to design the unit architecture of the desired integrated circuit. However, connecting two identical semiconductor units for signal routing in an integrated circuit requires one or more additional interconnect structures, such as metal lines and vias, which may extend the signal routing path, thereby increasing contact resistance and device complexity. Therefore, reducing the length of the signal routing path in the unit architecture of a semiconductor device is directly related to increasing device performance and device area gain.

[0006] As used herein, the term "semiconductor cell" may include a "standard cell" of a cell library used to design a cell architecture for an integrated circuit or semiconductor device. A semiconductor cell of an integrated circuit may include one or more active regions and gate structures that form one or more of passive devices and transistors configured to perform a logic operation or function.

[0007] The information disclosed in this background technology section is known to the inventors before implementing the embodiments of the present application, or is technical information acquired during the process of implementing the embodiments described herein. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0008] Various example embodiments provide a semiconductor device manufactured based on a cell architecture, which is formed by connecting multiple semiconductor cells based on a back side power distribution network (BSPDN), each of the multiple semiconductor cells implementing the same logic circuit, wherein each semiconductor cell takes the form of an inverted adjacent semiconductor cell, and an output pin of the semiconductor cell is connected to an input pin of an adjacent semiconductor cell.

[0009] According to an embodiment, a semiconductor device based on a cell architecture is provided, which cell architecture may include: a first semiconductor unit; and a second semiconductor unit, which is connected to the first semiconductor unit in a first direction so that an output pin of the first semiconductor unit is connected to an input pin of the second semiconductor unit, wherein the second semiconductor unit is in a form in which the first semiconductor unit is inverted.

[0010] According to an embodiment, the output pin of the first semiconductor unit may include a first metal wire and the input pin of the second semiconductor unit may include a second metal wire, wherein at least one of the first metal wire and the second metal wire extends in a first direction and is connected to each other.

[0011] According to an embodiment, the semiconductor device may further include: a first back side power rail along a first boundary of the cell architecture; a second back side power rail along a virtual center line of the cell architecture; and a third back side power rail along a second boundary of the cell architecture opposite to the first boundary in a second direction intersecting the first direction, wherein the first back side power rail to the third back side power rail extend in the first direction.

[0012] According to an embodiment, a semiconductor device based on a cell architecture is provided, which cell architecture may include: a first semiconductor cell; a second semiconductor cell connected to the first semiconductor cell so that an output pin of the first semiconductor cell is connected to an input pin of the second semiconductor cell in a first direction; and at least one back power rail formed at a back side of the cell architecture, wherein the first semiconductor cell and the second semiconductor cell include the same logic circuit, and both the first semiconductor cell and the second semiconductor cell are connected to the at least one back power rail.

[0013] According to an embodiment, a semiconductor device based on a unit architecture is provided, which unit architecture may include: a first semiconductor unit; and a second semiconductor unit, which is adjacent to and connected to the first semiconductor unit in a first direction, wherein the first semiconductor unit includes a first portion and a second portion below the first portion in a second direction intersecting the first direction, the first portion includes a first source / drain region and a first interconnect structure, wherein the second semiconductor unit includes a third portion and a fourth portion below the third portion in the second direction, the fourth portion includes a second source / drain region and a second interconnect structure, and wherein the first portion is symmetrical to the fourth portion.

[0014] According to an embodiment, the semiconductor device may further include a third semiconductor unit adjacent to and connected to the second semiconductor unit in a first direction, wherein the first to third semiconductor units include the same logic circuit, and wherein an output pin of the first semiconductor unit is connected to an input pin of the second semiconductor unit, and an output pin of the second semiconductor unit is connected to an input pin of the third semiconductor unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1A shows a schematic diagram of an inverter circuit, and Figure 1B According to an embodiment, Figure 1A A top view of a semiconductor unit of an inverter circuit;

[0017] Figure 2A Among them Figure 1A A schematic diagram of two buffer circuits connected to each other in the inverter circuit 10, and Figure 2B According to an embodiment, Figure 2A A schematic diagram of a top view of a unit structure of a buffer circuit;

[0018] Figure 3 According to another embodiment, Figure 2A A top view of a unit structure of a buffer circuit;

[0019] Figure 4A According to an embodiment, a backside power distribution network (BSPDN) is provided. Figure 1A A top view of a semiconductor unit of an inverter circuit shown in FIG. Figure 4B According to yet another embodiment, Figure 2A A top view of the cell architecture of the buffer circuit, and Figure 4Cis a top view of a cell architecture in which different buffer circuits are implemented according to an embodiment; and

[0020] Figure 5 is a diagram showing a method according to an embodiment including a method based on Figure 4A-4C 4 is a schematic block diagram of an electronic device of at least one semiconductor device including at least one of the semiconductor unit 40 and the unit architectures 400 and 400 ′ shown in FIG. DETAILED DESCRIPTION

[0021] The embodiments of the present disclosure described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and may be implemented in various other forms. Each of the embodiments provided in the following description does not exclude being associated with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. For example, even if the content described in a specific example or embodiment is not described in different examples or embodiments, these contents may also be understood to be related to different examples or embodiments or to be combined with different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure.

[0022] It should be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as "above another element of the semiconductor device", "above another element of the semiconductor device", "on another element of the semiconductor device", "below another element of the semiconductor device", "below another element of the semiconductor device", "under another element of the semiconductor device", "connected to another element of the semiconductor device" or "coupled to another element of the semiconductor device", it may be directly above, above, on, below, below, below, connected or coupled to another element, or there may be intermediate elements. Conversely, when an element of a semiconductor device is referred to as "directly above another element of the semiconductor device", "directly above another element of the semiconductor device", "directly on another element of the semiconductor device", "directly below another element of the semiconductor device", "directly below another element of the semiconductor device", "directly below another element of the semiconductor device", "directly connected to another element of the semiconductor device" or "directly coupled to another element of the semiconductor device", there are no intermediate elements. Throughout this disclosure, the same reference numerals refer to the same elements.

[0023] For ease of description, spatially relative terms such as "above", "above", "up", "upper", "below", "under", "lower", "lower", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc. may be used herein to describe the relationship of one element to another element as shown in the figure. It should be understood that spatially relative terms are intended to cover different orientations of the semiconductor device in use or operation other than the orientation depicted in the figure. For example, if the semiconductor device in the accompanying drawings is flipped, the elements described as "below" or "below" other elements will be oriented as "above" other elements. Therefore, the term "below" can cover both the above and below orientations. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article are interpreted accordingly. As another example, when a device or structure including elements referred to as "left" elements and "right" elements is oriented differently, these elements referred to as "left" elements and "right" elements can be "right" elements and "left" elements. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, in the case where the terms "lower" element and "upper" element are described as necessary to distinguish the two elements, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively.

[0024] It should be understood that although the terms "first", "second", "third", "fourth", "fifth", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0025] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. In this document, when the term "same" is used to compare the size of two or more elements, the term can cover "substantially the same" sizes.

[0026] It should also be understood that even if a step or operation of manufacturing a device or structure is described earlier than another step or operation, the step or operation may be performed later than the other steps or operations unless the other steps or operations are described as being performed after the step or operation.

[0027] A plurality of embodiments are described herein with reference to schematic illustrations of embodiments (and intermediate structures). Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments should not be construed as being limited to the specific shapes of the regions shown herein, but rather include shape deviations, for example, caused by manufacturing. The various regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of the layers and regions may be exaggerated for clarity.

[0028] For the sake of brevity, conventional elements, structures or layers of semiconductor devices including nanosheet transistors and fin field-effect transistors (FinFETs) and materials forming them may or may not be described in detail herein. For example, when a certain isolation layer or structure of the semiconductor device is irrelevant to the novel features of the embodiment, such layer or structure and the materials forming it may be omitted herein.

[0029] Figure 1A shows a schematic diagram of an inverter circuit, and Figure 1B According to an embodiment, Figure 1A A top view of a semiconductor unit of an inverter circuit.

[0030] The semiconductor units described herein and the unit architectures including one or more of the semiconductor units may be a basis for manufacturing a semiconductor device. Therefore, the semiconductor units and the unit architectures may include the same structural elements of the semiconductor device, and the front and back sides of the semiconductor units and the unit architectures described herein may indicate the front and back sides of the semiconductor device manufactured based on the semiconductor units and the unit architectures.

[0031] refer to Figure 1A , the inverter circuit 10 may include a p-type metal oxide semiconductor field effect transistor (PMOS) P1 and an n-type metal oxide semiconductor field effect transistor (NMOS) N1 to form a complementary metal oxide semiconductor (CMOS) device.

[0032] In the inverter circuit 10, the source terminal of the PMOS P1 is connected to a first voltage source (e.g., VDD), and the source terminal of the NMOS N1 is connected to a second voltage source (e.g., VSS) providing a voltage lower than the first voltage source, or is grounded. In addition, the gate terminals of the PMOS P1 and the NMOS N1 are connected to each other to receive a common gate input signal A, which is also referred to as an input signal A of the inverter circuit 10, and the drain terminals of the PMOS P1 and the NMOS N1 are connected to each other to generate an output signal Q of the inverter circuit 10.

[0033] refer to Figure 1B , which implements Figure 1A The semiconductor unit 100 of the inverter circuit 10 may include a first active region RX1 and a second active region RX2 extending in the D1 direction and arranged in the D2 direction, and a plurality of gate structures PC1, PC2, and PC3 extending in the D2 direction and arranged across the active regions RX1 and RX2 in the D1 direction. At least the gate structure PC2 may be provided for forming gate electrodes of the PMOS P1 and the NMOS N1 thereon. The active regions RX1 and RX2 may be provided for forming Figure 1A Source / drain regions and channel structures of PMOS P1 and NMOS N1 of inverter circuit 10. Here, D1 direction is a cell length direction or a channel length direction in which current flows between source / drain regions through a channel structure in a transistor. D2 direction intersecting with D1 direction is a cell height direction and a channel width direction in which the width of the channel structure is measured. Both D1 and D2 directions intersect with D3 direction, which is a vertical direction.

[0034] Two source / drain regions SD1 and SD2 may be formed on the first active region RX1, which may be doped with p-type impurities such as boron (B), gallium (Ga) and / or indium (In). Two source / drain regions SD3 and SD4 may be formed on the second active region RX2, which may be doped with n-type impurities such as phosphorus (P), arsenic (As) and / or antimony (Sb).

[0035] refer to Figure 1A and Figure 1B , the source / drain regions SD1 and SD2 may correspond to the source terminal and the drain terminal of the PMOS P1, respectively, and the source / drain regions SD3 and SD4 may correspond to the source terminal and the drain terminal of the NMOS N1, respectively. The source / drain regions SD1 and SD2 may be connected to each other through a channel structure formed under a gate structure PC2 corresponding to the gate terminal of the PMOS P1, and the source / drain regions SD3 and SD4 may be connected to each other through a channel structure formed under a gate structure PC2 corresponding to the gate terminal of the NMOS N1. The gate structures PC1 and PC3 in the semiconductor unit 100 may each be a dummy gate structure in the semiconductor unit 100. The source / drain regions SD1-SD4, the gate structures PC1-PC3, and the channel structure surrounded by the gate structure PC2 may be referred to as a semiconductor unit 100 and a front-end-of-line (FEOL) structure of a semiconductor device formed based on the semiconductor unit 100.

[0036] In addition, the semiconductor cell 100 may include two front power rails PR1 and PR2 extending in the D1 direction at the upper and lower boundaries of the semiconductor cell 100, respectively. The two cell boundaries may define the cell height of the semiconductor cell 100. The front power rail PR1 may connect the source / drain region SD1 of the PMOS P1 to the first voltage source through the contact structure CR1, and the front power rail PR2 may connect the source / drain region SD3 of the NMOS N1 to the second voltage source through the contact structure CR2. The contact structures CR1 and CR2 may be referred to as a middle-of-line (MOL) structure of a semiconductor device manufactured based on the semiconductor cell 100.

[0037] The semiconductor unit 100 may include a plurality of interconnect structures for signal routing to achieve Figure 1A The inverter circuit 10. The interconnect structure may include metal lines M11-M13 formed at a first metal layer, and a metal line M21 formed at a second metal layer above the first metal layer in the D3 direction. The front power rails PR1 and PR2 may also be formed at the same first metal layer where the metal lines M11-M13 are formed, but are not limited thereto. The interconnect structure may also include a plurality of vias V01-V03, V11, and V12 formed above or below the metal lines. Each of these vias may connect the metal lines M11-M13, M21, and two elements in the FEOL structure to each other. Figure 1B , via V01 is considered to partially overlap via V11 in the D3 direction. However, this partial overlap is depicted only to show that via V01 is formed below via V11 with metal line M11 therebetween. Therefore, in reality, via V01 may partially or completely overlap via V11 in the D3 direction. Similarly, via V02 may partially or completely overlap via V12 in the D3 direction. These interconnect structures may be referred to as back-end-of-line (BEOL) structures.

[0038] In order to make the semiconductor cell 100 realize the inverter circuit 10, the metal line M13 can be connected to the gate structure PC2 through the through hole V03 formed thereon to receive the common gate input signal A of the PMOS P1 and the NMOS N1. Here, the metal line M13 is used as the input pin of the semiconductor cell 100. The metal line M11 can be connected to the source / drain region SD2 of the PMOS P1 through the through hole V01, and the metal line M12 can be connected to the source / drain region SD4 of the NMOS N1 through the through hole V02. The two source / drain regions SD2 and SD4 can be connected to each other through the through holes V11 and V12 connected to the metal line M21, respectively, to generate the output signal Q of the inverter circuit 10. Here, the output signal Q can be output to the external circuit through at least one of the metal lines M11, M12 and M21. For example, the output signal Q can be output to the external circuit through the metal line M12 as the output pin of the semiconductor cell 100.

[0039] Each of the PMOS P1 and NMOS N1 implemented in the semiconductor unit 100 can be a FinFET or a nanosheet transistor, but is not limited thereto. FinFET has one or more fin structures as the channel structure of the transistor. The fin structure protrudes vertically from a base layer such as a substrate and extends horizontally, and at least three of its surfaces are surrounded by a gate structure. The nanosheet transistor is characterized in that one or more nanosheet channel layers serve as the channel structure of the transistor. The nanosheet channel layers are vertically stacked and extend horizontally based on the substrate, and all four surfaces of each of the nanosheet channel layers are surrounded by a gate structure. Nanosheet transistors are referred to as gate-all-around (GAA) transistors or multi-bridge channel field-effect transistors (MBCFETs).

[0040] In the above manner, the semiconductor unit 100 can be implemented therein as follows Figure 1A The inverter circuit 10 is shown in FIG.

[0041] As mentioned earlier, such as Figure 1A The logic circuits of the inverter circuit 10 are usually repeatedly arranged to form a desired circuit in an integrated circuit. Therefore, the cell architecture of a semiconductor device in which the logic circuits are repeatedly arranged may include a plurality of semiconductor cells implementing these logic circuits, which are arranged adjacent to each other in the cell length direction and connected to each other.

[0042] Figure 2A Among them Figure 1A A schematic diagram of two buffer circuits connected to each other in the inverter circuit 10, and Figure 2B According to an embodiment, Figure 2A Schematic diagram of a top view of a unit architecture of a buffer circuit.

[0043] refer to Figure 2A The buffer circuit 20 may include a first inverter circuit 20A and a second inverter circuit 20B, wherein the first inverter circuit 20A and the second inverter circuit 20B are formed by a PMOS P1 and an NMOS N1. Figure 1A The second inverter circuit 20B formed by PMOS P2 and NMOS N2 is also the same as the inverter circuit 10 of FIG. Figure 1A The buffer circuit 20 is formed in such a manner that the output node of the first inverter circuit 20A is connected to the input node of the second inverter circuit 20B. Therefore, the output signal Q of the first inverter circuit 20A is input to the second inverter circuit 20B as its input signal to generate the output signal Q' of the buffer circuit 20. In the buffer circuit 20, the first inverter circuit 20A can be referred to as an input CMOS device, and the second inverter circuit 20B can be referred to as an output CMOS device.

[0044] Figure 2B It shows that the Figure 2A The buffer circuit 20 of the cell architecture 200 is shown in FIG. Figure 1B The first semiconductor unit 200A and the second semiconductor unit 200B of the semiconductor unit 100 are arranged adjacent to each other in the D1 direction and connected to each other so that the output pin of the first semiconductor unit 200A is connected to the input pin of the second semiconductor unit 200B. The first semiconductor unit 200A and the second semiconductor unit 200B can be respectively implemented therein Figure 2A The first inverter circuit 20A and the second inverter circuit 20B of the buffer circuit 20. In this article, one semiconductor unit is the same as another unit may mean that the two semiconductor units have the same structural elements, such as source / drain regions, gate structures, and interconnect structures, and further, their positional relationships in the semiconductor unit are the same.

[0045] The connection of the two semiconductor units 200A and 200B can be performed so that the metal wire M12 as the output pin of the first semiconductor unit 200A and the metal wire M13 as the input pin of the second semiconductor unit 200B are extended in the D1 direction to be close to each other, and are connected to each other through additional vias V14 and V13 formed on the extended metal wires M12 and M13, respectively, and through additional metal wires M22 formed at the second metal layer. In addition, the front power rails PR1 and PR2 of the first semiconductor unit 200A can be connected to the front power rails PR1 and PR2 of the second semiconductor unit 200B, respectively.

[0046] However, if Figure 2B As shown, adding a metal line M22 and vias V13 and V14 to connect the first semiconductor unit 200A and the second semiconductor unit 200B to each other may extend the signal routing path, resulting in an increase in the contact resistance of the semiconductor device manufactured based on the unit architecture 200, which may at least deteriorate the connection performance and the device area gain. Therefore, another method of connecting two semiconductor units that implement the same inverter circuit can be provided as follows to improve the connection performance and the device area gain.

[0047] Figure 3 According to another embodiment, Figure 2A A top view of a cell architecture of a buffer circuit.

[0048] refer to Figure 3 , the first semiconductor unit 300A and the second semiconductor unit 300B may be provided to be adjacent to each other and connected in the D1 direction to form a Figure 2A The first semiconductor unit 300A and the second semiconductor unit 300B can be respectively implemented in Figure 2A The buffer circuit 20 shown in FIG. 20 includes a first inverter circuit 20A and a second inverter circuit 20B. Figure 2B The cell architecture 200 , the cell architecture 300 may be configured such that an output pin of the first semiconductor cell 300A is connected to an input pin of the second semiconductor cell 300B.

[0049] In the cell architecture 300, each of the semiconductor cells 300A and 300B may be connected to Figure 1B The semiconductor unit 100 is the same as that of FIG. 1 , except that in the second semiconductor unit 300B, the positions of the metal line M13′ and the via V03′ are the same as those of FIG. Figure 1B The semiconductor unit 100 shown has different positions of the metal lines M13 and the vias V03 , respectively.

[0050] For example, the first semiconductor unit 300A is configured so that the metal line M13 as its input pin is formed above the upper portion of the unit including the first active region RX1. In contrast, the second semiconductor unit 300B is configured so that the corresponding metal line M13' as its input pin can be formed above the lower portion of the unit including the second active region RX2, so that the extension of the metal line M13' can be connected to the metal line M12 as its output pin of the first semiconductor unit 300A. Therefore, the through hole V03' connecting the metal line M13' to the gate structure PC2 can be formed on the lower portion of the gate structure PC2 below the metal line M13' in the second semiconductor unit 300B, while the corresponding through hole V03 is formed on the upper portion of the gate structure PC2 in the first semiconductor unit 300A.

[0051] Due to the above configuration of the cell architecture 300, in which the output pin of the first semiconductor unit 300A including the metal line M12 is horizontally aligned with the input pin of the second semiconductor unit 300B including the metal line M13', additional interconnect structures such as the metal line M22 and the vias V13 and V14 can be omitted when designing the cell architecture 300, thereby shortening the signal routing path and reducing the contact resistance.

[0052] However, since the second semiconductor cell 300B has a different configuration and arrangement of its interconnection structure (such as metal line M13' and via V03') compared to the first semiconductor cell 300A which is the same as the semiconductor cell 100, the cell library may have to include the semiconductor cell 300B as a target Figure 1A A variant cell of the semiconductor cell 100 or 300A of the inverter circuit shown in and an additional design kit for the variant cell. Then, a large amount of resources are required in preparing, certifying and adding two different semiconductor cells or standard cells of the same logic circuit to the semiconductor cell library. Therefore, the present disclosure provides the formation of different cell architectures corresponding to the cell architectures 200 and 300 below, but without the need for variant cells and additional design kits, while shortening the signal routing path and reducing the contact resistance to improve the connection performance and device area gain.

[0053] Figure 4A is a back side power distribution network (BSPDN) based on an embodiment Figure 1A A top view of a semiconductor unit of the inverter circuit shown in FIG. Figure 4B According to yet another embodiment, Figure 2A A top view of a cell architecture of a buffer circuit. Figure 4C is a top view of a cell architecture in which different buffer circuits are implemented according to an embodiment.

[0054] refer to Figure 4A , which implements Figure 1A The semiconductor unit 40 of the inverter circuit 10 may have Figure 1B The semiconductor unit 100 has the same or similar structure as the semiconductor unit 100 except for the power rails and the contact structure. Therefore, although repeated description thereof may be omitted herein, different aspects of the semiconductor unit 40 are described herein.

[0055] The semiconductor unit 40 may include first to third back power rails BPR1, BPR2, and BPR3 formed at the back side thereof, while the semiconductor unit 100 includes front power rails PR1 and PR2 formed at the front side thereof. For example, the first back power rail BPR1 and the third back power rail BPR3 may be formed below the upper and lower boundaries of the semiconductor unit 40, respectively, and connected to a first voltage source (e.g., VDD), and the second back power rail BPR2 may be formed below a horizontal center line XX' between the first back power rail BPR1 and the third back power rail BPR3 of the semiconductor unit 40 and connected to a second voltage source (e.g., VSS). In contrast, the front power rails PR1 and PR2 of the semiconductor unit 100 may be formed above the upper and lower boundaries of the semiconductor unit 100, as shown in FIG. Figure 1B As shown. When a semiconductor device is manufactured based on semiconductor unit 40, back power rails BPR1-BPR3 may be formed at the back side of the semiconductor device vertically below the FEOL structure in the D3 direction. For example, these back power rails may be formed in a back isolation structure that replaces the silicon substrate of the semiconductor device on which the FEOL structure is formed. In contrast, when a semiconductor device is manufactured based on semiconductor unit 100, the front power rails PR1 and PR2 of semiconductor unit 100 may be formed at the level of the BEOL structure vertically above the FEOL structure.

[0056] The front power rails formed at the front side of the semiconductor device are constrained by the cell design rules for the placement, size, spacing, clearance, etc. of the FEOL, MOL, and BEOL structures in the corresponding semiconductor cell or cell architecture. Therefore, the positions of the front power rails PR1 and PR2 can be fixed at Figure 1B At the upper and lower boundaries of the semiconductor unit 100. However, the placement of the back power rails may not be subject to the cell design rules that are strictly applied to the front power rails. Therefore, in the semiconductor unit 40, the first back power rail BPR1 and the third back power rail BPR3 can be placed at the upper and lower boundaries of the semiconductor unit 40, respectively, and the second back power rail BPR2 can be located around the horizontal center line XX' of the semiconductor unit 40.

[0057] Based on the back power rails BPR1-BPR3, the first source / drain region SD1 of the PMOS P1 can be connected to the back power rail BPR1 through a first back contact structure BCR1 formed on the first source / drain region SD1, and the third source / drain region SD3 of the NMOS N1 can be connected to the back power rail BPR2 through a second back contact structure BCR2 formed on the third source / drain region SD3. The back power rails BPR1-BPR3 and the back contact structures BCR1-BCR2 can be formed in the back isolation structure to form a back power distribution network (BSPDN) for a semiconductor device to be manufactured based on the semiconductor unit 40.

[0058] refer to Figure 4B , a first semiconductor unit 400A and a second semiconductor unit 400B may be provided adjacent to and connected to each other in the D1 direction to form a semiconductor device that realizes Figure 2A The first semiconductor unit 400A and the second semiconductor unit 400B can be implemented in the cell architecture 400 of the buffer circuit 20. Figure 2A The first inverter circuit 20A and the second inverter circuit 20B of the buffer circuit 20 are similar to Figure 2B and Figure 3 The cell architectures 200 and 300 , the cell architecture 400 may be configured such that an output pin of a first semiconductor cell 400A is connected to an input pin of a second semiconductor cell 400B.

[0059] In the cell architecture 400, the first semiconductor cell 400A may be connected to Figure 4A However, the second semiconductor unit 400B is formed by simply following the Figure 4A The semiconductor unit 40 is formed by inverting the axis corresponding to the horizontal center line XX' shown in FIG.

[0060] Since the second semiconductor unit 400B is obtained by inverting the semiconductor unit 40 along the horizontal center line XX', the first back side power rail BPR1 set along the upper boundary in the semiconductor unit 40 can now be set along the lower boundary in the second semiconductor unit 400B. Similarly, the third back side power rail BPR3 set along the lower boundary in the semiconductor unit 40 can now be set along the upper boundary of the second semiconductor unit 400B. However, the second back side power rail BPR2 positioned along the horizontal center line XX' can maintain its position in the second semiconductor unit 400B. In addition, the first active region RX1, the source / drain regions SD1, SD2, and the interconnection structure including the first back side contact structure BCR1, the metal lines M13, M11, and the vias V03, V01, and V11 set between the first back side power rail BPR1 and the second back side power rail BPR2 in the semiconductor unit 40 are now set between the second back side power rail BPR2 and the third back side power rail BPR3 in the semiconductor unit 400B. Likewise, the second active region RX2, source / drain regions SD3, SD4, and an interconnect structure including a second back contact structure BCR2, a metal line M12, and vias V02 and V12 arranged between the second back power rail BPR2 and the third back power rail BPR3 in the semiconductor unit 40 are now arranged between the first back power rail BPR1 and the second back power rail BPR2 in the second semiconductor unit 400B.

[0061] Therefore, when the second semiconductor unit 400B adopts the form or shape of the inverted semiconductor unit 40 (or the first semiconductor unit 400A), the unit architecture 400 can be configured so that the source / drain region, interconnect structure and first back side power rail BPR1 above the horizontal center line of the first semiconductor unit 400A are the same as or diagonally symmetrical with the source / drain region, interconnect structure and first back side power rail BPR1 below the horizontal center line of the second semiconductor unit 400B.

[0062] After the second semiconductor unit 400B is obtained in this way, the second semiconductor unit 400B can be disposed on the right side of the first semiconductor unit 400A which is the same as the semiconductor unit 40, and at least one of the metal wire M12 as the output pin of the first semiconductor unit 400A and the metal wire M13 as the input pin of the second semiconductor unit 400B can be extended in the D1 direction to be connected to each other, thereby forming a structure as shown in FIG. Figure 4B Cell architecture 400 is shown.

[0063] Here, the unit architecture 400 can be constructed by connecting two identical Figure 4A The semiconductor unit 40 is configured with two identical Figure 4AOne of the semiconductor units 40 is simply inverted without using Figure 2B The additional interconnect structure formed in the cell architecture 200 and without using variant cells, i.e., Figure 3 The second semiconductor unit 300B of the unit architecture 300 is still the same as in Figure 3 As in the cell architecture 300 of the present invention, the cell architecture 400 can horizontally align the output pin including the metal line M12 of the first semiconductor cell 400A with the input pin including the metal line M13 of the second semiconductor cell 400B. Therefore, the simplicity of cell design and device manufacturing can be achieved, and further, the signal routing path can be shortened and the contact resistance can be reduced, thereby improving the connection performance and device area gain of the semiconductor device manufactured based on the cell architecture 400.

[0064] refer to Figure 4C , can be obtained by Figure 4A The third semiconductor unit 400C is connected to the same semiconductor unit 40 Figure 4B The cell architecture 400 is formed by combining the cell architecture 400 of the second semiconductor cell 400B. For example, the cell architecture 400' may be configured such that an output pin of the second semiconductor cell 400B is connected to an input pin of the third semiconductor cell 400C.

[0065] When forming the cell architecture 400', the third semiconductor cell 400C may be disposed on the right side of the second semiconductor cell 400B, and at least one of the metal wire M12 as the output pin of the second semiconductor cell 400B and the metal wire M13 as the input pin of the third semiconductor cell 400C may extend in the D1 direction to be connected to each other, thereby forming a structure as shown in FIG. Figure 4C The cell architecture 400' is shown.

[0066] Similar to the unit structure 400, the unit structure 400' can also be connected by three identical Figure 4A The semiconductor unit 40 is formed by three identical Figure 4A One of the semiconductor units 40 is simply inverted without using Figure 2B The additional interconnect structure formed in the cell architecture 200 and without using variant cells, i.e., Figure 3 The second semiconductor unit 300B of the unit architecture 300 of the cell architecture 400 ′ can be realized. Therefore, the simplicity of unit design and device manufacturing can be achieved, and further, the signal routing path can be shortened and the contact resistance can be reduced, thereby improving the connection performance and device area gain of the semiconductor device manufactured based on the unit architecture 400 ′.

[0067] Figure 5 is a diagram showing a method according to an embodiment including a method based on Figure 4A-4C4 is a schematic block diagram of an electronic device of at least one semiconductor device including at least one of the semiconductor unit 40 and the unit architectures 400 and 400 ′ shown in FIG.

[0068] refer to Figure 5 , the electronic device 1000 may include at least one processor 1100, a communication module 1200, an input / output module 1300, a storage device 1400, and a buffer random access memory (RAM) module 1500. According to an embodiment, the electronic device 1000 may be a mobile device such as a smartphone or a tablet computer, but is not limited thereto.

[0069] The processor 1100 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or any other processor that controls the operation of the electronic device 1000. The communication module 1200 may be implemented to perform wireless or wired communication with an external device. The input / output module 1300 may include at least one of a touch sensor, a touch panel, a keyboard, a mouse, a proximity sensor, a microphone, etc. for receiving an input, and at least one of a display, a speaker, etc. for generating an output signal processed by the processor 1100. The storage device 1400 may be implemented to store user data, output signals, etc. input through the input / output module 1300. The storage device 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc.

[0070] The buffer RAM module 1500 may temporarily store data used for processing operations of the electronic device 1000. For example, the buffer RAM 1500 may include a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0071] Although not in Figure 5 Although not shown in FIG. 1 , the electronic device 1000 may further include at least one sensor, such as an image sensor.

[0072] According to an embodiment, at least one component in the electronic device 1000 may be based on Figure 4A-4C The semiconductor unit 40 and the unit structures 400 and 400 ′ shown in FIG. 4 are formed by at least one of them.

[0073] The foregoing is a description of example embodiments and should not be construed as limiting the present disclosure. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications to the above embodiments are possible without substantially departing from the present disclosure.

Claims

1. A semiconductor device based on a cell architecture, the cell architecture comprising: a first semiconductor unit; as well as a second semiconductor unit connected to the first semiconductor unit in a first direction such that an output pin of the first semiconductor unit is connected to an input pin of the second semiconductor unit, The second semiconductor unit is in a form in which the first semiconductor unit is inverted.

2. The semiconductor device according to claim 1, wherein The output pin of the first semiconductor unit includes a first metal line, and the input pin of the second semiconductor unit includes a second metal line, and At least one of the first metal line and the second metal line extends in the first direction and is connected to each other.

3. The semiconductor device according to claim 2, wherein: Each of the first and second semiconductor cells includes a source / drain region connected to a back side power rail formed at a back side of the cell architecture.

4. The semiconductor device according to claim 1, wherein: The first semiconductor unit includes a first portion and a second portion below the first portion in a second direction intersecting the first direction, the first portion including a first source / drain region and a first interconnect structure, The second semiconductor unit includes a third portion and a fourth portion below the third portion in the second direction, the fourth portion includes a second source / drain region and a second interconnect structure, and Among them, the first part is the same as the fourth part.

5. The semiconductor device according to claim 1, wherein The first semiconductor unit includes a first portion and a second portion below the first portion in a second direction intersecting the first direction, the first portion including a first source / drain region and a first interconnect structure, The second semiconductor unit includes a third portion and a fourth portion below the third portion in the second direction, the fourth portion includes a second source / drain region and a second interconnect structure, and The first part is symmetrical to the fourth part.

6. The semiconductor device according to claim 5, wherein: The first portion and the third portion are separated from the second portion and the fourth portion by a virtual horizontal center line extending in the first direction on the first semiconductor unit and the second semiconductor unit, respectively.

7. The semiconductor device according to claim 1, comprising: a first backside power rail along a first boundary of the cell architecture; a second backside power rail along a virtual centerline of the cell architecture; as well as a third back side power rail along a second boundary of the cell structure opposite to the first boundary in a second direction intersecting the first direction, Wherein, the first back side power rail to the third back side power rail extend in the first direction.

8. The semiconductor device according to claim 7, wherein: The first back side power rail and the third back side power rail are connected to a first voltage source, and the second back side power rail is connected to a second voltage source different from the first voltage source.

9. The semiconductor device according to claim 8, wherein: The first semiconductor unit includes a first transistor and a second transistor, the first transistor includes a first source / drain region, the second transistor includes a second source / drain region, The second semiconductor unit includes a third transistor and a fourth transistor, the third transistor includes a third source / drain region, and the fourth transistor includes a fourth source / drain region. wherein the first source / drain region is connected to the first back side power rail and the fourth source / drain region is connected to the third back side power rail, and Wherein, the second source / drain region and the third source / drain region are connected to the second back side power rail.

10. The semiconductor device according to claim 1, wherein The first semiconductor unit and the second semiconductor unit include the same logic circuit.

11. A semiconductor device based on a cell architecture, the cell architecture comprising: a first semiconductor unit; a second semiconductor unit connected to the first semiconductor unit such that an output pin of the first semiconductor unit is connected to an input pin of the second semiconductor unit in a first direction; and at least one back power rail formed at the back side of the cell architecture, wherein the first semiconductor unit and the second semiconductor unit include the same logic circuit, and Therein, both the first semiconductor unit and the second semiconductor unit are connected to at least one back side power rail.

12. The semiconductor device according to claim 11, wherein The second semiconductor unit takes a form in which the first semiconductor unit is inverted.

13. The semiconductor device according to claim 12, wherein: The output pins and the input pins are aligned with each other in the first direction.

14. The semiconductor device according to claim 12, wherein: The at least one backside power rail comprises: a first backside power rail along a first boundary of the cell architecture; a second backside power rail along a virtual centerline of the cell architecture; and a third back side power rail along a second boundary of the cell structure opposite to the first boundary in a second direction intersecting the first direction, Wherein, the first back side power rail to the third back side power rail extend in the first direction.

15. The semiconductor device according to claim 11, wherein The first semiconductor unit includes a first portion and a second portion below the first portion in a second direction intersecting the first direction, the first portion including a first source / drain region and a first interconnect structure, The second semiconductor unit includes a third portion and a fourth portion below the third portion in the second direction, the fourth portion includes a second source / drain region and a second interconnect structure, and The first part is symmetrical to the fourth part.

16. The semiconductor device according to claim 15, wherein: The output pin of the first semiconductor unit includes a first metal line, and the input pin of the second semiconductor unit includes a second metal line, and At least one of the first metal line and the second metal line extends in the first direction and is connected to each other.

17. The semiconductor device according to claim 15, wherein: The first metal line is on one of the first portion and the second portion, and the second metal line is on one of the third portion and the fourth portion, and the one of the third portion and the fourth portion is aligned with the one of the first portion and the second portion in the first direction.

18. A semiconductor device comprising: a first semiconductor unit; as well as a second semiconductor unit, adjacent to and connected to the first semiconductor unit in a first direction, The first semiconductor unit includes a first portion and a second portion below the first portion in a second direction intersecting the first direction, the first portion includes a first source / drain region and a first interconnect structure, The second semiconductor unit includes a third portion and a fourth portion below the third portion in the second direction, the fourth portion includes a second source / drain region and a second interconnect structure, and The first part is symmetrical to the fourth part.

19. The semiconductor unit according to claim 18, wherein The first semiconductor unit and the second semiconductor unit include the same logic circuit, and The polarity of the first source / drain region in the first portion is the same as the polarity of the second source / drain region in the fourth portion.

20. The semiconductor device according to claim 18, further comprising a third semiconductor unit adjacent to and connected to the second semiconductor unit in the first direction, in, The first to third semiconductor units include the same logic circuit, and The output pin of the first semiconductor unit is connected to the input pin of the second semiconductor unit, and the output pin of the second semiconductor unit is connected to the input pin of the third semiconductor unit.

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