Semiconductor device

Abstract

A semiconductor device is provided. Embodiments provide a semiconductor device capable of achieving low resistance and low inductance of a circuit pattern in an insulating circuit board. According to one embodiment, a semiconductor device includes an insulating circuit board, an insulating circuit board, a semiconductor chip provided between the insulating circuit boards, and a board spacer. A conductive pattern included in a conductive plate of an insulating circuit board has a first side, a second side, a third side, and a fourth side disposed so as to surround a substrate spacer. The first side extends in the Y direction, the second side is arranged continuously with the first side and extends in the X direction orthogonal to the Y direction, the third side is arranged continuously with the second side and extends in the Y direction, and the fourth side is arranged continuously with the third side and extends obliquely with respect to the Y direction and the X direction.

Description

[0001] Reference to related applications

[0002] This application claims the priority of Japanese Patent Application No. 2023-120009 (filing date: July 24, 2023) as a basic application. The present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] There is known a semiconductor device including an insulating circuit substrate on which a semiconductor chip is mounted. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor device capable of achieving low resistance and low inductance of a circuit pattern in an insulating circuit substrate.

[0006] A semiconductor device according to an embodiment includes: a first insulating circuit substrate having a first conductive plate, a second conductive plate, and a first insulating substrate disposed between the first conductive plate and the second conductive plate; a second insulating circuit substrate having a third conductive plate, a fourth conductive plate, and a second insulating substrate disposed between the third conductive plate and the fourth conductive plate; a first semiconductor chip disposed between the first insulating circuit substrate and the second insulating circuit substrate; and a first spacer disposed between the first insulating circuit substrate and the second insulating circuit substrate. The first conductive plate has a first conductive pattern, the first spacer is disposed on the first conductive pattern, the first conductive pattern has a first side, a second side, a third side, and a fourth side disposed in a manner of surrounding the first spacer, the first side extending in a first direction, the second side being disposed continuously with the first side and extending in a second direction orthogonal to the first direction, the third side being disposed continuously with the second side and extending in the first direction, and the fourth side being disposed continuously with the third side and extending obliquely with respect to the first direction and the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a perspective view showing the outer appearance of the semiconductor device according to the first embodiment.

[0008] Figure 2 It is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figure 3 It is along Figure 2 Cross-sectional view along line III-III.

[0010] Figure 4This is an enlarged view of the periphery of the substrate spacer in the semiconductor device according to the first embodiment.

[0011] Figure 5 This is an enlarged view of the periphery of a substrate spacer in a semiconductor device of a comparative example.

[0012] Figure 6 It is a plan view showing the structure of a semiconductor device according to a second embodiment.

[0013] Figure 7 This is an enlarged view of the periphery of a substrate spacer in the semiconductor device according to the second embodiment.

[0014] Figure 8 It is a plan view showing the structure of a semiconductor device according to a third embodiment.

[0015] Fig. 9 This is an enlarged view of the periphery of a substrate spacer in the semiconductor device according to the third embodiment.

[0016] Description of Reference Numerals

[0017] 1…Main body, 2…Board terminal, 3…Board terminal, 3A…Board terminal, 3B…Board terminal, 4…Board terminal, 5…Lead terminal, 6…Molding, 10…Insulating circuit substrate, 11…Conductive plate, 11a…Conductive pattern, 11b…Conductive pattern, 11c…Conductive pattern, 11d…Conductive pattern, 11e…Conductive pattern, 11f…Conductive pattern, 11g…Conductive pattern, 12…Conductive plate, 13…Ceramic substrate, 14…Slit, 20…Insulating circuit substrate, 2 1…conductive plate, 22…conductive plate, 23…ceramic substrate, 30…semiconductor chip, 31…solder material, 32…bonding wire, 33…solder pad, 40…semiconductor chip, 41…solder material, 42…bonding wire, 43…solder pad, 50…chip spacer, 51…solder material, 52…solder material, 60…chip spacer, 61…solder material, 62…solder material, 70…substrate spacer, 71…solder material, 72…solder material, 80…substrate spacer. DETAILED DESCRIPTION

[0018] The following describes the embodiments with reference to the accompanying drawings. In the following description, components having the same function and configuration are denoted by common reference numerals. In addition, the embodiments shown below illustrate devices and methods for embodying the technical ideas of the embodiments, and do not define the materials, shapes, structures, and configurations of the components as those described below.

[0019] 1. First Implementation

[0020] A semiconductor device according to a first embodiment will be described. The semiconductor device includes a semiconductor chip and two insulating circuit substrates sandwiching the semiconductor chip from above and below, and has a package structure in which these are held by a mold member.

[0021] use Figure 1 , Figure 2 as well as Figure 3 , the structure of the semiconductor device of the first embodiment is described. Figure 1 It is a perspective view showing the outer appearance of the semiconductor device according to the first embodiment. Figure 2 It is a plan view showing the structure of the semiconductor device according to the first embodiment. Figure 3 It is along Figure 2 Cross-sectional view along line III-III.

[0022] The semiconductor device includes a main body 1, plate terminals 2, 3 and 4, and a plurality of lead terminals 5. The main body 1 includes a mold member 6, a lower insulating circuit substrate 10, an upper insulating circuit substrate 20, semiconductor chips 30 and 40, chip spacers 50 and 60, and substrate spacers 70 and 80.

[0023] The plate terminals 2, 3 and 4 are electrically connected to the conductive pattern (or circuit pattern) of the insulating circuit substrate 10. The lead terminals 5 are electrically connected to the semiconductor chips 30 and 40 or the conductive pattern. Figure 2 The top view shown shows the structure on the insulating circuit substrate 10 when viewed through the insulating circuit substrate 20 and the mold member 6 .

[0024] like Figure 2 As shown in the figure, a semiconductor chip 30 is provided on one end side of the insulating circuit substrate 10 in the X direction, and a semiconductor chip 40 is provided on the other end side of the insulating circuit substrate 10 in the X direction. Substrate spacers 70 and 80 are provided along the Y direction between the semiconductor chip 30 and the semiconductor chip 40. Hereinafter, the side of the insulating circuit substrate 10 where the semiconductor chip 30 is provided is referred to as one end in the X direction, and the side where the semiconductor chip 40 is provided is referred to as the other end in the X direction.

[0025] like Figure 3 As shown, the insulating circuit substrate 10 includes a conductive plate 11, a conductive plate 12, and a ceramic substrate 13. The ceramic substrate 13 is provided between the conductive plate 11 and the conductive plate 12. That is, the conductive plate 11 is arranged on the upper surface of the ceramic substrate 13, and the conductive plate 12 is arranged on the lower surface of the ceramic substrate 13. The thickness of each of the conductive plates 11 and 12 is, for example, about 0.4 mm. The conductive plates 11 and 12 are made of, for example, copper. The ceramic substrate 13 is formed of an insulating material and has electrical insulation.

[0026] The conductive plate 11 is provided with slits 14 formed by removing a part of the conductive plate 11 in a certain pattern. That is, the slits 14 are provided in the conductive plate 11 and are grooves formed by removing a part of the conductive plate 11.

[0027] The conductive plate 11 is separated into three conductive patterns (or circuit patterns) 11a, 11b, and 11c by the slits 14. The conductive patterns 11a, 11b, and 11c are electrically insulated from each other.

[0028] Similarly, the insulating circuit substrate 20 includes a conductive plate 21, a conductive plate 22, and a ceramic substrate 23. The ceramic substrate 23 is provided between the conductive plate 21 and the conductive plate 22. That is, the conductive plate 21 is arranged on the upper surface of the ceramic substrate 23, and the conductive plate 22 is arranged on the lower surface of the ceramic substrate 23. The thickness of each of the conductive plates 21 and 22 is, for example, about 0.4 mm. The conductive plates 21 and 22 are made of, for example, copper. The ceramic substrate 23 is formed of an insulating material and has electrical insulation.

[0029] Although not shown, the conductive plate 22 is separated by slits into a plurality of conductive patterns (or circuit patterns) that are electrically insulated from each other.

[0030] The semiconductor chip 30 is provided on the conductive pattern 11a via a solder material 31. The die spacer 50 is provided on the semiconductor chip 30 via a solder material 51. Furthermore, the conductive pattern of the conductive plate 22 is provided on the die spacer 50 via a solder material 52.

[0031] The semiconductor chip 30 includes, for example, a MOS field effect transistor (ie, MOSFET) or an IGBT (insulated gate bipolar transistor). Here, the semiconductor chip 30 is described assuming that it is a MOS field effect transistor. The semiconductor chip 30 has a gate, a source, and a drain as electrodes.

[0032] For example, the drain electrode of the semiconductor chip 30 is electrically connected to the conductive pattern 11 a via the solder material 31 . The source electrode of the semiconductor chip 30 is electrically connected to the chip spacer 50 via the solder material 51 .

[0033] The chip spacer 50 includes a conductive material and has conductivity. Therefore, the source electrode of the semiconductor chip 30 is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 51, the chip spacer 50, and the solder material 52. The chip spacer 50 also functions as a heat dissipation path for dissipating heat generated in the semiconductor chip 30 to the insulating circuit substrate 20.

[0034] The substrate spacer 70 is provided on the conductive pattern 11b via the solder material 71. The conductive pattern of the conductive plate 22 is provided on the substrate spacer 70 via the solder material 72.

[0035] The substrate spacer 70 has a circular shape when viewed from the Z direction, for example, and has a cylindrical shape having a thickness in the Z direction. The substrate spacer 70 includes a conductive material and has conductivity. Therefore, the conductive pattern 11b is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 71, the substrate spacer 70, and the solder material 72.

[0036] The semiconductor chip 40 is provided on the conductive pattern 11c via the solder material 41. The die spacer 60 is provided on the semiconductor chip 40 via the solder material 61. Furthermore, the conductive pattern of the conductive plate 22 is provided on the die spacer 60 via the solder material 62.

[0037] The semiconductor chip 40 includes, for example, a MOS field effect transistor or an IGBT. Here, the semiconductor chip 40 is described assuming that it is a MOS field effect transistor. The semiconductor chip 40 has a gate, a source, and a drain as electrodes.

[0038] For example, the drain electrode of the semiconductor chip 40 is electrically connected to the conductive pattern 11 c via the solder material 41 . The source electrode of the semiconductor chip 40 is electrically connected to the chip spacer 60 via the solder material 61 .

[0039] The chip spacer 60 includes a conductive material and has conductivity. Therefore, the source electrode of the semiconductor chip 40 is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 61, the chip spacer 60, and the solder material 62. The chip spacer 60 also functions as a heat dissipation path for dissipating heat generated in the semiconductor chip 40 to the insulating circuit substrate 20.

[0040] The substrate spacer 80 is provided on the conductive pattern 11c via a solder material. The conductive pattern of the conductive plate 22 is provided on the substrate spacer 80 via a solder material.

[0041] The substrate spacer 80 has a circular shape when viewed from the Z direction, for example, and has a cylindrical shape having a thickness in the Z direction. The substrate spacer 80 includes a conductive material and has conductivity. Therefore, the conductive pattern 11c is electrically connected to the conductive pattern of the conductive plate 22 via the solder material, the substrate spacer 80, and the solder material.

[0042] In addition, if Figure 2 As shown, the plate terminals 2 and 3 are provided at one end side of the insulating circuit substrate 10 in the Y direction, and the plate terminal 4 is provided at the other end side of the insulating circuit substrate 10 in the Y direction. Hereinafter, the side of the insulating circuit substrate 10 where the plate terminals 2 and 3 are provided is referred to as one end in the Y direction, and the side where the plate terminal 4 is provided is referred to as the other end in the Y direction.

[0043] A plate terminal 2 is arranged at one end of the conductive pattern 11a in the Y direction. The plate terminal 2 is joined to the conductive pattern 11a via a solder material. The plate terminal 2 is electrically connected to the conductive pattern 11a. A plate terminal 3 is arranged at one end of the conductive pattern 11b in the Y direction. The plate terminal 3 is joined to the conductive pattern 11b via a solder material. The plate terminal 3 is electrically connected to the conductive pattern 11b. Furthermore, a plate terminal 4 is arranged at the other end of the conductive pattern 11c in the Y direction. The plate terminal 4 is joined to the conductive pattern 11c via a solder material. The plate terminal 4 is electrically connected to the conductive pattern 11c.

[0044] The plate terminal 2 is supplied with a high voltage, for example. The plate terminal 2 is also referred to as a P terminal, for example. The plate terminal 3 is supplied with a low voltage lower than the high voltage supplied to the plate terminal 2. The plate terminal 3 is also referred to as an N terminal, for example. Furthermore, the plate terminal 4 outputs either the high voltage supplied to the plate terminal 2 or the low voltage supplied to the plate terminal 3. The plate terminal 4 is also referred to as an AC terminal, for example. The thickness of each of the plate terminals 2, 3, and 4 is, for example, 0.8 mm.

[0045] Furthermore, a plurality of lead terminals 5 are provided on the other end side of the insulating circuit substrate 10 in the Y direction.

[0046] A conductive pattern 11d and a conductive pattern 11e are arranged on the other end side in the Y direction of the insulating circuit substrate 10 relative to the semiconductor chip 30. The conductive patterns 11d and 11e are island-shaped patterns.

[0047] For example, the lead terminal 5 is bonded to the conductive pattern 11d via a solder material. The conductive pattern 11d is connected to the pad 33 of the semiconductor chip 30 via a bonding wire 32. The pad 33 is connected to the gate of the semiconductor chip 30. The lead terminal 5 is electrically connected to the gate of the semiconductor chip 30 via the conductive pattern 11d, the bonding wire 32, and the pad 33.

[0048] The other lead terminals 5 are joined to the conductive pattern 11e via a solder material. The lead terminals 5 are electrically connected to the conductive pattern 11e.

[0049] Furthermore, a conductive pattern 11f and a conductive pattern 11g are arranged on the other end side in the Y direction with respect to the semiconductor chip 40. The conductive patterns 11f and 11g are each an island-shaped pattern.

[0050] For example, the lead terminal 5 is bonded to the conductive pattern 11f via a solder material. The conductive pattern 11f is connected to the pad 43 of the semiconductor chip 40 via a bonding wire 42. The pad 43 is connected to the gate of the semiconductor chip 40. The lead terminal 5 is electrically connected to the gate of the semiconductor chip 40 via the conductive pattern 11f, the bonding wire 42 and the pad 43.

[0051] The other lead terminals 5 are joined to the conductive pattern 11g via a solder material. The lead terminals 5 are electrically connected to the conductive pattern 11g.

[0052] Next, use Figure 4 The conductive pattern 11 b to which the substrate spacer 70 is bonded via the solder material 71 will be described. Figure 4 This is an enlarged view of the substrate spacer 70 and its surroundings in the semiconductor device according to the first embodiment.

[0053] exist Figure 4 In the embodiment, when viewed from the Z direction, that is, when viewed from above with respect to the surface of the conductive plate 11 of the insulating circuit substrate 10 (or when viewed from an orthogonal direction), the first side 14aa of the conductive pattern 11b is arranged on the right side (or the other end side) in the X direction of the substrate spacer 70. The second side 14bb of the conductive pattern 11b is arranged on the upper side (or the other end side) in the Y direction of the substrate spacer 70. The third side 14cc of the conductive pattern 11b is arranged on the left side (or the one end side) in the X direction of the substrate spacer 70. Moreover, the fourth side 14dd of the conductive pattern 11b is arranged on the lower side (or the one end side) in the Y direction of the substrate spacer 70.

[0054] The first side 14aa, the second side 14bb, the third side 14cc, and the fourth side 14dd are continuous without interruption, and surround the substrate spacer 70. The first side 14aa extends in a straight line along the Y direction. The second side 14bb extends in a straight line along the X direction. The third side 14cc extends in a straight line along the Y direction. Moreover, the fourth side 14dd is inclined with respect to the X direction and the Y direction, in other words, extends in a straight line crossing the X direction and the Y direction.

[0055] The first side 14aa and the fourth side 14dd are arranged so that the interval between the first side 14aa and the fourth side 14dd becomes narrower as they go to the lower side (or one end side) in the Y direction. In other words, the first side 14aa and the fourth side 14dd are arranged so that the interval between the first side 14aa and the fourth side 14dd becomes narrower as they go to the direction away from the substrate spacer 70. In this case, the interval between the first side 14aa and the fourth side 14dd is smaller than the diameter of the substrate spacer 70.

[0056] Next, use Figure 4 The slits 14 provided around the substrate spacer 70 will be described.

[0057] The substrate spacer 70 has a circular shape. The slit 14 is provided around the substrate spacer 70. The slit 14 includes a first portion 14a, a second portion 14b, a third portion 14c, and a fourth portion 14d.

[0058] The first portion 14a is provided between the conductive pattern 11b and the conductive pattern 11c. The first portion 14a is arranged to be in contact with the circumference of the substrate spacer 70 when viewed from the Z direction and to extend linearly along the Y direction. Here, the circumference of the substrate spacer 70 refers to a curve forming the substrate spacer 70 when viewed from the Z direction.

[0059] The second portion 14b is provided continuously with the first portion 14a between the conductive pattern 11b and the conductive pattern 11c. The second portion 14b is arranged to be in contact with the circumference of the substrate spacer 70 when viewed from the Z direction, and extends linearly in the X direction.

[0060] The third portion 14c is provided continuously with the second portion 14b between the conductive pattern 11b and the conductive pattern 11a. The third portion 14c is arranged to be in contact with the circumference of the substrate spacer 70 when viewed from the Z direction, and extends linearly in the Y direction.

[0061] The fourth portion 14d is provided continuously with the third portion 14c between the conductive pattern 11b and the conductive pattern 11a. The fourth portion 14d is arranged to be in contact with the circumference of the substrate spacer 70 when viewed from the Z direction. The fourth portion 14d is inclined with respect to the X direction and the Y direction, in other words, extends in a straight line crossing the X direction and the Y direction.

[0062] The second portion 14b is continuously disposed with the first portion 14a without interruption. The third portion 14c is continuously disposed with the second portion 14b without interruption. Furthermore, the fourth portion 14d is continuously disposed with the third portion 14c without interruption. That is, the first portion 14a, the second portion 14b, the third portion 14c, and the fourth portion 14d are disposed so as to surround the substrate spacer 70.

[0063] The substrate spacer 70 is bonded to the region of the conductive pattern 11 b surrounded by the first portion 14 a to the fourth portion 14 d via a solder material.

[0064] In the first embodiment, a semiconductor device capable of achieving low resistance and low inductance of a conductive pattern (or circuit pattern) in an insulating circuit substrate can be provided.

[0065] Figure 5 It is an enlarged view of the substrate spacer 70 and its surroundings in the semiconductor device of the comparative example. In the comparative example, the slit 100 corresponds to the slit 14 .

[0066] like Figure 5As shown, in the semiconductor device of the comparative example, the first portion 100a, the second portion 100b, the third portion 100c, and the fourth portion 100d of the slit 100 are arranged so as to surround the substrate spacer 70. In other words, the first side 100aa, the second side 100bb, the third side 100cc, and the fourth side 100dd of the conductive pattern 11b are arranged so as to surround the substrate spacer 70. Moreover, the fifth portion 100e is arranged between the first portion 100a and the fourth portion 100d. Thus, the substrate spacer 70 is prevented from being displaced when the substrate spacer 70 is soldered.

[0067] If the fourth portion 100d extending in the X direction is provided in this way, and the fifth portion 100e is further provided between the first portion 100a and the fourth portion 100d, the conductive pattern 11b between the first portion 100a and the fourth portion 100d on the lower right side of the substrate spacer 70 becomes narrower. Therefore, there is a case where the resistance and inductance of the conductive pattern 11b increase. In addition, if the fourth portion 100d extending in the X direction is provided in the third portion 100c extending in the Y direction, the edge portion of the conductive pattern 11b, that is, the third side 100cc and the fourth side 100dd are arranged orthogonally. If the third side 100cc and the fourth side 100dd are orthogonal to each other in this way, the high-frequency component of the AC signal passes through the edge, which sometimes causes the inductance to increase.

[0068] In contrast, in the first embodiment, the fourth side 14dd of the conductive pattern 11b is arranged to be inclined relative to the X direction and the Y direction so as to be in contact with the substrate spacer 70, that is, arranged in a direction descending to the right when viewed from the Z direction. In other words, the first side 14aa and the fourth side 14dd of the conductive pattern 11b are arranged so that the interval between the first side 14aa and the fourth side 14dd becomes narrower as they go away from the substrate spacer 70.

[0069] In addition, if the slit 14 is focused, the fourth portion 14d of the slit 14 is arranged to be inclined with respect to the X direction and the Y direction so as to be in contact with the substrate spacer 70, that is, arranged in a direction descending to the right when viewed from the Z direction. In other words, the first portion 14a and the fourth portion 14d of the slit 14 are arranged so that the interval between the first portion 14a and the fourth portion 14d becomes narrower as it moves away from the substrate spacer 70.

[0070] Thus, it is not necessary to provide the fifth portion 100e between the first portion 14a and the fourth portion 14d of the slit 14, so that the substrate spacer 70 can be prevented from being displaced, and the resistance and inductance of the conductive pattern 11b can be reduced. In addition, since the third side 14cc and the fourth side 14dd of the conductive pattern 11b are arranged at an angle greater than a right angle, the inductance caused by the high-frequency component of the AC signal flowing through the conductive pattern 11b can be reduced compared to the case where the third side 14cc and the fourth side 14dd are arranged at a right angle.

[0071] In addition, in the configuration of the first embodiment, the insulating circuit substrates 10 and 20 can dissipate heat generated from the semiconductor chips 30 and 40 and the conductive pattern to the outside. Specifically, when the semiconductor device is operating, the heat generated from the semiconductor chips 30 and 40 and the conductive pattern is dissipated to the outside from both sides of the semiconductor device, that is, the insulating circuit substrates 10 and 20 arranged above and below the semiconductor chips 30 and 40.

[0072] As described above, according to the semiconductor device of the first embodiment, it is possible to achieve lower resistance and lower inductance of the conductive pattern (or circuit pattern) in the insulating circuit substrate.

[0073] 2. Second Implementation

[0074] Next, a semiconductor device according to a second embodiment is described. In the second embodiment, an example is shown in which the shape of the plate terminal 3 (ie, N terminal) is improved on the basis of the configuration of the first embodiment. In the second embodiment, the differences from the first embodiment are mainly described.

[0075] use Figure 6 as well as Figure 7 The configuration of the semiconductor device according to the second embodiment will be described.

[0076] In the semiconductor device of the second embodiment, the shape of plate terminal 3A is different from plate terminal 3 of the first embodiment. The other configurations are the same as those of the first embodiment.

[0077] Figure 6 It is a plan view showing the structure of a semiconductor device according to a second embodiment. Figure 7 It is an enlarged view of the periphery of the substrate spacer 70 in the semiconductor device according to the second embodiment.

[0078] The plate terminal 3A is arranged at one end of the conductive pattern 11b in the Y direction. The plate terminal 3A has a protruding portion A on one end side in the X direction. That is, the plate terminal 3A has a rectangular shape, and has a protruding portion A protruding from a part of one end side in the X direction of the rectangular shape. In other words, the plate terminal 3A includes a rectangular portion having a rectangular shape and a protruding portion A protruding from one end in the X direction of the rectangular portion. In addition, the distance from one end in the X direction of the rectangular portion or the protruding portion A to the substrate spacer 70 is shorter than the distance from the other end in the X direction of the rectangular portion to the substrate spacer 70.

[0079] The protrusion A overlaps with the conductive pattern 11b in the Z direction. The plate terminal 3A including the protrusion A is joined to the conductive pattern 11b via a solder material and is electrically connected to the conductive pattern 11b. The thickness of the plate terminal 3A is, for example, 0.8 mm.

[0080] The second embodiment includes a plate terminal 3A having a larger area than the plate terminal 3, and the plate terminal 3A is electrically connected to the conductive pattern 11b. That is, in the second embodiment, in addition to the plate terminal 3 shown in the first embodiment, the protrusion A is also electrically connected to the conductive pattern 11b.

[0081] Conductive pattern 11b near one end side of plate terminal 3A in the X direction is a current path where current flows intensively between plate terminal 3A and substrate spacer 70. Protrusion A is provided on this current path, so the current path can be shortened using only conductive pattern 11b.

[0082] This can further reduce the resistance and inductance in the plate terminal 3A and the conductive pattern 11 b .

[0083] As described above, the semiconductor device according to the second embodiment, in addition to the configuration of the first embodiment, further includes a plate terminal 3A with an increased area, thereby being able to further achieve lower resistance and lower inductance of the conductive pattern (or circuit pattern) in the insulating circuit substrate compared to the first embodiment.

[0084] 3. Third Implementation

[0085] Next, a semiconductor device according to a third embodiment will be described. In the third embodiment, an example is shown in which the shape of plate terminal 3A (ie, N terminal) is further improved compared to the second embodiment. In the third embodiment, the differences from the first embodiment will be mainly described.

[0086] use Figure 8 as well as Fig. 9 The configuration of the semiconductor device of the third embodiment will be described. In the semiconductor device of the third embodiment, the shape of plate terminal 3B is different from that of the first and second embodiments. The other configurations are the same as those of the first and second embodiments.

[0087] Figure 8 It is a plan view showing the structure of a semiconductor device according to a third embodiment. Fig. 9 It is an enlarged view of the periphery of a substrate spacer 70 in the semiconductor device according to the third embodiment.

[0088] The plate terminal 3B is arranged at one end of the conductive pattern 11b in the Y direction. The plate terminal 3B has a protrusion B at one end side in the X direction and the other end side in the Y direction. That is, the plate terminal 3B has a rectangular shape, and has a protrusion B protruding from a part of one end side in the X direction and a part of the other end side in the Y direction of the rectangular shape. In other words, the plate terminal 3B includes a rectangular portion having a rectangular shape and a protrusion B protruding from one end in the X direction of the rectangular portion and the other end in the Y direction of the rectangular portion. In addition, the distance from one end in the X direction of the rectangular portion or the protrusion B to the substrate spacer 70 is shorter than the distance from the other end in the X direction of the rectangular portion to the substrate spacer 70.

[0089] The protrusion B overlaps with the conductive pattern 11b in the Z direction. The plate terminal 3B including the protrusion B is joined to the conductive pattern 11b via a solder material and is electrically connected to the conductive pattern 11b. The thickness of the plate terminal 3B is, for example, 0.8 mm.

[0090] In the third embodiment, a plate terminal 3B having a larger area than the plate terminal 3 or 3A is provided, and the plate terminal 3B is electrically connected to the conductive pattern 11b. That is, in the third embodiment, in addition to the plate terminal 3 shown in the first embodiment, the protrusion B is also electrically connected to the conductive pattern 11b.

[0091] The conductive pattern 11b near one end side in the X direction and the other end side in the Y direction of the plate terminal 3B is a current path where current flows intensively between the plate terminal 3B and the substrate spacer 70. Since the protrusion B is provided on this current path, the path where current flows can be shortened using only the conductive pattern 11b.

[0092] This can further reduce the resistance and inductance in the plate terminal 3B and the conductive pattern 11 b .

[0093] As described above, according to the semiconductor device of the third embodiment, in addition to the structure of the first embodiment, it also has a plate terminal 3B with an increased area, so that compared with the first or second embodiment, it is possible to further achieve low resistance and low inductance of the conductive pattern (or circuit pattern) in the insulating circuit substrate.

[0094] In addition, in the first to third embodiments described above, an example in which the semiconductor device constitutes a MOS field effect transistor (i.e., MOSFET) is described, but the semiconductor device may also constitute other switching elements, such as an IGBT (insulated gate bipolar transistor). When the semiconductor device constitutes an IGBT, the source corresponds to the emitter, and the drain corresponds to the collector.

[0095] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: have: A first insulating circuit substrate having a first conductive plate, a second conductive plate, and a first insulating substrate disposed between the first conductive plate and the second conductive plate; A second insulating circuit substrate having a third conductive plate, a fourth conductive plate, and a second insulating substrate disposed between the third conductive plate and the fourth conductive plate; A first semiconductor chip is disposed between the first insulating circuit substrate and the second insulating circuit substrate; as well as a first spacer disposed between the first insulating circuit substrate and the second insulating circuit substrate; The first conductive plate has a first conductive pattern, disposing the first spacer on the first conductive pattern, The first conductive pattern has a first side, a second side, a third side, and a fourth side arranged to surround the first spacer. The first edge extends along a first direction, The second side is arranged continuously with the first side and extends along a second direction orthogonal to the first direction. The third side is arranged continuously with the second side and extends along the first direction, The fourth side is arranged continuously with the third side, and extends obliquely with respect to the first direction and the second direction.

2. The semiconductor device according to claim 1, wherein: As the first side and the fourth side move in a direction away from the first partition, a distance between the first side and the fourth side becomes narrower.

3. The semiconductor device according to claim 2, wherein: A distance between the first side and the fourth side is smaller than a diameter of the first spacer.

4. The semiconductor device according to claim 1, wherein: The first side, the second side, the third side, and the fourth side extend in a straight line, respectively.

5. The semiconductor device according to claim 1, wherein: The first conductive plate has the first conductive pattern, the second conductive pattern and the third conductive pattern, Around the first spacer, slits formed by removing the first conductive plate are provided between the first conductive pattern and the second conductive pattern and between the first conductive pattern and the third conductive pattern.

6. The semiconductor device according to claim 5, wherein: The slit has a first portion, a second portion, a third portion and a fourth portion, The first portion extends along the first direction, The second portion is disposed continuously with the first portion and extends along a second direction orthogonal to the first direction. The third portion is disposed continuously with the second portion and extends along the first direction. The fourth portion is disposed continuously with the third portion, and extends obliquely with respect to the first direction and the second direction.

7. The semiconductor device according to claim 1, wherein: Also available: a second semiconductor chip disposed between the first insulating circuit substrate and the second insulating circuit substrate; a second spacer, disposed between the first insulating circuit substrate and the second insulating circuit substrate; a third spacer, disposed between the first semiconductor chip and the second insulating circuit substrate; as well as The fourth spacer is provided between the second semiconductor chip and the second insulating circuit substrate.

8. The semiconductor device according to claim 1, wherein: further comprising a terminal provided at one end of the first conductive pattern in the first direction, The terminal includes a rectangular portion having a rectangular shape and a protruding portion protruding from one end of the rectangular portion in the second direction.

9. The semiconductor device according to claim 8, wherein: further comprising a terminal provided at one end of the first conductive pattern in the first direction, The terminal includes a rectangular portion having a rectangular shape and a protruding portion protruding from one end of the rectangular portion in the second direction and protruding from the other end of the rectangular portion in the first direction.

10. The semiconductor device according to claim 8, wherein: A distance from the protruding portion to the first spacer is shorter than a distance from the other end of the rectangular portion in the second direction to the first spacer.

11. The semiconductor device according to claim 1, wherein: The first semiconductor chip includes a MOS field effect transistor.

12. The semiconductor device according to claim 1, wherein: The first semiconductor chip includes an IGBT (insulated gate bipolar transistor).

13. The semiconductor device according to claim 1, wherein: The first insulating substrate and the second insulating substrate are ceramic substrates.

14. A semiconductor device, characterized in that: have: A first insulating circuit substrate having a first conductive plate including a first conductive pattern, a second conductive plate, and a first insulating substrate disposed between the first conductive plate and the second conductive plate; A second insulating circuit substrate having a third conductive plate, a fourth conductive plate, and a second insulating substrate disposed between the third conductive plate and the fourth conductive plate; A first semiconductor chip is disposed between the first insulating circuit substrate and the second insulating circuit substrate; a first spacer, provided between the first insulating circuit substrate and the second insulating circuit substrate, and arranged on the first conductive pattern; as well as A terminal is provided at one end of the first conductive pattern in a first direction, The terminal includes a rectangular portion having a rectangular shape and a protruding portion protruding from one end of the rectangular portion in a second direction orthogonal to the first direction.

15. The semiconductor device according to claim 14, wherein: A distance from the protruding portion to the first spacer is shorter than a distance from the other end of the rectangular portion in the second direction to the first spacer.

16. The semiconductor device according to claim 14, wherein: The protrusion protrudes from the other end of the rectangular portion in the first direction.

17. The semiconductor device according to claim 14, wherein: The first conductive pattern has a first side, a second side, a third side, and a fourth side arranged to surround the first spacer. The first edge extends along the first direction, The second side is arranged continuously with the first side and extends along a second direction orthogonal to the first direction. The third side is arranged continuously with the second side and extends along the first direction, The fourth side is arranged continuously with the third side, and extends obliquely with respect to the first direction and the second direction.

18. The semiconductor device according to claim 17, wherein: As the first side and the fourth side move in a direction away from the first partition, a distance between the first side and the fourth side becomes narrower.

19. The semiconductor device according to claim 18, wherein: A distance between the first side and the fourth side is smaller than a diameter of the first spacer.

20. The semiconductor device according to claim 17, wherein The first side, the second side, the third side, and the fourth side extend in a straight line, respectively.

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