Electronic fuse, manufacturing method thereof and solid-state memory

Abstract

The invention discloses an electronic fuse, a manufacturing method thereof and a solid-state memory, which can be used in the field of semiconductor devices, and the electronic fuse comprises a silicon substrate, a shallow trench isolation oxide layer and a polycrystalline silicon gate which are stacked in sequence, the polycrystalline silicon gate comprises a first ion doped region, a second ion doped region and a high-resistance region; the high-resistance region is located between the first ion doped region and the second ion doped region. Therefore, the first ion-doped region, the second ion-doped region and the high-resistance region are formed in the polycrystalline silicon gate, and the resistance of the high-resistance region is greater than that of the first ion-doped region and the second ion-doped region, so that the eFuse is in a high-resistance state after being programmed, and the eFuse can be in a high-resistance state by controlling the size of the high-resistance region. And the resistance value after eFuse programming can be in a relatively stable interval, so that the accuracy and long-term reliability of data reading are ensured.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to an electronic fuse and a manufacturing method thereof, and a solid-state memory. Background Art

[0002] With the rapid development of information technology, the demands for data security and permission management are increasing. As a one-time programmable (OTP) solid-state storage solution, the importance and application scope of electronic fuse (eFuse) are constantly expanding.

[0003] The principle of programming the eFuse device is to cause changes in the internal material structure through electric current heating, usually the melting of the metal wires to form a high-resistance state, thus serving as a storage medium for binary information. This process is irreversible, thus ensuring the durability and security of the stored data. However, if the resistance value of the eFuse is too large or too small after programming, it will affect its normal operation. Controlling the resistance value of the eFuse after programming in a relatively stable range is crucial to ensure the accuracy of data reading and long-term reliability.

[0004] Therefore, how to make the resistance value of the eFuse after programming be in a relatively stable range becomes a problem that needs to be solved. Summary of the invention

[0005] Based on the above problems, the present application provides an electronic fuse and a manufacturing method thereof, and a solid-state memory, which can make the resistance value of the eFuse after programming be in a relatively stable range.

[0006] The embodiments of the present application disclose the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides an electronic fuse, wherein the electronic fuse comprises:

[0008] A silicon substrate, a shallow trench isolation oxide layer and a polysilicon gate are stacked in sequence;

[0009] The polysilicon gate includes a first ion doping region, a second ion doping region and a high resistance region; the high resistance region is located between the first ion doping region and the second ion doping region.

[0010] Optionally, the high-resistance region is a non-ion-doped region.

[0011] Optionally, the width of the high resistance region is determined according to a target resistance after programming of the electronic fuse.

[0012] Optionally, the electronic fuse further includes: a metal silicide layer located on a side of the polysilicon gate away from the silicon substrate.

[0013] Optionally, the electronic fuse further includes: a first metal line electrically connected to the first ion-doped region, and a second metal line electrically connected to the second ion-doped region.

[0014] In a second aspect, an embodiment of the present application provides a method for manufacturing an electronic fuse, the method comprising:

[0015] providing a silicon substrate;

[0016] forming a shallow trench isolation oxide layer on one side of the silicon substrate;

[0017] Growing a polysilicon layer on a side of the shallow trench isolation oxide layer away from the silicon substrate;

[0018] Etching the polysilicon layer according to the designed polysilicon resistor shape to form a polysilicon gate;

[0019] Ion doping is performed on both ends of the polysilicon gate to form a first ion doping region, a second ion doping region and a high resistance region; the high resistance region is located between the first ion doping region and the second ion doping region.

[0020] Optionally, forming a shallow trench isolation oxide layer on one side of the silicon substrate includes:

[0021] Etching the surface of the silicon substrate to form a plurality of shallow trenches;

[0022] Silicon oxide is filled in the plurality of shallow trenches by chemical vapor deposition to form a shallow trench isolation oxide layer.

[0023] Optionally, after ion doping is performed on both ends of the polysilicon gate to form a first ion doping region, a second ion doping region and a high resistance region, the method further comprises:

[0024] Depositing a metal layer on a side of the polysilicon gate away from the silicon substrate;

[0025] The metal layer reacts with the surface of the polysilicon gate through heat treatment to form a metal silicide layer.

[0026] Optionally, after forming the metal silicide layer, the method further comprises:

[0027] A first metal wire and a second metal wire connected to the metal silicide layer are formed; the contact position between the first metal wire and the metal silicide layer is located in the first ion doping region, and the contact position between the second metal wire and the metal silicide layer is located in the second ion doping region.

[0028] In a third aspect, an embodiment of the present application provides a solid-state memory, wherein the memory includes the electronic fuse described in any implementation of the first aspect.

[0029] Compared with the prior art, this application has the following beneficial effects:

[0030] The embodiment of the present application provides an electronic fuse, which includes: a silicon substrate, a shallow trench isolation oxide layer and a polysilicon gate stacked in sequence; the polysilicon gate includes a first ion doping region, a second ion doping region and a high resistance region; the high resistance region is located between the first ion doping region and the second ion doping region. After the electronic fuse is programmed, the part with smaller resistance and lower melting point is fused, and the current will flow through the electronic fuse via the first ion doping region, the second ion doping region and the high resistance region, that is, the resistance of the electronic fuse will be determined by the resistance of the polysilicon gate. Thus, the first ion doping region, the second ion doping region and the high resistance region are formed in the polysilicon gate, and the resistance of the high resistance region is greater than that of the first ion doping region and the second ion doping region, which can make the eFuse present a high resistance state after programming, and can also control the size of the high resistance region so that the resistance value of the eFuse after programming can be in a relatively stable range, thereby ensuring the accuracy and long-term reliability of data reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A conventional OTP circuit structure diagram provided in an embodiment of the present application;

[0033] Figure 2 A structural diagram of an electronic fuse provided in an embodiment of the present application;

[0034] Figure 3 A top view of an electronic fuse provided in an embodiment of the present application;

[0035] Figure 4 A flow chart of a method for manufacturing an electronic fuse provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The electronic fuse and the manufacturing method thereof, and the solid-state memory provided in the present application can be used in the field of semiconductor devices. The above is only an example and does not limit the application field of the electronic fuse and the manufacturing method thereof, and the solid-state memory provided in the present application.

[0037] The terms "first", "second", "third" and "fourth" etc. in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0038] In the embodiments of the present application, the words "as an example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "as an example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the words "as an example" or "for example" is intended to present the relevant concepts in a specific way.

[0039] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0040] As mentioned above, with the rapid development of information technology, the demand for data security, device personalization and permission management is growing. Electronic fuse (eFuse for short), as a one-time programmable (OTP) solid-state storage solution, has demonstrated irreplaceable advantages in many fields with its unique information storage method, especially in data protection, device unique identification and precise authorization management. Its importance and application scope are constantly expanding.

[0041] The core mechanism of eFuse to achieve one-time permanent storage is that when information needs to be stored, the current or voltage pulse flowing through the eFuse is higher than a threshold, so that part of the eFuse area is melted due to the Joule heating effect, and then a high-resistance state is formed. In this way, the binary information "0" and "1" can be stored respectively through the low-resistance state and high-resistance state of the eFuse. This fusing process is irreversible, so the stored information cannot be erased or modified, thereby ensuring the persistence and security of the stored data. This feature makes eFuse an ideal choice for storing key data such as device serial numbers, encryption keys, and device identification codes (IDs), providing a tamper-proof authentication and data protection foundation for the device.

[0042] Although eFuse technology has shown significant advantages in the field of information security, its commercial application still faces several challenges. One of the primary issues is the control of the resistance value of the eFuse after programming. The ideal eFuse should be able to present a high-resistance state after programming, and the resistance value should be relatively stable and consistent, which is crucial to ensure the accuracy and long-term reliability of data reading.

[0043] In view of this, in order to improve the consistency and predictability of resistance after programming, an embodiment of the present application provides an electronic fuse, which includes: a silicon substrate, a shallow trench isolation oxide layer and a polysilicon gate stacked in sequence; the polysilicon gate includes a first ion doping region, a second ion doping region and a high resistance region; the high resistance region is located between the first ion doping region and the second ion doping region.

[0044] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] See also Figure 1 , which is a conventional OTP circuit structure diagram provided by an embodiment of the present application, wherein the OTP (One-Time Programmable) circuit includes a word line WL that provides a voltage to the gate of the MOSFET and a bit line BL that applies a voltage to the anode of the eFuse, and the cathode of the eFuse is coupled to the MOSFET. Based on the voltage applied to the gate of the MOSFET, current will flow through the eFuse, and a portion of the eFuse will accumulate heat to a melting point, causing a portion of the eFuse to blow out.

[0046] See also Figure 2 , which is a structural diagram of an electronic fuse provided in an embodiment of the present application, and the electronic fuse includes:

[0047] A silicon substrate 201 , a shallow trench isolation oxide layer 202 and a polysilicon gate 203 are stacked in sequence.

[0048] The polysilicon gate 203 includes a first ion-doped region 2031 , a second ion-doped region 2032 and a high-resistance region 2033 ; the high-resistance region 2033 is located between the first ion-doped region 2031 and the second ion-doped region 2032 .

[0049] For example, a shallow trench may be first etched on the silicon substrate 201, and then an insulating material such as silicon dioxide may be filled in the shallow trench to form a shallow trench isolation (STI) oxide layer 202, thereby reducing parasitic capacitance between devices and facilitating improving circuit speed.

[0050] Optionally, silicon dioxide can be filled in the shallow trench by methods such as chemical vapor deposition (CVD), and the deposited silicon dioxide can be higher than the shallow trench and cover the surface of the silicon substrate. Then, excess silicon dioxide is removed by performing methods such as chemical mechanical polishing (CMP) to expose the surface of the silicon substrate to form a shallow trench isolation oxide layer 202.

[0051] See also Figure 3 , this figure is a top view of an electronic fuse provided in an embodiment of the present application, the polysilicon gate 203 is located on the side of the shallow trench isolation oxide layer 202 away from the silicon substrate 201, and its top view shape can be etched into an "I" shape with a fuse neck with a smaller cross-sectional area.

[0052] Ion doping is performed on the surface of the polysilicon gate 203. Specifically, a first ion doping region 2031 and a second ion doping region 2032 can be formed in the polysilicon gate 203 by, for example, ion implantation. A high resistance region 2033 is provided between the first ion doping region 2031 and the second ion doping region 2032. That is, the first ion doping region 2031, the high resistance region 2033 and the second ion doping region 2032 are arranged in sequence along the first direction. The ion doping types of the first ion doping region 2031 and the second ion doping region 2032 are different. For example, the first ion doping region 2031 is an N-type ion doping region, and the second ion doping region 2032 is a P-type ion doping region; or the first ion doping region 2031 is a P-type ion doping region, and the second ion doping region 2032 is an N-type ion doping region.

[0053] Optionally, the high resistance region 2033 may be a non-ion doped region that has not been ion doped. Since ion doping can significantly reduce the resistance of the semiconductor, the resistance of the non-ion doped region will be higher than that of the first ion doped region 2031 and the second ion doped region 2032 .

[0054] Optionally, the width of the high resistance region 2023 is determined according to the target resistance after the eFuse is programmed. Specifically, the width of the high resistance region 2023 is the distance between the first ion doping region 2031 and the second ion doping region 2032 in the first direction. Since the resistance of the high resistance region 2023 is higher than that of the first ion doping region 2031 and the second ion doping region 2032, and the resistance is proportional to the length, the width of the high resistance region 2023 can be set to a fixed value according to the desired resistance after the eFuse is programmed, so that the eFuse is in a high resistance state after programming and the resistance value is in a relatively stable range.

[0055] Optionally, a metal silicide layer 204 is also provided on the side of the polysilicon gate 203 facing away from the silicon substrate 201. Metal silicide is a compound formed by the reaction of metal and silicon. During the eFuse programming process, a sufficiently high current or voltage is applied to the eFuse, and the metal silicide layer 204 will be blown due to the thermal effect. In particular, when the top view shape of the polysilicon gate 203 is an "I" shape, the top view shape of the metal silicide layer 204 located thereon is also an "I" shape. Since the resistance of the same material and length is smaller, the smaller the cross-sectional area, the higher the resistance. Therefore, the thinner part of the metal silicide layer 204 has a higher resistance. During the eFuse programming process, the blowout will occur at the thinner position of the metal silicide layer 204.

[0056] Optionally, the eFuse further comprises a first metal line 2051 electrically connected to the first ion-doped region 2031, and a second metal line 2052 electrically connected to the second ion-doped region 2032. Specifically, the first metal line 2051 and the second metal line 2052 may contact the surface of the metal silicide layer 204 to form an electrical connection, wherein the contact position between the first metal line 2051 and the metal silicide layer 204 is located in the first ion-doped region 2031, and the contact position between the second metal line 2052 and the metal silicide layer 204 is located in the second ion-doped region 2032.

[0057] Thus, the embodiment of the present application provides an electronic fuse, which includes: a silicon substrate, a shallow trench isolation oxide layer and a polysilicon gate stacked in sequence; the polysilicon gate includes a first ion doping region, a second ion doping region and a high resistance region; the high resistance region is located between the first ion doping region and the second ion doping region. After the electronic fuse is programmed, the part with smaller resistance and lower melting point is fused, and the current will flow through the electronic fuse via the first ion doping region, the second ion doping region and the high resistance region, that is, the resistance of the electronic fuse will be determined by the resistance of the polysilicon gate. Thus, the first ion doping region, the second ion doping region and the high resistance region are formed in the polysilicon gate, and the resistance of the high resistance region is greater than that of the first ion doping region and the second ion doping region, which can make the eFuse present a high resistance state after programming, and can also control the size of the high resistance region so that the resistance value of the eFuse after programming can be in a relatively stable range, thereby ensuring the accuracy and long-term reliability of data reading.

[0058] See also Figure 4 , which is a flow chart of a method for manufacturing an electronic fuse provided in an embodiment of the present application, the method comprising:

[0059] S401: Provide a silicon substrate.

[0060] S402: forming a shallow trench isolation oxide layer on one side of the silicon substrate.

[0061] For example, the surface of the silicon substrate may be etched first to form a plurality of shallow trenches; and then silicon oxide may be filled in the plurality of shallow trenches by chemical vapor deposition to form a shallow trench isolation oxide layer.

[0062] Optionally, a mask may be first formed on the surface of the silicon substrate, the mask covering areas that do not need to be etched and exposing areas on the surface of the silicon substrate that need to be etched into shallow grooves; then, the mask is removed, and the silicon substrate is etched by a dry etching method such as plasma etching or a wet etching method such as hydrofluoric acid etching to form a plurality of shallow grooves on the surface of the silicon substrate; then, the formed shallow grooves may be cleaned to remove impurities and damage layers that may remain on the groove walls, and a thin layer of silicon dioxide is deposited at the bottom of the cleaned shallow grooves as a liner to reduce stress that may be generated in subsequent processes; finally, silicon dioxide may be filled in the shallow trenches by methods such as chemical vapor deposition (CVD), and to ensure that the silicon dioxide can fill the trenches, the filled silicon dioxide may be higher than the surface of the silicon substrate, and then the wafer surface may be planarized by, for example, chemical mechanical polishing (CMP) technology to remove excess silicon dioxide and form a shallow trench isolation oxide layer. Optionally, in order to avoid loss of silicon substrate thickness due to over-polishing, stress is introduced into the silicon substrate, and a thin layer of silicon dioxide may remain on the surface of the planarized silicon substrate.

[0063] S403: growing a polysilicon layer on a side of the shallow trench isolation oxide layer facing away from the silicon substrate.

[0064] As an example, the polysilicon layer may be grown using a method such as chemical vapor deposition (CVD).

[0065] S404: etching the polysilicon layer according to the designed polysilicon resistor shape to form a polysilicon gate.

[0066] As an example, a mask may be formed on the surface of the polysilicon layer, the mask covering the area that does not need to be etched, exposing the area on the surface of the polysilicon layer that needs to be etched as a polysilicon gate; then, the polysilicon layer is etched by a dry etching method such as plasma etching or a wet etching method such as hydrofluoric acid etching to expose the shallow trench isolation oxide layer, thereby forming a polysilicon gate. The top view shape of the polysilicon gate may be an "I" shape.

[0067] S405: performing ion doping on both ends of the polysilicon gate to form a first ion doping region, a second ion doping region and a high resistance region.

[0068] The high resistance region is located between the first ion doping region and the second ion doping region, and the first ion doping region and the second ion doping region have different ion types.

[0069] Specifically, a mask that only exposes the first ion-doped region can be formed first, and then ion doping is performed on the exposed region by methods such as ion implantation, for example, N-type ion doping; then, the mask that only exposes the first ion-doped region is removed and a mask that only exposes the second ion-doped region is formed, and then ion doping is performed on the exposed region by methods such as ion implantation, for example, P-type ion doping; finally, the mask that only exposes the second ion-doped region is removed to obtain the first ion-doped region, the second ion-doped region and the high-resistance region, wherein the high-resistance region is a region that has not been ion-doped, and the high-resistance region is located at the fuse neck position, and its cross-sectional area is smaller than the cross-sectional areas of the first ion-doped region and the second ion-doped region.

[0070] S406: depositing a metal layer on a side of the polysilicon gate away from the silicon substrate.

[0071] As an example, a metal layer can be formed by depositing metal on the side of the polysilicon gate away from the silicon substrate by processes such as magnetron sputtering or evaporation. Preferably, the deposited metal is a metal such as titanium, cobalt or nickel that can react with silicon.

[0072] Optionally, before depositing the metal layer, a mask may be formed on the surface of the exposed shallow trench isolation oxide layer, for example, a silicon nitride hard mask may be formed.

[0073] S407: The metal layer reacts with the surface of the polysilicon gate through heat treatment to form a metal silicide layer.

[0074] Optionally, heat treatment can be performed first to react the portion of the metal layer in contact with the polysilicon gate surface to form a metal silicide; then, dry etching or wet etching is performed to remove the unreacted portion of the metal layer, that is, to remove the metal that is not in contact with the polysilicon gate; finally, annealing treatment can be performed to further optimize the structure and electrical properties of the metal silicide, reduce defects in the metal silicide, promote phase change, and obtain a denser metal silicide layer.

[0075] S408: forming a first metal line and a second metal line connected to the metal silicide layer.

[0076] Specifically, the contact position between the first metal wire and the metal silicide layer is located in the first ion-doped region, and the contact position between the second metal wire and the metal silicide layer is located in the second ion-doped region.

[0077] Optionally, a dielectric layer may be formed on the side of the metal silicide layer facing away from the silicon substrate. The dielectric layer may be an oxide, a nitride, a nitride oxide, or a stack of oxides and nitrides. The dielectric layer may be formed by methods such as chemical vapor deposition (CVD). After the dielectric layer is formed, the dielectric layer may be etched to the metal silicide layer, and at least one through hole may be formed at positions corresponding to the first ion-doped region and the second ion-doped region, respectively; then, metal may be filled in the through hole to form a first metal wire located in the first ion-doped region and a second metal wire located in the second ion-doped region, and the first metal wire and the second metal wire are used to be electrically connected to the bit line BL and the MOSFET, respectively.

[0078] Therefore, in the embodiment of the present application, first, a silicon substrate is provided; then, a shallow trench isolation oxide layer is formed on one side of the silicon substrate; then, a polysilicon layer is grown on the side of the shallow trench isolation oxide layer away from the silicon substrate; then, the polysilicon layer is etched according to the designed polysilicon resistor shape to form a polysilicon gate; finally, ion doping is performed on both ends of the polysilicon gate to form a first ion doping region, a second ion doping region and a high resistance region; the high resistance region is located between the first ion doping region and the second ion doping region. After the electronic fuse is programmed, the part with smaller resistance and lower melting point is melted, and the current will flow through the electronic fuse via the first ion doping region, the second ion doping region and the high resistance region, that is, the resistance of the electronic fuse will be determined by the resistance of the polysilicon gate. Therefore, in the electronic fuse manufactured by the method provided in the embodiment of the present application, a first ion-doped region, a second ion-doped region and a high-resistance region are formed in the polysilicon gate, wherein the resistance of the high-resistance region is greater than that of the first ion-doped region and the second ion-doped region. This can not only make the eFuse present a high-resistance state after programming, but also control the size of the high-resistance region so that the resistance value of the eFuse after programming can be in a relatively stable range, thereby ensuring the accuracy of data reading and long-term reliability.

[0079] In addition, the present application also provides a solid-state memory, which includes a plurality of electronic fuses described in any of the above embodiments.

[0080] It should be noted that each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the device embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the device embodiment. The method embodiment described above is only illustrative, and some or all of the steps can be selected according to actual needs to achieve the purpose of the embodiment scheme. Ordinary technicians in this field can understand and implement it without paying creative work.

[0081] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An electronic fuse, characterized in that: The electronic fuse comprises: A silicon substrate, a shallow trench isolation oxide layer and a polysilicon gate are stacked in sequence; The polysilicon gate includes a first ion doping region, a second ion doping region and a high resistance region; the high resistance region is located between the first ion doping region and the second ion doping region.

2. The electronic fuse according to claim 1, characterized in that: The high resistance region is a non-ion doped region.

3. The electronic fuse according to claim 1, characterized in that: The width of the high resistance region is determined according to a target resistance of the electronic fuse after programming.

4. The electronic fuse according to claim 1, characterized in that: The electronic fuse further includes: a metal silicide layer located on a side of the polysilicon gate away from the silicon substrate.

5. The electronic fuse according to claim 1, wherein: The electronic fuse further includes a first metal line electrically connected to the first ion-doped region, and a second metal line electrically connected to the second ion-doped region.

6. A method for manufacturing an electronic fuse, characterized in that: The method comprises: providing a silicon substrate; forming a shallow trench isolation oxide layer on one side of the silicon substrate; Growing a polysilicon layer on a side of the shallow trench isolation oxide layer away from the silicon substrate; Etching the polysilicon layer according to the designed polysilicon resistor shape to form a polysilicon gate; Ion doping is performed on both ends of the polysilicon gate to form a first ion doping region, a second ion doping region and a high resistance region; the high resistance region is located between the first ion doping region and the second ion doping region.

7. The method according to claim 6, characterized in that The step of forming a shallow trench isolation oxide layer on one side of the silicon substrate comprises: Etching the surface of the silicon substrate to form a plurality of shallow trenches; Silicon oxide is filled in the plurality of shallow trenches by chemical vapor deposition to form a shallow trench isolation oxide layer.

8. The method according to claim 6, characterized in that After ion doping is performed on both ends of the polysilicon gate to form a first ion doping region, a second ion doping region and a high resistance region, the method further includes: Depositing a metal layer on a side of the polysilicon gate away from the silicon substrate; The metal layer reacts with the surface of the polysilicon gate through heat treatment to form a metal silicide layer.

9. The method according to claim 8, characterized in that After forming the metal silicide layer, the method further comprises: A first metal wire and a second metal wire connected to the metal silicide layer are formed; the contact position between the first metal wire and the metal silicide layer is located in the first ion doping region, and the contact position between the second metal wire and the metal silicide layer is located in the second ion doping region.

10. A solid-state memory, characterized in that: The memory includes the electronic fuse according to any one of claims 1 to 5.

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