Semiconductor interconnection structure and manufacturing method thereof

Abstract

The invention provides a semiconductor interconnection structure and a manufacturing method thereof, and the semiconductor interconnection structure comprises a dielectric layer which comprises grooves arranged at intervals; the first barrier layer is formed on the bottom surface and the side wall of the groove; the lining layer is formed on the bottom surface and the side wall of the first barrier layer; the interconnection metal is formed in the lining layer; the insulating layer is formed on the surfaces of the dielectric layer, the first barrier layer and the lining layer; the metal cover is formed on the surface of part of the interconnection metal; and the second barrier layer is formed on the surfaces of the rest of the interconnection metal, and the second barrier layer is positioned between the metal cover and the insulating layer so as to isolate the metal cover from the lining layer. According to the interconnection structure, the situation that metal elements in the metal cover are diffused into the lining layer can be avoided, and therefore the reliability of the interconnection structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor interconnect structure and a manufacturing method thereof. Background Art

[0002] In the manufacturing process of integrated circuits, the back end of line (BEOL) includes forming vias and line networks (collectively referred to as interconnect structures) on the wafer. In the interconnect structures of existing semiconductor processes, a liner is usually used for copper filling, and a metal cap is used to mitigate electromagnetic migration. Since the metal cap is located on top of the liner, it is easy for the metal elements in the metal cap to diffuse into the liner, resulting in an increase in resistivity and degradation of the metal cap layer interface. Therefore, there is room for improvement. Summary of the invention

[0003] The present invention provides a semiconductor interconnection structure and a manufacturing method thereof, so as to improve the technical problem that metal elements in a metal cover are easily diffused into a liner in the semiconductor interconnection structure.

[0004] The present invention provides a semiconductor interconnect structure, comprising: a dielectric layer, wherein the dielectric layer includes grooves arranged at intervals; A first barrier layer formed on the bottom surface and sidewalls of the trench; A liner layer formed on the bottom surface and sidewalls of the first barrier layer; Interconnect metal formed inside the liner; an insulating layer formed on surfaces of the dielectric layer, the first barrier layer and the liner; a metal cap formed on a surface of a portion of the interconnect metal; and A second barrier layer is formed on the surface of the remaining interconnection metals, and the second barrier layer is located between the metal cover and the insulating layer to isolate the metal cover from the liner.

[0005] In one embodiment of the present invention, in the horizontal direction, the metal cover is in a polygonal shape, the second barrier layer is in a polygonal ring shape, and the second barrier layer surrounds the metal cover.

[0006] In one embodiment of the present invention, the top surface of the dielectric layer is coplanar with the top surface of the first barrier layer, the top surface of the first barrier layer is coplanar with the top surface of the liner, and the top surface of the liner is coplanar with the top surface of the interconnect metal.

[0007] In one embodiment of the present invention, the top surface of the insulating layer is coplanar with the top surface of the second barrier layer, and the top surface of the second barrier layer is higher than the top surface of the metal cover.

[0008] In one embodiment of the present invention, the semiconductor interconnect structure further includes a dielectric cap formed on surfaces of the insulating layer, the metal cap and the second barrier layer.

[0009] The present invention also provides a method for manufacturing a semiconductor interconnect structure, comprising: Providing a dielectric layer, forming spaced trenches on the dielectric layer; forming a first barrier layer on the bottom surface and sidewalls of the trench, forming a liner on the bottom surface and sidewalls of the first barrier layer, and forming an interconnect metal inside the liner; forming an insulating layer on surfaces of the dielectric layer, the first barrier layer and the liner; forming a second barrier layer on a surface of a portion of the interconnect metal, wherein the second barrier layer is adjacent to the insulating layer; A metal cap is formed on the surface of the remaining interconnection metals, wherein the metal cap is located inside the second barrier layer, and the metal cap is isolated from the liner by the second barrier layer.

[0010] In one embodiment of the present invention, the step of forming an insulating layer on the surfaces of the dielectric layer, the first barrier layer and the liner comprises: Depositing an inhibitor layer on the surface of the interconnect metal, wherein the inhibitor layer comprises at least one of phosphorus, sulfur, silicon, carbon, nitrogen, thiol, silane, phosphonate, and benzotriazole; forming an insulating layer on the surfaces of the dielectric layer, the first barrier layer and the liner by using a self-aligned deposition process; The inhibitor layer on the interconnect metal surface is removed.

[0011] In one embodiment of the present invention, after the step of removing the inhibitor layer on the surface of the interconnect metal, the method further comprises: forming a blocking dielectric layer on the surfaces of the interconnection metal and the insulating layer; Etching the barrier dielectric layer on the surface of the insulating layer and part of the interconnect metal surface to retain the second barrier layer at the edge of the insulating layer; A metal cap is formed on the surface of the interconnect metal between the second barrier layers.

[0012] In one embodiment of the present invention, the steps of forming a first barrier layer on the bottom surface and sidewalls of the trench, forming a liner on the bottom surface and sidewalls of the first barrier layer, and forming an interconnect metal inside the liner include: forming a first barrier layer on the surface of the dielectric layer, the bottom surface and the sidewall of the trench; forming a liner on the surface of the first barrier layer corresponding to the top of the dielectric layer and on the bottom surface and sidewall of the first barrier layer corresponding to the groove; forming a metal layer on the surface of the liner corresponding to the top of the dielectric layer and on the inside and top of the liner corresponding to the groove; The metal layer, the liner on the surface of the dielectric layer and the first barrier layer are ground so that the top surface of the dielectric layer, the top surface of the first barrier layer, the top surface of the liner and the top surface of the metal layer are coplanar, wherein the metal layer on the surface of the liner corresponding to the groove is recorded as interconnect metal.

[0013] In one embodiment of the present invention, after the step of forming a metal cap on the surface of the remaining interconnect metal, the metal cap being located inside the second barrier layer, and isolating the metal cap from the liner through the second barrier layer, the method further comprises: A dielectric cap is formed on surfaces of the insulating layer, the metal cap, and the second barrier layer.

[0014] Beneficial effects of the present invention: A semiconductor interconnect structure and a manufacturing method thereof proposed by the present invention, in which a second barrier layer is provided to isolate a metal cover and a liner, can avoid the diffusion of metal elements in the metal cover into the liner, thereby improving the reliability of the interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 The figure is a schematic diagram of the interconnection structure provided in the prior art.

[0017] Figure 2 Provided in the prior art Figure 1 Corresponding electron microscope images.

[0018] Figure 3 Provided in the prior art Figure 1 Schematic diagram of the corresponding curve of the diffusion of metal elements from the metal cover into the liner.

[0019] Figure 4 A cross-sectional schematic diagram of a semiconductor interconnect structure provided by an embodiment of the present invention.

[0020] Figure 5A schematic diagram of the distribution of a metal cap and a second barrier layer on a dielectric layer in a semiconductor interconnect structure provided by one embodiment of the present invention.

[0021] Figure 6 A schematic structural diagram of a method for manufacturing a semiconductor interconnect structure provided by an embodiment of the present invention.

[0022] Figure 7 A schematic diagram of a structure for forming a trench on a dielectric layer according to an embodiment of the present invention.

[0023] Figure 8 A schematic structural diagram of forming a first barrier layer on a surface of a dielectric layer, a bottom surface and a sidewall of a trench provided in one embodiment of the present invention.

[0024] Fig. 9 A schematic diagram of a structure in which a liner is formed on the surface of a first barrier layer according to an embodiment of the present invention.

[0025] Fig.10 A schematic diagram of a structure for forming a metal layer on a liner according to an embodiment of the present invention.

[0026] Fig.11 A schematic diagram of the structure after the metal layer, the liner layer and the first barrier layer are ground according to an embodiment of the present invention.

[0027] Fig.12 A schematic diagram of a structure for depositing an inhibitor layer on the surface of an interconnect metal according to an embodiment of the present invention.

[0028] Fig.13 A schematic structural diagram of forming an insulating layer on the surfaces of a dielectric layer, a first barrier layer and a liner provided in one embodiment of the present invention.

[0029] Fig.14 A schematic diagram of the structure for removing an inhibitor layer provided by one embodiment of the present invention.

[0030] Fig.15 A schematic diagram of a structure for forming a blocking dielectric layer on the surfaces of an interconnect metal and an insulating layer provided by an embodiment of the present invention.

[0031] Fig.16 A schematic structural diagram of etching a blocking dielectric layer provided by an embodiment of the present invention.

[0032] Fig.17 A schematic diagram of a structure for forming a metal cover on the surface of an interconnect metal according to an embodiment of the present invention.

[0033] Fig.18 A schematic diagram of a structure in which a dielectric cover is formed on an insulating layer, a second barrier layer, and a metal cover according to an embodiment of the present invention.

[0034] Description of Figure Numbers 10. Dielectric layer; 100. Inhibitor layer; 110. Groove; 20. First barrier layer; 30. Liner; 40. Interconnect metal; 410. Metal layer; 50. Insulating layer; 60. Second barrier layer; 610. Blocking dielectric layer; 70. Metal cover; 80. Dielectric cover. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0036] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0037] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0038] See also Figures 1 to 3 In the semiconductor interconnect structure of the prior art, there is a metal cap 70 located on top of the liner 30, and it is easy for the metal elements in the metal cap 70 to diffuse into the liner 30, thereby increasing the resistivity and deteriorating the interface of the metal cap 70 layer. Figure 3 It is a composition diagram measured by secondary ion mass spectrometry (SIMS). The horizontal axis is time (Seconds) and the vertical axis is intensity / count (Log / Counts). The horizontal axis can be understood as the measured depth position increasing with the scanning time, and the vertical axis can be understood as the component concentration (the more signal counts, the higher the component content). Please refer to Figures 4 to 18In order to avoid the situation in the prior art where the metal elements in the metal cover 70 diffuse into the liner 30, the present invention proposes a semiconductor interconnect structure and a manufacturing method thereof, which can be applied to the semiconductor interconnect structure. By setting a second barrier layer 60 between the metal cover 70 and the liner 30, the metal elements in the metal cover 70 can be prevented from diffusing into the liner 30, thereby improving the reliability of the interconnect structure. The following is a detailed analysis through specific embodiments.

[0039] See also Figure 4 and Figure 5 In one embodiment of the present invention, a semiconductor interconnect structure is provided, which may include a dielectric layer 10 , a first barrier layer 20 , a liner 30 , an interconnect metal 40 , an insulating layer 50 , a metal cap 70 and a second barrier layer 60 .

[0040] In one embodiment of the present invention, the dielectric layer 10 may be formed on a substrate, which may be formed of any suitable semiconductor material, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC) and multilayers thereof. Although silicon is the main semiconductor material used in wafer manufacturing, the substrate may also use alternative semiconductor materials as additional layers, such as but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc. The dielectric layer 10 may be deposited using any conventional deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD).

[0041] Specifically, the dielectric layer 10 may be formed of a low dielectric constant material, for example, the dielectric layer 10 may be formed of porous silicon carbon nitride (porous SiCN), silicon dioxide (SiO2), hydrogenated silicon carbide (SiCOH), silicon carbide (SiCO) or octamethylcyclotetrasiloxane. The dielectric layer 10 may include grooves 110 arranged at intervals. Figure 4 The groove 110 is not marked in the figure. In the method for manufacturing the semiconductor interconnect structure below, Figure 7 Marked in.

[0042] In one embodiment of the present invention, Figure 4As shown, the first barrier layer 20 may be formed on the bottom surface and sidewalls of the trench 110, the first barrier layer 20 may be in a U-shape, and the concave portion of the first barrier layer 20 faces upward. The liner 30 may be formed on the bottom surface and sidewalls of the first barrier layer 20, the liner 30 may be in a U-shape, and the concave portion of the liner 30 faces upward. An interconnect metal 40 may be formed inside the liner 30.

[0043] Specifically, the first barrier layer 20 may be formed of tantalum (Ta) or tantalum nitride (TaN), and the first barrier layer 20 is used to prevent any conductive material from diffusing into the dielectric layer 10. The liner 30 may be formed of ruthenium (Ru) or a ruthenium alloy, and the ruthenium liner 30 is used to achieve better filling of the internal interconnection metal 40. The interconnection metal 40 may be formed of copper (Cu), aluminum (Al), tungsten (W) or an alloy thereof (e.g., Cu-Al alloy).

[0044] In one embodiment of the present invention, the insulating layer 50 may be formed on the surfaces of the dielectric layer 10, the first barrier layer 20 and the liner 30, the metal cap 70 may be formed on the surface of a portion of the interconnect metal 40, the second barrier layer 60 may be formed on the surface of the remaining interconnect metal 40, and the second barrier layer 60 is located between the metal cap 70 and the insulating layer 50.

[0045] Specifically, the insulating layer 50 may be formed of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiNO) or silicon carbon nitride oxynitride (SiCyNx:H), and the insulating layer 50 may insulate the first barrier layer 20 and the liner 30, and reduce the stress on the top of the first barrier layer 20 and the liner 30. The second barrier layer 60 may isolate the metal cap 70 from the liner 30, and prevent the metal elements in the metal cap 70 from diffusing into the liner 30, thereby improving the reliability of the interconnection structure.

[0046] See also Figure 4 and Figure 5 In one embodiment of the present invention, in the horizontal direction, the metal cover 70 may be in a polygonal shape, the second barrier layer 60 may be in a polygonal ring shape, and the second barrier layer 60 surrounds the metal cover 70. For example, Figure 5 In the embodiment, the metal cover 70 is in a rectangular shape, the second barrier layer 60 may be in a rectangular ring shape, and the second barrier layer 60 surrounds the metal cover 70 .

[0047] See also Figure 4 and Figure 5In one embodiment of the present invention, the top surface of the dielectric layer 10 is coplanar with the top surface of the first barrier layer 20, the top surface of the first barrier layer 20 is coplanar with the top surface of the liner 30, and the top surface of the liner 30 is coplanar with the top surface of the interconnect metal 40. The top surface of the insulating layer 50 is coplanar with the top surface of the second barrier layer 60, and the top surface of the second barrier layer 60 is higher than the top surface of the metal cap 70. The semiconductor interconnect structure further includes a dielectric cap 80, which is formed on the surfaces of the insulating layer 50, the metal cap 70, and the second barrier layer 60.

[0048] Specifically, in the process of forming the first barrier layer 20 and the liner 30 in the trench 110, as shown in FIG. Figure 8 , Fig. 9 , Fig.10 and Fig.11 First, a first barrier layer 20 and a liner 30 are sequentially formed on the surface of the dielectric layer 10, the bottom surface and the sidewall of the trench 110. Then, a metal layer 410 is formed on the surface of the dielectric layer 10 and inside the liner 30. After that, the metal layer 410, the liner 30 and the first barrier layer 20 are synchronously polished in sequence to remove the metal layer 410, the liner 30 and the first barrier layer 20 on the surface of the dielectric layer 10, remove the metal layer 410 above the trench 110, retain the metal layer 410, the liner 30 and the first barrier layer 20 inside the trench 110, and the metal layer 410 inside the trench 110 is recorded as the interconnect metal 40.

[0049] Specifically, the metal layer 410, the liner 30, and the first barrier layer 20 are polished synchronously in sequence, and the top surface of the dielectric layer 10, the top surface of the first barrier layer 20, the top surface of the liner 30, and the top surface of the interconnect metal 40 are coplanar, so that the top surface of the dielectric layer 10, the top surface of the first barrier layer 20, the top surface of the liner 30, and the top surface of the interconnect metal 40 are flush, ensuring structural stability, accuracy and consistency, thereby improving device performance and reliability. The insulating layer 50 is formed on the surface of the dielectric layer 10, the first barrier layer 20, and the liner 30, which can reduce the stress between the insulating layer 50 and the dielectric layer 10, the first barrier layer 20, and the liner 30.

[0050] See also Figure 6 In one embodiment of the present invention, a method for manufacturing a semiconductor interconnect structure is provided, which may include the following steps.

[0051] Step S10, providing a dielectric layer, and forming spaced trenches on the dielectric layer.

[0052] Specifically, the dielectric layer 10 may be formed on a substrate, and the substrate may be formed of any suitable semiconductor material, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC) and multilayers thereof.

[0053] Specifically, the dielectric layer 10 may be formed of a low dielectric constant material. The dielectric layer 10 may include grooves 110 arranged at intervals. Figure 4 The groove 110 is not marked in the figure. In the method for manufacturing the semiconductor interconnect structure below, Figure 7 Marked in.

[0054] Step S20, forming a first barrier layer on the bottom surface and side walls of the trench, forming a liner on the bottom surface and side walls of the first barrier layer, and forming an interconnect metal inside the liner.

[0055] Specifically, the first barrier layer 20 may be formed on the bottom surface and sidewalls of the trench 110, the first barrier layer 20 may be in a U-shape, and the concave portion of the first barrier layer 20 faces upward. The liner 30 may be formed on the bottom surface and sidewalls of the first barrier layer 20, the liner 30 may be in a U-shape, and the concave portion of the liner 30 faces upward. An interconnect metal 40 may be formed inside the liner 30.

[0056] Step S30: forming an insulating layer on the surfaces of the dielectric layer, the first barrier layer and the liner.

[0057] Specifically, the insulating layer 50 may be formed of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiNO) or silicon carbon nitride oxide (SiCyNx:H). The insulating layer 50 may insulate the first barrier layer 20 and the liner 30 and reduce the stress on the top of the first barrier layer 20 and the liner 30.

[0058] Step S40: forming a second barrier layer on the surface of a portion of the interconnect metal, wherein the second barrier layer is adjacent to the insulating layer.

[0059] Specifically, the second barrier layer 60 can isolate the metal cover 70 from the liner 30 and prevent the metal elements in the metal cover 70 from diffusing into the liner 30 , thereby improving the reliability of the interconnection structure.

[0060] Step S50: forming a metal cap on the surface of the remaining interconnected metals, wherein the metal cap is located inside the second barrier layer, and the second barrier layer is used to isolate the metal cap from the liner.

[0061] See also Figures 7 to 18 , which is a method for manufacturing a semiconductor interconnect structure, corresponds to a specific structural diagram under different process technologies, and is described in detail below.

[0062] See also Figure 7 In one embodiment of the present invention, a dielectric layer 10 is provided, and trenches 110 arranged at intervals are formed on the dielectric layer 10 .

[0063] Specifically, a patterned photoresist layer (not shown in the figure) may be formed on the dielectric layer 10 , and the exposed dielectric layer 10 may be etched using the patterned photoresist layer as a mask to form the trench 110 on the dielectric layer 10 .

[0064] See also Figures 8 to 11 In one embodiment of the present invention, step S20 may include step S210, step S220, step S230 and step S240.

[0065] Step S210: forming a first barrier layer on the surface of the dielectric layer, the bottom surface and the sidewall of the trench.

[0066] Specifically, Figure 8 As shown, the first barrier layer 20 can be grown along the surface profile of the dielectric layer 10 and the surface profile of the bottom and sidewall of the trench 110. When the first barrier layer 20 grows uniformly, the first barrier layer 20 formed after a set time has a surface profile that is proportionally enlarged to the surface profile of the dielectric layer 10 and the surface profile of the bottom and sidewall of the trench 110.

[0067] Specifically, the first barrier layer 20 may be deposited by using any conventional deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD).

[0068] Step S220 , forming a liner on the surface of the first barrier layer corresponding to the top of the dielectric layer, and on the bottom surface and sidewalls of the first barrier layer corresponding to the trench.

[0069] Specifically, Fig. 9 As shown, the liner 30 can be grown along the surface profile of the first barrier layer 20 corresponding to the top of the dielectric layer 10 and the surface profile of the bottom and sidewall of the first barrier layer 20 corresponding to the groove 110. In the case where the liner 30 grows uniformly, the liner 30 formed after a set time has a surface profile that is proportionally enlarged to the surface profile of the first barrier layer 20 corresponding to the top of the dielectric layer 10 and the surface profile of the bottom and sidewall of the first barrier layer 20 corresponding to the groove 110.

[0070] Specifically, the liner 30 may be deposited by using any conventional deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD).

[0071] Step S230 , forming a metal layer on the surface of the liner corresponding to the top of the dielectric layer, and inside and top of the liner corresponding to the trench.

[0072] Specifically, Fig.10 As shown, the metal layer 410 inside the groove 110 is used as the interconnect metal 40, and the metal layer 410 on the surface of the liner 30 corresponding to the top of the dielectric layer 10 and the metal layer 410 on the top of the liner 30 corresponding to the groove 110 will be removed in the subsequent grinding process.

[0073] Step S240, grinding the metal layer, the liner and the first barrier layer on the surface of the dielectric layer so that the top surface of the dielectric layer, the top surface of the first barrier layer, the top surface of the liner and the top surface of the metal layer are coplanar, wherein the metal layer on the surface of the liner corresponding to the groove is recorded as interconnect metal.

[0074] Specifically, Fig.11 As shown, the metal layer 410, the liner 30, and the first barrier layer 20 are polished in sequence by chemical mechanical polishing (CMP) until the metal layer 410, the liner 30, and the first barrier layer 20 on the surface of the dielectric layer 10 are removed, the metal layer 410 above the groove 110 is removed, and the metal layer 410, the liner 30, and the first barrier layer 20 inside the groove 110 are retained.

[0075] See also Figure 12 to Figure 14 In one embodiment of the present invention, step S30 may include step S310, step S320 and step S330.

[0076] Step S310 , depositing an inhibitor layer on the surface of the interconnect metal, wherein the inhibitor layer includes at least one of phosphorus, sulfur, silicon, carbon, nitrogen, thiol, silane, phosphonate, and benzotriazole.

[0077] Specifically, Fig.12 As shown, an inhibitor layer 100 can be deposited on the surface of the interconnect metal 40 by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The inhibitor layer 100 used for surface modification, especially the self-assembled monolayer (SAM), can be attached to the material surface through different anchoring groups to achieve the purpose of inhibiting certain reactions or changing the surface properties. For example, anchoring groups include but are not limited to elements such as sulfur, silicon, carbon, nitrogen and their compounds, such as thiols, silanes, phosphonates and benzotriazoles, etc. These groups can form stable chemical bonds with different surface materials, thereby achieving surface functionalization.

[0078] Step S320: forming an insulating layer on the surfaces of the dielectric layer, the first barrier layer and the liner by using a self-aligned deposition process.

[0079] Specifically, Fig.13 As shown, since the inhibitor layer 100 has been deposited on the surface of the interconnect metal 40, a self-aligned (SA) deposition process can be performed on the surfaces of the dielectric layer 10, the first barrier layer 20 and the liner 30 on the peripheral side of the interconnect metal 40. The insulating layer 50 can be deposited on the surfaces of the dielectric layer 10, the first barrier layer 20 and the liner 30 on the peripheral side of the interconnect metal 40 by any conventional deposition technology, for example, physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0080] Step S330 , removing the inhibitor layer on the surface of the interconnect metal.

[0081] Specifically, Fig.14 As shown, the inhibitor layer 100 previously deposited on the surface of the interconnect metal 40 can be removed by dry gas immersion or wet process to restore the activity of the surface of the interconnect metal 40 for subsequent processing or deposition.

[0082] Specifically, dry gas immersion is, for example, plasma treatment in a vacuum environment, or in the presence of hydrogen (H2), nitrogen (N2), ammonia (NH3), carbon dioxide (CO2), oxygen (O2), air or a mixture thereof, and the treatment can be performed at ambient temperature or elevated temperature. Wet processing is, for example, acid washing, acid etching, solution cleaning or solution etching at ambient temperature or elevated temperature.

[0083] See also Figures 15 to 17 In one embodiment of the present invention, after step S330, step S40 may include step S410 and step S420, and step S50 may include step S510.

[0084] Step S410: forming a second barrier layer on the surfaces of the interconnect metal and the insulating layer.

[0085] Specifically, Fig.15As shown, the blocking dielectric layer 610 can be grown along the surface profile of the insulating layer 50 and the surface profile of the interconnection metal 40. In the case where the blocking dielectric layer 610 grows uniformly, the blocking dielectric layer 610 formed after a set time has a surface profile that is proportionally enlarged with the surface profiles of the insulating layer 50 and the surface profiles of the interconnection metal 40.

[0086] Specifically, the blocking dielectric layer 610 may be deposited by using any conventional deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD).

[0087] Step S420, etching the second barrier layer on the surface of the insulating layer and on a portion of the interconnect metal surface, and retaining the second barrier layer at the edge of the insulating layer.

[0088] Specifically, Fig.16 As shown, a patterned photoresist layer (not shown) can be formed on the surface of the blocking dielectric layer 610 , and the exposed blocking dielectric layer 610 is etched using the patterned photoresist layer as a mask to form a second blocking layer 60 at the boundary between the insulating layer 50 and the interconnect metal 40 .

[0089] Step S510: forming a metal cap on the surface of the interconnect metal between the second barrier layers.

[0090] Specifically, Fig.17 As shown, a metal cap 70 may be formed on the surface of the interconnection metal 40 by a deposition and etching process, and the metal cap 70 is located inside the second barrier layer 60 .

[0091] See also Fig.18 In one embodiment of the present invention, after step S50 , step S60 may be included. Step S60 may be represented as forming a dielectric cap 80 on the surfaces of the insulating layer 50 , the metal cap 70 and the second barrier layer 60 .

[0092] In summary, the present invention proposes a semiconductor interconnect structure and a method for manufacturing the same. In the semiconductor interconnect structure, a second barrier layer is provided to isolate the metal cover and the liner, thereby preventing the metal elements in the metal cover from diffusing into the liner, thereby improving the reliability of the interconnect structure.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the art without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention. As used in the description herein and in the following entire claims, unless otherwise specified, "one", and "the" include plural references. Similarly, as used in the description herein and in the following entire claims, unless otherwise specified, the meaning of "in..." includes "in..." and "on...".

Claims

1. A semiconductor interconnect structure, characterized in that: include: a dielectric layer, wherein the dielectric layer includes grooves arranged at intervals; A first barrier layer formed on the bottom surface and sidewalls of the trench; A liner layer formed on the bottom surface and sidewalls of the first barrier layer; Interconnect metal formed inside the liner; an insulating layer formed on surfaces of the dielectric layer, the first barrier layer and the liner; a metal cap formed on a surface of a portion of the interconnect metal; as well as A second barrier layer is formed on the surface of the remaining interconnection metals, and the second barrier layer is located between the metal cover and the insulating layer to isolate the metal cover from the liner.

2. The semiconductor interconnect structure according to claim 1, characterized in that: In the horizontal direction, the metal cover is in a polygonal shape, the second barrier layer is in a polygonal ring shape, and the second barrier layer surrounds the metal cover.

3. The semiconductor interconnect structure according to claim 1, characterized in that: The top surface of the dielectric layer is coplanar with the top surface of the first barrier layer, the top surface of the first barrier layer is coplanar with the top surface of the liner layer, and the top surface of the liner layer is coplanar with the top surface of the interconnect metal.

4. The semiconductor interconnect structure according to claim 1, wherein: A top surface of the insulating layer is coplanar with a top surface of the second barrier layer, and a top surface of the second barrier layer is higher than a top surface of the metal cap.

5. The semiconductor interconnect structure according to claim 1, wherein: The semiconductor interconnect structure further includes a dielectric cap formed on surfaces of the insulating layer, the metal cap and the second barrier layer.

6. A method for manufacturing a semiconductor interconnect structure, characterized in that: include: Providing a dielectric layer, forming spaced trenches on the dielectric layer; forming a first barrier layer on the bottom surface and sidewalls of the trench, forming a liner on the bottom surface and sidewalls of the first barrier layer, and forming an interconnect metal inside the liner; forming an insulating layer on surfaces of the dielectric layer, the first barrier layer and the liner; forming a second barrier layer on a surface of a portion of the interconnect metal, wherein the second barrier layer is adjacent to the insulating layer; A metal cap is formed on the surface of the remaining interconnection metals, wherein the metal cap is located inside the second barrier layer, and the metal cap is isolated from the liner by the second barrier layer.

7. The method for manufacturing a semiconductor interconnect structure according to claim 6, characterized in that: The step of forming an insulating layer on the surfaces of the dielectric layer, the first barrier layer and the liner comprises: Depositing an inhibitor layer on the surface of the interconnect metal, wherein the inhibitor layer comprises at least one of phosphorus, sulfur, silicon, carbon, nitrogen, thiol, silane, phosphonate, and benzotriazole; forming an insulating layer on the surfaces of the dielectric layer, the first barrier layer and the liner by using a self-aligned deposition process; The inhibitor layer on the interconnect metal surface is removed.

8. The method for manufacturing a semiconductor interconnect structure according to claim 7, characterized in that: After the step of removing the inhibitor layer on the surface of the interconnect metal, the method further comprises: forming a blocking dielectric layer on the surfaces of the interconnection metal and the insulating layer; Etching the barrier dielectric layer on the surface of the insulating layer and part of the interconnect metal surface to retain the second barrier layer at the edge of the insulating layer; A metal cap is formed on the surface of the interconnect metal between the second barrier layers.

9. The method for manufacturing a semiconductor interconnect structure according to claim 6, characterized in that: The steps of forming a first barrier layer on the bottom surface and sidewalls of the trench, forming a liner on the bottom surface and sidewalls of the first barrier layer, and forming an interconnect metal inside the liner include: forming a first barrier layer on the surface of the dielectric layer, the bottom surface and the sidewall of the trench; forming a liner on the surface of the first barrier layer corresponding to the top of the dielectric layer and on the bottom surface and sidewall of the first barrier layer corresponding to the groove; forming a metal layer on the surface of the liner corresponding to the top of the dielectric layer and on the inside and top of the liner corresponding to the groove; The metal layer, the liner on the surface of the dielectric layer and the first barrier layer are ground so that the top surface of the dielectric layer, the top surface of the first barrier layer, the top surface of the liner and the top surface of the metal layer are coplanar, wherein the metal layer on the surface of the liner corresponding to the groove is recorded as interconnect metal.

10. The method for manufacturing a semiconductor interconnect structure according to claim 6, characterized in that: After the step of forming a metal cover on the surface of the remaining interconnected metal, the metal cover is located inside the second barrier layer, and isolating the metal cover from the liner through the second barrier layer, the method comprises: A dielectric cap is formed on surfaces of the insulating layer, the metal cap, and the second barrier layer.

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