A fully digitally controlled programmable titanium-sapphire femtosecond oscillator carrier envelope offset frequency locking device

Abstract

This invention discloses a fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device, comprising an avalanche photodetector, a power divider, a first RF conditioning circuit, a second RF conditioning circuit, a frequency and phase discrimination circuit, a programmable proportional circuit, a programmable integral circuit, a programmable bias circuit, an inverting summation circuit, a programmable limiting circuit, an anti-saturation integral circuit, an output buffer circuit, a main control circuit, and a host computer. This invention enables the carrier envelope offset frequency to be locked to the repetition frequency. Employing a fully digitally controlled programmable PI circuit, combined with innovative anti-saturation integral and output limiting functions, it offers advantages such as low latency, high precision, high stability, and high security.

Description

Technical Field

[0001] This invention belongs to the field of femtosecond laser technology in optoelectronic information science, specifically relating to a fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device. Background Technology

[0002] Attosecond laser pulses are among the most effective tools for studying ultrafast physics processes. They can be used for tomographic imaging of molecules and atoms, capturing in real time the evolution of hole density after ionization of atoms and even biological / chemical molecules, as well as the time delay of electron ionization in different states of gas molecules, atoms, and solid surfaces. Attosecond pulses can not only study the motion of outermost electrons but can also be combined with X-ray diffraction, electron diffraction, and other methods to provide ultrafast time-resolved imaging techniques for studying solid materials and biomaterials, offering novel research methods for condensed matter physics, new materials, ultrafast chemistry, and nuclear physics.

[0003] As the seed source for attosecond beamlines, the stability of the carrier envelope phase of a Ti:sapphire femtosecond oscillator plays a crucial role in generating isolated attosecond pulses. The carrier envelope phase (CEP) refers to the phase difference between the envelope of the optical pulse and the peak value of the internal electric field. When a laser pulse propagates through a medium, dispersion causes the group velocity and phase velocity of the pulse to be unequal, resulting in a phase difference between the carrier peak and the envelope peak during propagation. This affects the intensity distribution of the electric field in the pulse, with a particularly significant impact on pulses of the periodic magnitude. When When the value is 0 or π, the carrier coincides with the envelope peak, and the envelope strength is the highest; however, when... When the value is other than f, the electric field strength within the envelope decreases. Therefore, carrier envelope phase control technology is crucial for generating stable optical pulse output from Ti:sapphire oscillators and is a key technology in the generation of isolated attosecond pulses. Femtosecond laser pulse sequences in the frequency domain are characterized by a frequency repetition frequency f of the oscillator. rep Given a comb-like sequence of longitudinal modes with intervals, the frequency of the nth longitudinal mode can be expressed as f. n =nf rep +f ceo f ceo This is the starting point of the entire comb-shaped spectral structure, also known as the carrier envelope offset frequency. The carrier envelope offset frequency and the carrier envelope phase have the following relationship:

[0004]

[0005] Therefore, locking the carrier envelope phase can be achieved by locking the carrier envelope offset frequency. In the process of generating isolated attosecond pulses, it is necessary to select pulse sequences with the same carrier envelope phase from the optical pulses at a certain period. To achieve this, the carrier envelope offset frequency needs to be locked to a repetition frequency of 1 / m, so that every m pulses will have the same carrier envelope phase.

[0006] A PI servo controller is fundamental for ensuring high-precision locking of the carrier envelope offset frequency and repetition frequency. Currently, there is no integrated frequency-locking device that can directly lock the carrier envelope offset frequency of a Ti:Sapphire oscillator to a repetition frequency of 1 / m. Laser frequency-locking devices can be divided into two main categories: digital and analog. Digital frequency-locking devices typically have a bandwidth of only tens of kHz, and digital operations introduce high latency, resulting in longer locking times and making locking difficult. Therefore, analog PI controllers are usually used to lock the carrier envelope offset frequency. Conventional analog PI controllers can achieve bandwidths of several MHz, but require manual adjustment of P and I parameters, which is cumbersome and cannot achieve high-precision tuning. In addition, conventional analog PI controllers suffer from integral saturation, which introduces severe overshoot into the control system. Furthermore, the uncontrollable output amplitude of ordinary PI controllers poses a risk of damaging the controlled system. Finally, conventional analog PI controllers typically have only one integral loop, which cannot quickly suppress high-frequency and low-frequency interference, resulting in poor loop dynamic performance. This causes the controlled system to drift slowly even after locking, posing a risk of loss of lock. Summary of the Invention

[0007] To overcome the shortcomings of existing technologies, this invention provides a fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device. It employs a programmable PI circuit with anti-saturation integration function to overcome the problems of inaccurate parameter tuning and easy saturation of traditional analog PI controllers. This device can precisely lock the carrier envelope offset frequency of the Ti:sapphire oscillator to one-eighth of the repetition frequency, offering advantages such as low delay, anti-saturation, and precise tuning. To achieve the above objectives, the specific technical solution of this invention is as follows:

[0008] The aforementioned fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device specifically includes:

[0009] Avalanche photodetectors are used to detect carrier envelope offset frequency and repetition frequency;

[0010] A power divider is used to split the power of the avalanche photodetector output signal into two output signals.

[0011] The first radio frequency conditioning circuit is used to filter and amplify the first output signal of the power divider in order to extract the carrier envelope offset frequency.

[0012] The second RF conditioning circuit is used to filter, attenuate, divide, and amplify the second output signal of the power divider in order to extract the repetition frequency.

[0013] Frequency and phase detector circuits are used to identify the phase difference between the repetition frequency and the carrier envelope offset frequency;

[0014] Programmable scaling circuits are used to amplify or attenuate phase error signals;

[0015] Programmable integrator circuit for filtering and integrating phase error signals;

[0016] A programmable bias circuit is used to fine-tune the bias voltage in the output signal of a PI circuit.

[0017] An inverting summator circuit is used to sum the outputs of proportional circuits, integrator circuits, and bias circuits.

[0018] A programmable limiting circuit is used to set the upper and lower limits of the output voltage.

[0019] An anti-saturation integrator circuit is used to generate an anti-saturation integrator trigger signal, which triggers the integrator circuit to stop integrating when it reaches critical saturation.

[0020] Output buffer circuit is used to isolate the output load and enhance the circuit's load-carrying capacity.

[0021] The avalanche photodetector detects an optical beat frequency signal containing a carrier envelope offset frequency and a repetition frequency. After passing through the power divider, it is split into two output signals. One output signal is input to the first RF conditioning circuit to extract the carrier envelope offset frequency, and the other output signal is input to the second RF conditioning circuit to extract the repetition frequency. The carrier envelope offset frequency and the repetition frequency are input together to the frequency and phase discrimination circuit to obtain their phase error signal. The phase error signal passes through the programmable proportional and programmable integrator in sequence to achieve amplification, attenuation, integration, and filtering. At the output, it is summed with the bias voltage generated by the programmable bias circuit. The programmable limiting circuit is used to limit the upper and lower limit voltages of the PI circuit output and, combined with the anti-saturation integrator circuit, generates an anti-saturation integration trigger signal. The integrator circuit stops integrating when it is critically saturated, thus preventing the integrator circuit from saturating in hardware. Finally, the output of the PI circuit is output to the external controlled system through the buffer circuit. The entire device sends instructions to the main control circuit through the host computer software. The main control circuit writes data into each module, thereby realizing parameter tuning of fully digital control.

[0022] Furthermore, the output signal of the avalanche photodetector is connected to the input terminal of the power divider. The power divider splits the input signal into two paths and outputs the first path. The first path is connected to the input terminal of the first radio frequency conditioning circuit to extract the carrier envelope offset frequency. The second path is connected to the input terminal of the second radio frequency conditioning circuit to extract the repetition frequency.

[0023] The output of the first radio frequency conditioning circuit is connected to the input of the frequency and phase discrimination circuit. The first radio frequency conditioning circuit includes a first bandpass filter, a fixed gain amplifier circuit, and a first voltage-controlled gain amplifier circuit in sequence. The first bandpass filter is used to filter out other frequency components that are not related to the carrier envelope offset frequency. The fixed gain amplifier circuit and the first voltage-controlled gain amplifier circuit are used to realize programmable amplification of the carrier envelope offset frequency.

[0024] The output of the second RF conditioning circuit is connected to the input of the frequency and phase discrimination circuit. The second conditioning circuit includes, in sequence, a π-type attenuation circuit, a second bandpass filter, a frequency divider circuit, a third bandpass filter, and a second voltage-controlled gain amplifier circuit. The π-type attenuation circuit is used to attenuate the power of the repetition frequency to prevent excessive input power from damaging the frequency divider. The second bandpass filter is used to filter out frequency components that are not related to the repetition frequency. The frequency divider circuit is used to divide the repetition frequency by eight. The third bandpass filter is used to filter the square wave output by the frequency divider circuit into a sine wave. The second voltage-controlled gain amplifier circuit is used to realize programmable amplification or attenuation of the repetition frequency.

[0025] Furthermore, the frequency and phase discrimination circuit includes a digital frequency and phase discriminator and an active loop filter. The frequency and phase discriminator is a voltage-type output with polarity control function; the active loop filter is a third-order loop used to filter out high-frequency components in the output signal.

[0026] Furthermore, the programmable proportional circuit includes an instrumentation amplifier circuit, a polarity control circuit, a programmable attenuation circuit, and a programmable amplification circuit. The instrumentation amplifier circuit is used for low-noise pre-amplification of the phase error signal, the polarity control circuit is used to change the positive and negative polarities of the error signal, and the programmable attenuation circuit and programmable amplification circuit are used to achieve high-precision attenuation and high-precision amplification of the error signal.

[0027] The instrument amplifier circuit has a gain of eight times, and the programmable attenuation circuit can achieve 65,536 levels of attenuation for the error signal. The programmable amplifier circuit consists of three fixed-gain amplifier circuits connected in series. The first-stage fixed-gain amplifier circuit has a gain of 32 times, the second-stage fixed-gain amplifier circuit has a gain of 8 times, and the third-stage fixed-gain amplifier circuit has a gain of 2 times. The three fixed-gain amplifier circuits can be turned on or off independently. When all three amplifier circuits are turned on, the gain is 512 times, and when all three are turned off, the gain is 1 time. The programmable attenuation circuit is implemented using a multiplier DAC and an IV converter circuit. The gain of the attenuation circuit is changed by controlling the output resistance of the multiplier DAC by writing digital codes. The multiplier DAC is 16 bits and can achieve 0 to 65,535 levels of attenuation. The larger the input code, the smaller the attenuation.

[0028] Furthermore, the programmable integrating circuit comprises two parts: a fast integrating circuit and a slow integrating circuit. The fast integrating circuit includes a first integrating circuit, a second integrating circuit, and a third integrating circuit; the slow integrating circuit includes a fourth integrating circuit. The first, second, and third integrating circuits are connected in series. Each of the first, second, and third integrating circuits is equipped with four sets of integrating capacitors for coarse adjustment of the unity-gain bandwidth. The bandwidth adjustment range of the three integrating circuits is 0.1Hz to 100kHz. The second and third integrating circuits can be independently turned on or off. The bandwidth adjustment range of the fourth integrating circuit is 0.001Hz to 100Hz. The first, second, third, and fourth integrating circuits can be independently reset.

[0029] The first, second, third, and fourth integrating circuits are all implemented using a multiplier DAC and an integrating circuit. The unity-gain bandwidth of the integrating circuit is changed by controlling the output resistance of the multiplier DAC by writing digital codes. The multiplier DAC is 16-bit, and the larger the input code, the lower the unity-gain bandwidth. The integrating circuit achieves fine adjustment of the unity-gain bandwidth by changing the input code.

[0030] Furthermore, the programmable bias circuit includes a first bias circuit and a second bias circuit, both with a bias adjustment range of -10V to 10V and a bias adjustment accuracy of 0.15mV.

[0031] Furthermore, the inverting summing circuit includes a first summing circuit and a second summing circuit. The first summing circuit is used to sum the outputs of the first integrating circuit, the second integrating circuit, the third integrating circuit, and the first bias circuit. The second summing circuit is used to sum the outputs of the fourth integrating circuit and the second bias circuit. Both the first summing circuit and the second summing circuit can independently control whether the output of the circuit participates in the summing.

[0032] Furthermore, the programmable limiting circuit includes a fast integral limiting circuit and a slow integral limiting circuit. Both the fast integral limiting circuit and the slow integral limiting circuit include an upper limit limiting circuit and a lower limit limiting circuit. The limiting range of the upper limit limiting circuit is 0V to 10V, and the limiting accuracy is 0.15mV. The limiting range of the lower limit limiting circuit is -10V to 0V, and the limiting accuracy is 0.15mV.

[0033] Furthermore, the anti-saturation integrator circuit includes a first comparator, a second comparator, a third comparator, and a multiplexer. The first comparator is used to determine the polarity of the current error signal, the second comparator is used to determine whether the PI circuit output has reached the upper limit voltage, and the third comparator is used to determine whether the PI circuit output has reached the lower limit voltage. The conditional integration strategy of the anti-saturation integrator circuit is as follows:

[0034] When the error signal is positive, if the PI circuit output reaches the upper limit voltage, the multiplexer is triggered to output an anti-saturation signal.

[0035] When the error signal is negative, if the PI circuit output reaches the lower limit voltage, the multiplexer is triggered to output an anti-saturation signal.

[0036] When the error signal polarity is positive, if the PI circuit output reaches the lower limit voltage, the multiplexer will not be triggered to output the anti-saturation signal.

[0037] When the error signal is negative, if the PI circuit output reaches the upper limit voltage, the multiplexer will not be triggered to output the anti-saturation signal.

[0038] When the PI circuit output does not reach either the upper or lower limit voltage, the multiplexer output anti-saturation signal will not be triggered regardless of the polarity of the error signal.

[0039] Furthermore, the output buffer circuit includes a first buffer circuit and a second buffer circuit. The first output buffer circuit is used for the output of the fast integration circuit; the second output buffer circuit is used for the output of the slow integration circuit. The output circuit adopts an optocoupler-isolated load.

[0040] Compared with the prior art, the present invention has the following advantages:

[0041] (1) Low latency. The structure of the analog PI circuit is adopted, which eliminates the latency problem caused by the calculation and processing in the digital frequency lock controller, thus ensuring that the controller can respond to the influence of external interference on the Ti:Sapphire oscillator in a timely manner.

[0042] (2) High locking stability. The multi-stage PI circuit structure with fast and slow dual feedback loops can effectively suppress high-frequency interference in the error signal and eliminate the slow drift of the carrier envelope offset frequency caused by changes in operating temperature and pump power.

[0043] (3) Wide bandwidth adjustment range. By adopting a strategy of coarse adjustment of the unity-gain integral bandwidth based on switching capacitors and fine adjustment of the unity-gain integral bandwidth by changing the input code, the bandwidth adjustment range of the PI control circuit can be from the mHz level to hundreds of kHz, which has a very high frequency resolution.

[0044] (4) Good safety. By adopting a limiting circuit and an anti-saturation integral circuit structure, and combining it with a conditional integral strategy, the saturation problem of the integrator can be effectively eliminated, avoiding serious overshoot caused by integrator saturation, reducing the risk of damage to the controlled object, and improving the reliability of the controller.

[0045] (5) Easy to operate and high parameter tuning accuracy. It adopts a fully digital control architecture. The host computer sends digital codes to the main controller to realize the setting of circuit parameters and the precise tuning of P and I parameters. Unlike traditional analog PI controllers, it does not require manual switching and adjustment. Moreover, the more bits the digital code has, the higher the parameter tuning accuracy. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the overall structure of the present invention;

[0047] Figure 2 This is a schematic diagram of the radio frequency conditioning circuit of the present invention;

[0048] Figure 3 This is a schematic diagram of the programmable proportional circuit of the present invention;

[0049] Figure 4 This is a schematic diagram of the programmable integrator circuit of the present invention;

[0050] Figure 5 This is a schematic diagram of the programmable limiting circuit and the anti-saturation integrating circuit of the present invention. Detailed Implementation

[0051] The following description, in conjunction with the accompanying drawings, further illustrates the fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device of the present invention.

[0052] like Figure 1As shown, a fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device includes an avalanche photodetector, a power divider, a first RF conditioning circuit, a second RF conditioning circuit, a frequency and phase detector circuit, a programmable proportional circuit, a programmable integrator circuit, a programmable bias circuit, an inverting summator circuit, a programmable limiting circuit, an anti-saturation integrator circuit, an output buffer circuit, a main control circuit, and a host computer. The avalanche photodetector detects an optical beat frequency signal containing the carrier envelope offset frequency and the repetition frequency. The output signal of the avalanche photodetector is connected to the input of the power divider, which splits the input into two output signals. The first output signal is input to the first RF conditioning circuit to extract the carrier envelope offset frequency; the second output signal is input to the second RF conditioning circuit to extract the repetition frequency. The carrier envelope offset frequency and the repetition frequency are both input to the frequency and phase detector circuit to obtain their phase error signal. The phase error signal is then passed through a programmable proportional circuit and a programmable integrator to achieve amplification, attenuation, integration, and filtering. A programmable bias circuit generates a bias voltage, which is then superimposed on the output of the PI circuit via an inverting summator. The output of the inverting summator is connected to the input of a programmable limiting circuit. The programmable limiting circuit limits the upper and lower voltage limits of the PI circuit output. An anti-saturation integrator circuit generates an anti-saturation integrator trigger signal, which causes the integrator to stop integrating at the critical saturation point, preventing saturation. The output of the limiting circuit is connected to the input of an output buffer circuit, which isolates the load and outputs a feedback signal to the controlled system. The main control circuit is used to set circuit parameters. The host computer communicates with the main control circuit to achieve fully digital control parameter tuning.

[0053] like Figure 2 The diagram shows the schematic of the radio frequency (RF) conditioning circuit of this invention. The RF conditioning circuit includes a first RF conditioning circuit and a second RF conditioning circuit. In this embodiment, the first RF conditioning circuit is used to extract the carrier envelope offset frequency, which is 8MHz, with a power of approximately -50dBm. This first RF conditioning circuit sequentially includes a first bandpass filter, a fixed-gain amplifier circuit, and a first voltage-controlled gain amplifier circuit. The passband range of the first bandpass filter is 6MHz to 12.4MHz, used to filter out other frequency components, including repetition frequencies. In the fixed-gain amplifier circuit, a high-speed amplifier with low noise and low harmonic distortion and a loss-compensation structure is selected to provide low-noise front-end amplification, achieving a signal-to-noise ratio higher than 30dB. The first voltage-controlled gain amplifier circuit is used to implement programmable amplification of the carrier envelope offset frequency. The voltage-controlled amplifier can provide a gain of 0dB to 40dB, with a control voltage between 0V and 2V. The control voltage is linear with the gain in decibels. The purpose of the voltage-controlled amplification is to adjust the amplitude of the carrier envelope offset frequency to meet the input requirements of the frequency and phase discrimination circuit.

[0054] In this embodiment, the second RF conditioning circuit is used to extract the repetition frequency. The repetition frequency is 64MHz, and the power is approximately 6dBm. The second conditioning circuit sequentially includes a π-type attenuator circuit, a second bandpass filter, a three-stage D flip-flop, a third bandpass filter, and a second voltage-controlled gain amplifier circuit. The π-type attenuator circuit is used to attenuate the power of the repetition frequency to prevent excessive input power from damaging the frequency divider; it can attenuate the repetition frequency by 6dB, the purpose of which is to reduce the amplitude of the repetition frequency to protect the frequency divider circuit. The passband range of the second bandpass filter is 58MHz to 68MHz, used to filter other frequency components, including the carrier envelope offset frequency. The three-stage D flip-flops form an octet frequency divider circuit, each stage of the D flip-flop can provide a 2-fold frequency divider, and the three-stage D flip-flops adopt a cascaded structure, which can realize the division of the 64MHz repetition frequency into 8MHz. The third bandpass filter circuit is used to filter out the high-order harmonic components in the frequency-divided signal, filtering the square wave output by the frequency divider circuit into a sine wave. The second voltage-controlled gain amplifier circuit can provide a gain of -20dB to 20dB, which is used to amplify or attenuate the repetition frequency after frequency division. The control voltage is between 0V and 2V, and the control voltage and gain are linear in decibels. The purpose of voltage-controlled amplification is to adjust the amplitude of the repetition frequency to meet the input requirements of the frequency discrimination and phase discrimination circuit.

[0055] In this embodiment, the frequency and phase discrimination circuit includes a digital frequency and phase discriminator and an active loop filter. The frequency and phase discriminator is a voltage-type output with polarity control function; the active loop filter is a third-order loop used to filter out high-frequency components in the output signal.

[0056] like Figure 3 The diagram shows the schematic of the programmable proportional circuit of this invention. In this embodiment, the programmable proportional circuit sequentially includes an instrumentation amplifier circuit, a polarity control circuit, a programmable attenuation circuit, and a three-stage fixed-gain amplifier circuit. The instrumentation amplifier circuit has an eight-fold fixed gain and is used for low-noise front-end amplification of the error signal. The polarity control circuit is used to change the polarity of the error signal. The polarity is controlled by an analog switch; when the switch is closed, the output and input polarities are the same; when the switch is open, the output and input polarities are opposite. The programmable attenuator consists of a multiplier DAC and an IV conversion circuit. The output current is changed by controlling the output impedance of the R-2R ladder resistor network inside the multiplier DAC through digital code. Different currents result in different output voltages after passing through the IV conversion circuit. The input code and output voltage of the multiplier DAC have the following relationship:

[0057]

[0058] Where D is the input code, R FBHere, is the internal feedback resistor of the multiplier DAC, and n is the number of bits in the multiplier DAC. The multiplier DAC has 16 bits, an attenuation coefficient between 0 and 1, an input and output voltage range between -15V and 15V, and a minimum attenuation accuracy of 0.3mV. The three-stage fixed-gain amplifier circuit has gains of 32x, 8x, and 2x respectively. Each stage of the amplifier circuit uses an independent analog switch to control the gain on or off. The three-stage fixed-gain amplifier circuit can provide seven gain values: 512x, 256x, 64x, 32x, 16x, 2x, and 1x.

[0059] like Figure 4 The diagram shows the schematic of the programmable integrator (PI) circuit of this invention. In this embodiment, the programmable PI circuit includes a fast PI circuit and a slow PI circuit. The fast PI circuit includes a first integrator circuit, a second integrator circuit, a third integrator circuit, a first bias circuit, and a first summing circuit. The inputs and outputs of the three integrator circuits satisfy the following relationship:

[0060]

[0061] Where C1 is the integrating capacitor and R1 is the integrating resistor of the integrator. In this implementation, each integrator stage uses four sets of capacitors: 1nF, 44nF, 550nF, and 4.7uF. R1 is implemented using the R-2R resistor network of a multiplication DAC. The unity-gain bandwidth of the three integrators is determined by C1 and R1, with the following relationship:

[0062]

[0063] The unity-gain bandwidth of the three integrators can be changed by adjusting C1 and R1. When switching different integrating capacitors, the unity-gain bandwidth of the integrators can be coarsely adjusted. When changing the input code of the multiplication DAC, the unity-gain bandwidth of the integrators can be finely adjusted. The bandwidth adjustment range of the three integrators is 1Hz to 100KHz. When the unity-gain bandwidth of the three integrators is set the same, it can provide an attenuation of -60dB / dec.

[0064] The first bias circuit generates the output bias for the fast integrator circuit. This output bias can be used to fine-tune the output voltage for precise locking. The voltage tuning accuracy of the first bias circuit is 0.15mV. The first summing circuit sums the outputs of the proportional circuit, the fast integrator circuit, and the first bias circuit to obtain the total output signal. The three outputs can be independently controlled to participate in the summation, resulting in the fast integrator output signal. The fast integrator circuit has an anti-saturation function. When the external anti-saturation integrator trigger signal is valid, the integrator enters the anti-saturation state. At this time, the input will switch to GND, and the integrator will maintain the current integral value.

[0065] The slow PI circuit includes a fourth integrator circuit, a second bias circuit, and a second summing circuit. The fourth integrator circuit has a larger integrating capacitor than the first integrator circuit, resulting in a long integration saturation time and a unity-gain bandwidth near 0Hz, effectively suppressing low-frequency interference in the controlled system. The fourth integrator circuit has four sets of integrating capacitors: 1uF, 33uF, 100uF, and 550uF. The unity-gain bandwidth of the slow integrator circuit is set to a minimum of 0.001Hz. The second bias circuit sets the output bias of the slow integrator circuit, with a voltage tuning accuracy of 0.15mV. The second summing circuit sums the outputs of the fourth integrator circuit and the second bias circuit to obtain the slow integrator output signal. The two outputs can be independently controlled to participate in the summation.

[0066] like Figure 5 The diagram shows the schematic of the limiting and anti-saturation circuit. In this implementation, the limiting and anti-saturation circuit can be divided into a fast PI limiting and anti-saturation output circuit and a slow PI limiting output circuit. The fast PI limiting and anti-saturation output circuit includes an upper limit limiting circuit, a lower limit limiting circuit, a first comparator, a second comparator, a third comparator, a multiplexer, and an output buffer circuit. The upper and lower limit limiting circuits adopt a bias limiting structure, with an upper limit voltage range of 0V to 10V and a lower limit voltage range of -10V to 0V, both with an adjustment accuracy of 0.15mV. The anti-saturation integration circuit is implemented using a three-stage comparator and a multiplexer. The first comparator is used to compare whether the polarity of the current input error signal is positive or negative. The second comparator is used to compare whether the current PI controller output exceeds the upper limit voltage. The third comparator is used to compare whether the current PI controller output is lower than the lower limit voltage. The three comparators are combined to form the following conditional integration strategy:

[0067] ① When the error signal is positive, if the PI controller output reaches the upper limit voltage, the integrator will saturate the upper limit if integration continues. Therefore, the anti-saturation trigger signal is set to be valid.

[0068] ② When the error signal is negative, if the PI controller output reaches the lower limit voltage, the integrator will saturate the lower limit if integration continues. Therefore, the anti-saturation trigger signal is set to be valid.

[0069] ③ When the error signal is positive, if the PI controller output reaches the lower limit voltage, the integrator will continue to integrate and exit saturation. Therefore, the anti-saturation integration trigger signal is set to invalid.

[0070] ④ When the error signal is negative, if the PI controller output reaches the upper limit voltage, the integrator will continue to integrate and exit saturation. Therefore, the anti-saturation integration trigger signal is set to invalid.

[0071] ⑤ When the PI controller output does not reach either the upper or lower limit, the integrator remains unchanged regardless of the polarity of the error signal, and the anti-saturation integral trigger signal is set to invalid.

[0072] The slow PI limiting circuit includes a second upper limit limiting circuit, a second lower limit limiting circuit, and a second output buffer circuit. The limiting voltage of the second upper limit limiting circuit is 0V to 10V, and the limiting voltage of the second lower limit limiting circuit is -10V to 0V, with an adjustment accuracy of 0.15mV. The first buffer circuit and the second buffer circuit are used to isolate the load and improve the load-carrying capacity of the entire device.

[0073] It can be seen that the output buffer circuit includes a first buffer circuit and a second buffer circuit. The first output buffer circuit is used for the output of the fast integration circuit; the second output buffer circuit is used for the output of the slow integration circuit. The output circuit uses an optocoupler to isolate the load.

[0074] In addition, in this embodiment, the programmable bias circuit includes a first bias circuit and a second bias circuit, both with a bias adjustment range of -10V to 10V and a bias adjustment accuracy of 0.15mV. The inverting summing circuit includes a first summing circuit and a second summing circuit. The first summing circuit is used to sum the outputs of the first integrator circuit, the second integrator circuit, the third integrator circuit, and the first bias circuit; the second summing circuit is used to sum the outputs of the fourth integrator circuit and the second bias circuit; both the first and second summing circuits can independently control whether the circuit outputs participate in the summation.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device, characterized in that, The device includes: Avalanche photodetectors are used to detect carrier envelope offset frequency and repetition frequency; A power divider is used to split the power of the avalanche photodetector output signal into two output signals. The first radio frequency conditioning circuit is used to filter and amplify the first output signal of the power divider in order to extract the carrier envelope offset frequency. The second RF conditioning circuit is used to filter, attenuate, divide, and amplify the second output signal of the power divider in order to extract the repetition frequency. Frequency and phase detector circuits are used to identify the phase difference between the repetition frequency and the carrier envelope offset frequency; Programmable scaling circuits are used to amplify or attenuate phase error signals; Programmable integrator circuit for filtering and integrating phase error signals; A programmable bias circuit is used to fine-tune the bias voltage in the output signal of a programmable integrator circuit. An inverting summator circuit is used to sum the outputs of proportional circuits, integrator circuits, and bias circuits. A programmable limiting circuit is used to set the upper and lower limits of the output voltage. An anti-saturation integrator circuit is used to generate an anti-saturation integrator trigger signal, which triggers the integrator circuit to stop integrating when it reaches critical saturation. Output buffer circuit is used to isolate the output load and enhance the circuit's load-carrying capacity; The programmable integrating circuit comprises a fast integrating circuit and a slow integrating circuit. The fast integrating circuit includes a first integrating circuit, a second integrating circuit, and a third integrating circuit. The slow integrating circuit includes a fourth integrating circuit. The first, second, and third integrating circuits are connected in series. Each of the first, second, and third integrating circuits is equipped with four sets of integrating capacitors for coarse adjustment of the unity-gain bandwidth. The bandwidth adjustment range of the three integrating circuits is 0.1Hz to 100kHz. The second and third integrating circuits can be independently turned on or off. The bandwidth adjustment range of the fourth integrating circuit is 0.001Hz to 100Hz. The first, second, third, and fourth integrating circuits can be independently reset.

2. The fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that, The output signal of the avalanche photodetector is connected to the input terminal of the power divider. The power divider splits the input signal into two paths and outputs the first path. The first path is connected to the input terminal of the first radio frequency conditioning circuit to extract the carrier envelope offset frequency. The second path is connected to the input terminal of the second radio frequency conditioning circuit to extract the repetition frequency. The output of the first radio frequency conditioning circuit is connected to the input of the frequency and phase discrimination circuit. The first radio frequency conditioning circuit includes a first bandpass filter, a fixed gain amplifier circuit, and a first voltage-controlled gain amplifier circuit in sequence. The first bandpass filter is used to filter out other frequency components that are not related to the carrier envelope offset frequency. The fixed gain amplifier circuit and the first voltage-controlled gain amplifier circuit are used to realize programmable amplification of the carrier envelope offset frequency. The output of the second RF conditioning circuit is connected to the input of the frequency and phase discrimination circuit. The second RF conditioning circuit includes, in sequence, a π-type attenuation circuit, a second bandpass filter, a frequency divider circuit, a third bandpass filter, and a second voltage-controlled gain amplifier circuit. The π-type attenuation circuit is used to attenuate the power of the repetition frequency to prevent excessive input power from damaging the frequency divider. The second bandpass filter is used to filter out frequency components that are not related to the repetition frequency. The frequency divider circuit is used to divide the repetition frequency by eight. The third bandpass filter is used to filter the square wave output by the frequency divider circuit into a sine wave. The second voltage-controlled gain amplifier circuit is used to realize programmable amplification or attenuation of the repetition frequency.

3. The fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that, The frequency and phase discrimination circuit includes a digital frequency and phase discriminator and an active loop filter. The frequency and phase discriminator is a voltage-type output with polarity control function. The active loop filter is a third-order loop used to filter out high-frequency components in the output signal.

4. The fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that, The programmable proportional circuit includes an instrumentation amplifier circuit, a polarity control circuit, a programmable attenuation circuit, and a programmable amplification circuit. The instrumentation amplifier circuit is used for low-noise pre-amplification of the phase error signal. The polarity control circuit is used to change the positive and negative polarities of the error signal. The programmable attenuation circuit and the programmable amplification circuit are used to achieve high-precision attenuation and high-precision amplification of the error signal.

5. The fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that, The programmable bias circuit includes a first bias circuit and a second bias circuit, both with a bias adjustment range of -10V to 10V and a bias adjustment accuracy of 0.15mV.

6. The fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 5, characterized in that, The inverting summing circuit includes a first summing circuit and a second summing circuit. The first summing circuit is used to sum the outputs of the first integrator circuit, the second integrator circuit, the third integrator circuit, and the first bias circuit. The second summing circuit is used to sum the outputs of the fourth integrator circuit and the second bias circuit. Both the first and second summing circuits can independently control whether the circuit outputs participate in the summing.

7. The fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that, The programmable limiting circuit includes a fast integral limiting circuit and a slow integral limiting circuit. Both the fast integral limiting circuit and the slow integral limiting circuit include an upper limit limiting circuit and a lower limit limiting circuit. The limiting range of the upper limit limiting circuit is 0V to 10V, and the limiting accuracy is 0.15mV. The limiting range of the lower limit limiting circuit is -10V to 0V, and the limiting accuracy is 0.15mV.

8. The fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that, The anti-saturation integrator circuit includes a first comparator, a second comparator, a third comparator, and a multiplexer. The first comparator is used to determine the polarity of the current error signal, the second comparator is used to determine whether the output of the programmable integrator circuit has reached the upper limit voltage, and the third comparator is used to determine whether the output of the programmable integrator circuit has reached the lower limit voltage. The conditional integration strategy of the anti-saturation integrator circuit is as follows: When the error signal is positive, if the output of the programmable integrator reaches the upper limit voltage, the multiplexer is triggered to output an anti-saturation signal. When the error signal is negative, if the output of the programmable integrator circuit reaches the lower limit voltage, the multiplexer is triggered to output an anti-saturation signal. When the error signal polarity is positive, if the output of the programmable integrator circuit reaches the lower limit voltage, the multiplexer will not be triggered to output the anti-saturation signal. When the error signal is negative, if the output of the programmable integrator circuit reaches the upper limit voltage, the multiplexer will not be triggered to output the anti-saturation signal. When the output of the programmable integrator circuit does not reach either the upper or lower limit voltage, the multiplexer output anti-saturation signal will not be triggered regardless of the polarity of the error signal.

9. A fully digitally controlled programmable Ti:sapphire femtosecond oscillator carrier envelope offset frequency locking device according to claim 1, characterized in that, The output buffer circuit includes a first buffer circuit and a second buffer circuit. The first buffer circuit is used for the output of the fast integration circuit, and the second buffer circuit is used for the output of the slow integration circuit. The output circuit uses an optocoupler to isolate the load.

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