SiC MOSFET short-circuit protection circuit capable of being integrated on chip and chip

Abstract

The invention discloses an on-chip integrated SiC MOSFET short-circuit protection circuit and chip, and the protection circuit comprises a logic control unit which is used for processing an input signal Vin and a short-circuit fault signal, the output end of the logic control unit is connected with a drive circuit, and the logic control unit inputs a fault signal to the drive circuit when a short-circuit fault occurs; the driving circuit is used for driving the SiC MOSFET; the short-circuit protection circuit is used for sending a short-circuit fault signal to the logic control unit when a short-circuit fault occurs; the Ids detection circuit is used for detecting the value of drain-source current Ids of the SiC MOSFET and inputting a voltage in direct proportion to the drain-source current Ids to the short-circuit protection circuit; the reset circuit is used for resetting the short-circuit protection circuit completing the short-circuit protection action; two comparators are added in the short-circuit protection circuit, and different threshold voltages are set to judge whether HSF or FUL faults occur or not. The method can be widely applied to the technical field of short-circuit protection.

Description

Technical Field

[0001] The present invention relates to the technical field of short-circuit protection of power devices, and in particular to a SiC MOSFET short-circuit protection circuit and a chip that can be integrated on a chip. Background Art

[0002] In recent years, SiC MOSFET has been widely used in motor drive, new energy vehicles, photovoltaic power generation and other fields due to its high voltage resistance, high temperature resistance and low conduction loss. The drain-source current of SiC MOSFET has an unsaturated characteristic and will withstand a very high current in a short-circuit state. In order to ensure the high reliability of SiC MOSFET, a short-circuit protection circuit for SiC MOSFET is very important.

[0003] At present, short-circuit protection circuits for SiC MOSFET are mainly divided into three categories. The first category is the desaturation overcurrent detection method, which detects the drain-source current I of the SiC MOSFET. ds and drain-source voltage V ds To judge the short circuit fault, when a short circuit fault occurs, I ds will rise rapidly and V ds Rise to the bus voltage, by detecting I ds and V ds It can determine whether HSF or FUL occurs, but the response time of this method is slow because it needs to set the leading edge blanking time. The second type is based on the source inductance detection method, which detects I by connecting a sampling resistor and a sampling capacitor in parallel with the source parasitic inductance. ds This method is the easiest to integrate and has a faster protection speed. The third type is the gate voltage detection method. When HSF occurs, the Miller platform of the gate-source voltage disappears, and when FUL occurs, a voltage spike will appear in the gate-source voltage. By detecting V GS The state of the short circuit fault can be judged, but this method has low detection accuracy and is difficult to integrate. Summary of the invention

[0004] In order to solve at least one of the technical problems existing in the prior art to a certain extent, the present invention aims to provide a fast, reliable, and easily on-chip integrated SiC MOSFET short-circuit protection circuit and chip.

[0005] The technical solution adopted by the present invention is:

[0006] A SiC MOSFET short-circuit protection circuit that can be integrated on a chip, comprising:

[0007] A logic control unit, used for processing an input signal Vin and a short-circuit fault signal, wherein an output end thereof is connected to a drive circuit, and a fault signal is input to the drive circuit when a short-circuit fault occurs; a first input end of the logic control unit is connected to an input signal Vin, a second input end is connected to an output end of a short-circuit protection circuit, and a third input end is connected to an output end of a reset circuit;

[0008] A drive circuit, used to drive the SiC MOSFET; the input end of the drive circuit is connected to the output end of the logic control unit, and the output end is connected to the gate of the SiC MOSFET;

[0009] The short-circuit protection circuit is used to send a short-circuit fault signal to the logic control unit when a short-circuit fault occurs; the first input terminal of the short-circuit protection circuit is connected to I ds The output end of the detection circuit is connected, and the output end is connected to the logic control unit; wherein the short-circuit protection circuit is provided with two comparators, which judge whether a HSF fault or a FUL fault occurs by combining a preset threshold voltage;

[0010] I ds Detection circuit for detecting the drain-source current I of SiC MOSFET ds The value of the drain-source current I ds proportional to the voltage; the I ds The input terminal of the detection circuit is connected to the source of the SiC MOSFET;

[0011] The reset circuit is used to reset the short-circuit protection circuit that completes the short-circuit protection action; the input end of the reset circuit is connected to the input signal Vin, and the output end is connected to the third input end of the logic control unit.

[0012] Further, the logic control unit includes a first SR latch m1, a second inverter inv2, and a first AND gate and1;

[0013] The R input terminal of the first SR latch m1 is connected to the output terminal of the reset circuit, and the S input terminal is connected to the output terminal of the short-circuit protection circuit; the input terminal of the second inverter inv2 is connected to the Q output terminal of the latch m1, and the output terminal is connected to an input terminal of the first AND gate and1; the other input terminal of the first AND gate and1 is connected to the input signal Vin, and the output terminal of the first AND gate and1 is connected as the output terminal of the logic control unit.

[0014] Further, the driving circuit includes a third inverter inv3, a first buffer buffer1, a second buffer buffer2, a plurality of parallel-connected PLDMOS and a plurality of parallel-connected NLDMOS;

[0015] The input end of the third inverter inv3 is connected to the output end of the logic control unit, and the output end is connected to the input end of the first buffer buffer1 and the input end of the second buffer buffer2; the output end of the first buffer buffer1 is connected to the gates of multiple parallel PLDMOS; the output end of the second buffer buffer2 is connected to the gates of multiple parallel NLDMOS; the source of the parallel NLDMOS is connected to the ground GND, and the drain is connected to the drain of the parallel PLDMOS; the source of the parallel PLDMOS is connected to the power supply VDDH; the drain of the NLDMOS and the drain of the PLDMOS are connected as the output end of the driving short circuit, and are connected to the gate of the SiC MOSFET.

[0016] Furthermore, the I ds The detection circuit includes a first diode D1, a first capacitor C1, a first resistor R1, a second diode D2, and a second resistor R2;

[0017] The cathode of the first diode D1 is connected to the ground GND, and the anode is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the cathode of the second diode D2; the anode of the diode D2 is connected to the source of the SiC MOSFET; the first capacitor C1 is connected in parallel with the first diode D1; and the second resistor R2 is connected in parallel with the second diode D2.

[0018] Furthermore, the short circuit protection circuit includes a first comparator com1, a second comparator com2, a third comparator com3, a first OR gate or1, a first NAND gate nand1 and a level shifter level shifter;

[0019] The non-inverting input terminal of the first comparator com1 is connected to I ds The output voltage Vo of the detection circuit, the inverting input terminal is connected to the first threshold voltage Vref1; the non-inverting input terminal of the second comparator com2 is connected to the voltage V div , the inverting input terminal is connected to the second threshold voltage Vref2, where the voltage V div The non-inverting input terminal of the third comparator com1 is connected to I ds The output voltage Vo of the detection circuit, the inverting input terminal is connected to the third threshold voltage Vref3;

[0020] The two input ends of the first OR gate or1 are respectively connected to the output end of the second comparator com2 and the output end of the third comparator com3, and the output end is connected to one input end of the first NAND gate nand1; the other input end of the first NAND gate nand1 is connected to the output end of the first comparator com1, and the output end is connected to the input end of the level shifter level shifter; the output end of the level shifter is connected to the S input end of the latch m1.

[0021] Furthermore, the voltage V div The sampling circuit includes a second capacitor C2 and a third capacitor C3, wherein the second capacitor C2 and the third capacitor C3 are connected in series between the drain and the source of the SiC MOSFET, and a voltage V is obtained at the connection point between the second capacitor C2 and the third capacitor C3. div .

[0022] Further, the reset circuit includes a first inverter inv1, a first NOR gate nor1;

[0023] The input end of the first inverter inv1 is connected to the input signal Vin, and the output end is connected to one input end of the first NOR gate nor1; the other input end of the first NOR gate nor1 is connected to the input signal Vin, and the output end is connected to the R input end of the latch m1.

[0024] Furthermore, the SiC MOSFET short-circuit protection circuit also includes a digital isolator;

[0025] The digital isolator is used to transmit and convert the digital signal at the input end, and the output end thereof outputs the input signal Vin.

[0026] Furthermore, the SiC MOSFET short-circuit protection circuit is integrated using a BCD process.

[0027] Another technical solution adopted by the present invention is:

[0028] A chip includes the above-mentioned on-chip integrated SiC MOSFET short-circuit protection circuit.

[0029] The beneficial effects of the present invention are as follows: the present invention improves the source parasitic inductance detection method, adds two comparators in the short circuit protection circuit, and sets different threshold voltages to determine whether a HSF or FUL fault occurs. In addition, by reasonably setting different threshold voltages, the protection speed of HSF and FUL can be improved, and the values ​​required for capacitor C1, resistor R1 and resistor R2 can be greatly reduced, so that the present invention has the characteristics of fast protection and easy integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the embodiments of the present invention or the drawings of related technical solutions in the prior art are introduced below. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 4 is a principle block diagram of a SiC MOSFET short-circuit protection circuit in an embodiment of the present invention.

[0032] Figure 2 4 is a circuit schematic diagram of a SiC MOSFET short-circuit protection circuit in an embodiment of the present invention.

[0033] Figure 3 This is the output waveform of the SiC MOSFET in the embodiment of the present invention when it works normally under the double pulse test.

[0034] Figure 4 1 is an output waveform of HSF when the SiC MOSFET is not short-circuit protected in the embodiment of the present invention.

[0035] Figure 5 1 is an output waveform of FUL when the SiC MOSFET is not short-circuited in the embodiment of the present invention.

[0036] Figure 6 FIG. 1 is a partial output waveform of HSF generated when the SiC MOSFET in an embodiment of the present invention adopts the short-circuit protection circuit of the present invention. FIG.

[0037] Figure 7 FIG. 1 is a partial output waveform of FUL after the SiC MOSFET in the embodiment of the present invention adopts the short-circuit protection circuit of the present invention. FIG. DETAILED DESCRIPTION

[0038] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limitations of the present invention. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0039] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0040] In the description of the present invention, the meaning of "several" is one or more, the meaning of "more" is two or more, and the meanings of "greater than", "less than", "exceed" and the like are understood as not including the number itself, and the meanings of "above", "below", "within" and the like are understood as including the number itself. If there is a description of the first and the second, it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features. In addition, "and / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship.

[0041] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0042] Terminology explanation:

[0043] HSF: refers to the fault caused when the switch tube is turned on when the load is short-circuited.

[0044] FUL: refers to a fault caused by a sudden short circuit of the load when the switch tube is fully turned on.

[0045] BCD process: BCD refers to Bipolar, CMOS, and DMOS. BCD process means that the same process includes these three processes: Bipolar, CMOS, and DMOS.

[0046] like Figure 1 As shown, this embodiment provides a SiC MOSFET short-circuit protection circuit that can be integrated on a chip, and its structure includes a logic control unit, a drive circuit, a reset circuit, a short-circuit protection circuit, an I ds Detection circuit;

[0047] A logic control unit, used for processing an input signal Vin and a short-circuit fault signal, wherein an output end thereof is connected to a drive circuit, and a fault signal is input to the drive circuit when a short-circuit fault occurs; a first input end of the logic control unit is connected to an input signal Vin, a second input end is connected to an output end of a short-circuit protection circuit, and a third input end is connected to an output end of a reset circuit;

[0048] A drive circuit, used to drive the SiC MOSFET; the input end of the drive circuit is connected to the output end of the logic control unit, and the output end is connected to the gate of the SiC MOSFET;

[0049] The short-circuit protection circuit is used to send a short-circuit fault signal to the logic control unit when a short-circuit fault occurs; the first input terminal of the short-circuit protection circuit is connected to I ds The output end of the detection circuit is connected, and the output end is connected to the logic control unit; wherein the short-circuit protection circuit is provided with two comparators, which judge whether a HSF fault or a FUL fault occurs by combining a preset threshold voltage;

[0050] I ds Detection circuit for detecting the drain-source current I of SiC MOSFET ds The value of the drain-source current I ds proportional to the voltage; the I ds The input terminal of the detection circuit is connected to the source of the SiC MOSFET;

[0051] The reset circuit is used to reset the short-circuit protection circuit that completes the short-circuit protection action; the input end of the reset circuit is connected to the input signal Vin, and the output end is connected to the third input end of the logic control unit.

[0052] See also Figure 2 , in some embodiments, the logic control unit includes a first SR latch m1, a second inverter inv2, and a first AND gate and1;

[0053] The R input terminal of the first SR latch m1 is connected to the output terminal of the reset circuit, and the S input terminal is connected to the output terminal of the short-circuit protection circuit; the input terminal of the second inverter inv2 is connected to the Q output terminal of the latch m1, and the output terminal is connected to an input terminal of the first AND gate and1; the other input terminal of the first AND gate and1 is connected to the input signal Vin, and the output terminal of the first AND gate and1 is connected as the output terminal of the logic control unit.

[0054] See also Figure 2 , in some embodiments, the driving circuit includes a third inverter inv3, a first buffer buffer1, a second buffer buffer2, a plurality of parallel-connected PLDMOS and a plurality of parallel-connected NLDMOS;

[0055] The input end of the third inverter inv3 is connected to the output end of the logic control unit, and the output end is connected to the input end of the first buffer buffer1 and the input end of the second buffer buffer2; the output end of the first buffer buffer1 is connected to the gates of multiple parallel PLDMOS; the output end of the second buffer buffer2 is connected to the gates of multiple parallel NLDMOS; the source of the parallel NLDMOS is connected to the ground GND, and the drain is connected to the drain of the parallel PLDMOS; the source of the parallel PLDMOS is connected to the power supply VDDH; the drain of the NLDMOS and the drain of the PLDMOS are connected as the output end of the driving short circuit, and are connected to the gate of the SiC MOSFET.

[0056] See also Figure 2 In some embodiments, the I ds The detection circuit includes a first diode D1, a first capacitor C1, a first resistor R1, a second diode D2, and a second resistor R2;

[0057] The cathode of the first diode D1 is connected to the ground GND, and the anode is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the cathode of the second diode D2; the anode of the diode D2 is connected to the source of the SiC MOSFET; the first capacitor C1 is connected in parallel with the first diode D1; and the second resistor R2 is connected in parallel with the second diode D2.

[0058] See also Figure 2 In some embodiments, the short circuit protection circuit includes a first comparator com1, a second comparator com2, a third comparator com3, a first OR gate or1, a first NAND gate nand1 and a level shifter level shifter;

[0059] The non-inverting input terminal of the first comparator com1 is connected to I ds The output voltage Vo of the detection circuit, the inverting input terminal is connected to the first threshold voltage Vref1; the non-inverting input terminal of the second comparator com2 is connected to the voltage V div , the inverting input terminal is connected to the second threshold voltage Vref2, where the voltage V div The non-inverting input terminal of the third comparator com1 is connected to I ds The output voltage Vo of the detection circuit, the inverting input terminal is connected to the third threshold voltage Vref3;

[0060] The two input ends of the first OR gate or1 are respectively connected to the output end of the second comparator com2 and the output end of the third comparator com3, and the output end is connected to one input end of the first NAND gate nand1; the other input end of the first NAND gate nand1 is connected to the output end of the first comparator com1, and the output end is connected to the input end of the level shifter level shifter; the output end of the level shifter is connected to the S input end of the latch m1.

[0061] Optionally, the voltage V div The sampling circuit includes a second capacitor C2 and a third capacitor C3, wherein the second capacitor C2 and the third capacitor C3 are connected in series between the drain and the source of the SiC MOSFET, and a voltage V is obtained at the connection point between the second capacitor C2 and the third capacitor C3. div .

[0062] See also Figure 2 , in some embodiments, the reset circuit includes a first inverter inv1, a first NOR gate nor1;

[0063] The input end of the first inverter inv1 is connected to the input signal Vin, and the output end is connected to one input end of the first NOR gate nor1; the other input end of the first NOR gate nor1 is connected to the input signal Vin, and the output end is connected to the R input end of the latch m1.

[0064] See also Figure 2 As an optional implementation, the SiC MOSFET short-circuit protection circuit further includes a digital isolator; the digital isolator is used to transmit and convert the digital signal at the input end, and the output end thereof outputs the input signal Vin.

[0065] The above circuit is explained in detail below with reference to the accompanying drawings and specific embodiments.

[0066] (1) Working mode of the logic control unit:

[0067] When SiC MOSFET is working normally, the overcurrent fault signal I oc is low level, and the short-circuit fault signal Fault after being latched by the m1 register is also low level, so it does not affect the driving signal of the SiC MOSFET gate. oc It will become a high level pulse, and after passing through the SR latch, the signal Fault becomes a high level. After passing through the inverter inv2, Fault is ANDed with the output Vin of the digital isolator, and finally generates a low output level.

[0068] (2) Working mode of driving circuit:

[0069] The output of the logic control unit is inverted by inverter inv3 and connected to the input terminals of buffer1 and buffer2 at the same time. Buffer1 and buffer2 are voltage buffers for driving parallel PLDMOS and parallel NLDMOS respectively. In this example, the number of parallel PLDMOS and NLDMOS used to drive SiC MOSFET is large, and the aspect ratio is also large, so buffer1 and buffer2 have strong current driving capabilities.

[0070] (3)I ds Working mode of the detection circuit:

[0071] When the SiC MOSFET is turned on, I ds Rising, an induced voltage Vss will be generated at the power source due to the existence of source parasitic inductance, where Vss = dI ds / dt, Vss is negative relative to the ground GND, capacitor C1, resistor R1, resistor R2 form an RC integrator to output the integrated voltage Vo, where Vo = ∫ {Vss / (R1 + R2) C1} dt, so by detecting Vo, it is immediately determined whether a short circuit fault occurs. When the SiC MOSFET is turned on normally, I ds At a normal level, Vo is below the threshold voltage; when the SiC MOSFET fails during turn-on, I ds It rises rapidly and Vo will exceed the threshold voltage. When the SiC MOSFET is turned on normally without HSF fault, Vss changes from a negative value to GND, and Vo discharges back to GND through D2. When FUL fault occurs again, Vo will exceed the set threshold voltage.

[0072] (4) Working mode of short circuit protection circuit:

[0073] The input terminals of the short circuit protection circuit are respectively connected to I ds The output end of the detection circuit is connected to the output end of the reset circuit, and the output end is connected to the logic control unit, which is used to send a fault signal to the logic control unit when a short circuit fault occurs. The short circuit protection circuit includes a second capacitor C2 and a third capacitor C3, and the divided voltage V of the capacitor C2 and the capacitor C3 is div Connect to the non-inverting input of com2.

[0074] When the SiC MOSFET is turned on normally, Vo does not exceed the first threshold voltage Vref1, and Ioc outputs a low level; when the SiC MOSFET has an HSF fault, Vo exceeds the first threshold voltage Vref1, com1 outputs a low level, nand1 outputs a high level, and after conversion by the level shifter, a high level pulse Ioc is output; when the SiC MOSFET is turned on normally and no HSF fault occurs, Vo returns to the normal level GND, and the voltage divider V of C2 and C3 div When the voltage drops below the set second threshold voltage Vref2, com2 outputs a low level, which means that the SiC MOSFET has been turned on normally. Com3 is used to determine whether a FUL fault occurs subsequently. The third threshold voltage Vref3 is set smaller, so protection action can be taken more quickly when a FUL fault occurs.

[0075] See also Figure 3 , Figure 3 The figure shows the output waveform of SiC MOSFET when it works normally under the double pulse test. The rated continuous current of SiC MOSFET used in this example is 32A, so this example is tested with a power supply voltage of 800V and a drain-source current of 32A as the standard.

[0076] See also Figure 4 , Figure 4 This is the output waveform of HSF when SiC MOSFET is not short-circuited. In this example design, HSF fault will occur at 22us. It can be seen that when the protection circuit is not used, the short-circuit peak current is as high as 188A and the drain-source voltage is maintained at 477V; see Figure 5 , Figure 5 This is the output waveform of FUL when the SiC MOSFET is not short-circuit protected. The FUL fault occurs at 23us. At this time, the short-circuit peak current is 189A and the drain-source voltage is maintained at about 481V.

[0077] See also Figure 6 , Figure 6 The local output waveform of HSF after the short-circuit protection circuit of the present invention is adopted for SiC MOSFET. The results show that the short-circuit peak current is suppressed to 107A after the protection circuit is adopted, and the short-circuit protection time is only 31ns; see Figure 7 , Figure 7 The local output waveform of FUL after the short-circuit protection circuit of the present invention is used for SiC MOSFET. The results show that the short-circuit peak current is suppressed to 133A after the protection circuit is used, and the short-circuit protection time is only 40ns. Therefore, no matter what kind of short-circuit fault occurs, the short-circuit protection circuit of the present invention can quickly shut down the SiC MOSFET to ensure the safe operation of the SiC MOSFET.

[0078] Furthermore, in this example, no capacitors with excessively large capacitance are used, and no inductors are required, so the entire chip can be integrated using the BCD process, greatly improving practicality.

[0079] In summary, the present invention provides a short-circuit protection circuit for SiC MOSFET that can be integrated on-chip, which can respond faster to short-circuit fault events, quickly shut down SiC MOSFET, effectively protect SiC MOSFET, reduce power consumption when short circuit occurs, and improve device reliability; at the same time, it also has the characteristics of easy integration and greater practical value. Specifically, the present invention can suppress the peak current to 107A when a hard switch short-circuit fault (HSF) occurs in SiC MOSFET, and suppress the peak current to 133A when a load short-circuit fault (FUL) occurs; the short-circuit protection time for HSF and FUL is 31ns and 40ns respectively.

[0080] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0081] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0082] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A SiC MOSFET short-circuit protection circuit that can be integrated on-chip, characterized in that: include: A logic control unit is used to process the input signal Vin and the short-circuit fault signal, and its output end is connected to the drive circuit. When a short-circuit fault occurs, a fault signal is input to the drive circuit; The first input terminal of the logic control unit is connected to the input signal Vin, the second input terminal is connected to the output terminal of the short-circuit protection circuit, and the third input terminal is connected to the output terminal of the reset circuit; A driving circuit for driving SiC MOSFET; The input end of the driving circuit is connected to the output end of the logic control unit, and the output end is connected to the gate of the SiC MOSFET; The short-circuit protection circuit is used to send a short-circuit fault signal to the logic control unit when a short-circuit fault occurs; the first input terminal of the short-circuit protection circuit is connected to I ds The output end of the detection circuit is connected, and the output end is connected to the logic control unit; wherein the short-circuit protection circuit is provided with two comparators, which judge whether a HSF fault or a FUL fault occurs by combining a preset threshold voltage; I ds Detection circuit for detecting the drain-source current I of SiC MOSFET ds The value of the drain-source current I ds proportional to the voltage; the I ds The input terminal of the detection circuit is connected to the source of the SiC MOSFET; The reset circuit is used to reset the short-circuit protection circuit after completing the short-circuit protection action; the input end of the reset circuit is connected to the input signal Vin, and the output end is connected to the logic control unit.

2. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that: The logic control unit includes a first SR latch m1, a second inverter inv2, and a first AND gate and1; The R input terminal of the first SR latch m1 is connected to the output terminal of the reset circuit, and the S input terminal is connected to the output terminal of the short-circuit protection circuit; the input terminal of the second inverter inv2 is connected to the Q output terminal of the latch m1, and the output terminal is connected to an input terminal of the first AND gate and1; the other input terminal of the first AND gate and1 is connected to the input signal Vin, and the output terminal of the first AND gate and1 is connected as the output terminal of the logic control unit.

3. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that: The driving circuit includes a third inverter inv3, a first buffer buffer1, a second buffer buffer2, a plurality of parallel-connected PLDMOS and a plurality of parallel-connected NLDMOS; The input end of the third inverter inv3 is connected to the output end of the logic control unit, and the output end is connected to the input end of the first buffer buffer1 and the input end of the second buffer buffer2; the output end of the first buffer buffer1 is connected to the gates of multiple parallel PLDMOS; the output end of the second buffer buffer2 is connected to the gates of multiple parallel NLDMOS; the source of the parallel NLDMOS is connected to the ground GND, and the drain is connected to the drain of the parallel PLDMOS; the source of the parallel PLDMOS is connected to the power supply VDDH; the drain of the NLDMOS and the drain of the PLDMOS are connected as the output end of the driving short circuit, and are connected to the gate of the SiC MOSFET.

4. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that: I ds The detection circuit includes a first diode D1, a first capacitor C1, a first resistor R1, a second diode D2, and a second resistor R2; The cathode of the first diode D1 is connected to the ground GND, and the anode is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the cathode of the second diode D2; the anode of the diode D2 is connected to the source of the SiC MOSFET; the first capacitor C1 is connected in parallel with the first diode D1; and the second resistor R2 is connected in parallel with the second diode D2.

5. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that: The short circuit protection circuit comprises a first comparator com1, a second comparator com2, a third comparator com3, a first OR gate or1, a first NAND gate nand1 and a level shifter level shifter; The non-inverting input terminal of the first comparator com1 is connected to I ds The output voltage Vo of the detection circuit, the inverting input terminal is connected to the first threshold voltage Vref1; the non-inverting input terminal of the second comparator com2 is connected to the voltage V div , the inverting input terminal is connected to the second threshold voltage Vref2, where the voltage V div The non-inverting input terminal of the third comparator com1 is connected to I ds The output voltage Vo of the detection circuit, the inverting input terminal is connected to the third threshold voltage Vref3; The two input ends of the first OR gate or1 are respectively connected to the output end of the second comparator com2 and the output end of the third comparator com3, and the output end is connected to one input end of the first NAND gate nand1; the other input end of the first NAND gate nand1 is connected to the output end of the first comparator com1, and the output end is connected to the input end of the level shifter level shifter; the output end of the level shifter is connected to the S input end of the latch m1.

6. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 5, characterized in that: The voltage V div The sampling circuit includes a second capacitor C2 and a third capacitor C3, wherein the second capacitor C2 and the third capacitor C3 are connected in series between the drain and the source of the SiC MOSFET, and a voltage V is obtained at the connection point between the second capacitor C2 and the third capacitor C3. div .

7. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that: The reset circuit comprises a first inverter inv1 and a first NOR gate nor1; The input end of the first inverter inv1 is connected to the input signal Vin, and the output end is connected to one input end of the first NOR gate nor1; the other input end of the first NOR gate nor1 is connected to the input signal Vin, and the output end is connected to the R input end of the latch m1.

8. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that: The SiC MOSFET short-circuit protection circuit also includes a digital isolator; The digital isolator is used to transmit and convert the digital signal at the input end, and the output end thereof outputs the input signal Vin.

9. A SiC MOSFET short-circuit protection circuit capable of being integrated on a chip according to any one of claims 1 to 8, characterized in that: The SiC MOSFET short-circuit protection circuit is integrated using a BCD process.

10. A chip, characterized in that: It comprises a SiCMOSFET short-circuit protection circuit that can be integrated on a chip as described in any one of claims 1 to 9.

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