Modular static synchronous compensator and super-capacitor direct voltage synchronous network control method thereof

Abstract

Modular static synchronous compensator and super-capacitor direct voltage synchronous network control method thereof, each phase comprising n H-bridge circuit modules and n super-capacitor clusters, further comprising n DC / DC modules, the H-bridge circuit modules and the DC / DC modules being connected in series to form two-stage power modules; the H-bridge circuit module control comprising a super-capacitor direct voltage power synchronous ring, a virtual excitation ring, a virtual impedance and current limiting control ring, an inner current ring and a control mode selection; the DC / DC module control comprising a direct current voltage closed loop and a direct current closed loop; the application adds DC / DC conversion between the conventional H-bridge module and the super-capacitor to realize wide-range discharge of the super-capacitor and improve energy utilization; the control strategy is combined to realize interface control of alternating current reactive power and direct current active power, completely filter out double-frequency power flowing into the super-capacitor while maintaining constant direct current voltage, and greatly prolong the service life of the super-capacitor.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power electronics and phase modifier, and in particular, relates to a static synchronous phase modifier module level topology and a network construction control method thereof based on super capacitor direct voltage synchronous. BACKGROUND

[0002] With the increasing proportion of power electronic converters in power systems, the physical form of new power systems gradually changes from a mechanical electromagnetic system dominated by synchronous generators to a hybrid system of power semiconductors and ferromagnetic elements jointly dominated by power electronic devices and synchronous machines. With the increasing proportion of power electronic converter devices in power systems, the system inertia will be greatly reduced, the system frequency index will be deteriorated, and in severe cases, frequency stability accidents will occur. In weak system and low physical inertia power grids, the grid-connection safety of new energy is seriously affected, resulting in a significant impact on the accommodation capacity of new energy. The synchronous phase modifier has unique advantages in improving inertia support and improving the frequency and voltage characteristics of new energy, and has received extensive attention in the past decade. However, the current synchronous phase modifier has problems such as high price, large floor area, complex system, and difficult operation and maintenance, which need to be solved. At present, the static synchronous phase modifier composed of cascaded H-bridge static var compensator (SVG) and super capacitor energy storage element combined with network control strategy can realize the functional replacement of the synchronous phase modifier, and has the characteristics of small floor area, simple system operation and maintenance, and relatively low cost. However, since the SVG needs enough H-bridge power modules to support the AC side voltage, the DC side voltage of the power module is adjusted in a narrow range, i.e. the super capacitor discharge voltage range connected to the DC side of the module is narrow, resulting in low energy utilization rate of the super capacitor. In order to release enough energy to support the inertia of the power grid, the static synchronous phase modifier of the conventional SVG topology is configured with a large number of super capacitors, which has the problems of large system volume and high cost; at the same time, the single-stage topology control has low freedom degree, and can only reduce the double-frequency power flowing into the super capacitor by increasing the passive filter, which cannot completely filter out and will cause the temperature of the super capacitor to rise and the service life to be reduced. SUMMARY

[0003] In order to solve the problems in the prior art, the present application provides a modular static synchronous phase modifier and a super capacitor direct voltage synchronous network construction control method, which adds a DC / DC converter between the conventional H-bridge module and the super capacitor to realize wide-range discharge of the super capacitor and improve the energy utilization rate; combined with the control strategy, the AC reactive power and the DC side active power are controlled to interface, so that the double-frequency power flowing into the super capacitor is completely filtered out while maintaining the constant DC voltage, greatly prolonging the service life of the super capacitor.

[0004] The present application adopts the following technical solutions.

[0005] The application provides a modular static synchronous compensator, each phase comprising n H-bridge circuit modules and n super capacitor clusters, the AC side of each H-bridge circuit module being cascaded, the DC side of each H-bridge circuit module being connected to a super capacitor cluster,

[0006] The H-bridge circuit module comprises a first bypass switch, an H-bridge circuit, a first support capacitor, a first voltage-sharing resistor set and a first DC fuse, wherein the first bypass switch is connected in parallel between the first AC end and the second AC end of the H-bridge circuit module, the first support capacitor and the first voltage-sharing resistor set are connected in parallel between the DC positive pole and the DC negative pole of the H-bridge circuit module, and the DC fuse is connected in series on the DC positive pole line.

[0007] The modular static synchronous compensator further comprises n DC / DC modules, the H-bridge circuit module and the DC / DC module being connected in series to form a two-stage power module, each DC / DC module comprising a second support capacitor, a second voltage-sharing resistor set, m half-bridge circuits, m filter inductors, a capacitor-side main contactor, a battery-side pre-charging contactor, a pre-charging resistor, a second DC fuse and a Hall current sensor, wherein the second support capacitor is connected in parallel between the DC positive pole and the DC negative pole of the H-bridge circuit module, each half-bridge circuit comprises two switching devices and an anti-parallel diode connected to the switching devices, the high-voltage DC side of each half-bridge circuit is connected to the DC positive pole and the DC negative pole of the H-bridge circuit module, the midpoint of each half-bridge circuit is connected to the first DC positive pole of the DC / DC module through the filter inductor, and the second voltage-sharing resistor set is connected in parallel between the first DC positive pole and the DC negative pole of the DC / DC module; one end of the capacitor-side main contactor is connected to the first DC positive pole of the DC / DC module, and the other end is connected to the second DC positive pole of the DC / DC module, and the capacitor-side main contactor is used for connecting and disconnecting the connection between the DC / DC module and the super capacitor cluster; one end of the pre-charging resistor is connected to the first DC positive pole of the DC / DC module, and the other end is connected to one end of the battery-side pre-charging contactor, the other end of the battery-side pre-charging contactor is connected to the second DC positive pole of the DC / DC module, the combination of the battery-side pre-charging contactor and the pre-charging resistor is used for charging the first support capacitor when the H-bridge circuit module starts and charging the second support capacitor when the DC / DC module starts, the Hall current sensor and the second DC fuse are both connected in series to the DC negative pole of the DC / DC module, and the second DC fuse is used for cutting off the fault current when a DC short circuit occurs on the super capacitor cluster side, the second DC positive pole of the DC / DC module is connected to the positive pole of the super capacitor cluster, and the DC negative pole of the DC / DC module is connected to the negative pole of the super capacitor cluster.

[0008] Preferably, the number of H-bridge circuit modules, DC / DC modules and super capacitor clusters satisfies the following relationship:

[0009]

[0010] In the formula, k is the fluctuation margin of the AC bus voltage, x% is the voltage division ratio of the grid-connected reactor, U is the AC bus voltage, U dcmin is the lower limit of the DC voltage.

[0011] Preferably, the number of half-bridge circuits in the DCDC module satisfies the following relationship:

[0012]

[0013] In the formula, P total is the total power of the converter composed of m half-bridge circuits, and P1 is the power of the converter composed of a single half-bridge circuit;

[0014] m is an integer greater than or equal to 3.

[0015] Preferably, in the DCDC module, when the super capacitor cluster absorbs energy from the grid side through the two-stage power module, the switching devices of the upper bridge arms of the m half-bridge circuits are in PWM modulation state, and the switching devices of the lower bridge arms of the m half-bridge circuits are turned off, at this time, the DCDC module is a BUCK voltage reduction circuit; when the super capacitor cluster releases energy to the grid side through the two-stage power module, the switching devices of the lower bridge arms of the m half-bridge circuits are in PWM modulation state, and the switching devices of the upper bridge arms of the m half-bridge circuits are turned off, at this time, the DCDC module is a BOOST voltage increase circuit.

[0016] The duty cycle D in the PWM adjustment pulse of each switching device in the DCDC module satisfies the following relationship:

[0017] D=1-U DC2 / U DC1

[0018] In the formula, U DC1 is the DC voltage across the second support capacitor, and U DC2 is the DC voltage across the second voltage-sharing resistor complete device.

[0019] Preferably, the inductance of the filter inductor satisfies the following relationship:

[0020]

[0021] In the formula, Li is the inductance of the i-th filter inductor, i=1, 2, …, m; f is the switching frequency of the half-bridge circuit, and rhalf is the ripple rate of the half-bridge circuit output current.

[0022] The capacitance of the second support capacitor satisfies the following relationship:

[0023]

[0024] In the formula, C2 is the capacitance of the second support capacitor, V ppThe output voltage of the half-bridge circuit.

[0025] Preferably, the minimum value of the total storage energy of all super capacitor clusters on each phase is E s , the minimum value of the single release energy of all super capacitor clusters is E o , the rated working voltage of each super capacitor cluster is U1, and the capacitor voltage of each super capacitor cluster after discharge is U2, the capacitance value of a single super capacitor cluster satisfies the following relationship:

[0026]

[0027] In the formula, C is the capacitance value of a single super capacitor cluster, and n is the total number of super capacitor clusters on each phase.

[0028] The application also provides a super-capacitor direct-voltage synchronous grid control method for a modular static synchronous compensator, wherein the H-bridge circuit module control comprises a super-capacitor direct-voltage power synchronous ring, a virtual excitation ring, a virtual impedance and current limiting control ring, an inner current ring and a control mode selection; the DCDC module control comprises a direct-current voltage closed loop and a direct-current current closed loop.

[0029] Preferably, in the super-capacitor direct-voltage power synchronous ring, the difference between the square of the actual value V dc of the voltage of the super capacitor cluster and the square of the voltage instruction value V dcref is input, and after proportional integral control PI of the voltage of the super capacitor cluster, an active power instruction value P ref is obtained, the difference between the active power instruction value P ref and the actual value P m of the active power is input into the angular velocity proportional control K DW with inertia negative feedback to generate an angular velocity adjustment amount Δω of the internal electromotive force, and the angular velocity adjustment amount Δω of the internal electromotive force and the rated angular velocity ω n of the internal electromotive force generate an actual value ω of the angular velocity of the internal electromotive force and are converted into a phase angle θ of the internal electromotive force; meanwhile, the difference between the reactive power instruction value Q ref and the actual value Q m of the reactive power is input into the reactive control K iQ to generate an amplitude adjustment amount ΔE of the internal electromotive force, and the amplitude adjustment amount ΔE of the internal electromotive force and the rated value E0 of the internal electromotive force generate an actual value E of the amplitude of the internal electromotive force; the actual value E of the amplitude of the internal electromotive force and the phase angle θ of the internal electromotive force constitute an internal electromotive force vector.

[0030] The active power instruction value P ref satisfies the following relationship:

[0031]

[0032] In the formula, K PVCA , K IVCAKp and Ki are proportional and integral coefficients of the voltage proportional-integral control of the supercapacitor cluster, s is a Laplace operator;

[0033] The angular velocity adjustment amount Δω of the internal potential satisfies the following relationship:

[0034]

[0035] Kp and Ki are proportional and integral coefficients of the voltage proportional-integral control of the supercapacitor cluster, s is a Laplace operator; DW , J are proportional and inertia time constants of the synchronous machine, s is a Laplace operator;

[0036] The phase angle θ of the internal potential satisfies the following relationship:

[0037] θ = ∫ Δω + ω n dt

[0038] The amplitude actual value E of the internal potential satisfies the following relationship:

[0039]

[0040] Kp and Ki are proportional and integral coefficients of the voltage proportional-integral control of the supercapacitor cluster, s is a Laplace operator; iQ is an integral coefficient of reactive power control.

[0041] Preferably, in the closed-loop control mode, the internal potential vector is converted into components Ea, Eb, Ec in the stationary coordinate system, and then, together with the H-bridge circuit module voltages Uma, Umb, Umc, it is used as the input data of the virtual impedance and current limiting control loop to generate the instantaneous values of the current command values iaref, ibref, icref, thereby achieving current limiting control and impedance optimization; in the current inner loop, the difference between the instantaneous values of the current command values iaref, ibref, icref and the actual values of the currents ia, ib, ic is subjected to proportional-resonant control PR, and then, together with the H-bridge circuit module voltages Uma, Umb, Umc, it generates the three-phase modulation voltages Ua_ref, Ub_ref, Uc_ref; in the open-loop control mode, the internal potential vector is converted into components Ea, Eb, Ec in the stationary coordinate system, and then directly used as the three-phase modulation voltages Ua_ref, Ub_ref, Uc_ref; the closed-loop control mode and the open-loop control mode are switched according to actual needs by the control mode selection; the voltage command values are subjected to carrier phase shift to generate the trigger pulse signals of the switching devices in the H-bridge circuit module;

[0042] In the virtual impedance and current limiting control link, the H-bridge circuit module voltages Uma, Umb, Umc are first used to generate the dq-axis components U dp , U qp of the positive sequence voltage of the H-bridge circuit module and the dq-axis components U dn , U qn of the negative sequence voltage of the H-bridge circuit module, which satisfy the following relationship:

[0043]

[0044] wherein, is the phase angle of the H-bridge module voltage;

[0045] the dq-axis component of the positive-sequence voltage of the H-bridge module U dp , U dq and the dq-axis component of the negative-sequence voltage of the H-bridge module U dn , U dn and the actual value of the amplitude of the internal potential E, based on the virtual resistance R v and the virtual reactance X v generate the dq-axis component of the positive-sequence current command value I dPref , I qPref the dq-axis component of the negative-sequence current command value I dNref , I qNref satisfying the following relationship:

[0046]

[0047] the dq-axis component of the positive-sequence current command value I dPref , I qPref the dq-axis component of the negative-sequence current command value I dNref , I qNref are obtained through linear transformation to obtain the three-phase positive-sequence current command I refAP , I refBP , I refCP and the three-phase negative-sequence current command I refAN , I refBN , I refCN satisfying the following relationship:

[0048]

[0049]

[0050] wherein, θ P is the phase angle of the positive-sequence internal potential, which is equal to the phase angle θ of the internal potential; θ N is the phase angle of the negative-sequence internal potential, which is opposite to the phase angle θ of the internal potential;

[0051] Finally, the three-phase positive-sequence current command I refAP , I refBP , I refCP and the three-phase negative-sequence current command I refAN , I refBN , I refCN are added and then subjected to proportional current limiting to achieve a constant phase angle of the fault current, thereby obtaining the instantaneous values of the three-phase current command values aref, ibref, icref, which satisfy the following relationship:

[0052]

[0053] wherein K Iref is a proportional current limiting coefficient, 0 Iref <1;

[0054] The instantaneous values of the three-phase current command values iaref, ibref, icref generate three-phase modulation voltages Ua_ref, Ub_ref, Uc_ref through the current inner loop, satisfying the following relationship:

[0055]

[0056] wherein k PPR , k IPR are proportional and integral coefficients of proportional-resonant control, respectively, I a , I b , I c are sampling values of three-phase currents of the H-bridge circuit module, I aref , I bref , I cref are three-phase current command values;

[0057] The obtained three-phase modulation voltages Ua_ref, Ub_ref, Uc_ref are subjected to carrier phase-shifted modulation to generate pulse signals of switching devices in the H-bridge circuit module.

[0058] Preferably, in the DC voltage closed loop, the difference between the DC voltage command value U ref and the average filtered sampling value U C of the capacitance voltage of the super capacitor cluster is subjected to the DC voltage loop to obtain a DC current command value I ref , and the DC voltage command value U ref is compared with the sampling value U ac of the AC voltage and the sampling value I ac of the AC current of the two-stage power module to obtain a DC current feedforward value I dcp ; in the DC current closed loop, the difference between the DC voltage command value U ref , the DC current feedforward value I dcp and the sampling value I dc of the DC current of the two-stage power module is subjected to dead-beat control to generate a duty cycle adjustment amount, and the duty cycle adjustment amount and a duty cycle feedforward value D0 generate a duty cycle D; the duty cycle generates trigger pulse signals of switching devices of each half-bridge circuit in the DC / DC module through phase-shifted carrier;

[0059] The DC current command value I ref satisfies the following relationship:

[0060]

[0061] In the formula, K pD , K iD are the proportional coefficient and integral coefficient of the DC voltage loop respectively;

[0062] Wherein, the DC current feedforward value I dcp satisfies the following relationship:

[0063]

[0064] The DC current instruction passes through the deadbeat control to generate the duty ratio D, which satisfies the following relationship:

[0065]

[0066] In the formula, L is the inductance of the filter inductance, ΔT is the execution period of the DCDC module, K pil is the proportional coefficient of the deadbeat control.

[0067] The beneficial effects of the present application at least include, compared with the prior art, the conventional synchronous phase modifier is expensive, occupies a large area, the system is complex, and the operation and maintenance are difficult; the static synchronous phase modifier formed by combining the static var compensator (SVG) adopting the cascaded H-bridge and the super-capacitor energy storage element and the grid control strategy needs to be configured with a large number of super-capacitors, and has the problems of large system volume and high cost; at the same time, the single-stage topology control has low freedom degree, can only reduce the double-frequency power flowing into the super-capacitor by increasing the passive filter, and cannot completely filter out, which causes the temperature of the super-capacitor to rise and the service life to decrease. The DC / DC conversion is added between the conventional H-bridge module and the super-capacitor, the wide-range discharge of the super-capacitor is realized to improve the energy utilization rate; the AC reactive power and the DC side active power are combined to realize the interface control, the double-frequency power flowing into the super-capacitor is completely filtered out while maintaining the constant DC voltage, the service life of the super-capacitor is greatly prolonged; the modular design is adopted, the cost, volume and flexible expansion have certain advantages compared with the conventional synchronous phase modifier, and the maintenance is simple and the reliability is high. BRIEF DESCRIPTION OF DRAWINGS

[0068] Figure 1 It is the wiring principle diagram of the modular static synchronous phase modifier proposed by the present application;

[0069] Figure 2 It is the topology structure diagram of the H-bridge circuit module in the modular static synchronous phase modifier proposed by the present application;

[0070] Figure 3 It is the topology structure diagram of the DCDC module in the modular static synchronous phase modifier proposed by the present application;

[0071] Figure 4The figure is a control architecture diagram of an H-bridge circuit module in a modular static synchronous compensator proposed in the application, including an overcapacity direct voltage synchronous loop and a virtual excitation loop.

[0072] Figure 5 The figure is a control architecture diagram of an H-bridge circuit module in a modular static synchronous compensator proposed in the application, including a virtual impedance and current limiting control loop, an inner current loop and a control model selection.

[0073] Figure 6 The figure is a control architecture diagram of a DC / DC module in a modular static synchronous compensator proposed in the application, including a direct current voltage closed loop and a direct current closed loop. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical scheme and advantages of the application clearer, the technical scheme of the application will be described clearly and completely below in combination with the drawings in the embodiments of the application. The embodiments described in the application are only a part of the embodiments of the application, rather than all the embodiments. All other embodiments obtained by those skilled in the art without creative labor on the basis of the spirit of the application belong to the protection scope of the application.

[0075] The existing static synchronous compensator adopting a network control strategy composed of cascaded H-bridges and overcapacity energy storage elements does not contain a DC / DC converter, so a large number of super capacitor clusters need to be configured, and there are problems of large system volume and high cost. At the same time, the single-stage topology has low control freedom, and can only reduce the double-frequency power flowing into the super capacitor by increasing a passive filter, and cannot completely filter out, which causes the temperature of the super capacitor to rise and the service life to decrease.

[0076] The application adds a DC / DC converter between the conventional H-bridge module and the super capacitor cluster, realizes wide-range discharge of the super capacitor cluster to improve energy utilization rate, realizes interface control of alternating current reactive power and direct current active power by combining a control strategy, completely filters out the double-frequency power flowing into the super capacitor while maintaining constant direct current voltage, greatly prolongs the service life of the super capacitor, adopts modular design, has certain advantages in cost, volume and flexible expansion compared with the conventional static synchronous compensator, and is simple to maintain and has high reliability.

[0077] As Figure 1The figure shows the wiring principle for connecting a modular static synchronous condenser to an AC grid. The AC side of the modular static synchronous condenser is connected to the high-voltage AC grid through a grid-connected reactor and an AC starting circuit. The AC starting circuit includes a first circuit breaker QF1, a second circuit breaker QF2, an isolating switch QS1, and a starting resistor R. The AC starting circuit is used to connect the power module to the high-voltage AC grid and soft-start the power module. The AC starting circuit also includes a first grounding switch QE1, a second grounding switch QE2, a voltage transformer TV1, and a current transformer TA1. One end of the grid-connected reactor L is connected to the grid through the AC starting circuit, and the other end is connected to the AC side of the power module. The grid-connected reactor is used to filter and limit fault current. The grid-connected reactor is also equipped with bushing current transformers LA1-LA3.

[0078] The present invention proposes a modular static synchronous condenser with the same three-phase circuit structure. Each phase includes a two-stage power module consisting of an H-bridge circuit module and a DC-DC module connected in series, and a supercapacitor cluster. The AC sides of the two-stage power modules on each phase are cascaded, and the DC sides of the two-stage power modules on each phase are respectively connected to the supercapacitor cluster.

[0079] Specifically, each phase includes n AC-side cascaded power modules. Figure 1 AM1, ..., AMn represent n AC-side cascaded two-stage power modules of phase A, BM1, ..., BMn represent n AC-side cascaded two-stage power modules of phase B, and CM1, ..., CMn represent n AC-side cascaded two-stage power modules of phase C; each power module is a two-stage power module; Figure 1 In the figure, AD1, ..., ADn represent n supercapacitor clusters of phase A, BD1, ..., BDn represent n supercapacitor clusters of phase B, and CD1, ..., CDn represent n supercapacitor clusters of phase C. One supercapacitor cluster is connected to the DC side of a two-stage power module.

[0080] Specifically, the number of two-stage power modules per phase depends mainly on the AC bus voltage of the power grid and the DC voltage of the two-stage power module. Assuming that the AC bus voltage is U, the fluctuation margin of the AC bus voltage is k, and the range of the DC voltage is U dcmin ~U dcmax , the voltage division ratio of the grid-connected reactor is x%, then the number of two-stage power modules required for each phase satisfies the following relationship:

[0081]

[0082] Where U dcmin is the lower limit of DC voltage.

[0083] like Figure 2As shown, the two-stage power module includes an H-bridge circuit module and a DCDC module; the AC side of the H-bridge circuit module is connected to the power grid, the DC side of the H-bridge circuit module is connected to the high-voltage side of the DCDC module, and the low-voltage side of the DCDC module is connected to the super capacitor cluster; the H-bridge circuit module is used to realize AC-DC conversion, and the DCDC module is used to convert to realize wide-range super capacitor voltage utilization.

[0084] Specifically, as shown in the figure, Figure 2 As shown, the H-bridge circuit module includes a first bypass switch KM1, an H-bridge circuit, a first support capacitor C1, a first voltage-sharing resistor complete device R1, and a first DC fuse FU1; wherein the first bypass switch is connected in parallel between the first AC end ACL and the second AC end ACN of the H-bridge circuit module, and when the two-stage power module fails, the first bypass switch is closed and the two-stage power module exits operation; the first support capacitor C1 and the first voltage-sharing resistor complete device R1 are connected in parallel between the DC positive electrode UDC1+ and the DC negative electrode UDC- of the H-bridge circuit module; wherein the H-bridge circuit includes two half-bridge circuits S1 and S2, each half-bridge circuit includes two switching devices and a diode connected in anti-parallel with the switching device, the AC side of the H-bridge circuit is connected to the first AC end ACL and the second AC end ACN of the H-bridge circuit module, and the DC side of the H-bridge circuit is connected to the DC positive electrode UDC1+ and the DC negative electrode UDC- of the H-bridge circuit module to realize AC-DC conversion; the DC fuse is connected in series on the DC positive electrode line, and is used to cut off the fault current when the DC of the rear-stage DCDC side is short-circuited.

[0085] Further, in the H-bridge circuit module, the switching devices in the two half-bridge circuits are alternately and complementarily turned on, when the switching devices of the upper bridge arm of the half-bridge circuit S1 and the switching devices of the lower bridge arm of the half-bridge circuit S2 are turned on, the switching devices of the lower bridge arm of the half-bridge circuit S1 and the switching devices of the upper bridge arm of the half-bridge circuit S2 are turned off; conversely, when the switching devices of the upper bridge arm of the half-bridge circuit S1 and the switching devices of the lower bridge arm of the half-bridge circuit S2 are turned off, the switching devices of the lower bridge arm of the half-bridge circuit S1 and the switching devices of the upper bridge arm of the half-bridge circuit S2 are turned on; thereby realizing AC-DC conversion.

[0086] Specifically, as shown in the figure, Figure 2As shown, the DCDC module comprises: a second support capacitor C2, a second voltage-sharing resistor complete device R2, m half-bridge circuits, m filter inductors L1-Lm, a capacitor-side main contactor KM2, a battery-side pre-charging contactor KM3, a pre-charging resistor R3, a second DC fuse FU2, and a Hall current sensor LA; wherein the second support capacitor C2 is connected in parallel between the DC positive pole UDC+ and the DC negative pole UDC- of the H-bridge circuit module; m is an integer greater than or equal to 3, and in the embodiment of the present application, m is 3; the DCDC module adopts three half-bridge circuits S3, S4, and S5, each of which comprises two switching devices and anti-parallel diodes connected with the switching devices; the high-voltage DC side of each half-bridge circuit is connected with the DC positive pole UDC+ and the DC negative pole UDC- of the H-bridge circuit module; the midpoint of each half-bridge circuit is connected with the first DC positive pole UDC2+ of the DCDC module through a filter inductor; the second voltage-sharing resistor complete device R2 is connected in parallel between the first DC positive pole UDC2+ and the DC negative pole UDC- of the DCDC module; one end of the capacitor-side main contactor KM2 is connected with the first DC positive pole UDC2+ of the DCDC module, and the other end is connected with the second DC positive pole UDC3+ of the DCDC module; the capacitor-side main contactor is used to turn on and turn off the connection between the two-stage power module and the super capacitor cluster; one end of the pre-charging resistor R3 is connected with the first DC positive pole UDC2+ of the DCDC module, and the other end is connected with one end of the battery-side pre-charging contactor KM3; the other end of the battery-side pre-charging contactor KM3 is connected with the second DC positive pole UDC3+ of the DCDC module; the combination of the battery-side pre-charging contactor and the pre-charging resistor is used to charge the first support capacitor C1 and the second support capacitor C2 in the two-stage power module when the two-stage power module starts; the Hall current sensor LA and the second DC fuse FU2 are both connected in series with the DC negative pole UDC- of the DCDC module; the second DC fuse is used to cut off the fault current when a DC short circuit occurs on the super capacitor cluster side; the second DC positive pole UDC3+ of the DCDC module is connected with the positive pole of the super capacitor cluster, and the DC negative pole UDC- of the DCDC module is connected with the negative pole of the super capacitor cluster.

[0087] The midpoints of the m half-bridge circuits in the DCDC module are connected in parallel with the super capacitor cluster through m filter inductors and further through a pre-charging circuit, realizing DC step-down conversion from the ACDC side to the super capacitor cluster side and step-up conversion from the super capacitor side to the ACDC side; when a short circuit fault occurs on the super capacitor cluster side, the switching devices in each half-bridge circuit are controlled to be locked, the fault current on the super capacitor cluster side is blocked, the fault current is quickly cut off, and the fault feedback is avoided from being enlarged.

[0088] Further, in the DCDC module, when the super capacitor cluster absorbs energy from the grid side through the two-stage power module, the switching devices of the upper bridge arms of the three half-bridge circuits S3, S4 and S5 are in PWM modulation state, and the switching devices of the lower bridge arms of the three half-bridge circuits S3, S4 and S5 are turned off, at this time, the DCDC module is a BUCK voltage reduction circuit; when the super capacitor cluster releases energy to the grid side through the two-stage power module, the switching devices of the lower bridge arms of the three half-bridge circuits S3, S4 and S5 are in PWM modulation state, and the switching devices of the upper bridge arms of the three half-bridge circuits S3, S4 and S5 are turned off, at this time, the DCDC module is a BOOST voltage increase circuit.

[0089] The parameter determination method of the DCDC module of the two-stage power module includes:

[0090] In the DCDC module, the total power of the converter composed of m half-bridge circuits is P total , the power of the converter composed of a single half-bridge circuit is P1, and the number of half-bridge circuits in the DCDC module satisfies the following relationship:

[0091]

[0092] The duty cycle D in the PWM adjustment pulse of each switching device in the DCDC module satisfies the following relationship:

[0093] D=1-U DC2 U DC1

[0094] In the formula, U DC1 is the DC voltage across the second support capacitor C2, and U DC2 is the DC voltage across the second voltage-sharing resistor set R2.

[0095] The inductance of the filter inductor satisfies the following relationship:

[0096]

[0097] In the formula, Li is the inductance of the i-th filter inductor, i=1, 2, …, m; f is the switching frequency of the half-bridge circuit, and r half is the ripple rate of the output current of the half-bridge circuit and the output voltage;

[0098] Therefore, the capacitance of the second support capacitor satisfies the following relationship:

[0099]

[0100] In the formula, C2 is the capacitance of the second support capacitor, V pp is the output voltage of the half-bridge circuit.

[0101] Specifically, each super capacitor cluster comprises a plurality of super capacitor modules connected in series, and each super capacitor module comprises a plurality of super capacitor cell monomers, so as to realize energy storage.

[0102] The minimum value of the total storage energy of all super capacitor clusters on each phase is E s The minimum value of the single release energy of all super capacitor clusters is E o The rated working voltage of each super capacitor cluster is U1, and the capacitor voltage after discharge of each super capacitor cluster is U2, so the capacitance value of a single super capacitor cluster satisfies the following relationship:

[0103]

[0104] In the formula, C is the capacitance value of a single super capacitor cluster, and n is the total number of super capacitor clusters on each phase.

[0105] The modular static synchronous compensator further comprises a controller, which communicates with each two-stage power module through an optical fiber, collects power module electrical information and issues modulation instructions, so as to realize control and protection of the static synchronous compensator unit.

[0106] The application further provides a super-capacitor direct-voltage synchronous network control method of a modular static synchronous compensator, which comprises H-bridge circuit module control and DCDC module control which are independent of each other.

[0107] As shown in Figure 4 and Figure 5 , the H-bridge circuit module control comprises a super-capacitor direct-voltage power synchronous ring, a virtual excitation ring, a virtual impedance and current limiting control ring, a current inner ring and control mode selection; the H-bridge circuit module control realizes simulation of the characteristics of the static synchronous compensator, and has active inertia and reactive voltage support capability.

[0108] In the super-capacitor direct-voltage power synchronous ring, the difference between the square of the actual value V dc of the voltage of the super capacitor cluster and the square of the voltage instruction value V dcref is input, and after proportional integral control PI of the voltage of the super capacitor cluster, an active power instruction value P ref is obtained, the difference between the active power instruction value P ref and the actual value P m of the active power is subjected to angular velocity proportional control K with inertia negative feedback DW to generate an angular velocity adjustment amount Δω of the internal electromotive force, the angular velocity adjustment amount Δω of the internal electromotive force and the rated angular velocity ω n of the internal electromotive force generate the actual value ω of the angular velocity of the internal electromotive force and are converted into the phase angle θ of the internal electromotive force; at the same time, the difference between the reactive power instruction value Q ref and the actual value Q m of the reactive power is subjected to reactive control KiQ The amplitude adjustment amount ΔE of the internal electromotive force, the amplitude adjustment amount ΔE of the internal electromotive force and the rated value E0 of the internal electromotive force generate the amplitude actual value E of the internal electromotive force; the amplitude actual value E of the internal electromotive force and the phase angle θ of the internal electromotive force constitute the internal electromotive force vector;

[0109] In the embodiment, the active power instruction value P ref Satisfy the following relationship:

[0110]

[0111] In the formula, K PVCA , K IVCA , s is the Laplace operator respectively;

[0112] The angular velocity adjustment amount Δω of the internal electromotive force satisfies the following relationship:

[0113]

[0114] In the formula, K DW , J are the angular velocity proportional coefficient and the inertia time constant of the synchronous machine respectively, s is the Laplace operator;

[0115] The phase angle θ of the internal electromotive force satisfies the following relationship:

[0116] θ = ∫Δω + ω n dt

[0117] In the embodiment, the amplitude actual value E of the internal electromotive force satisfies the following relationship:

[0118]

[0119] In the formula, K iQ is the reactive power control integral coefficient.

[0120] In the closed-loop control mode, after the inner potential vector is converted into the components Ea, Eb, and Ec in the stationary coordinate system, it is used together with the H-bridge circuit module voltage Uma, Umb, and Umc as the input data of the virtual impedance and current limiting control loop. The virtual impedance and current limiting control loop generates the instantaneous values ​​iaref, ibref, and icref of the current command value, and realizes current limiting control and impedance optimization at the same time. In the current inner loop, the difference between the instantaneous values ​​iaref, ibref, and icref of the current command value and the actual current values ​​ia, ib, and ic is controlled by proportional resonance PR and then compared with the H-bridge circuit module voltage Um a, Umb, and Umc generate the three-phase modulation voltages Ua_ref, Ub_ref, and Uc_ref. In open-loop control mode, the internal potential vector is converted into components Ea, Eb, and Ec in the stationary coordinate system and directly used as the three-phase modulation voltages Ua_ref, Ub_ref, and Uc_ref. The closed-loop control mode and open-loop control mode are switched by the control mode selector according to actual needs. The voltage command value generates the trigger pulse signal of the switching device in the H-bridge circuit module through carrier phase shifting, which can simulate the characteristics of the synchronous phase regulator and has the ability to support active inertia and reactive voltage.

[0121] In the embodiment, in the virtual impedance and current limiting control link, the H-bridge circuit module voltages Uma, Umb, and Umc are first used to generate the dq axis component U of the positive sequence voltage of the H-bridge circuit module. dp 、U qp and the dq axis component U of the negative sequence voltage of the H-bridge circuit module dn 、U qn , satisfying the following relationship:

[0122]

[0123] Where, is the voltage phase angle of the H-bridge circuit module.

[0124] Then use the dq axis component U of the positive sequence voltage of the H bridge circuit module dp 、U dq and the dq axis component U of the negative sequence voltage of the H-bridge circuit module dn 、U dn , and the actual value of the internal potential amplitude E, based on the virtual resistance R v and virtual reactance X v , generates the positive sequence current command value dq axis component I dPref , I qPref , negative sequence current command value dq axis component I dNref , I qNref , satisfying the following relationship:

[0125]

[0126] Positive sequence current command value dq axis component I dPref qPref Negative sequence current command value dq axis component I dNref qNref Three-phase positive sequence current command I refAP refBP refCP and three-phase negative sequence current command I refAN refBN refCN satisfy the following relationship:

[0127]

[0128] wherein θ P is the phase angle of the positive sequence internal electromotive force, equal to the phase angle θ of the internal electromotive force; θ N is the phase angle of the negative sequence internal electromotive force, opposite to the phase angle θ of the internal electromotive force;

[0129] Finally, three-phase positive sequence current command I refAP refBP refCP and three-phase negative sequence current command I refAN refBN refCN corresponding to the phase angle of the fault current unchanged, the instantaneous values of the three-phase current command values are aref, ibref, icref, satisfying the following relationship:

[0130]

[0131] wherein K Iref is the proportional current limiting coefficient, 0 < K Iref < 1.

[0132] The instantaneous values of the three-phase current command values are aref, ibref, icref, which pass through the current inner loop to generate three-phase modulation voltages Ua_ref, Ub_ref, Uc_ref, satisfying the following relationship:

[0133]

[0134] wherein k PPR , k IPR are the proportional coefficient and integral coefficient of the proportional-resonant control, respectively, I a , I b , I c are the sampling values of the three-phase currents of the H-bridge circuit module, I aref , I bref , I cref are the three-phase current command values. ​​​​​​​​​​

[0135] The obtained three-phase modulation voltage Ua_ref, Ub_ref, Uc_ref is subjected to carrier phase-shift modulation to generate a pulse signal of a switching device in the H-bridge circuit module.

[0136] As shown in Figure 6 , the DCDC module control includes a direct current voltage closed loop and a direct current closed loop; in the direct current voltage closed loop, the direct current voltage instruction value U ref is compared with the difference between the mean value filtered super capacitor cluster capacitor voltage sampling value U C and the direct current voltage ring to obtain the direct current instruction value I ref , and the direct current voltage instruction value U ref is compared with the sampling value U ac of the alternating current voltage and the sampling value I ac of the alternating current of the two-stage power module to obtain the direct current feedforward value I dcp ; in the direct current closed loop, the direct current voltage instruction value U ref and the direct current feedforward value I dcp are compared with the difference between the sampling value I dc of the direct current of the two-stage power module to generate a duty cycle adjustment amount after deadbeat control, and the duty cycle adjustment amount and the duty cycle feedforward value D0 generate the duty cycle D. The duty cycle generates a trigger pulse signal of a switching device of each half-bridge circuit in the DCDC module through phase-shifted carrier, realizing the direct voltage tracking of the DCDC module and the suppression of the super capacitor cluster double-frequency current.

[0137] In the embodiment, since the mean value filtering filters out the double-frequency content in the super capacitor cluster capacitor voltage sampling value U C , the obtained direct current instruction value I ref does not contain double-frequency components, realizing the suppression of the super capacitor cluster double-frequency current. The direct current instruction value I ref satisfies the following relationship:

[0138]

[0139] In the formula, K pD and K iD are the proportional coefficient and the integral coefficient of the direct current voltage ring respectively.

[0140] The direct current feedforward value I dcp satisfies the following relationship:

[0141]

[0142] The direct current instruction is subjected to deadbeat control to generate the duty cycle D, which satisfies the following relationship:

[0143]

[0144] In the formula, L is the inductance of the filter inductor, ΔT is the execution cycle of the DCDC module, K pil is the proportional coefficient of the dead-beat control.

[0145] The duty ratio is modulated by n phase-shifted carriers to generate the trigger pulse signals of the switching devices of each half-bridge circuit in the DCDC module. Finally, since the DC current command value does not have a double-frequency component, the control can simultaneously achieve double-frequency suppression of the over-capacity current.

[0146] The over-capacity direct-voltage synchronization network construction control method of the static synchronous compensator module-level topology provided by the present application is a two-level control architecture, and the two-level control strategies are independent and do not interfere with each other.

[0147] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0148] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or punched tape, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0149] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0150] Computer readable program instructions for carrying out operations of the present disclosure can be assembly instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0151] Finally, it should be noted that the above-mentioned embodiments are merely used to illustrate the technical solutions of the present application, but not to limit it. Although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that the specific embodiments of the present application can be modified or replaced, and any modification or replacement without departing from the spirit and scope of the present application should be covered in the protection scope of the claims of the present application.

Claims

1. A modular static synchronous condenser, each phase comprising n H-bridge circuit modules and n supercapacitor clusters, wherein the AC sides of the H-bridge circuit modules are cascaded, and the DC sides of the H-bridge circuit modules are connected to the supercapacitor clusters, characterized in that: The H-bridge circuit module includes: a first bypass switch, an H-bridge circuit, a first supporting capacitor, a first grading resistor assembly, and a first DC fuse; wherein the first bypass switch is connected in parallel between the first AC terminal and the second AC terminal of the H-bridge circuit module, the first supporting capacitor and the first grading resistor assembly are connected in parallel between the DC positive electrode and the DC negative electrode of the H-bridge circuit module, and the DC fuse is connected in series with the DC positive electrode line; The modular static synchronous condenser also includes: n DCDC modules, an H-bridge circuit module and a DCDC module connected in series to form a two-stage power module; each DCDC module includes: a second supporting capacitor, a second equalizing resistor set, m half-bridge circuits, m filter inductors, a capacitor-side main contactor, a battery-side pre-charging contactor, a pre-charging resistor, a second DC fuse, and a Hall current sensor; wherein the second supporting capacitor is connected in parallel between the DC positive and DC negative poles of the H-bridge circuit module, each half-bridge circuit includes two switching devices and a diode anti-parallel to the switching device, the high-voltage DC side of each half-bridge circuit is connected to the DC positive and DC negative poles of the H-bridge circuit module, the midpoint of each half-bridge circuit is connected to the first DC positive pole of the DCDC module through the filter inductor, and the second equalizing resistor set is connected in parallel between the first DC positive and DC negative poles of the DCDC module; one end of the capacitor-side main contactor is connected to the DC The first DC positive pole of the DC module is connected, and the other end is connected to the second DC positive pole of the DCDC module. The capacitor-side main contactor is used to connect and disconnect the connection between the DCDC module and the supercapacitor cluster. One end of the pre-charging resistor is connected to the first DC positive pole of the DCDC module, and the other end is connected to one end of the battery-side pre-charging contactor. The other end of the battery-side pre-charging contactor is connected to the second DC positive pole of the DCDC module. The combination of the battery-side pre-charging contactor and the pre-charging resistor is used to charge the first supporting capacitor when the H-bridge circuit module is started and to charge the second supporting capacitor when the DCDC module is started. The Hall current sensor and the second DC fuse are both connected in series to the DC negative pole of the DCDC module. The second DC fuse is used to cut off the fault current when a DC short circuit occurs on the supercapacitor cluster side. The second DC positive pole of the DCDC module is connected to the positive pole of the supercapacitor cluster, and the DC negative pole of the DCDC module is connected to the negative pole of the supercapacitor cluster.

2. The modular static synchronous condenser according to claim 1, characterized in that: The number of H-bridge circuit modules, DCDC modules, and supercapacitor clusters satisfies the following relationship: Where k is the fluctuation margin of the AC bus voltage, x% is the voltage divider ratio of the grid-connected reactor, U is the AC bus voltage, and U dcmin is the lower limit of DC voltage.

3. The modular static synchronous condenser according to claim 1, characterized in that: The number of half-bridge circuits in the DCDC module satisfies the following relationship: Where, P total is the total power of the converter consisting of m half-bridge circuits, and P1 is the power of the converter consisting of a single half-bridge circuit; m is an integer greater than or equal to 3.

4. The modular static synchronous condenser according to claim 3, characterized in that: In the DCDC module, when the supercapacitor cluster absorbs energy from the grid side through the two-stage power module, the switching devices of the upper bridge arms of the m half-bridge circuits are all in the PWM modulation state, and the switching devices of the lower bridge arms of the m half-bridge circuits are all turned off. At this time, the DCDC module is a buck circuit; when the supercapacitor cluster releases energy to the grid side through the two-stage power module, the switching devices of the lower bridge arms of the m half-bridge circuits are all in the PWM modulation state, and the switching devices of the upper bridge arms of the m half-bridge circuits are all turned off. At this time, the DCDC module is a boost circuit; The duty cycle D of the PWM adjustment pulse of each switching device in the DCDC module satisfies the following relationship: D=1-U DC2 U DC1 Where U DC1 is the DC voltage across the second supporting capacitor, U DC2 is the DC voltage across the second voltage-equalizing resistor assembly.

5. The modular static synchronous condenser according to claim 4, characterized in that: The inductance of the filter inductor satisfies the following relationship: Where Li is the inductance of the i-th filter inductor, i = 1, 2, ..., m; f is the switching frequency of the half-bridge circuit, and r is the ripple rate of the output current of the bridge circuit; The capacitance of the second supporting capacitor satisfies the following relationship: Where C2 is the capacitance of the second supporting capacitor, V pp is the output voltage of the half-bridge circuit.

6. The modular static synchronous condenser according to claim 5, characterized in that: The minimum total energy storage of all supercapacitor clusters in each phase is E s , the minimum single release energy of all supercapacitor clusters is E o , the rated operating voltage of each supercapacitor cluster is U1, and the capacitor voltage of each supercapacitor cluster after discharge is U2. Then the capacitance of a single supercapacitor cluster satisfies the following relationship: Where C is the capacitance of a single supercapacitor cluster, and n is the total number of supercapacitor clusters on each phase.

7. A method for controlling a super-capacitance direct-pressure synchronous network of a modular static synchronous condenser, implemented by using the super-capacitance direct-pressure synchronous network control system of a modular static synchronous condenser according to any one of claims 1 to 6, characterized in that: The H-bridge circuit module control includes: super-capacitive direct voltage power synchronization loop, virtual excitation loop, virtual impedance and current limiting control loop, current inner loop and control mode selection; the DCDC module control includes DC voltage closed loop and DC current closed loop; In the supercapacitor direct pressure power synchronization ring, the actual voltage value of the supercapacitor cluster is V dc The square of the voltage command value V dcref The difference between the squares of is the input, and the active power command value P is obtained after the voltage proportional integral control PI of the supercapacitor cluster. ref , active power command value P ref and the actual value of active power P m The difference is fed back by inertia Angular velocity proportional control K DW The angular velocity adjustment amount Δω of the internal potential is then generated. The angular velocity adjustment amount Δω of the internal potential is equal to the rated angular velocity ω of the internal potential. n Generate the actual value of the angular velocity of the internal potential ω and convert it into the phase angle θ of the internal potential; at the same time, the reactive power command value Q ref and the actual value of reactive power Q m The difference is controlled by reactive power K iQ Then, the amplitude adjustment amount ΔE of the internal potential is generated. The amplitude adjustment amount ΔE of the internal potential and the internal potential rated value E0 generate the actual amplitude value E of the internal potential; the actual amplitude value E of the internal potential and the phase angle θ of the internal potential constitute the internal potential vector; Active power command value P ref Satisfies the following relationship: Where K PVCA , K IVCA are the proportional coefficient and integral coefficient of the voltage proportional-integral control of the supercapacitor cluster, respectively, and s is the Laplace operator; The angular velocity adjustment amount Δω of the internal potential satisfies the following relationship: Where K DW , J are the angular velocity proportional coefficient and the synchronous machine inertia time constant, s is the Laplace operator; The phase angle θ of the internal potential satisfies the following relationship: θ=∫(Dω+ω) n )dt The actual value E of the internal potential amplitude satisfies the following relationship: Where K iQ is the reactive power control integral coefficient.

8. The method for controlling super-capacity direct pressure synchronous networking of a modular static synchronous condenser according to claim 7, characterized in that: In the closed-loop control mode, after the inner potential vector is converted into the components Ea, Eb, and Ec in the stationary coordinate system, it is used together with the H-bridge circuit module voltage Uma, Umb, and Umc as the input data of the virtual impedance and current limiting control loop. The virtual impedance and current limiting control loop generates the instantaneous values ​​iaref, ibref, and icref of the current command value, and realizes current limiting control and impedance optimization at the same time. In the current inner loop, the difference between the instantaneous values ​​iaref, ibref, and icref of the current command value and the actual current values ​​ia, ib, and ic is proportionally resonated. After controlling PR, the three-phase modulation voltages Ua_ref, Ub_ref, and Uc_ref are generated with the H-bridge circuit module voltages Uma, Umb, and Umc. In open-loop control mode, the internal potential vector is converted into components Ea, Eb, and Ec in the stationary coordinate system and directly used as the three-phase modulation voltages Ua_ref, Ub_ref, and Uc_ref. The closed-loop control mode and open-loop control mode are switched according to actual needs by the control mode selection. The voltage command value generates the trigger pulse signal of the switching device in the H-bridge circuit module through carrier phase shifting. In the virtual impedance and current limiting control link, the H-bridge circuit module voltage Uma, Umb, and Umc are first used to generate the dq axis component U of the H-bridge circuit module positive sequence voltage. dp 、U qp and the dq axis component U of the negative sequence voltage of the H-bridge circuit module dn 、U qn , satisfying the following relationship: Where, is the voltage phase angle of the H-bridge circuit module; Then use the dq axis component U of the positive sequence voltage of the H bridge circuit module dp 、U dq and the dq axis component U of the negative sequence voltage of the H-bridge circuit module dn 、U dn , and the actual value of the internal potential amplitude E, based on the virtual resistance R v and virtual reactance X v , generates the positive sequence current command value dq axis component I dPref , I qPref , negative sequence current command value dq axis component I dNref , I qNref , satisfying the following relationship: Positive sequence current command value dq axis component I dPref , I qPref , negative sequence current command value dq axis component I dNref , I qNref The three-phase positive sequence current command I is obtained through linear transformation refAP , I refBP , I refCP And three-phase negative sequence current command I refAN , I refBN , I refCN , satisfying the following relationship: Where θ P is the phase angle of the positive sequence internal potential, which is equal to the phase angle θ of the internal potential; θ N is the phase angle of the negative sequence internal potential, which is opposite to the phase angle θ of the internal potential; Finally, the three-phase positive sequence current command I refAP , I refBP , I refCP And three-phase negative sequence current command I refAN , I refBN , I refCN After the corresponding addition, the phase angle of the fault current is kept constant through proportional current limiting, and the instantaneous values ​​of the three-phase current command values ​​iaref, ibref, and icref are obtained, which satisfy the following relationship: Where K Iref is the proportional current limiting coefficient, 0 <K Iref <1; The instantaneous values ​​iaref, ibref, and icref of the three-phase current command values ​​are converted into three-phase modulation voltages Ua_ref, Ub_ref, and Uc_ref through the current inner loop, satisfying the following relationship: Where k PPR 、k IPR are the proportional coefficient and integral coefficient of proportional resonance control, I a , I b , I c They are the sampling values ​​of the three-phase current of the H-bridge circuit module, I aref , I bref , I cref is the three-phase current command value; The obtained three-phase modulated voltages Ua_ref, Ub_ref, and Uc_ref are modulated by carrier phase shift to generate pulse signals for the switching devices in the H-bridge circuit module.

9. The method for controlling super-capacity direct pressure synchronous networking of a modular static synchronous condenser according to claim 7, characterized in that: In the DC voltage closed loop, the DC voltage command value U ref The capacitor voltage sampling value U of the supercapacitor cluster after mean filtering C The difference between the two values ​​is passed through the DC voltage loop to obtain the DC current command value I ref , while the DC voltage command value U ref The sampling value U of the AC voltage of the two-stage power module ac , AC current sampling value I ac Compare to obtain the DC current feedforward value I dcp ; In the DC current closed loop, the DC voltage command value U ref , DC current feedforward value I dcp The sampling value of the DC current of the two-stage power module I dc The difference between the two is controlled by deadbeat to generate the duty cycle adjustment value, and the duty cycle adjustment value and the duty cycle feedforward value D0 generate the duty cycle D; The duty cycle generates a trigger pulse signal for the switching devices of each half-bridge circuit in the DCDC module through a phase-shifted carrier; DC current command value I ref , satisfying the following relationship: Where K pD , K iD are the proportional coefficient and integral coefficient of the DC voltage loop respectively; Among them, the DC current feedforward value I dcp Satisfies the following relationship: The DC current command generates a duty cycle D after deadbeat control, which satisfies the following relationship: Where L is the inductance of the filter inductor, ΔT is the execution cycle of the DCDC module, and K pil is the proportional coefficient of deadbeat control.

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