Fully differential operational amplifier circuit

Abstract

The invention provides a fully differential operational amplifier circuit. The fully differential operational amplification circuit comprises a differential input pair and two reverse amplification circuits. The grid electrode of the first amplifier tube and the grid electrode of the second amplifier tube in the differential input pair respectively and correspondingly receive a first input signal and a second input signal, and the first input signal and the second input signal are differential signals. The input end of the first reverse amplification circuit receives a first input signal, and the output end of the first reverse amplification circuit is connected with the back gate of the second amplification tube. The input end of the second reverse amplification circuit receives a second input signal, and the output end of the second reverse amplification circuit is connected with the back gate of the first amplification tube. In the fully differential operational amplifier circuit, the potential of the back gate of the other amplifier tube is reversely adjusted according to the input signal received by the gate of each amplifier tube in the differential input pair, so that the transconductance of the differential input pair can be improved, and the gain of the fully differential operational amplifier circuit can be increased.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fully differential operational amplifier circuit. Background Art

[0002] The fully differential operational amplifier circuit is a special amplifier circuit that can perform differential amplification on the received differential signal, that is, it simultaneously amplifies the positive signal and the negative signal in the differential signal and gives their difference at the output. The fully differential operational amplifier circuit realizes the amplification of the differential signal and offsets the interference of the common-mode signal. This circuit is designed for signal amplification and suppression of common-mode interference and is widely used in communication systems, audio equipment, sensor interfaces and other fields.

[0003] However, currently the gain of the fully differential operational amplifier circuit is relatively small, so that the fully differential operational amplifier circuit can only be used in scenarios with relatively small gain requirements.

[0004] Therefore, how to improve the gain of the fully differential operational amplifier circuit is a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of this, the present invention provides a fully differential operational amplifier circuit to improve the gain of the fully differential operational amplifier circuit.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] The present application provides a fully differential operational amplifier circuit, comprising: a differential input pair and two reverse amplifier circuits; wherein:

[0008] The gate of the first amplifier tube and the gate of the second amplifier tube in the differential input pair respectively receive a first input signal and a second input signal, and the first input signal and the second input signal are differential signals;

[0009] An input end of the first reverse amplifier circuit receives the first input signal, and an output end of the first reverse amplifier circuit is connected to a back gate of the second amplifier tube;

[0010] The input end of the second reverse amplifier circuit receives the second input signal, and the output end of the second reverse amplifier circuit is connected to the back gate of the first amplifier tube.

[0011] Optionally, it also includes: an output stage; wherein:

[0012] The drain of the first amplifier tube and the drain of the second amplifier tube are respectively connected to the two input terminals of the output stage;

[0013] The two output ends of the output stage serve as the two output ends of the fully differential operational amplifier circuit respectively.

[0014] Optionally, it further includes: two first operational amplifiers; wherein:

[0015] The input terminals of the two first operational amplifiers are respectively connected to the sources of the two marked PMOS tubes;

[0016] The output voltages of the output terminals of the two first operational amplifiers are used to replace the bias voltages received by the gates of the two target PMOS tubes respectively;

[0017] The output ends of the two first operational amplifiers are also connected to the back gates of the two target PMOS tubes respectively;

[0018] The two PMOS tubes mentioned above are a pair of PMOS tubes respectively connected to the two output ends of the fully differential operational amplifier circuit in the output stage.

[0019] Optionally, it further includes: two second operational amplifiers; wherein:

[0020] The input terminals of the two second operational amplifiers are respectively connected to the sources of the two marked NMOS tubes;

[0021] The output voltages of the output terminals of the two second operational amplifiers are used to replace the bias voltages received by the gates of the two target NMOS transistors respectively;

[0022] The output ends of the two second operational amplifiers are also connected to the back gates of the two target NMOS tubes respectively;

[0023] The two target NMOS tubes are two NMOS tubes in the output stage respectively connected to the two output ends of the fully differential operational amplifier circuit.

[0024] Optionally, each operational amplifier in the fully differential operational amplifier circuit includes: four switch tubes; wherein:

[0025] The gate of the first switch tube is connected to the gate of the second switch tube, and the connection point receives a bias voltage corresponding to itself;

[0026] The gate of the third switch tube is connected to the gate of the fourth switch tube;

[0027] The source of the first switch tube is connected to the source of the second switch tube;

[0028] The source of the third switch tube serves as the input end of the operational amplifier;

[0029] The drain of the first switch tube is connected to the drain of the third switch tube;

[0030] The drain of the second switch tube is connected to the drain of the fourth switch tube, and the connection point serves as the output end of the operational amplifier.

[0031] Optionally, if the input end of the operational amplifier is connected to a corresponding PMOS tube, the first switch tube and the second switch tube are both PMOS tubes, the third switch tube and the fourth switch tube are both NMOS tubes, a connection point between a source of the first switch tube and a source of the second switch tube receives a power supply voltage, and a source of the fourth switch tube is grounded;

[0032] If the input end of the operational amplifier is connected to the corresponding NMOS tube, the first switch tube and the second switch tube are both NMOS tubes, the third switch tube and the fourth switch tube are both PMOS tubes, the connection point between the source of the first switch tube and the source of the second switch tube is grounded, and the source of the fourth switch tube receives the power supply voltage.

[0033] Optionally, the output stage includes: at least two pairs of fifth switch tubes and at least two pairs of sixth switch tubes; wherein:

[0034] The gates of the two fifth switch tubes in each pair of the fifth switch tubes are connected, and the connection points receive a bias voltage corresponding to themselves;

[0035] The fifth switch tubes located on one side of each pair of the fifth switch tubes are connected in series, the source of the formed series branch receives the supply voltage, and the drain of the formed series branch is connected to the first output end of the output stage;

[0036] The fifth switch tubes located on the other side of each pair of the fifth switch tubes are connected in series, the source of the formed series branch receives the supply voltage, and the drain of the formed series branch serves as the second output end of the output stage;

[0037] The gates of the two sixth switch tubes in each pair of the sixth switch tubes are connected, and the connection points receive a bias voltage corresponding to themselves;

[0038] The sixth switch tubes located on one side of each pair of the sixth switch tubes are connected in series, the source of the formed series branch is grounded, and the drain of the formed series branch is connected to the first output end of the output stage;

[0039] The sixth switch tubes located at the other side of each pair of the sixth switch tubes are connected in series, the source of the formed series branch is grounded, and the drain of the formed series branch is connected to the second output end of the output stage;

[0040] The two connection points of any two adjacent pairs of the fifth switch tubes are respectively used as the two input ends of the output stage, or the two connection points of any two adjacent pairs of the sixth switch tubes are respectively used as the two input ends of the output stage;

[0041] Each pair of the fifth switch tubes are PMOS tubes, and each pair of the sixth switch tubes are NMOS tubes.

[0042] Optionally, the output stage further includes: two seventh switch tubes; wherein:

[0043] The two fifth switch tubes whose sources receive the power supply voltage are respectively connected in parallel with the two seventh switch tubes;

[0044] A connection point of the gates of the two fifth switch tubes whose sources receive the power supply voltage is connected to the second output end of the output stage;

[0045] The gate electrodes of the two seventh switch tubes are connected, and the connection point is connected to the first output terminal of the output electrode;

[0046] Each seventh switch tube is a PMOS tube.

[0047] Optionally, each of the reverse amplifier circuits includes: an eighth switch tube and a third amplifier tube; wherein:

[0048] The drain of the eighth switch tube is connected to the drain of the third amplifier tube;

[0049] In the eighth switch tube and the third amplifier tube, one source receives the power supply voltage and the other source is grounded.

[0050] Optionally, if both amplifier tubes in the differential input pair are NMOS tubes, the third amplifier tube is an NMOS tube, the eighth switch tube is a PMOS tube, the source of the third amplifier tube is grounded, and the source of the eighth switch tube receives the power supply voltage;

[0051] If both amplifier tubes in the differential input pair are PMOS tubes, the third amplifier tube is a PMOS tube, the eighth switch tube is an NMOS tube, the source of the third amplifier tube receives the power supply voltage, and the source of the eighth switch tube is grounded.

[0052] It can be seen from the above technical solution that the present invention provides a fully differential operational amplifier circuit. The fully differential operational amplifier circuit includes a differential input pair and two reverse amplifier circuits. The gate of the first amplifier tube and the gate of the second amplifier tube in the differential input pair respectively receive the first input signal and the second input signal, and the first input signal and the second input signal are differential signals. The input end of the first reverse amplifier circuit receives the first input signal, and the output end of the first reverse amplifier circuit is connected to the back gate of the second amplifier tube. The input end of the second reverse amplifier circuit receives the second input signal, and the output end of the second reverse amplifier circuit is connected to the back gate of the first amplifier tube. In the fully differential operational amplifier circuit, since the potential of the back gate of another amplifier tube is reversely adjusted according to the input signal received by the gate of each amplifier tube in the differential input pair, the transconductance of the differential input pair can be improved, thereby the gain of the fully differential operational amplifier circuit can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0054] Figure 1-Figure 7 The schematic diagrams are respectively structural diagrams of seven implementation modes of the fully differential operational amplifier circuit provided in the embodiments of the present application;

[0055] Figure 8a and Figure 8b The following are schematic diagrams of the structures of two implementation modes of the operational amplifier provided in the embodiments of the present application. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0057] In this application, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0058] In order to improve the gain of the fully differential operational amplifier circuit, the embodiment of the present application provides a fully differential operational amplifier circuit, and its specific structure can be seen in Figure 1 or Figure 2 , specifically comprising: a differential input pair 10 and two reverse amplifier circuits 20 and 30.

[0059] The gate of the first amplifier tube Mf1 and the gate of the second amplifier tube Mf2 in the differential input pair 10 receive the first input signal INP and the second input signal INN respectively. The first input signal INP and the second input signal INN are differential signals.

[0060] An input end of the first reverse amplifier circuit 20 receives a first input signal INP, and an output end of the first reverse amplifier circuit 20 is connected to a back gate of the second amplifier tube Mf2.

[0061] An input end of the second inverting amplifier circuit 30 receives a second input signal INN, and an output end of the second inverting amplifier circuit 30 is connected to a back gate of the first amplifier tube Mf1.

[0062] Optionally, the first amplifier tube Mf1 and the second amplifier tube Mf2 can both be MOS tubes using FD-SOI (Fully Depleted Silicon-On-Insulator) technology. In practical applications, including but not limited to this, as long as they are MOS tubes, they are within the protection scope of this application. No specific limitation is made here and it can be determined according to the specific situation.

[0063] In practical applications, the differential input pair 10 specifically includes a first amplifier tube Mf1, a second amplifier tube Mf2 and a tail current source 11. If the first amplifier tube Mf1 and the second amplifier tube Mf2 are both NMOS tubes, then Figure 1As shown, the source of the first amplifier tube Mf1 is connected to the source of the second amplifier tube Mf2, the connection point is connected to the input end of the tail current source 11, and the output end of the tail current source 11 is grounded GND. If the first amplifier tube Mf1 and the second amplifier tube Mf2 are both PMOS tubes, then Figure 2 As shown, the source of the first amplifier tube Mf1 is connected to the source of the second amplifier tube Mf2, and the connection point is connected to the output end of the tail current source 11, and the input end of the tail current source 11 receives the power supply voltage VCC.

[0064] It should be noted that the tail current source 11 can be implemented by adding a bias voltage to a MOS tube. Since the function of implementing the tail current source 11 by adding a bias voltage to a MOS tube is already very mature in the prior art, it will not be described in detail here.

[0065] In the fully differential operational amplifier circuit, since the potential of the back gate of another amplifier tube is reversely adjusted according to the input signal received by the gate of each amplifier tube in the differential input pair 10, the transconductance of the differential input pair 10 can be improved, thereby increasing the gain of the fully differential operational amplifier circuit.

[0066] Another embodiment of the present application provides a specific implementation of the reverse amplifier circuit, which is applicable to the first reverse amplifier circuit 20 and the second reverse amplifier circuit 30. The specific structure of this implementation can be found in Figure 1 or Figure 2 , which specifically includes: an eighth switch tube M8 and a third amplifier tube Mf3.

[0067] The drain of the eighth switch tube M8 is connected to the drain of the third amplifier tube Mf3. In the eighth switch tube M8 and the third amplifier tube Mf3, one source receives the power supply voltage VCC and the other source is grounded GND.

[0068] Optionally, the eighth switch tube M8 may be a MOS tube using FD-SOI technology. In practical applications, including but not limited to this, as long as it is a MOS tube, it is within the protection scope of this application. No specific limitation is made here and it may depend on the specific situation.

[0069] Optionally, the third amplifier tube Mf3 can be a MOS tube using FD-SOI technology. In practical applications, including but not limited to this, as long as it is a MOS tube, it is within the protection scope of this application. No specific limitation is made here and it can be determined according to the specific situation.

[0070] If both amplifiers in the differential input pair 10 are NMOS tubes, then Figure 1 As shown, the third amplifier tube Mf3 is an NMOS tube, the eighth switch tube M8 is a PMOS tube, the source of the third amplifier tube Mf3 is grounded GND, and the source of the eighth switch tube M8 receives the power supply voltage VCC.

[0071] If both amplifiers in the differential input pair 10 are PMOS tubes, then Figure 2 As shown, the third amplifier tube Mf3 is a PMOS tube, the eighth switch tube M8 is an NMOS tube, the source of the third amplifier tube Mf3 receives the power supply voltage VCC, and the source of the eighth switch tube M8 is grounded GND.

[0072] In this embodiment, this implementation only includes one switch tube and one amplifier tube, so the structure of this implementation is relatively simple, so the cost of this implementation is relatively low, thereby reducing the overall cost of the fully differential operational amplifier circuit.

[0073] The above is only one implementation of the reverse amplifier circuit. In practical applications, including but not limited to this, no specific limitation is made here and it may be determined according to the specific circumstances, all of which are within the protection scope of this application.

[0074] Another embodiment of the present application provides another implementation of a fully differential operational amplifier circuit, and its specific structure can be found in Figure 3 or Figure 4 This implementation, based on the above implementation, further includes: an output stage.

[0075] The drain of the first amplifier tube Mf1 and the drain of the second amplifier tube Mf2 are respectively connected to the two input terminals of the output stage. The two output terminals of the output stage are respectively used as the two output terminals of the full differential operational amplifier circuit. The output terminals are used to convert the current outputted by the drain of the first amplifier tube Mf1 and the drain of the second amplifier tube Mf2 into a voltage for output.

[0076] In this embodiment, since the output stage converts the current outputted by the drain of the first amplifier tube Mf1 and the drain of the second amplifier tube Mf2 into a voltage for output, the immunity of the fully differential operational amplifier circuit to external noise is improved, thereby improving the stability and reliability of the fully differential operational amplifier circuit.

[0077] The present application embodiment provides a specific implementation of the above output stage. The specific structure can be found in Figure 3 or Figure 4 , specifically including: at least two pairs of fifth switch tubes M5 and at least two pairs of sixth switch tubes M6. The connection relationship of each tube is as follows:

[0078] The gates of the two fifth switch tubes M5 in each pair of the fifth switch tubes M5 are connected, and the connection points receive the bias voltage corresponding to themselves.

[0079] The fifth switch tubes M5 on one side of each pair of fifth switch tubes M5 are connected in series, the source of the formed series branch receives the power supply voltage VCC, and the drain of the formed series branch is connected to the first output terminal VN of the output stage.

[0080] The fifth switch tubes M5 on the other side of each pair of fifth switch tubes M5 are connected in series, the source of the formed series branch receives the power supply voltage VCC, and the drain of the formed series branch serves as the second output terminal VP of the output stage.

[0081] The gates of the two sixth switch tubes M6 in each pair of sixth switch tubes M6 are connected, and the connection points receive the bias voltage corresponding to themselves.

[0082] The sixth switch tubes M6 on one side of each pair of sixth switch tubes M6 are connected in series, the source of the formed series branch is grounded GND, and the drain of the formed series branch is connected to the first output terminal VN of the output stage.

[0083] The sixth switch tubes M6 on the other side of each pair of sixth switch tubes M6 are connected in series, the source of the formed series branch is grounded GND, and the drain of the formed series branch is connected to the second output terminal VP of the output stage.

[0084] Each pair of fifth switch tubes M5 are PMOS tubes, and each pair of sixth switch tubes M6 are NMOS tubes.

[0085] Optionally, each pair of fifth switch tubes M5 can be a MOS tube using FD-SOI technology. In practical applications, including but not limited to this, as long as it is a MOS tube, it is within the protection scope of this application. No specific limitation is made here and it can be determined according to the specific situation.

[0086] Optionally, each pair of sixth switch tubes M6 can be a MOS tube using FD-SOI technology. In practical applications, including but not limited to this, as long as it is a MOS tube, it is within the protection scope of this application. No specific limitation is made here and it can be determined according to the specific situation.

[0087] If both amplifiers in the differential input pair 10 are NMOS tubes, then Figure 3 As shown, the two connection points of any two adjacent pairs of fifth switch tubes M5 serve as the two input terminals of the above output stage respectively.

[0088] If both amplifiers in the differential input pair 10 are PMOS tubes, then Figure 4 As shown, the two connection points of any two adjacent pairs of sixth switch tubes M6 serve as the two input terminals of the above output stage respectively.

[0089] It should be noted that the implementation of the above output stage is already very mature in the prior art, and its working principle will not be described in detail here.

[0090] The above is only a specific implementation of the above output stage. In practical applications, including but not limited to this, no specific limitation is made here. It can be determined according to the specific situation and is within the protection scope of this application.

[0091] The present application embodiment provides another specific implementation of the above output stage, and its specific structure can be found in Figure 5 ( Figure 5 Only in Figure 3 This embodiment is based on the above embodiment and further includes: to two seventh switch tubes M7. The connection relationship of each tube is as follows:

[0092] The two fifth switch tubes M5 whose sources receive the power supply voltage VCC are respectively connected in parallel with the two seventh switch tubes M7. The connection point of the gates of the two fifth switch tubes M5 whose sources receive the power supply voltage VCC is connected to the second output terminal of the output stage. The gates of the two seventh switch tubes M7 are connected, and the connection point is connected to the first output terminal of the output stage. Each seventh switch tube M7 and the fifth switch tube M5 connected to it are used for common mode feedback.

[0093] Each seventh switch tube M7 is a PMOS tube.

[0094] Optionally, each seventh switch tube M7 can be a MOS tube using FD-SOI technology. In practical applications, including but not limited to this, as long as it is a MOS tube, it is within the protection scope of this application. No specific limitation is made here and it may depend on the specific situation.

[0095] It should be noted that the implementation of the above output stage is already very mature in the prior art, and its working principle will not be described in detail here.

[0096] The above is only a specific implementation of the above output stage. In practical applications, including but not limited to this, no specific limitation is made here. It can be determined according to the specific situation and is within the protection scope of this application.

[0097] Another embodiment of the present application provides another implementation of a fully differential operational amplifier circuit, and its specific structure can be found in Figure 6 ( Figure 6 Only in Figure 5 This embodiment, based on the above embodiment, further includes: two first operational amplifiers 41.

[0098] The input terminals of the two first operational amplifiers 41 are respectively connected to the source electrodes of the two target PMOS tubes. The output voltages of the output terminals of the two first operational amplifiers 41 are respectively used to replace the bias voltages received by the gate electrodes of the two target PMOS tubes. The output terminals of the two first operational amplifiers 41 are also respectively connected to the back gate electrodes of the two target PMOS tubes.

[0099] The two PMOS tubes mentioned above are a pair of PMOS tubes respectively connected to the two output ends of the full differential operational amplifier circuit in the above output stage.

[0100] In this embodiment, since the gates of the two marked PMOS tubes respectively receive the output voltages of the output ends of the two first operational amplifiers 41, and the back gates of the two marked PMOS tubes are respectively connected to the output ends of the two first operational amplifiers 41, that is, the back gates of the two marked PMOS tubes are modulated, the output resistance of the two marked PMOS tubes is increased, thereby increasing the output resistance of the fully differential operational amplifier circuit, and further increasing the gain of the fully differential operational amplifier circuit.

[0101] Another embodiment of the present application provides another implementation of a fully differential operational amplifier circuit, and its specific structure can be found in Figure 7 ( Figure 7 Only in Figure 6 This embodiment, based on the above embodiment, further includes: two second operational amplifiers 42.

[0102] The input terminals of the two second operational amplifiers 42 are respectively connected to the source electrodes of the two target NMOS tubes. The output voltages of the output terminals of the two second operational amplifiers 42 are respectively used to replace the bias voltages received by the gate electrodes of the two target NMOS tubes. The output terminals of the two second operational amplifiers 42 are also respectively connected to the back gate electrodes of the two target NMOS tubes.

[0103] The two target NMOS tubes are two NMOS tubes respectively connected to the two output ends of the fully differential operational amplifier circuit in the above-mentioned output stage.

[0104] In this embodiment, since the gates of the two marked NMOS tubes respectively receive the output voltages of the output ends of the two second operational amplifiers 42, and the back gates of the two marked NMOS tubes are respectively connected to the output ends of the two second operational amplifiers 42, that is, the back gates of the two marked NMOS tubes are modulated, the output resistance of the two marked NMOS tubes is increased, thereby further increasing the output resistance of the fully differential operational amplifier circuit, and further increasing the gain of the fully differential operational amplifier circuit.

[0105] Another embodiment of the present application provides a specific implementation of an operational amplifier, which is applicable to each operational amplifier in a fully differential operational amplifier circuit. The specific structure of this implementation can be found in Figure 8a or Figure 8b , specifically including: four switching tubes M1~M2.

[0106] The gate of the first switch tube M1 is connected to the gate of the second switch tube M2, and the connection point receives a bias voltage corresponding to itself. The gate of the third switch tube M3 is connected to the gate of the fourth switch tube M4.

[0107] The source of the first switch tube M1 is connected to the source of the second switch tube M2. The source of the third switch tube M3 serves as the input end of the operational amplifier.

[0108] The drain of the first switch tube M1 is connected to the drain of the third switch tube M3. The drain of the second switch tube M2 is connected to the drain of the fourth switch tube M4, and the connection point serves as the output end of the operational amplifier.

[0109] Optionally, the first switch tube M1, the second switch tube M2, the third switch tube M3, and the fourth switch tube M4 can all be MOS tubes using FD-SOI technology. In practical applications, including but not limited to this, as long as they are MOS tubes, they are within the protection scope of this application. No specific limitation is made here and it depends on the specific situation.

[0110] The bias voltage received by the connection point between the gate of the first switch tube M1 and the gate of the second switch tube M2 is used to bias the first switch tube M1 and the second switch tube M2. The first switch tube M1 is used to provide current to the third switch tube M3, and the second switch tube M2 is used to provide current to the fourth switch tube M4. The second switch tube M2 and the fourth switch tube M4 constitute an amplifier circuit, and the third switch tube M3 is used to provide a correct voltage bias to the fourth switch tube M4, so that the operational amplifier operates in a low-voltage field.

[0111] If the input of the operational amplifier is connected to the corresponding PMOS tube, then Figure 8a As shown, the first switch tube M1 and the second switch tube M2 are both PMOS tubes, the third switch tube M3 and the fourth switch tube M4 are both NMOS tubes, the connection point between the source of the first switch tube M1 and the source of the second switch tube M2 receives the power supply voltage VCC, and the source of the fourth switch tube M4 is grounded GND.

[0112] If the input of the operational amplifier is connected to the corresponding NMOS tube, then Figure 8b As shown, the first switch tube M1 and the second switch tube M2 are both NMOS tubes, the third switch tube M3 and the fourth switch tube M4 are both PMOS tubes, the connection point between the source of the first switch tube M1 and the source of the second switch tube M2 is grounded GND, and the source of the fourth switch tube M4 receives the power supply voltage VCC.

[0113] The above is only a specific implementation of the operational amplifier. In practical applications, including but not limited to this, no specific limitation is made here and it may be determined according to the specific circumstances, all of which are within the protection scope of this application.

[0114] For the above description of the disclosed embodiments, the features recorded in each embodiment in this specification can be replaced or combined with each other, so that professionals in the field can implement or use the present application. The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with a preferred embodiment, it is not used to limit the present invention. Any technician familiar with the field can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A fully differential operational amplifier circuit, characterized in that: include: A differential input pair and two inverting amplifier circuits; wherein: The gate of the first amplifier tube and the gate of the second amplifier tube in the differential input pair respectively receive a first input signal and a second input signal, and the first input signal and the second input signal are differential signals; An input end of the first reverse amplifier circuit receives the first input signal, and an output end of the first reverse amplifier circuit is connected to a back gate of the second amplifier tube; The input end of the second reverse amplifier circuit receives the second input signal, and the output end of the second reverse amplifier circuit is connected to the back gate of the first amplifier tube.

2. The fully differential operational amplifier circuit according to claim 1, characterized in that: Also includes: Output stage; where: The drain of the first amplifier tube and the drain of the second amplifier tube are respectively connected to the two input terminals of the output stage; The two output ends of the output stage serve as the two output ends of the fully differential operational amplifier circuit respectively.

3. The fully differential operational amplifier circuit according to claim 2, characterized in that: Also includes: Two first operational amplifiers; wherein: The input terminals of the two first operational amplifiers are respectively connected to the sources of the two marked PMOS tubes; The output voltages of the output terminals of the two first operational amplifiers are used to replace the bias voltages received by the gates of the two target PMOS tubes respectively; The output ends of the two first operational amplifiers are also connected to the back gates of the two target PMOS tubes respectively; The two PMOS tubes mentioned above are a pair of PMOS tubes respectively connected to the two output ends of the fully differential operational amplifier circuit in the output stage.

4. The fully differential operational amplifier circuit according to claim 2, wherein: Also includes: Two second operational amplifiers; wherein: The input terminals of the two second operational amplifiers are respectively connected to the sources of the two marked NMOS tubes; The output voltages of the output terminals of the two second operational amplifiers are used to replace the bias voltages received by the gates of the two target NMOS transistors respectively; The output ends of the two second operational amplifiers are also connected to the back gates of the two target NMOS tubes respectively; The two target NMOS tubes are two NMOS tubes in the output stage respectively connected to the two output ends of the fully differential operational amplifier circuit.

5. The fully differential operational amplifier circuit according to claim 3 or 4, characterized in that: Each operational amplifier in the fully differential operational amplifier circuit includes: four switch tubes; wherein: The gate of the first switch tube is connected to the gate of the second switch tube, and the connection point receives a bias voltage corresponding to itself; The gate of the third switch tube is connected to the gate of the fourth switch tube; The source of the first switch tube is connected to the source of the second switch tube; The source of the third switch tube serves as the input end of the operational amplifier; The drain of the first switch tube is connected to the drain of the third switch tube; The drain of the second switch tube is connected to the drain of the fourth switch tube, and the connection point serves as the output end of the operational amplifier.

6. The fully differential operational amplifier circuit according to claim 5, characterized in that: If the input end of the operational amplifier is connected to the corresponding PMOS tube, the first switch tube and the second switch tube are both PMOS tubes, the third switch tube and the fourth switch tube are both NMOS tubes, the connection point between the source of the first switch tube and the source of the second switch tube receives the power supply voltage, and the source of the fourth switch tube is grounded; If the input end of the operational amplifier is connected to the corresponding NMOS tube, the first switch tube and the second switch tube are both NMOS tubes, the third switch tube and the fourth switch tube are both PMOS tubes, the connection point between the source of the first switch tube and the source of the second switch tube is grounded, and the source of the fourth switch tube receives the power supply voltage.

7. The fully differential operational amplifier circuit according to claim 2, characterized in that: The output stage includes: at least two pairs of fifth switch tubes and at least two pairs of sixth switch tubes; wherein: The gates of the two fifth switch tubes in each pair of the fifth switch tubes are connected, and the connection points receive a bias voltage corresponding to themselves; The fifth switch tubes located on one side of each pair of the fifth switch tubes are connected in series, the source of the formed series branch receives the supply voltage, and the drain of the formed series branch is connected to the first output end of the output stage; The fifth switch tubes located on the other side of each pair of the fifth switch tubes are connected in series, the source of the formed series branch receives the supply voltage, and the drain of the formed series branch serves as the second output end of the output stage; The gates of the two sixth switch tubes in each pair of the sixth switch tubes are connected, and the connection points receive a bias voltage corresponding to themselves; The sixth switch tubes located on one side of each pair of the sixth switch tubes are connected in series, the source of the formed series branch is grounded, and the drain of the formed series branch is connected to the first output end of the output stage; The sixth switch tubes located at the other side of each pair of the sixth switch tubes are connected in series, the source of the formed series branch is grounded, and the drain of the formed series branch is connected to the second output end of the output stage; The two connection points of any two adjacent pairs of the fifth switch tubes are respectively used as the two input ends of the output stage, or the two connection points of any two adjacent pairs of the sixth switch tubes are respectively used as the two input ends of the output stage; Each pair of the fifth switch tubes are PMOS tubes, and each pair of the sixth switch tubes are NMOS tubes.

8. The fully differential operational amplifier circuit according to claim 7, characterized in that: The output stage further includes: two seventh switch tubes; wherein: The two fifth switch tubes whose sources receive the power supply voltage are respectively connected in parallel with the two seventh switch tubes; A connection point of the gates of the two fifth switch tubes whose sources receive the power supply voltage is connected to the second output end of the output stage; The gate electrodes of the two seventh switch tubes are connected, and the connection point is connected to the first output terminal of the output electrode; Each seventh switch tube is a PMOS tube.

9. The fully differential operational amplifier circuit according to any one of claims 1 to 8, characterized in that: Each of the reverse amplifier circuits comprises: an eighth switch tube and a third amplifier tube; wherein: The drain of the eighth switch tube is connected to the drain of the third amplifier tube; In the eighth switch tube and the third amplifier tube, one source receives the power supply voltage and the other source is grounded.

10. The fully differential operational amplifier circuit according to claim 9, characterized in that: If both amplifier tubes in the differential input pair are NMOS tubes, the third amplifier tube is an NMOS tube, the eighth switch tube is a PMOS tube, the source of the third amplifier tube is grounded, and the source of the eighth switch tube receives the power supply voltage; If both amplifier tubes in the differential input pair are PMOS tubes, the third amplifier tube is a PMOS tube, the eighth switch tube is an NMOS tube, the source of the third amplifier tube receives the power supply voltage, and the source of the eighth switch tube is grounded.

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