Cascade structure delay circuit and signal delay method applied to multi-stage delay unit

Abstract

The embodiment of the invention discloses a cascade structure delay circuit, a signal delay method applied to a multi-stage delay unit, semiconductor test equipment and a time sequence generation chip, the circuit comprises a clock source, a signal input source and the multi-stage delay unit, and the multi-stage delay unit comprises at least two delay units connected in a cascade mode; the signal input end of the first-stage delay unit in the multiple stages of delay units is connected with a signal input source; and each delay unit in the multiple stages of delay units is used for delaying an input signal according to the delay configuration value received by the respective delay time configuration end, outputting a delayed output signal, and updating the delay configuration value according to the update interval time set by each delay unit. According to the embodiment of the invention, the overall delay precision and delay time range of the multi-stage delay unit is expanded, and the time precision of the synthetic waveform of the time sequence generation device of the semiconductor test equipment is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a cascade structure delay circuit, a signal delay method applied to a multi-stage delay unit, and a semiconductor test device and a timing generation chip. Background Art

[0002] The timing generator (TG) is an important component of semiconductor test equipment. It is responsible for synthesizing the output waveform according to user requirements and sampling the input signal according to the sampling time configured by the user, with a time resolution of up to ps level.

[0003] Currently, TG is usually implemented with a dedicated integrated circuit, and its functional architecture is to first adjust the time delay of the level signal representing the data, and then convert the adjusted signal into the required waveform format for output. The timing of the edge of the output signal is controlled by adjusting the clock phase.

[0004] Signal delay adjustment can also be achieved through a delay function module inside a general programmable logic device. For example, some FPGAs usually include delay units, which can be divided into input delay units (IDELAY) and output delay units (ODELAY). However, when the delay unit updates the delay configuration value (tap value), it usually takes at least multiple reference clock cycles. In the scenario where the delay configuration value needs to be updated continuously and quickly, the current delay function module cannot achieve a more flexible setting of the interval time for updating the delay configuration value, nor can it shorten the interval time between two updates of the delay configuration value. Summary of the invention

[0005] To solve the above problems, an embodiment of the present disclosure provides a cascade structure delay circuit, which includes: a clock source, a signal input source, and a multi-stage delay unit, wherein the multi-stage delay unit includes at least two delay units connected in a cascade manner; each delay unit in the multi-stage delay unit includes a clock input terminal and a delay time configuration terminal, the clock input terminal is connected to the clock source, and the delay time configuration terminal is used to receive delay configuration information, the delay configuration information is used to set a delay configuration value representing the delay time of the delay unit, and an update interval time of the delay configuration value, and the update interval time is a time set based on a reference clock signal output by the clock source; the signal input terminal of the first-stage delay unit in the multi-stage delay unit is connected to the signal input source; each delay unit in the multi-stage delay unit is used to delay the input signal according to the delay configuration value received by the respective delay time configuration terminals, output the delayed output signal, and update the delay configuration value according to the update interval time of each delay unit, wherein the time difference for updating the delay configuration value between any two delay units in the multi-stage delay unit is less than or equal to the update interval time.

[0006] In some embodiments, the multiple stages of delay cells are connected in series.

[0007] In some embodiments, the circuit also includes at least one buffer unit, each buffer unit in the at least one buffer unit is located between two adjacent delay units, and the two delay units connected to each buffer unit are different; each buffer unit in the at least one buffer unit is used to forward the signal output by the upper delay unit of the two connected delay units to the lower delay unit in the adjacent delay unit.

[0008] In some embodiments, the multi-stage delay unit includes at least one input delay unit and at least one output delay unit; each buffer unit in at least one buffer unit is located between an output delay unit and an input delay unit, and the upper-level delay unit of the buffer unit includes the output delay unit, and the lower-level delay unit of the buffer unit includes the input delay unit.

[0009] In some embodiments, the buffer unit in at least one buffer unit is further used to: output a signal received from a connected upper-level delay unit, or receive a signal input from outside the cascade structure delay circuit; the buffer units in at least one buffer unit respectively include a signal transmission control terminal and a signal external port; the buffer unit in at least one buffer unit is further used to: output a signal received from a connected upper-level delay unit from the signal external port, or send a signal received from the signal external port to a connected lower-level delay unit according to a control signal received from the signal transmission control terminal.

[0010] In some embodiments, the input delay unit includes a first signal input terminal and a second signal input terminal; when the first-level delay unit is an input delay unit, the next-level delay unit of the first-level delay unit is an output delay unit, and the first-level delay unit is used to: receive a signal from a signal input source through the first signal input terminal, and send the received signal to the next-level delay unit of the first-level delay unit; when other delay units except the first-level delay unit in the multi-level delay unit include an input delay unit, the input delay unit included in the other delay units is used to: receive a signal sent by a corresponding buffer unit through the second signal input terminal.

[0011] In some embodiments, the output delay unit includes a third signal input terminal; when the first-level delay unit is an output delay unit, the first-level delay unit is used to: receive a signal from a signal input source through the third signal input terminal of the first-level delay unit, and send the received signal to the corresponding buffer unit.

[0012] In some embodiments, the circuit also includes a control unit, which is used to: determine whether there is a target delay unit that meets the update conditions in the multi-stage delay unit; if there is a target delay unit, send an update signal and a delay configuration value to the target delay unit, wherein the update conditions include: the time difference between the time when the target delay unit last updated the delay configuration value and the current time is greater than or equal to the update interval time corresponding to the target delay unit; the target delay unit is used to: in response to receiving the update signal and the delay configuration value, delay the input signal according to the received delay configuration value.

[0013] In some embodiments, the control unit is further configured to: send an update signal and a delay configuration value to a delay unit in the multi-stage delay unit in each clock cycle of the reference clock signal.

[0014] According to another aspect of an embodiment of the present disclosure, a signal delay method applied to a multi-stage delay unit is provided, the method comprising: based on preset delay configuration information, setting a delay configuration value and an update interval time corresponding to each delay unit in the multi-stage delay unit, wherein the update interval time is a time set based on a reference clock signal output by a preset clock source; receiving an input signal through a signal input end of a first-stage delay unit of the multi-stage delay unit, and delaying the input signal by each delay unit in the multi-stage delay unit to output a delayed output signal; in response to the current time reaching the update time of any delay unit in the multi-stage delay unit, updating the original delay configuration value based on the currently received delay configuration value, wherein the difference between the time of currently updating the delay configuration value and the time of last updating the delay configuration value is less than or equal to the update interval time.

[0015] In some embodiments, the method further includes: for a target output delay unit connected to a buffer unit included in the multi-stage delay unit, outputting a delayed output signal output by the target output delay unit through the buffer unit; or, inputting a signal input from outside the cascade structure delay circuit to a target input delay unit connected to the buffer unit through the buffer unit.

[0016] According to another aspect of an embodiment of the present disclosure, a test device is provided, which includes: a signal input module, a clock source module, a timing generation module, a timing control module, a test drive module, and an analysis module, wherein the timing generation module includes a multi-stage delay unit, and the signal input module, the clock source module and the multi-stage delay unit constitute the above-mentioned cascade structure delay circuit; a timing control module, which is used to calculate the delay time according to the input timing setting information; generate delay configuration information based on the delay time; send the delay configuration information to the timing generation module; the timing generation module, which is used to delay the electrical signal of the input signal, and input the electrical signal of the delayed output signal into the test drive module; the test drive module, which is used to generate a test excitation signal according to the received electrical signal of the output signal, and send the test excitation signal to the device under test; receive a response signal returned by the device under test, and send the response signal to the timing generation module; the timing generation module, which is further used to sample the response signal to obtain a sampled signal, and send the sampled signal to the analysis module; the analysis module, which is used to compare the sampled signal with the input signal to generate test result information.

[0017] According to another aspect of an embodiment of the present disclosure, a timing generation chip is provided, wherein the timing generation chip includes the above-mentioned cascade structure delay circuit.

[0018] The cascade structure delay circuit, signal delay method applied to multi-stage delay unit, semiconductor test equipment and timing generation chip provided by the above embodiments of the present disclosure, by setting a multi-stage delay unit, multiple delay units are connected in a cascade manner, the signal input end of the multi-stage delay unit receives a signal from a signal input source, each delay unit delays according to the delay configuration value received by its own delay time configuration end, and updates the delay configuration value. Since each delay unit included in the multi-stage delay unit can independently update the delay configuration value, therefore, the embodiment of the present disclosure can shorten the time difference between any two updates of the delay configuration value of the multi-stage delay unit to less than or equal to the update interval time of each delay unit, thereby effectively compressing the reference clock cycle consumed by each update of the delay time of the entire multi-stage delay unit, and can more accurately adjust the time corresponding to the signal edge of the output signal, expand the overall delay accuracy and delay time range of the multi-stage delay unit, and help improve the time accuracy of the synthesized waveform of the timing generation device of the semiconductor test equipment.

[0019] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps;

[0021] Figure 1 is a structural diagram of a cascade structure delay circuit provided by an exemplary embodiment of the present disclosure;

[0022] Figure 2 is another structural schematic diagram of a multi-stage delay unit provided by an exemplary embodiment of the present disclosure;

[0023] Figure 3A is an exemplary timing diagram of the relationship between an input signal, an output signal and a delay time provided by an exemplary embodiment of the present disclosure;

[0024] Figure 3B is an exemplary timing diagram of a transmission signal of a three-stage delay unit provided by an exemplary embodiment of the present disclosure;

[0025] Figure 4 is another structural schematic diagram of a multi-stage delay unit provided by an exemplary embodiment of the present disclosure;

[0026] Figure 5A is a structural schematic diagram of a cascade structure delay circuit including a buffer unit provided by an exemplary embodiment of the present disclosure;

[0027] Figure 5B is a schematic structural diagram of a buffer unit provided by an exemplary embodiment of the present disclosure;

[0028] Fig. 6A is a structural schematic diagram of a cascade structure delay circuit in which a first-stage delay unit is an input delay unit provided by an exemplary embodiment of the present disclosure;

[0029] Figure 6B It is a structural schematic diagram of a cascade structure delay circuit in which a first-stage delay unit is an output delay unit provided by an exemplary embodiment of the present disclosure;

[0030] Figure 7 is a flow chart of a signal delay method applied to a multi-stage delay unit provided by an exemplary embodiment of the present disclosure;

[0031] Figure 8 It is a schematic structural diagram of a semiconductor testing device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0033] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0034] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0035] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0036] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0037] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0038] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0039] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0040] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0041] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0042] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0043] Application Overview

[0044] In some current FPGAs, the delay of the transmission signal can be adjusted through IDELAY / ODELAY resources. When the delay length of a single IDELAY or ODELAY does not meet the delay requirements, the IDELAY / ODELAY can be cascaded. However, the current cascade scheme takes a long time to change the signal delay. For example, in the TIME mode of the delay unit, it takes at least 20 reference clock cycles; in the COUNT mode, it takes at least 3 reference clock cycles. Therefore, the current delay scheme cannot update the delay time more quickly, and cannot control the edge position of the output signal with high precision.

[0045] The disclosed embodiment aims to solve this problem. By updating the delay configuration value of the multi-stage delay unit, the time difference between any two updates of the delay configuration value of the multi-stage delay unit can be shortened to less than or equal to the update interval time of each delay unit, effectively compressing the reference clock cycle consumed by the entire multi-stage delay unit for each update of the delay time, and the moment corresponding to the signal edge of the output signal can be adjusted more accurately, thereby expanding the overall delay accuracy and delay time range of the multi-stage delay unit, which helps to improve the time accuracy of the synthesized waveform of the timing generation device of the semiconductor testing equipment.

[0046] Exemplary Circuit Configuration

[0047] Figure 1 The schematic diagram of the structure of the cascade structure delay circuit provided by an exemplary embodiment of the present disclosure is shown in FIG. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

[0048] like Figure 1 As shown, the circuit includes: a clock source 101, a signal input source 102, and a multi-stage delay unit 103. The clock source 101 can be a circuit that generates a clock signal, such as a crystal oscillator, etc. The signal input source 102 can be a circuit that generates or transmits a digital signal, such as a level signal representing data generated or transmitted in an FPGA.

[0049] The multi-stage delay unit 103 includes at least two delay units connected in a cascade manner. The delay unit may be a circuit for changing the edge position of a signal. For example, the edge of the initial signal changing from a low level to a high level is at time t0. After inputting the delay unit, after delay, the edge of the output signal changing from a low level to a high level is at time t0+δt.

[0050] There are many ways to cascade the delay units. For example, Figure 2 Connect as shown. Figure 2 In the figure, the first-stage delay unit receives the signal input from the signal input source 102 through the input port DATAIN, and then outputs the signal to the input port CASC_IN of the second-stage delay unit through the output port CASC_OUT. The second-stage delay unit then returns the signal to another input port CASC_RETURN of the first-stage delay unit through the output port DATAOUT, and finally outputs the signal from another output port DATAOUT of the first-stage delay unit.

[0051] Optional, such as Figure 1 As shown, the multi-stage delay units 103 are connected in series in sequence, that is, the signal output by the delay unit of the previous stage is used as the input signal of the delay unit of the next stage. Figure 1 The circuit shown includes N-stage delay units. The connection between the delay units can be direct connection (i.e., the signal output end of the previous delay unit is connected to the signal input end of the next delay unit) or indirect connection (e.g., a signal buffer unit is set between two delay units). By implementing the multi-stage delay unit 103 in series, the connection between the delay units can be more flexible, the number of delay units can be more easily expanded, and the setting method of the delay unit is simpler, thereby improving the flexibility of the use of the cascade structure delay circuit.

[0052] In this embodiment, each delay unit in the multi-stage delay unit 103 includes a clock input terminal and a delay time configuration terminal, the clock input terminal is connected to the clock source 101, and the delay time configuration terminal is used to receive delay configuration information. The clock source 101 can provide a reference clock signal to the delay unit. The delay configuration information can set a delay configuration value representing the delay time of the delay unit, and an update interval time of the delay configuration value, the update interval time refers to the time interval between two operations of updating the delay configuration value of a single delay unit, and the update interval time is usually determined based on the reference clock signal output by the clock source. As an example, for a certain delay unit, the update interval time of its delay configuration value is equal to three clock cycles of the reference clock signal, that is, at least three clock cycles are required to effectively perform an operation of updating the delay configuration value. Generally, the update interval time can be related to the update mode of the delay unit set by the delay configuration value. For example, in an FPGA, the delay unit needs to be at least 20 reference clock cycles in TIME mode to update the delay configuration value; in COUNT mode, it needs to be at least 3 reference clock cycles in order to update the delay configuration value.

[0053] The delay configuration information may be received from an external input of the cascade structure delay circuit, for example, from a controller for controlling the operation of the cascade structure delay circuit. Figure 1 As shown, S_1, S_2, ..., S_N are input delay configuration information.

[0054] In this embodiment, if Figure 1 As shown, the signal input end of the first-stage delay unit in the multi-stage delay unit 103 is connected to the signal input source 102. Each delay unit in the multi-stage delay unit 103 is used to delay the input signal according to the delay configuration value received by the respective delay time configuration end, output the delayed output signal, and update the delay configuration value according to the update interval time set by each delay unit. Among them, the time difference between any two delay units in the multi-stage delay unit 103 for updating the delay configuration value is less than or equal to the update interval time. As shown in the above example, the delay unit in the COUNT mode needs to spend at least 3 reference clock cycles to update the delay configuration value, that is, the update interval time is 3 reference clock cycles. If the multi-stage delay unit 103 includes three delay units, after one delay unit updates the delay configuration value, the delay configuration value of another delay unit can be updated after one, two or three clock cycles, so as to achieve the purpose of treating the multi-stage delay unit as a whole and shortening the time difference between two updates of the delay configuration value.

[0055] Usually, each delay unit is provided with a tap delay line. Multiple delay units are connected in series, that is, multiple tap delay lines are connected in series to form a longer tap delay line. The tap delay line can establish a signal transmission path of corresponding length according to the input delay configuration value (tap value), which means that when the electrical signal of the input signal is transmitted through the transmission path, it will consume a corresponding delay time, so that when the delay unit is actually applied, the level duration of the signal can be extended. For example, Figure 3A As shown, the rising edge of the original level signal of the input signal received by the delay unit is at time t1, and the falling edge is at time t2. At a certain time before time t1, the tap value is updated, and the delay unit delays the low-level signal according to the tap value, that is, the duration of the low-level signal is extended by the corresponding delay time, and the rising edge position of the signal is delayed to time t3. Some time after time t3, the tap value is updated again, and the delay unit delays the high-level signal according to the new tap value, that is, the duration of the high-level signal is extended by the corresponding delay time, and the falling edge position of the signal is delayed to time t4.

[0056] The circuit provided by the above-mentioned embodiment of the present disclosure sets a multi-stage delay unit, connects the multiple delay units in a cascade manner, the signal input end of the multi-stage delay unit receives a signal from a signal input source, and each delay unit delays according to the delay configuration value received by its own delay time configuration end, and updates the delay configuration value. Since each delay unit included in the multi-stage delay unit can independently update the delay configuration value, the embodiment of the present disclosure can shorten the time difference between any two updates of the delay configuration value of the multi-stage delay unit to less than or equal to the update interval time, thereby effectively compressing the reference clock cycle consumed by each update of the delay time of the entire multi-stage delay unit, and can more accurately adjust the time corresponding to the signal edge of the output signal, thereby expanding the overall delay accuracy and delay time range of the multi-stage delay unit, and helping to improve the time accuracy of the waveform when the timing generation device of the semiconductor test equipment is synthesized.

[0057] In some optional implementations, such as Figure 4 As shown, the circuit further includes a control unit 104, and the control unit 104 is used for:

[0058] Determine whether there is a target delay unit that meets the update condition in the multi-level delay unit. If there is a target delay unit, send an update signal and a delay configuration value to the target delay unit, wherein the update condition includes: the time difference between the time when the target delay unit last updated the delay configuration value and the current time is greater than or equal to the update interval time corresponding to the target delay unit.

[0059] The target delay unit is used to:

[0060] In response to receiving the update signal and the delay configuration value, the input signal is delayed according to the received delay configuration value.

[0061] Specifically, for a certain delay unit, when the delay unit needs to delay the input signal, the control unit 104 can determine whether the delay unit currently meets the update condition. If the update condition is met, an update signal and a delay configuration value are sent to the delay unit. The update signal can be triggered in various ways. For example, in an FPGA, if the delay unit receives a load signal, the load signal can be used as an update signal to instruct the delay unit to update the tap value. For another example, the received tap value itself can be used as an update signal. If a new tap value is received, the input signal can be delayed according to the new tap value when the update time corresponding to the current update interval time is reached.

[0062] Typically, the control unit 104 can monitor in real time whether each delay unit meets the update condition, that is, to judge the update condition of each delay unit in turn, and the delay unit for which the update condition judgment is currently being performed is the target delay unit, that is, to judge whether the time elapsed from the moment when the target delay unit last updated the delay configuration value to the current moment is greater than or equal to the interval time required to update the delay configuration value (that is, the update interval time). It should be noted that, for a delay unit, the delay configuration value before the update and the delay configuration value after the update can be the same or different, and need to be set according to the actual application scenario.

[0063] In this embodiment, the control unit 104 determines the update condition of each delay unit, and sends an update signal and a delay configuration value to the delay unit when the update condition is met, thereby achieving flexible and accurate control of the update time of the delay configuration value.

[0064] In some optional implementations, the control unit 104 is further configured to:

[0065] In each clock cycle of the reference clock signal, an update signal and a delay configuration value are sent to a delay unit in the multi-stage delay unit.

[0066] like Figure 3B As shown, it shows a timing diagram of the three-level delay unit alternatingly updating the delay configuration value. Among them, tapA (including tapA1, tapA2...), tapB (including tapB1, tapB2...), tapC (including tapC1, tapC2...) are the delay configuration values ​​of the first-level delay unit, the second-level delay unit, and the third delay unit, respectively. As shown in the figure, the update interval time of the delay configuration value of each delay unit is three reference clock cycles. The first reference clock cycle corresponds to the first-level delay unit. At the end of the first reference clock cycle, the first-level delay unit meets the update condition. At this time, the control unit 104 sends an update signal and the delay configuration value tapA2 to the first-level delay unit, and the delay configuration value of the first-level delay unit changes from tapA1 to tapA2;

[0067] The second reference clock cycle corresponds to the second-stage delay unit. At the end of the second reference clock cycle, the second-stage delay unit meets the update condition. At this time, the control unit 104 sends an update signal and a delay configuration value tapB2 to the second-stage delay unit, and the delay configuration value of the second-stage delay unit changes from tapB1 to tapB2.

[0068] The third reference clock cycle corresponds to the third-level delay unit. At the end of the third reference clock cycle, the third-level delay unit meets the update condition. At this time, the control unit 104 sends an update signal and a delay configuration value tapC2 to the third-level delay unit, and the delay configuration value of the second-level delay unit changes from tapC1 to tapC2.

[0069] According to this rule, at the end of each cycle of the reference clock, the delay configuration value is updated in the order of tapA1, tapB1, tapC1, tapA2, tapB2, tapC2, tapA3, tapB3, tapC3, ... It should be understood that Figure 3B The reference clock signal shown is used to provide an update interval for each delay unit to update the delay configuration value, rather than to provide a timing cycle for the delay time of the delay unit. That is, after each update interval is reached and the delay configuration value is updated, the delay unit delays the input signal according to the new delay configuration value and outputs a delayed output signal.

[0070] It should be noted that Figure 3B The timing of updating the tap value shown is a special case, that is, at the end of each reference clock cycle, the update condition of a delay unit is met, that is, at the end of each reference clock cycle, the tap value of a delay unit can be updated. In actual scenarios, whether the tap value needs to be updated depends on the actual situation. The control unit 104 needs to send an update signal. For example, Figure 3B At the end of the fourth clock cycle shown, the delay configuration value of the first-level delay unit is updated from tapA2 to tapA3. At this time, if the time interval between the second-level delay unit or the third-level delay unit and the last update of the tap value is greater than three reference clock cycles, the tap value can be updated together with the first-level delay unit.

[0071] This embodiment updates the delay configuration value by different delay units in sequence according to the clock cycle of the reference clock signal, thereby minimizing the time interval for updating the delay configuration value and reducing the time consumed in updating the delay configuration value, thereby further improving the accuracy of adjusting the delay time of the input signal.

[0072] In some optional implementations, the circuit further includes at least one buffer unit, and each buffer unit in the at least one buffer unit is located between two adjacent delay units.

[0073] Each buffer unit in the at least one buffer unit is used to forward a signal output by an upper delay unit in two connected delay units to a lower delay unit in an adjacent delay unit.

[0074] like Figure 5AAs shown, a buffer unit is connected between the first-stage delay unit and the second-stage delay unit, the buffer unit is connected to the signal output end of the first-stage delay unit and the signal input end of the second-stage delay unit, the first-stage delay unit is the upper-stage delay unit of the buffer unit, and the second-stage delay unit is the lower-stage delay unit of the buffer unit. A buffer unit is also connected before the N-stage delay unit, that is, the N-stage delay unit is the lower-stage delay unit of the buffer unit.

[0075] In this embodiment, by providing a buffer unit between two adjacent delay units, the waveform of the signal transmitted between the delay units can be made more stable, and the signal can be extracted from the buffer unit as required, thereby improving the application flexibility of the delay circuit.

[0076] In some optional implementations, the multi-stage delay unit 103 includes at least one input delay unit and at least one output delay unit.

[0077] Each buffer unit in the at least one buffer unit is located between an output delay unit and an input delay unit, and the upper delay unit of the buffer unit includes the output delay unit, and the lower delay unit of the buffer unit includes the input delay unit.

[0078] like Fig. 6A and Figure 6B As shown, IDELAY is an input delay unit and ODELAY is an output delay unit. Usually, one IDELAY corresponds to one ODELAY, and the corresponding IDELAY and ODELAY are set in the same delay module. For example, in an FPGA, multiple BITSLICEs are included, each BITSLICE includes an IDELAY and an ODELAY, that is, a bit slice can include a delay module, in which the IDELAY is used to receive the signal of the input bit slice, and the ODELAY is used to output the signal in the bit slice. In order to transmit the signal between BITSLICEs, a buffer unit (IOBUF) can be set between the BITSLICEs, that is, an IOBUF is set between the ODELAY of one BITSLICE and the IDELAY of another BITSLICE. IOBUF receives the signal from its upper delay unit ODELAY and forwards the signal to its lower delay unit IDELAY.

[0079] By setting the buffer unit between the output delay unit and the input delay unit, this embodiment can connect different delay modules in series through the buffer unit when an input delay unit and an output delay unit are set in the same delay module, thereby greatly improving the utilization rate of the delay module inside the logic device and improving the application flexibility of the entire delay circuit.

[0080] In some optional implementations, the buffer unit in at least one buffer unit is further used to: output a signal received from a connected upper-level delay unit, or receive data input from outside the cascade structure delay circuit.

[0081] like Figure 5B As shown, the buffer unit includes an I / O port, which can be connected to other devices to output the signal output by the upper delay unit of the buffer unit to other devices; or receive input signals from other devices and input the received signals into the lower delay unit of the buffer unit.

[0082] By utilizing the buffer unit, this embodiment can directly output the signal of a delay unit located at an intermediate level from a plurality of delay units connected in series. The output signal is not delayed by the delay unit at the lower level. Therefore, the position of the level edge of the output signal can be made more diverse, thereby greatly improving the flexibility of setting the delay time and further expanding the application scope of the delay circuit; it can also receive input data from other devices, thereby expanding the source of data input.

[0083] The buffer units in the at least one buffer unit mentioned above each include a signal transmission control terminal and a signal external connection port. The signal transmission control terminal is used to control the change of the path of the signal flow of the buffer unit, and the signal external connection port is used to output the signal received from the upper delay unit to the outside of the multi-stage delay unit. Figure 5B As shown, the T port is the signal transmission control port, and the I / O port is the signal external connection port.

[0084] The buffer unit in at least one buffer unit is further configured to:

[0085] According to the control signal received by the signal transmission control terminal, the signal received from the connected upper delay unit is output from the signal external connection port, or the signal received from the signal external connection port is sent to the connected lower delay unit.

[0086] As an example, the structure of the buffer unit can be as follows Figure 5B As shown, I is the input port, which is connected to the upper delay unit of the buffer unit, and O is the output port, which is connected to the lower delay unit of the buffer unit. G1 and G2 are the input buffer gate and the output buffer gate, respectively, and T is the signal transmission control terminal. For example, when T is 0 (low level), G1 is turned on, and the signal output by the previous delay unit can be input from the I port to the next delay unit through the O port, or output to the external circuit through the I / O port. When T is 1 (high level), G1 is in a high-impedance state, and the signal of the external circuit can be input into the buffer unit from the I / O port, and input into the lower delay unit from the O port.

[0087] By setting a signal transmission control terminal and a signal external port, this embodiment can flexibly control the change of the signal transmission path of the buffer unit, and effectively output the signal transmitted by the intermediate-stage delay unit of the multi-stage delay unit to the external circuit or input data from the external circuit to the intermediate-stage delay unit, thereby improving the flexibility of circuit application.

[0088] In some optional implementations, the input delay unit includes a first signal input terminal and a second signal input terminal;

[0089] When the first-stage delay unit is an input delay unit, the next-stage delay unit of the first-stage delay unit is an output delay unit, and the first-stage delay unit is used to: receive a signal from a signal input source 102 through a first signal input terminal, and send the received signal to the next-stage delay unit of the first-stage delay unit.

[0090] When other delay units except the first-stage delay unit in the multi-stage delay unit 103 include an input delay unit, the input delay unit included in the other delay units is used to receive a signal sent by a corresponding buffer unit through the second signal input terminal.

[0091] like Fig. 6A As shown, IDELAY1 is a first-stage delay unit, ODELAY is a second-stage delay unit, and both IDELAY1 and IDELAY2 include a first signal input terminal DATAIN and a second signal input terminal IDATAIN. The DATAIN terminal of IDELAY1 is connected to the signal input source 102, and the IDATAIN terminal of IDELAY2 is connected to the buffer unit IOBUF. Usually, according to the characteristics of the delay unit in the FPGA, the DATAIN terminal cannot receive the signal input from the IOBUF, so the DATAIN terminal can be directly connected to the signal input source. The IDATAIN terminal cannot directly receive the signal from the signal input source, and can only receive the signal input from the IOBUF. Therefore, inside the signal path of the multi-stage delay unit, the IDATAIN terminal of IDELAY needs to receive the signal of the connected buffer unit to realize the series connection of the multi-stage delay unit.

[0092] In this embodiment, when the first-stage delay unit is an input delay unit, the first signal input terminal receives the signal from the signal input source, and the second signal input terminals of other input delay units other than the first-stage delay unit receive the signal from the buffer unit. This effectively utilizes the characteristics of the input delay unit to realize the series connection of multiple-stage delay units, thereby reducing the difficulty of setting up the multiple-stage delay units and facilitating the stable output of delayed signals.

[0093] In some optional implementations, the output delay unit includes a third signal input terminal.

[0094] When the first-stage delay unit is an output delay unit, the first-stage delay unit is used to:

[0095] The signal from the signal input source 102 is received through the third signal input terminal of the first-stage delay unit, and the received signal is sent to the corresponding buffer unit.

[0096] like Figure 6B As shown, ODELAY1 is a first-stage delay unit, IDELAY is a second-stage delay unit, and a buffer unit IOBUF is between ODELAY1 and IDELAY. The ODATAIN terminals of ODELAY1 and ODELAY2 are the third signal input terminals, the ODATAIN terminal of ODELAY1 is connected to the signal input source 102, and the ODATAIN terminal of ODELAY2 is connected to the signal output terminal of IDELAY. Generally, according to the characteristics of the delay unit in the FPGA, the ODATAIN terminal can receive a signal input from the signal input source, and can also receive a signal input from IDELAY. Therefore, through the ODATAIN terminal of ODELAY, the series connection of multiple delay units can be realized.

[0097] In this embodiment, when the first-stage delay unit is an output delay unit, the third signal input terminal receives the signal from the signal input source, and the output delay units of other stages also receive the signal through the third signal input terminal, thereby effectively utilizing the characteristics of the output delay unit to realize the series connection of multiple stages of delay units, without setting different signal input terminals for the same type of delay units, thereby further reducing the difficulty of setting multiple stages of delay units and facilitating the stable output of delayed signals.

[0098] Exemplary Methods

[0099] Figure 7 FIG. 1 is a flow chart of a signal delay method applied to a multi-stage delay unit provided by an exemplary embodiment of the present disclosure. This embodiment can be applied in Figure 1 The cascade structure delay circuit is shown in Figure 1. Figure 7 As shown, the method comprises the following steps:

[0100] Step 701: Based on preset delay configuration information, set the delay configuration value and update interval time corresponding to each delay unit included in the multi-stage delay unit.

[0101] The update interval is based on a preset clock source (such as Figure 1The reference clock signal output by the clock source 101 shown in the figure is set at a time. For a delay unit, the delay configuration value is updated once at each update interval. Usually, a tap delay line (Tap Delay Line) is provided in each delay unit. The tap delay line can establish a signal transmission path of corresponding length according to the input delay configuration value (tap value), indicating that when the electrical signal of the input signal is transmitted through the transmission path, a corresponding delay time will be consumed, so that when the delay unit is actually applied, the level duration of the signal can be extended.

[0102] like Figure 3B As shown, the first-level delay unit updates the tap value at the beginning of clock cycles with cycle numbers of 2, 5, and 8 of the reference clock signal, the second-level delay unit updates the tap value at the beginning of clock cycles with cycle numbers of 3, 6, and 9 of the reference clock signal, and the third-level delay unit updates the tap value at the beginning of clock cycles with cycle numbers of 4, 7, and 10 of the reference clock signal.

[0103] Step 702: receiving an input signal through a signal input terminal of a first-stage delay unit of a multi-stage delay unit, and delaying the input signal by each delay unit in the multi-stage delay unit to output a delayed output signal.

[0104] like Figure 1 As shown, the first delay unit of the multi-stage delay unit receives an input signal from a signal input source, the signal output terminal of the last delay unit outputs a delayed output signal, and the intermediate delay unit inputs the delayed signal to the next delay unit.

[0105] Step 703 , in response to the current time reaching the update time of any delay unit in the multi-stage delay unit, the original delay configuration value is updated based on the currently received delay configuration value.

[0106] Among them, the difference between the time of currently updating the delay configuration value and the time of last updating the delay configuration value is less than or equal to the update interval time. For example, in FPGA, the delay unit in COUNT mode requires at least 3 reference clock cycles to update the delay configuration value, that is, the update interval time is 3 reference clock cycles. If the multi-stage delay unit 103 includes three delay units, then after one delay unit updates the delay configuration value, the delay configuration value of another delay unit can be updated after one, two or three clock cycles, thereby achieving the purpose of shortening the time difference between two updates of the delay configuration value by taking the multi-stage delay unit as a whole. Specifically, for a delay unit, if the current time reaches the update time of the delay unit, the delay configuration value of the delay unit is updated, and according to the updated delay configuration value, the delay unit delays the current input signal. Usually, the delay unit can receive the following Figure 4The control unit 104 sends an update signal, and when the delay unit receives the update signal, it can update the delay configuration value according to the reference clock signal when the update time is reached (for example, the rising edge or falling edge of the current clock cycle). Regarding the relationship between the edge positions of the input signal, the output signal and the delayed level signal, and the example of each delay unit alternately updating the delay configuration value, reference can be made to the above embodiment. Figure 3A and Figure 3B The description will not be repeated here.

[0107] The method provided by the above-mentioned embodiment of the present disclosure sets the delay configuration value and update interval time corresponding to each delay unit included in the multi-stage delay unit, and updates the original delay configuration value based on the currently received delay configuration value when any delay unit reaches the update time according to the update interval time. Since the operation of updating the delay configuration value is performed by the multi-stage delay unit, and each delay unit can independently update the delay configuration value, the embodiment of the present disclosure can shorten the time difference between any two updates of the delay configuration value of the multi-stage delay unit to be less than or equal to the update interval time, thereby effectively compressing the reference clock cycle consumed by each update of the delay time of the entire multi-stage delay unit, and can accurately adjust the time corresponding to the signal edge of the output signal, thereby expanding the overall delay accuracy and delay time range of the multi-stage delay unit, which helps to improve the time accuracy of the waveform when the timing generation device of the semiconductor test equipment is synthesized.

[0108] Optionally, the method further includes:

[0109] For the target output delay unit connected to the buffer unit included in the multi-stage delay unit 103, the delayed output signal output by the target output delay unit is output through the buffer unit; or, the signal input from the outside of the above-mentioned cascade structure delay circuit is input to the target input delay unit connected to the buffer unit through the buffer unit.

[0110] Specifically, Fig. 6A As shown, ODELAY is connected to IOBUF, so ODELAY is the target output delay unit, IDELAY1 is the pre-stage delay unit of ODELAY, and the signal transmitted by ODELAY is output through IOBUF. IDELAY2 is the target input delay unit connected to IOBUF, and IOBUF can send the signal input by the external circuit to IDELAY2.

[0111] As another example, Figure 6BAs shown, ODELAY1 is connected to IOBUF, so ODELAY1 is the target output delay unit. ODELAY1 has no previous delay unit, and the signal transmitted by ODELAY1 is output through IOBUF. IDELAY is the target input delay unit connected to IOBUF, and IOBUF can send the signal input by the external circuit to IDELAY.

[0112] By utilizing the buffer unit, this embodiment can directly output the signal of a delay unit located at an intermediate level from a plurality of delay units connected in series. The output signal is not delayed by the delay unit at the lower level. Therefore, the position of the level edge of the output signal can be made more diverse, thereby greatly improving the flexibility of setting the delay time and further expanding the application range of the delay circuit.

[0113] Exemplary Devices

[0114] refer to Figure 8 The embodiment of the present disclosure also provides a semiconductor test device, including a signal input module 801, a clock source module 802, a timing generation module 803, a timing control module 804, a test drive module 805, and an analysis module 806. The timing generation module 803 (TG, Timing Generation) includes a multi-stage delay unit. The signal input module 801, the clock source module 802 and the multi-stage delay unit constitute the cascade structure delay circuit described in the above embodiment, that is, the signal input module 801 includes Figure 1 The signal input source 102 shown, the clock source module 802 includes Figure 1 A clock source 101 is shown.

[0115] Typically, the signal input module 801 may include a graph algorithm generator, a graph generator, a multiplexing selection unit, a waveform synthesis unit, etc. The graph algorithm generator and the graph generator are used to generate a test graph according to an algorithm and a test vector, respectively. The multiplexing selection unit may select a test graph generated by the graph algorithm generator or the graph generator. The waveform synthesis unit is used to synthesize a waveform format according to a waveform format set by a user, thereby obtaining a signal for testing.

[0116] In this embodiment, the timing control module 804 is used to calculate the delay time according to the input timing setting information; generate delay configuration information based on the delay time; and send the delay configuration information to the timing generation module 803.

[0117] Specifically, in the semiconductor test equipment, the timing control module 804 determines the reference clock beat and the delay time within a single clock beat corresponding to the signal edge of the output signal of the timing generation module 803, and determines the sampling clock beat of the response signal and the signal delay time information within a single clock beat according to the timing information of the signal edge provided by the signal input module 801 and the sampling position information of the response signal input from the device under test (DUT) 807. Based on the above information, the timing control module 804 generates delay configuration information and inputs it into the multi-stage delay unit included in the above-mentioned TG module.

[0118] In this embodiment, the timing generation module 803 is used to delay the electrical signal of the input signal and input the delayed electrical signal of the output signal to the test driving module 805 .

[0119] Generally, the electrical signal output by the multi-stage delay unit included in the TG module is the synthetic waveform signal required for semiconductor testing. The TG module delays the output of the input signal and delays the sampling of the response signal fed back by the test drive module 805, so as to realize the synthesis of the timing relationship of the output signal edge and the fine control of the signal sampling position.

[0120] In this embodiment, the test drive module 805 is used to generate a test excitation signal based on the electrical signal of the received output signal, and send the test excitation signal to the device under test 807; receive a response signal returned by the device under test 807, and send the response signal to the timing generation module 803.

[0121] The device under test 807 may be various types of devices, for example, including but not limited to a memory chip, a logic processing chip, etc.

[0122] Typically, the test drive module 805 may include a pin circuit (PE), which is an interface between the test resources of the test equipment and the device under test. It provides an excitation signal to the device under test and receives a response signal output by the device under test, and feeds the received response signal back to the above-mentioned TG module.

[0123] In this embodiment, the timing generation module 803 is further used to sample the response signal to obtain a sampled signal, and send the sampled signal to the analysis module 806 .

[0124] In this embodiment, the analysis module 806 is used to compare the sampled signal with the input signal to generate test result information.

[0125] Specifically, the analysis module 806 can compare the sampled signal with the input signal to obtain a comparison result, generate optimization strategy information according to the comparison result, and repair the device under test 807 according to the optimization strategy information. The analysis module 806 can also generate the waveform of the response signal output by the device under test 807 and the waveform of the test stimulus signal, which are displayed to the user through the user interface of the waveform analysis tool so that the user can analyze. The above test result information may include but is not limited to the above comparison result, the displayed waveform, the optimization strategy information, etc.

[0126] In addition, the semiconductor test equipment may also include an input device, an output device, and necessary memory, etc. Among them, the input device may include, for example, a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting test signals. The output device may include, for example, a display, a printer, and a communication network and its connected remote output device, etc., for outputting test result information. The memory is used to store the signal input by the above-mentioned input device, and the signal generated during the operation of the cascade structure delay circuit. The memory may include a volatile memory and / or a non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc.

[0127] The semiconductor testing equipment provided by the above-mentioned embodiments of the present disclosure, by introducing a cascade structure delay circuit, can adjust the time corresponding to the edge of the signal with a smaller granularity, thereby improving the time accuracy of the synthetic waveform, helping to improve the accuracy of the excitation signal and the sampling accuracy of the response signal of the device under test, thereby improving the accuracy of testing the device under test.

[0128] The embodiment of the present disclosure further provides a timing generation chip, on which a cascade structure delay circuit is integrated. For example, the chip may be an FPGA chip, on which the cascade structure delay circuit is implemented. The technical details of the cascade structure delay circuit are as follows: Figure 1-6B As shown in the relevant description, no further description is given here.

[0129] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0130] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other.

[0131] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0132] The circuits of the present disclosure may be implemented in many ways. For example, the circuits of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the functions of the circuits of the present disclosure. Thus, the present disclosure also covers recording media storing programs for executing the functions of the circuits of the present disclosure.

[0133] It should also be noted that in the circuit of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as an equivalent solution of the present disclosure.

[0134] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0135] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A cascade delay circuit, comprising: A clock source, a signal input source, and a multi-stage delay unit, wherein the multi-stage delay unit includes at least two delay units connected in a cascade manner; Each delay unit in the multi-stage delay unit comprises a clock input terminal and a delay time configuration terminal, wherein the clock input terminal is connected to the clock source, and the delay time configuration terminal is used to receive delay configuration information, wherein the delay configuration information is used to set a delay configuration value representing the delay time of the delay unit, and an update interval time of the delay configuration value, wherein the update interval time is a time set based on a reference clock signal output by the clock source; The signal input end of the first-stage delay unit in the multi-stage delay unit is connected to the signal input source; Each delay unit in the multi-stage delay unit is used to delay the input signal according to the delay configuration value received by the respective delay time configuration end, output the delayed output signal, and update the delay configuration value according to the update interval time of each delay unit, wherein the time difference for updating the delay configuration value between any two delay units in the multi-stage delay unit is less than or equal to the update interval time.

2. The circuit according to claim 1, wherein The multi-stage delay units are connected in series in sequence.

3. The circuit according to claim 2, wherein: The circuit further comprises at least one buffer unit, each buffer unit of the at least one buffer unit being located between two adjacent delay units; Each buffer unit in the at least one buffer unit is used to forward a signal output by an upper delay unit in two connected delay units to a lower delay unit in the adjacent delay units.

4. The circuit according to claim 3, wherein: The multi-stage delay unit includes at least one input delay unit and at least one output delay unit; Each buffer unit in the at least one buffer unit is located between an output delay unit and an input delay unit, and the upper delay unit of the buffer unit includes the output delay unit, and the lower delay unit of the buffer unit includes the input delay unit.

5. The circuit according to claim 4, wherein: The buffer unit in the at least one buffer unit is further configured to: Outputting a signal received from a connected upper delay unit, or receiving data input from outside the cascade structure delay circuit; The buffer units in the at least one buffer unit respectively include a signal transmission control terminal and a signal external connection port; The buffer unit in the at least one buffer unit is further configured to: According to the control signal received by the signal transmission control terminal, the signal received from the connected upper delay unit is output from the signal external connection port, or the signal received from the signal external connection port is sent to the connected lower delay unit.

6. A circuit according to claim 4 or 5, wherein: The input delay unit comprises a first signal input terminal and a second signal input terminal; When the first-stage delay unit is an input delay unit, the next-stage delay unit of the first-stage delay unit is an output delay unit, and the first-stage delay unit is used for: receiving a signal from the signal input source through the first signal input terminal, and sending the received signal to a next-stage delay unit of the first-stage delay unit; When other delay units in the multi-stage delay unit except the first-stage delay unit include an input delay unit, the input delay unit included in the other delay units is used to: A signal sent by the corresponding buffer unit is received through the second signal input terminal.

7. A circuit according to claim 4 or 5, wherein: The output delay unit comprises a third signal input terminal; When the first-stage delay unit is an output delay unit, the first-stage delay unit is used for: The signal from the signal input source is received through the third signal input terminal of the first-stage delay unit, and the received signal is sent to the corresponding buffer unit.

8. The circuit according to claim 1, wherein: The circuit further comprises a control unit, which is configured to: Determine whether there is a target delay unit that meets the update condition in the multi-stage delay unit, and if the target delay unit exists, send an update signal and a delay configuration value to the target delay unit, wherein the update condition includes: the time difference between the time when the target delay unit last updated the delay configuration value and the current time is greater than or equal to the update interval time corresponding to the target delay unit; The target delay unit is used for: In response to receiving the update signal and the delay configuration value, the input signal is delayed according to the received delay configuration value.

9. The circuit according to claim 8, wherein The control unit is further configured to: In each clock cycle of the reference clock signal, the update signal and the delay configuration value are sent to a delay unit in the multi-stage delay unit.

10. A signal delay method applied to a multi-stage delay unit, comprising: Based on the preset delay configuration information, setting the delay configuration value and update interval time corresponding to each delay unit included in the multi-stage delay unit, wherein the update interval time is a time set based on the reference clock signal output by the preset clock source; An input signal is received through a signal input terminal of a first-stage delay unit of the multi-stage delay unit, and each delay unit in the multi-stage delay unit delays the input signal and outputs a delayed output signal; In response to the current time reaching the update time of any delay unit in the multi-stage delay unit, the original delay configuration value is updated based on the currently received delay configuration value, wherein the difference between the time of currently updating the delay configuration value and the time of last updating the delay configuration value is less than or equal to the update interval time.

11. The method according to claim 10, wherein: The method further comprises: For the target output delay unit connected to the buffer unit included in the multi-stage delay unit, the delayed output signal output by the target output delay unit is output through the buffer unit; or, the signal input from outside the cascade structure delay circuit is input to the target input delay unit connected to the buffer unit through the buffer unit.

12. A semiconductor testing device comprising: A signal input module, a clock source module, a timing generation module, a timing control module, a test drive module, and an analysis module, wherein the timing generation module includes a multi-stage delay unit, and the signal input module, the clock source module, and the multi-stage delay unit constitute a cascade structure delay circuit as described in any one of claims 1 to 9; The timing control module is used to calculate the delay time according to the input timing setting information; generate delay configuration information based on the delay time; and send the delay configuration information to the timing generation module; The timing generation module is used to delay the electrical signal of the input signal and input the delayed electrical signal of the output signal into the test drive module; The test drive module is used to generate a test excitation signal according to the received electrical signal of the output signal, and send the test excitation signal to the device under test; receive a response signal returned by the device under test, and send the response signal to the timing generation module; The timing generation module is further used to sample the response signal to obtain a sampling signal, and send the sampling signal to the analysis module; The analysis module is used to compare the sampled signal with the input signal to generate test result information.

13. A timing generation chip, characterized in that: The method comprises a cascade structure delay circuit according to any one of claims 1 to 9.

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