Multi-channel data synthesis device, method and chip
Through the multi -layer synthetic circuit structure, the signal frequency is increased layer by layer, and the problem of high -frequency work of digital modules is difficult to achieve, which significantly improves the working performance of the digital hybrid SOC.
Patent Information
- Application Number
- CN202411357825.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-01-24
AI Technical Summary
The prior art is difficult to realize high-frequency operation of digital modules, resulting in the inability to increase the frequency of the digital signal input to the current rudder DAC, the dynamic performance of the current rudder DAC is difficult to utilize, and the working performance of the digital-analog hybrid SOC is reduced.
A multi-layer synthetic circuit structure is adopted. Each layer of synthetic circuit includes two selectors and a first sampling circuit. The input signal is sampled in turn with a sampling frequency of 2n, the signal frequency is increased layer by layer, and finally output to the digital-to-analog converter.
Under the premise that the operating frequency of the digital module, the signal frequency of the input to the digital modular converter is significantly improved, and the dynamicity of the current rudder digital modulus converter is fully used to achieve high -speed digital modulus conversion. Essence
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Figure CN119363119A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of electronic circuits, and specifically relates to a multi-channel data synthesis device, method and chip. Background Art
[0002] A current-steering DAC (Digital-Analog converter) is a device that converts digital signals into analog signals. It can be integrated with a digital module on a hybrid digital-analog SOC (System on Chip). The digital module outputs a digital signal to the current-steering DAC, which then converts the input binary-coded digital signal into an analog signal.
[0003] It can be understood that in order to achieve high-speed digital-to-analog conversion in a hybrid SOC, it is necessary to increase the operating frequency of the digital module and the current steering DAC. In the prior art, EDA (Electronic Design Automation) tools are usually used to design a hybrid SOC. When the manufacturing process size remains unchanged, the operating frequency of the digital module will be limited by the speed of the digital standard cell library.
[0004] Specifically, if the operating frequency of the digital module is increased, the duty cycle of the digital signal it outputs will fluctuate, causing the sampling time or lock time of the DFF (D Flip-Flop, D-type trigger) circuit in the current steering DAC to be too short, making it impossible to read the data signal normally. In addition, due to the existence of wire inductance from the digital module to the power supply and ground, the high-frequency digital module will also increase the fluctuation of the wire inductance of the power supply and ground.
[0005] Therefore, it is difficult to achieve high-frequency operation of the digital module in the prior art, and the frequency of the digital signal input to the current-steering DAC cannot be increased, resulting in the dynamic performance of the current-steering DAC being difficult to effectively utilize and the working performance of the digital-analog hybrid SOC being reduced. Summary of the invention
[0006] The purpose of the embodiments of the present application is to provide a multi-channel data synthesis device, method and chip, which can solve the problem that the frequency of the digital signal input to the current-steering DAC cannot be increased, resulting in the dynamic performance of the current-steering DAC being difficult to effectively utilize and the working performance of the digital-analog hybrid SOC being reduced.
[0007] In a first aspect, an embodiment of the present application provides a multi-channel data synthesis device, the multi-channel data synthesis device comprising at least one layer of synthesis circuits connected in sequence, the input end of the first layer of synthesis circuits is connected to the output end of the digital module, and the output end of the last layer of synthesis circuits is connected to the input end of the digital-to-analog converter, wherein:
[0008] Each layer of synthesis circuit includes at least one two-way selector and a first sampling circuit connected to each two-way selector;
[0009] The two-way selector is used to receive input signals input from two corresponding input circuits, wherein the input circuit corresponding to the two-way selector in the first-layer synthesis circuit is the digital module, and the input circuit corresponding to the two-way selector in other synthesis circuits except the first layer is any first sampling circuit of the synthesis circuit in the previous layer; sampling is performed in turn from the two input signals at a sampling frequency of 2n to obtain a sampling signal, wherein n is the signal frequency of the input signal; and the sampling signal is sent to the connected first sampling circuit;
[0010] The first sampling circuit is used to perform data alignment on the sampling signal to obtain an output signal; and send the output signal to the corresponding output circuit, wherein the output circuit corresponding to the first sampling circuit in other synthesis circuits except the last layer is any two-way selector of the next layer of synthesis circuit, and the output circuit corresponding to the first sampling circuit in the last layer of synthesis circuit is the digital-to-analog converter.
[0011] Optionally, each layer of the synthesis circuit further includes two second sampling circuits corresponding to each two-way selector, wherein:
[0012] The second sampling circuit is used to receive an input signal inputted by the input circuit corresponding to a route; perform data alignment on the input signal to obtain a first intermediate signal; and send the first intermediate signal to the two-way selector;
[0013] The two-way selector is specifically used to receive two ways of the first intermediate signals; take the signal frequency of the first intermediate signal as n, and sample the two ways of the first intermediate signals in turn according to the sampling frequency of 2n to obtain sampling signals.
[0014] Optionally, each layer of the synthesis circuit further includes two third sampling circuits corresponding to each two-way selector, wherein:
[0015] The second sampling circuit is specifically configured to send the first intermediate signal to the connected third sampling circuit;
[0016] The third sampling circuit is used to perform data alignment on the received first intermediate signal to obtain a second intermediate signal; and send the second intermediate signal to the two-way selector;
[0017] The two-way selector is specifically used to receive two ways of the second intermediate signals respectively; take the signal frequency of the second intermediate signal as n, and sample the two ways of the second intermediate signals in turn according to the sampling frequency of 2n to obtain a sampled signal.
[0018] Optionally, the two-way selector includes a clock unit and a selection unit, wherein:
[0019] The clock unit is used to generate a clock signal according to a sampling frequency of 2n;
[0020] The selection unit is used to take the two input signals as target signals in turn according to the clock signal, sample the target signals, and obtain sampled signals.
[0021] Optionally, the clock unit further includes a clock delay module, wherein:
[0022] The clock delay module is used to adjust the clock signal generated by the clock unit through an inverter when an error in the sampling signal is detected.
[0023] Optionally, the clock delay module includes three, and the clock unit includes a frequency division module, wherein:
[0024] The frequency division module is used to obtain a clock input signal; perform frequency division processing on the clock input signal to obtain a group of two clock signals;
[0025] The clock delay module is used to perform phase adjustment on the clock input signal and the two clock signals respectively.
[0026] In a second aspect, an embodiment of the present application provides a multi-channel data synthesis method, which is applied to an m-th layer synthesis circuit in a multi-channel data synthesis device, wherein the multi-channel data synthesis device includes at least one layer of synthesis circuits connected in sequence, the input end of the first layer synthesis circuit is connected to the output end of the digital module, and the output end of the last layer synthesis circuit is connected to the input end of the digital-to-analog converter, and m is a positive integer less than or equal to the total number of layers of the synthesis circuit, including:
[0027] Receive input signals input from input circuits corresponding to two routes; wherein, when the value of m is 1, the input circuit is the digital module, and when the value of m is greater than 1, the input circuit is any first sampling circuit of the upper layer synthesis circuit;
[0028] Sampling the two input signals in turn at a sampling frequency of 2n to obtain a sampling signal, wherein n is the signal frequency of the input signal;
[0029] Performing data alignment on the sampling signal to obtain an output signal;
[0030] The output signal is sent to the corresponding output circuit; wherein, when the value of m is less than the total number of layers of the synthesis circuit, the output circuit is any two-way selector of the next layer of synthesis circuit, and when the value of m is the total number of layers of the synthesis circuit, the output circuit is the digital-to-analog converter.
[0031] Optionally, the step of receiving input signals inputted by input circuits corresponding to two routes includes:
[0032] receiving input signals inputted by the input circuits corresponding to the two routes;
[0033] Performing data alignment on the input signal to obtain a first intermediate signal;
[0034] The signal frequency of the first intermediate signal is taken as n, and sampling is performed in turn from the two first intermediate signals at a sampling frequency of 2n to obtain a sampled signal.
[0035] Optionally, taking the signal frequency of the first intermediate signal as n and sampling the two first intermediate signals in turn at a sampling frequency of 2n to obtain a sampled signal includes:
[0036] performing data alignment on the first intermediate signal to obtain a second intermediate signal;
[0037] The signal frequency of the second intermediate signal is taken as n, and sampling is performed in turn from the two second intermediate signals at a sampling frequency of 2n to obtain a sampled signal.
[0038] Optionally, sampling the two input signals in turn at a sampling frequency of 2n to obtain a sampled signal includes:
[0039] Generate a clock signal according to a sampling frequency of 2n;
[0040] According to the clock signal, the two input signals are taken as target signals in turn, and the target signals are sampled to obtain sampled signals.
[0041] Optionally, the method further comprises:
[0042] In case an error in the sampling signal is detected, adjusting the clock signal;
[0043] According to the adjusted clock signal, the two input signals are taken as target signals in turn, and the target signals are sampled to obtain sampled signals.
[0044] Optionally, generating a clock signal includes:
[0045] Get the clock input signal;
[0046] Performing frequency division processing on the clock input signal to obtain a set of two clock signals;
[0047] The adjusting the clock signal comprises:
[0048] Phase adjustment is performed on the clock input signal and the two clock signals respectively.
[0049] In a third aspect, an embodiment of the present application provides a chip, which includes a digital module, a digital-to-analog conversion module, and an analog radio frequency circuit, wherein the digital-to-analog conversion module includes the multi-channel data synthesis device and the digital-to-analog converter described in any one of the above items.
[0050] In the solution provided by the embodiment of the present application, the multi-channel data synthesis device includes at least one layer of synthesis circuits connected in sequence, the input end of the first layer of synthesis circuits is connected to the output end of the digital module, the output end of the last layer of synthesis circuits is connected to the input end of the digital-to-analog converter, and each layer of synthesis circuits includes at least one two-way selector and a first sampling circuit connected to each two-way selector; wherein the two-way selector is used to receive input signals input from two corresponding input circuits, wherein the input circuit corresponding to the two-way selector in the first layer of synthesis circuits is a digital module, and the input circuit corresponding to the two-way selector in other synthesis circuits except the first layer is any first sampling circuit of the synthesis circuit in the previous layer; sampling is performed from the two input signals in turn according to a sampling frequency of 2n to obtain a sampling signal, wherein n is the signal frequency of the input signal; the sampling signal is sent to the connected first sampling circuit; the first sampling circuit is used to perform data alignment on the sampling signal to obtain an output signal; the output signal is sent to the corresponding output circuit, wherein the output circuit corresponding to the first sampling circuit in other synthesis circuits except the last layer is any two-way selector of the synthesis circuit in the next layer, and the output circuit corresponding to the first sampling circuit in the last layer of synthesis circuits is a digital-to-analog converter.
[0051] In this way, the input signal is continuously sampled through the two-way selectors in each layer of the synthesis circuit, and the multiple signals output by the digital module are finally converted into one output signal input to the digital-to-analog converter. Moreover, in the process of each sampling, the frequency of the output signal obtained is continuously increased, so that the frequency of the signal finally output to the digital-to-analog converter is significantly increased compared to the signal frequency output by the digital module. Therefore, without increasing the operating frequency of the digital module, the frequency of the signal input to the digital-to-analog converter is increased, so as to make full use of the dynamics of the current-steering digital-to-analog converter, realize high-speed digital-to-analog conversion, and improve the working performance of the digital-to-analog hybrid SOC. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] Figure 1 is a schematic diagram of a device for synthesizing multiple data channels according to an exemplary embodiment;
[0053] Figure 2 is an overall structural diagram of a multi-channel data synthesis device according to an exemplary embodiment;
[0054] Figure 3 is a structural schematic diagram of a synthesis circuit according to an exemplary embodiment;
[0055] Figure 4 is a schematic diagram of the internal structure of a two-way selector according to an exemplary embodiment;
[0056] Figure 5 is a schematic diagram showing a two-way selector sampling an input signal according to an exemplary embodiment;
[0057] Figure 6 is a schematic diagram showing error sampling of an input signal by a two-way selector according to an exemplary embodiment;
[0058] Figure 7 is a schematic structural diagram of a clock unit according to an exemplary embodiment;
[0059] Figure 8 A schematic diagram of a multi-channel data synthesis method according to an exemplary embodiment;
[0060] Fig. 9 A schematic diagram of a chip is shown according to an exemplary embodiment. DETAILED DESCRIPTION
[0061] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.
[0062] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0063] The following is a detailed description of the multi-channel data synthesis device method provided by the embodiment of the present application through specific embodiments and their application scenarios in conjunction with the accompanying drawings.
[0064] The current-steering DAC is a device that converts digital signals into analog signals. It can be integrated with the digital module on a mixed-analog SOC. The digital module outputs digital signals to the current-steering DAC, and the current-steering DAC then converts the input binary-coded digital signals into analog signals.
[0065] It is understandable that in order to achieve high-speed digital-to-analog conversion in a hybrid SOC, it is necessary to increase the operating frequency of the digital module and the current-steering DAC. However, the increase in the operating frequency of the digital module will cause fluctuations in the duty cycle of the digital signal it outputs, resulting in the current-steering DAC being unable to read the data signal normally. It will also increase the fluctuations in the wire inductance of the power supply and ground.
[0066] Therefore, it is difficult to increase the frequency of the digital signal input to the current steering DAC in the related art, resulting in that the dynamic performance of the current steering DAC is difficult to be effectively utilized and the working performance of the digital-analog hybrid SOC is reduced. In order to solve the above problems, a multi-channel data synthesis device in the present application is proposed.
[0067] Figure 1 It is a schematic diagram of a device for synthesizing multiple data channels according to an exemplary embodiment, wherein the device for synthesizing multiple data channels includes one or more layers of synthesizing circuits connected in sequence.
[0068] If the synthesis circuit has only one layer, the input end of the synthesis circuit is connected to the output end of the digital module, and the output end of the synthesis circuit is connected to the input end of the digital-to-analog converter.
[0069] If the synthesis circuit has multiple layers, the input end of the synthesis circuit of the first layer is connected to the output end of the digital module, and the output end of the synthesis circuit of the last layer is connected to the input end of the digital-to-analog converter.
[0070] That is to say, the first-layer synthesis circuit receives the output signal of the digital module, the second-layer synthesis circuit receives the output signal of the first-layer synthesis circuit, and so on. Finally, the output signal of the last-layer synthesis circuit is input into the digital-to-analog converter for digital-to-analog conversion.
[0071] in:
[0072] Each layer of synthesis circuit includes one or more two-way selectors and a first sampling circuit connected to each two-way selector;
[0073] A two-way selector is used to receive input signals input from two corresponding input circuits, wherein the input circuit corresponding to the two-way selector in the first-layer synthesis circuit is a digital module, and the input circuit corresponding to the two-way selector in other synthesis circuits except the first layer is any first sampling circuit of the synthesis circuit in the previous layer; sampling is performed in turn from the two-way input signals at a sampling frequency of 2n to obtain a sampling signal, wherein n is the signal frequency of the input signal; and the sampling signal is sent to the connected first sampling circuit;
[0074] The first sampling circuit is used to perform data alignment on the sampling signal to obtain an output signal; the output signal is sent to the corresponding output circuit, wherein the output circuit corresponding to the first sampling circuit in other synthesis circuits except the last layer is any two-way selector of the next layer synthesis circuit, and the output circuit corresponding to the first sampling circuit in the last layer synthesis circuit is a digital-to-analog converter.
[0075] That is to say, each layer of the synthesis circuit includes one or more two-way selectors, and the output end of each two-way selector is connected to the input end of a first sampling circuit, wherein the two-way selector is a combinational logic circuit that can receive two signals and output one signal. The first sampling circuit can use a DFF circuit, which is a digital logic circuit for aligning the input signal. The digital-to-analog converter can be a current-steering DAC or other types of DAC, and the present application does not make any specific limitations on this.
[0076] In the present application, the frequencies of the signals output by the digital module are consistent. Therefore, the frequencies of the two input signals received by the two-way selectors in the first-layer synthesis circuit are the same. After sampling by the two-way selectors in the first-layer synthesis circuit, the signal frequency of the sampled signal is twice the signal frequency output by the digital module. Then, after being processed by the first sampling circuit in the first-layer synthesis circuit, the signal frequency remains unchanged, and the output signal of the first-layer synthesis circuit is obtained.
[0077] If the synthesis circuit has only one layer, then the two-way selector in the synthesis circuit can receive two input signals with a signal frequency of x input from the digital module, and take turns sampling from the two input signals at a sampling frequency of 2x to obtain a sampling signal, and then send the sampling signal to the connected first sampling circuit;
[0078] The output circuit corresponding to the first sampling circuit in the synthesis circuit is a digital-to-analog converter. The first sampling circuit performs data alignment on the sampling signal to obtain an output signal, and then sends the output signal of the synthesis circuit to the digital-to-analog converter. The digital-to-analog converter can convert the output signal from a digital signal to an analog signal.
[0079] If the synthesis circuit has more than one layer, then the two-way selector in the synthesis circuit of the first layer can receive two input signals with a signal frequency of x input from the digital module, and take turns sampling from the two input signals at a sampling frequency of 2x to obtain a sampling signal of the first layer, and then send the sampling signal to the connected first sampling circuit;
[0080] The output circuit corresponding to the first sampling circuit in the first-layer synthesis circuit is a two-way selector of the second-layer synthesis circuit, and the first sampling circuit performs data alignment on the received sampling signal to obtain the output signal of the first layer, and then sends the output signal of the first layer to the two-way selector of the second-layer synthesis circuit;
[0081] The two-way selector of the second-layer synthesis circuit can receive two input signals with a signal frequency of 2x, and take turns sampling from the two input signals according to a sampling frequency of 4x to obtain a sampling signal of the second layer, and then send the sampling signal to the connected first sampling circuit;
[0082] If the second-layer synthesis circuit is the last layer, then the output circuit corresponding to the first sampling circuit in the second-layer synthesis circuit is a digital-to-analog converter, and the first sampling circuit performs data alignment on the sampling signal of the second layer to obtain an output signal, and then sends the output signal to the digital-to-analog converter, and the digital-to-analog converter can convert the output signal from a digital signal to an analog signal;
[0083] If the second-layer synthesis circuit is not the last layer, then the output circuit corresponding to the first sampling circuit in the second-layer synthesis circuit is a two-way selector of the next-layer synthesis circuit, and the first sampling circuit performs data alignment on the received sampling signal to obtain the output signal of the second layer, and then sends the output signal of the second layer to the two-way selector of the next-layer synthesis circuit;
[0084] By analogy, the frequencies of the two input signals received by the two-way selectors in each layer of the synthesis circuit are the same. Let n represent the signal frequency of the input signal, then the two-way selectors sample at a sampling frequency of 2n, and the signal frequency of the output signal of each layer of the synthesis circuit is twice the signal frequency of the corresponding input signal.
[0085] In this way, the input signal is continuously sampled through the two-way selectors in each layer of the synthesis circuit. During each sampling process, the frequency of the output sampling signal is increased. Ultimately, the output signal input to the digital-to-analog converter has a higher signal frequency.
[0086] In addition, in the present application, the first sampling circuit in the last layer synthesis circuit can not only generate an output signal, but also simultaneously generate an inverted signal of the output signal. The inverted signal can be used to amplify and filter the output signal, which has certain reference significance.
[0087] For example, if Figure 2 As shown, it is an overall structural diagram of a multi-channel data synthesis device in the present application, wherein the digital module outputs 8 input signals, and the multi-channel data synthesis device includes 3 layers of synthesis circuits connected in sequence, wherein the first layer of synthesis circuits includes 4 two-way selectors and 4 DFF circuits, the second layer of synthesis circuits includes 2 two-way selectors and 2 DFF circuits, and the third layer of synthesis circuits includes 1 two-way selector and 1 DFF circuit. Therefore, the multi-channel data synthesis device has a total of 7 two-way selectors and 7 DFF circuits.
[0088] Specifically, the digital module outputs 8 signals with a frequency of Fck / 8, namely D1, D2, ..., D8. These 8 signals can be used as 4 groups of 2-way input signals and input into the 4 two-way selectors included in the first-layer synthesis circuit respectively, wherein the sampling frequency of the 4 two-way selectors included in the first-layer synthesis circuit is Fck / 4, and then processed by the 4 DFF circuits in the first-layer synthesis circuit to obtain 4 signals with a signal frequency of Fck / 4;
[0089] These 4-way signals can be used as 2 groups of 2-way input signals, respectively input to 2 2-way selectors included in the second-layer synthesis circuit, wherein the sampling frequency of the 4 2-way selectors included in the second-layer synthesis circuit is Fck / 2, and then processed by the 2 DFF circuits in the second-layer synthesis circuit to obtain 2-way signals with a signal frequency of Fck / 2;
[0090] These two signals can be used as a group of two input signals and respectively input into the two-way selectors in the third-layer synthesis circuit, wherein the sampling frequency of the two-way selectors in the third-layer synthesis circuit is Fck. After being processed by the DFF circuit in the third-layer synthesis circuit, a signal Dout with a signal frequency of Fck and an inverted signal Doutb of Dout are obtained and output to the digital-to-analog converter.
[0091] In one implementation, each layer of the synthesis circuit further includes two second sampling circuits corresponding to each two-way selector, wherein:
[0092] A second sampling circuit is used to receive an input signal inputted by the input circuit corresponding to a route; perform data alignment on the input signal to obtain a first intermediate signal; and send the first intermediate signal to the two-way selector;
[0093] The two-way selector is specifically used to receive two-way first intermediate signals; take the signal frequency of the first intermediate signal as n, and sample the two-way first intermediate signals in turn according to the sampling frequency of 2n to obtain a sampling signal.
[0094] That is to say, in each layer of synthesis circuit, two second sampling circuits can be respectively set before each two-way selector included in the synthesis circuit of this layer. The second sampling circuit can also adopt DFF circuit, which is used to perform data alignment on each signal before it is input into the two-way selector to obtain a first intermediate signal, and then the two-way selector samples the first intermediate signal, so as to avoid modulation errors of the input signal input into the two-way selector.
[0095] In one implementation, each layer of the synthesis circuit further includes two third sampling circuits corresponding to each two-way selector, wherein:
[0096] A second sampling circuit, specifically configured to send the first intermediate signal to a connected third sampling circuit;
[0097] A third sampling circuit is used to perform data alignment on the received first intermediate signal to obtain a second intermediate signal; and send the second intermediate signal to the two-way selector;
[0098] The two-way selector is specifically used to receive two-way second intermediate signals respectively; taking the signal frequency of the second intermediate signal as n, sampling from the two-way second intermediate signals in turn according to the sampling frequency of 2n to obtain a sampling signal.
[0099] That is to say, in each layer of synthesis circuit, two third sampling circuits can be set before each two-way selector included in the synthesis circuit of this layer, and the second sampling circuit can be set after the second sampling circuit. The DFF circuit can also be used to perform a second data alignment on each signal before it is input into the two-way selector, so as to further avoid modulation errors of the input signal and improve the accuracy of digital-to-analog conversion.
[0100] like Figure 3 , which is a schematic diagram of the structure of a synthesis circuit of a certain layer in a multi-channel data synthesis device, including 2 second sampling circuits, 2 third sampling circuits, 1 two-way selector and 1 first sampling circuit.
[0101] After the input signal D0 is input into each layer of synthesis circuit, it first needs to undergo data alignment of the second sampling circuit to obtain a first intermediate signal. Then, the first intermediate signal is input into the third sampling circuit for a second data alignment to obtain a second intermediate signal d0. The conversion process of the input signal D1 is similar, and the corresponding second intermediate signal d1 can be obtained. Furthermore, the two second intermediate signals are input into the two-way selector for sampling to obtain a sampling signal dout. The sampling signal is then input into the data alignment of the first sampling circuit to finally obtain an output signal Dout and an inverted signal Doutb corresponding to the output signal.
[0102] Among them, if it is based on a 22-nanometer SOC manufacturing process, the output frequency of the digital module may be 614.4 MHz. In the first-layer synthesis circuit, the second sampling circuit and the third sampling circuit can both use a DFF circuit with a beat frequency of 614.4 MHz, and the first sampling circuit can use a DFF circuit with a beat frequency of 1.2288 GHz, that is, the beat frequency of each DFF circuit is equal to the input signal frequency, and so on. Alternatively, according to specific business scenarios and application requirements, DFF circuits with different beat frequencies can be used to achieve better signal processing effects as much as possible. This application does not limit this.
[0103] In one implementation, the two-way selector includes a clock unit and a selection unit, wherein:
[0104] A clock unit, used for generating a clock signal according to a sampling frequency of 2n;
[0105] The selection unit is used to take the two input signals as target signals in turn according to the clock signal, sample the target signals, and obtain sampled signals.
[0106] In the embodiment of the present application, the two-way selector needs to sample the two input signals in turn at a sampling frequency twice that of the input signals. Therefore, a certain mechanism is required to determine the sampling timing of the two-way selector for the two input signals.
[0107] Specifically, the two-way selector includes a clock unit and a selection unit, wherein the clock unit is used to generate a clock signal, and the frequency of the clock signal is the same as the sampling frequency of the two-way selector. Then, the selection unit can determine the input signal that currently needs to be sampled according to the clock signal as the target signal, and then sample the target signal to obtain a sampled signal.
[0108] The clock unit may adopt a PLL (Phase-Locked Loop) module, or may adopt other devices to generate a clock signal, which is not limited in the present application.
[0109] In this way, the two-way selector can sample the two-way input signals in turn during sampling, so that the obtained sampling signal modulates the data of the two-way input signals, thereby avoiding data loss.
[0110] For example, Figure 4As shown, it is a schematic diagram of the internal structure of a two-way selector, wherein anaclk / 2 and anaclk / 2' are used to represent the values of a group of clock signals, the values of anaclk / 2 and anaclk / 2' are both 0 or 1, and the values of the two are different at the same time, switching between 0 and 1 respectively at a frequency twice that of the input signal; the clock signals corresponding to the two input signals d0 and d1 are consistent, so that according to the values of anaclk / 2 and anaclk / 2', the input signals can be sampled alternately.
[0111] For example, when anaclk / 2 is 1 and anaclk / 2' is 0, the selection unit takes the input signal d0 as the target signal, that is, the sampling result at the current moment is dout=d0. When anaclk / 2 is 0 and anaclk / 2' is 1, the selection unit takes the input signal d1 as the target signal, that is, the sampling result at the current moment is dout=d1. Therefore, as anaclk / 2 and anaclk / 2' switch between 0 and 1 respectively, the two selectors can sample the two input signals in turn.
[0112] like Figure 5 As shown, it is a schematic diagram of a two-way selector sampling an input signal in the manner of the above embodiment, wherein the time interval between any two adjacent moments from t1 to t8 is equal, serving as a sampling interval of the two-way selector, and d0 is sampled at moment t1, d1 is sampled at moment t2, and so on.
[0113] Then, from t1 to t8, d0 and d1 went through 4 cycles, where the value of d0 in each cycle was 01 0 1, and the value of d1 in each cycle was 0 1 1 0. The two-way selector went through 8 cycles, and d0 and d1 were sampled in turn in each cycle. The values of the sampling signal dout in the 8 cycles were 0 0 1 1 0 1 1 0.
[0114] In one implementation, the clock unit further includes a clock delay module, wherein:
[0115] The clock delay module is used to adjust the clock signal generated by the clock unit through an inverter when a sampling signal error is detected.
[0116] It is understandable that the two-way selector may make an error during sampling, e.g. Figure 6 As shown, sampling errors can produce results different from Figure 4The output dout', starting from time t5, the value of the sampling signal dout in the subsequent 4 sampling cycles should be 0 1 1 0, but it is mistakenly sampled as 1 0 0 1. In this case, the final output signal will also have errors, resulting in a waste of system resources.
[0117] In order to solve this problem, a clock delay module can be set in the two-way selector. The clock delay module is composed of multiple inverters of different numbers. When the clock signal passes through an inverter, it will experience a propagation delay. Therefore, the inverter can extend the time for the clock signal to reach the selection unit, which is equivalent to changing the phase of the clock signal, thereby adjusting the clock signal so that the two-way selector can continue to sample from the two input signals in turn according to predetermined rules.
[0118] Among them, the clock delay module can determine that the sampling signal is wrong after receiving error messages fed back by other subsequent modules, or it can determine that the sampling signal is wrong according to user input instructions, which is not limited in this application.
[0119] In one implementation, the clock delay module includes three, and the clock unit includes a frequency division module, wherein:
[0120] A frequency division module is used to obtain a clock input signal; the clock input signal is frequency-divided to obtain a set of two clock signals;
[0121] The clock delay module is used to adjust the phases of the clock input signal and the two clock signals.
[0122] That is to say, Figure 7 As shown, it is a structural schematic diagram of a clock unit in a two-way selector, and the clock unit includes a frequency division module and three clock delay modules, wherein one clock delay module is before the frequency division module of the clock unit, and two clock delay modules are after the frequency division module of the clock unit.
[0123] A clock delay module is added before and after the clock signal is divided. The clock input signal ANACLK first undergoes phase adjustment by a clock delay module to obtain a first adjustment signal Anaclk. Then, after being beaten by the division module, a group of clock signals Anaclk / 2 and Anaclk / 2' are obtained. Furthermore, Anaclk / 2 and Anaclk / 2' are respectively phase adjusted by a clock delay module to obtain a group of adjusted clock signals anaclk / 2 and anaclk / 2'. Therefore, the clock delay module can control the phase of each group of clock signals anaclk / 2 and anaclk / 2' to achieve adjustment of the clock signal.
[0124] Alternatively, the number and location of the clock delay modules may also be changed according to current business requirements and application scenarios, which is not limited in this application.
[0125] It can be seen from the above that the technical solution provided by the embodiment of the present application continuously samples the input signal through the two-way selectors in each layer of the synthesis circuit, and finally converts the multi-way signals output by the digital module into one output signal input to the digital-to-analog converter, and in each sampling process, the frequency of the obtained output signal is continuously increased, so that the frequency of the signal finally output to the digital-to-analog converter is significantly increased compared to the signal frequency output by the digital module, thereby increasing the frequency of the signal input to the digital-to-analog converter without increasing the operating frequency of the digital module, so as to make full use of the dynamics of the current-steering digital-to-analog converter, realize high-speed digital-to-analog conversion, and improve the working performance of the digital-to-analog hybrid SOC.
[0126] like Figure 8 As shown, an embodiment of the present invention further provides a multi-channel data synthesis method, which is applied to the m-th layer synthesis circuit in a multi-channel data synthesis device, wherein the multi-channel data synthesis device includes at least one layer of synthesis circuits connected in sequence, the input end of the first layer synthesis circuit is connected to the output end of the digital module, and the output end of the last layer synthesis circuit is connected to the input end of the digital-to-analog converter, and m is a positive integer less than or equal to the total number of layers of the synthesis circuit, including:
[0127] Step S11: receiving input signals inputted by input circuits corresponding to two routes; wherein, when the value of m is 1, the input circuit is the digital module; and when the value of m is greater than 1, the input circuit is any first sampling circuit of the upper layer synthesis circuit;
[0128] Step S12: sampling the two input signals in turn at a sampling frequency of 2n to obtain a sampling signal, wherein n is the signal frequency of the input signal;
[0129] Step S13: performing data alignment on the sampling signal to obtain an output signal;
[0130] Step S14: Send the output signal to the corresponding output circuit; wherein, when the value of m is less than the total number of layers of the synthesis circuit, the output circuit is any two-way selector of the next layer of synthesis circuit, and when the value of m is the total number of layers of the synthesis circuit, the output circuit is the digital-to-analog converter.
[0131] In one implementation, the step of receiving input signals inputted by input circuits corresponding to two routes includes:
[0132] receiving input signals inputted by the input circuits corresponding to the two routes;
[0133] Performing data alignment on the input signal to obtain a first intermediate signal;
[0134] The signal frequency of the first intermediate signal is taken as n, and sampling is performed in turn from the two first intermediate signals at a sampling frequency of 2n to obtain a sampled signal.
[0135] In one implementation, taking the signal frequency of the first intermediate signal as n and sampling the two first intermediate signals in turn at a sampling frequency of 2n to obtain a sampled signal includes:
[0136] performing data alignment on the first intermediate signal to obtain a second intermediate signal;
[0137] The signal frequency of the second intermediate signal is taken as n, and sampling is performed in turn from the two second intermediate signals at a sampling frequency of 2n to obtain a sampled signal.
[0138] In one implementation, sampling the two input signals in turn at a sampling frequency of 2n to obtain a sampled signal includes:
[0139] Generate a clock signal according to a sampling frequency of 2n;
[0140] According to the clock signal, the two input signals are taken as target signals in turn, and the target signals are sampled to obtain sampled signals.
[0141] In one implementation, the method further includes:
[0142] In case an error in the sampling signal is detected, adjusting the clock signal;
[0143] According to the adjusted clock signal, the two input signals are taken as target signals in turn, and the target signals are sampled to obtain sampled signals.
[0144] In one implementation, generating a clock signal includes:
[0145] Get the clock input signal;
[0146] Performing frequency division processing on the clock input signal to obtain a set of two clock signals;
[0147] The adjusting the clock signal comprises:
[0148] Phase adjustment is performed on the clock input signal and the two clock signals respectively.
[0149] It can be seen from the above that the technical solution provided by the embodiment of the present application continuously samples the input signal through the two-way selectors in each layer of the synthesis circuit, and finally converts the multi-way signals output by the digital module into one output signal input to the digital-to-analog converter, and in each sampling process, the frequency of the obtained output signal is continuously increased, so that the frequency of the signal finally output to the digital-to-analog converter is significantly increased compared to the signal frequency output by the digital module, thereby increasing the frequency of the signal input to the digital-to-analog converter without increasing the operating frequency of the digital module, so as to make full use of the dynamics of the current-steering digital-to-analog converter, realize high-speed digital-to-analog conversion, and improve the working performance of the digital-to-analog hybrid SOC.
[0150] The embodiment of the present invention further provides a chip, such as Fig. 9 As shown, the chip includes a digital module, a digital-to-analog conversion module and an analog radio frequency circuit, wherein the digital-to-analog conversion module includes a multi-channel data synthesis device and a digital-to-analog converter as described in any one of the embodiments of the present application.
[0151] The chip shown may be a SOC chip, in which a digital module, a digital-to-analog conversion module and an analog radio frequency circuit are all integrated. In addition, other components may also be integrated on the SOC chip, including but not limited to a memory.
[0152] As can be seen from the above, in the solution provided by the present application, the input signal is continuously sampled through the two-way selectors in each layer of the synthesis circuit, and the multiple signals output by the digital module are finally converted into one output signal input to the digital-to-analog converter, and in each sampling process, the frequency of the output signal obtained is continuously increased, so that the frequency of the signal finally output to the digital-to-analog converter is significantly increased compared to the signal frequency output by the digital module, thereby increasing the frequency of the signal input to the digital-to-analog converter without increasing the operating frequency of the digital module, so as to make full use of the dynamics of the current-steering digital-to-analog converter, realize high-speed digital-to-analog conversion, and improve the working performance of the digital-to-analog hybrid SOC.
[0153] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.
[0154] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0155] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0156] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A multi-channel data synthesis device, characterized in that: The multi-channel data synthesis device comprises at least one layer of sequentially connected synthesis circuits, the input end of the first layer of synthesis circuits is connected to the output end of the digital module, and the output end of the last layer of synthesis circuits is connected to the input end of the digital-to-analog converter, wherein: Each layer of synthesis circuit includes at least one two-way selector and a first sampling circuit connected to each two-way selector; The two-way selector is used to receive input signals input from two corresponding input circuits, wherein the input circuit corresponding to the two-way selector in the first-layer synthesis circuit is the digital module, and the input circuit corresponding to the two-way selector in other synthesis circuits except the first layer is any first sampling circuit of the synthesis circuit in the previous layer; sampling is performed in turn from the two input signals at a sampling frequency of 2n to obtain a sampling signal, wherein n is the signal frequency of the input signal; and the sampling signal is sent to the connected first sampling circuit; The first sampling circuit is used to perform data alignment on the sampling signal to obtain an output signal; and send the output signal to the corresponding output circuit, wherein the output circuit corresponding to the first sampling circuit in other synthesis circuits except the last layer is any two-way selector of the next layer of synthesis circuit, and the output circuit corresponding to the first sampling circuit in the last layer of synthesis circuit is the digital-to-analog converter.
2. The multi-channel data synthesis device according to claim 1, characterized in that: Each layer of the synthesis circuit also includes two second sampling circuits corresponding to each two-way selector, wherein: The second sampling circuit is used to receive an input signal inputted by the input circuit corresponding to a route; perform data alignment on the input signal to obtain a first intermediate signal; and send the first intermediate signal to the two-way selector; The two-way selector is specifically used to receive two ways of the first intermediate signals; take the signal frequency of the first intermediate signal as n, and sample the two ways of the first intermediate signals in turn according to the sampling frequency of 2n to obtain sampling signals.
3. The multi-channel data synthesis device according to claim 2, characterized in that: Each layer of the synthesis circuit also includes two third sampling circuits corresponding to each two-way selector, wherein: The second sampling circuit is specifically configured to send the first intermediate signal to the connected third sampling circuit; The third sampling circuit is used to perform data alignment on the received first intermediate signal to obtain a second intermediate signal; and send the second intermediate signal to the two-way selector; The two-way selector is specifically used to receive two ways of the second intermediate signals respectively; take the signal frequency of the second intermediate signal as n, and sample the two ways of the second intermediate signals in turn according to the sampling frequency of 2n to obtain a sampled signal.
4. The multi-channel data synthesis device according to claim 1, characterized in that: The two-way selector comprises a clock unit and a selection unit, wherein: The clock unit is used to generate a clock signal according to a sampling frequency of 2n; The selection unit is used to take the two input signals as target signals in turn according to the clock signal, sample the target signals, and obtain sampled signals.
5. The multi-channel data synthesis device according to claim 4, characterized in that: The clock unit also includes a clock delay module, wherein: The clock delay module is used to adjust the clock signal generated by the clock unit through an inverter when an error in the sampling signal is detected.
6. The multi-channel data synthesis device according to claim 5, characterized in that: The clock delay module includes three, and the clock unit includes a frequency division module, wherein: The frequency division module is used to obtain a clock input signal; perform frequency division processing on the clock input signal to obtain a group of two clock signals; The clock delay module is used to perform phase adjustment on the clock input signal and the two clock signals respectively.
7. A multi-channel data synthesis method, characterized in that: The m-th layer synthesis circuit used in a multi-channel data synthesis device, wherein the multi-channel data synthesis device comprises at least one layer of synthesis circuits connected in sequence, the input end of the first layer synthesis circuit is connected to the output end of the digital module, and the output end of the last layer synthesis circuit is connected to the input end of the digital-to-analog converter, wherein m is a positive integer less than or equal to the total number of layers of the synthesis circuit, and comprises: Receive input signals input from input circuits corresponding to two routes; wherein, when the value of m is 1, the input circuit is the digital module, and when the value of m is greater than 1, the input circuit is any first sampling circuit of the upper layer synthesis circuit; Sampling the two input signals in turn at a sampling frequency of 2n to obtain a sampling signal, wherein n is the signal frequency of the input signal; Performing data alignment on the sampling signal to obtain an output signal; The output signal is sent to the corresponding output circuit; wherein, when the value of m is less than the total number of layers of the synthesis circuit, the output circuit is any two-way selector of the next layer of synthesis circuit, and when the value of m is the total number of layers of the synthesis circuit, the output circuit is the digital-to-analog converter.
8. The multi-channel data synthesis method according to claim 7, characterized in that: The step of receiving input signals inputted by input circuits corresponding to two routes comprises: receiving input signals inputted by the input circuits corresponding to the two routes; Performing data alignment on the input signal to obtain a first intermediate signal; The signal frequency of the first intermediate signal is taken as n, and sampling is performed in turn from the two first intermediate signals at a sampling frequency of 2n to obtain a sampled signal.
9. The multi-channel data synthesis method according to claim 8, characterized in that: The method of taking the signal frequency of the first intermediate signal as n and sampling the two first intermediate signals in turn at a sampling frequency of 2n to obtain a sampled signal includes: performing data alignment on the first intermediate signal to obtain a second intermediate signal; The signal frequency of the second intermediate signal is taken as n, and sampling is performed in turn from the two second intermediate signals at a sampling frequency of 2n to obtain a sampled signal.
10. The multi-channel data synthesis method according to claim 7, characterized in that: The step of sampling the two input signals in turn at a sampling frequency of 2n to obtain a sampled signal comprises: Generate a clock signal according to the sampling frequency of 2n; According to the clock signal, the two input signals are taken as target signals in turn, and the target signals are sampled to obtain sampled signals.
11. The multi-channel data synthesis method according to claim 10, characterized in that: The method further comprises: In case an error in the sampling signal is detected, adjusting the clock signal; According to the adjusted clock signal, the two input signals are taken as target signals in turn, and the target signals are sampled to obtain sampled signals.
12. The multi-channel data synthesis method according to claim 11, characterized in that: The generating of the clock signal comprises: Get the clock input signal; Performing frequency division processing on the clock input signal to obtain a set of two clock signals; The adjusting the clock signal comprises: Phase adjustment is performed on the clock input signal and the two clock signals respectively.
13. A chip, characterized in that: The chip includes a digital module, a digital-to-analog conversion module and an analog radio frequency circuit, wherein the digital-to-analog conversion module includes the multi-channel data synthesis device and the digital-to-analog converter according to any one of claims 1 to 6.