Parallel operation system with annular communication

Abstract

The invention discloses a parallel operation system with an annular communication function. The parallel operation system comprises a host and a slave which are both circuit units, an optical fiber module, a bidirectional signal conversion module and a processor are arranged in the circuit unit; the circuit units are sequentially connected through the optical fiber transmission channel to form a communication loop; an optical fiber module of the circuit unit receives an optical signal sent by a previous communication node on a communication loop, converts the optical signal into a digital signal and sends the digital signal to a bidirectional signal conversion module; the bidirectional signal conversion module converts the digital signal into an LVDS signal and sends the LVDS signal to the processor; the processor integrates the circuit information into the LVDS signal to obtain a new LVDS signal, and sends the new LVDS signal to the bidirectional signal conversion module; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal and sends the parallel data signal to the optical fiber module; and the optical fiber module converts the parallel data signal into an optical signal and sends the optical signal to a next communication node through the communication loop. The parallel operation system has good anti-interference performance and is suitable for long-distance data communication.

Description

Technical Field

[0001] The present invention relates to the technical field of parallel systems, and in particular to a parallel system with ring communication. Background Art

[0002] The existing power supply, load and source-carrying product systems are paralleled, and data transmission is physically realized mainly by analog medium parallel networking. The disadvantages are poor anti-interference, more wiring harnesses, limited driving ability, and inability to network over long distances. Compared with analog media, optical fiber has the advantages of high bandwidth, high speed, and strong anti-interference. Prior art 201610257991.0 discloses a high-speed real-time power supply parallel system that uses optical fiber connection communication. The disadvantage of this invention is that three pairs of optical modules are used for communication in network topology, which is wasteful and increases the instability of the system.

[0003] The existing power supply, load and source-load product system are paralleled, and phase synchronization is physically realized mainly by analog medium parallel networking. The host obtains the synchronous phase pulse after the real-time host main frequency is divided, and sent to the parallel bus through the analog medium, and both the host and the slave obtain the synchronous phase pulse from the parallel bus. The disadvantages are poor anti-interference, more wiring harnesses, limited driving capacity, and inability to network over long distances. Prior art 202210792612.3 discloses a multi-machine phase synchronization system and method based on optical fiber transmission, which uses optical fiber for phase synchronization. The disadvantage of this invention is that the digital reference source is directly sent as a synchronous phase signal, and is used as the digital reference source phase of the local machine after the slave receives it. When it is a reference source at the MHZ unit level, it occupies too much bandwidth. At the same time, the higher the frequency, the more unstable the transmission recognition, resulting in the scale limitation of the network and the disadvantage of phase mismatch caused by the slave losing the clock.

[0004] The parallel operation of circuit units can realize the modularization and large capacity of power supply, load and source-load products, and is the key to realizing the combination of high-power and high-voltage systems. After the power supply, load and source-load products are connected in parallel to expand the current and capacity, on the one hand, it is necessary to take current equalization measures to realize the current equalization control when the circuit units are operated in parallel, and on the other hand, it is necessary to measure and count the current of each unit and the total current after parallel connection. After the power supply, load and source-load products are connected in series to expand the voltage and capacity, on the one hand, it is necessary to take voltage equalization measures to realize the voltage equalization control when the circuit units are operated in series, and on the other hand, it is necessary to measure and count the voltage of each unit and the total voltage after parallel connection.

[0005] At present, the current sharing control and current summing measurement are mainly realized based on hardware circuits. For example, in the prior art 201610257991.0, the slave sends the local current information to the host through the sampling circuit, and the host receives the current information of each slave and sends it to the adder input to obtain the total current at this moment. In this solution, analog signals are transmitted in the link, the hardware circuit is relatively complex, the anti-interference performance is poor, and the measurement value error is large.

[0006] At present, the current sharing control and current summing measurement are also realized based on software transmission. The slave sends the local current information to the switchboard through the sampling circuit and the A / D conversion circuit. The host receives the current information of each slave, and the host's own circuit is also converted into a digital signal through the sampling circuit and the internal A / D conversion circuit. The host software adds the digital signals of the host and all the slaves to obtain the total current at this moment. In this solution, the digital signal is transmitted in the link, and the anti-interference performance is moderate, but the timing is difficult to align during measurement, resulting in large measurement errors for instantaneous values.

[0007] At present, current equalization control and current summation measurement are realized by using similar high-speed transceiver module technology for master-slave serial connection. For example, a high-speed real-time power supply parallel system disclosed in prior art 201610257991.0 has the disadvantage that the slave machine is required to sum up the data of the previous module in sequence, thereby increasing the amount of calculation of the slave machine, and summing up layer by layer in the entire system, reducing the reliability of the data. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a parallel system with ring communication, which has good anti-interference performance and is suitable for long-distance data communication.

[0009] In order to solve the above technical problems, the present invention discloses a parallel system with ring communication, including a host and multiple slaves, the host and the slaves are both a circuit unit, connected in series or in parallel; the circuit unit is a power supply, a load or a source load;

[0010] Each circuit unit is provided with a first optical fiber module, a bidirectional signal conversion module and a processor; the processor acquires circuit information of the circuit unit in real time;

[0011] Each of the circuit units is connected in sequence through an optical fiber transmission channel to form a first communication loop, and each of the circuit units serves as a communication node on the first communication loop;

[0012] For each of the circuit units, the first optical fiber module of the circuit unit receives an optical signal emitted by a previous communication node on the first communication loop, and converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor; the processor integrates the circuit information of the circuit unit into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the first optical fiber module; the first optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node through the first communication loop.

[0013] As an optional implementation manner, the number of the first communication loops is at least two, and the communication nodes where the hosts on each of the first communication loops are located are sequentially connected through an optical fiber transmission channel to form a second communication loop, and the circuit unit corresponding to each of the hosts on the first communication loops serves as a communication node on the second communication loop;

[0014] The host on the first communication loop is any circuit unit on the first communication loop, wherein the circuit unit further includes a second optical fiber module, and the processor of the circuit unit obtains circuit information on the first communication loop in real time;

[0015] For each circuit unit corresponding to the host on the first communication loop, the second optical fiber module of the circuit unit receives the optical signal emitted by the previous communication node on the second communication loop, and converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor of the circuit unit; the processor integrates the circuit information on the first communication loop into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the second optical fiber module of the circuit unit; the second optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node on the second communication loop through the second communication loop.

[0016] As another optional implementation manner, the circuit information of each circuit unit includes current value information of the circuit unit;

[0017] The processor of the circuit unit corresponding to each host on the first communication loop also performs a current summary calculation:

[0018] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and adds the current values ​​of all other circuit units to the current value of the circuit unit to obtain the current total current value of the first communication loop.

[0019] As another optional implementation, the processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for current balancing:

[0020] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and finds the target circuit unit corresponding to the minimum current value through a sorting algorithm, calculates the current value difference between the target circuit unit and the current value of the circuit unit corresponding to the host, and determines whether the current value difference exceeds a preset value. If so, a first control signal is generated, and the first control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the voltage according to the first control signal.

[0021] As another optional implementation, the circuit information of each circuit unit includes voltage value information of the circuit unit;

[0022] The processor of the circuit unit corresponding to each host on the first communication loop also outputs a control signal for voltage balancing:

[0023] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the voltage value information sent by all other circuit units on the first communication loop, finds the target circuit unit corresponding to the minimum voltage value through a sorting algorithm, calculates the voltage value difference between the target circuit unit and the circuit unit corresponding to the host, determines whether the voltage value difference exceeds a preset value, generates a second control signal if it exceeds, and outputs the second control signal to the target circuit unit through the first communication loop so that the target circuit unit increases the current threshold according to the first control signal.

[0024] As another optional implementation, the circuit information on the first communication loop includes at least one of a current value of each circuit unit on the first communication loop, a total value of current values ​​of all circuit units on the first communication loop, and a voltage value of each circuit unit on the first communication loop.

[0025] As another optional implementation, the number of the slaves does not exceed 255.

[0026] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0027] In the embodiment of the present invention, the information collected by each circuit unit is modulated into the optical fiber medium through digital signal for transmission. Since the link transmits digital signals, it has strong anti-interference ability. In addition, the optical fiber medium has a fast transmission speed and can be applied to long-distance transmission and scenarios with high real-time requirements. The physical electrical isolation between the host and each slave is achieved through the optical fiber module, and the circuit equipment can also be protected. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a structural schematic diagram of a parallel system with ring communication disclosed in an embodiment of the present invention;

[0030] Figure 2 is a schematic diagram of a signal conversion process inside a circuit unit A disclosed in an embodiment of the present invention;

[0031] Figure 3 It is a schematic diagram of data bit allocation of an LVDS signal disclosed in an embodiment of the present invention;

[0032] Figure 4 It is a structural schematic diagram of another parallel system with ring communication disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Embodiment 1

[0035] See also Figures 1 to 3 The embodiment of the present invention discloses a parallel system with ring communication, including a host and a plurality of slaves, wherein the host and the slaves are each a circuit unit, connected in series or in parallel; the circuit unit is a power supply, a load or a source-load; wherein:

[0036] Each circuit unit is provided with a first optical fiber module, a bidirectional signal conversion module and a processor; the processor acquires circuit information of the circuit unit in real time;

[0037] Each of the circuit units is connected in sequence through an optical fiber transmission channel to form a first communication loop, and each of the circuit units serves as a communication node on the first communication loop;

[0038] For each of the circuit units, the first optical fiber module of the circuit unit receives an optical signal emitted by a previous communication node on the first communication loop, and converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor; the processor integrates the circuit information of the circuit unit into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the first optical fiber module; the first optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node through the first communication loop.

[0039] In this embodiment, the bidirectional signal conversion module is not limited to being an independent chip or being integrated in a processor to run as an algorithm.

[0040] In this embodiment, when the system is running, one of the power modules in the loop is designated as the host, and the rest are slaves. The host sends the local current information. Assuming that the host serial number is 1, the high-speed receiving module of the slave with serial number N receives the parameter information of the first N-1 power supplies in parallel, and its high-speed sending module sends the parameter information of N power supplies in parallel. In this way, the loop undergoes a complete transmission, collects the readback of each parameter of all devices in the loop, and transmits it back to the host device. The current information is one of the parameters of the parameter readback, and the current of each slave is finally transmitted back to the host device. The digital processor of the host adds up to obtain the total current of the system. The measured data here include but are not limited to current, resistance, power, and voltage, and the corresponding sum information can be obtained according to the above method. When the system output is in series, the voltage readback is transmitted to the host device, and the digital processor of the host adds up to obtain the total voltage of the system. The time error of this execution is the same as that of the above, and the optimization measures are the same.

[0041] Specifically, the input optical signal is originally parallel digital information. After the optical fiber module restores it to parallel digital information, the bidirectional signal conversion module converts the parallel data signal into an LVDS signal, not only for anti-interference considerations, but also because the LVDS signal helps the processor read and write data, thereby increasing the processing speed: see Figure 3LVDS is a serial signal. The data bits of each master and slave are reserved in advance. The processor only needs to read the data of different data bits to know the data of each master and slave. The processor only needs to write the local information directly in the corresponding position. After the processor sends the information to the bidirectional signal conversion module, the bidirectional signal conversion module converts the LVDS signal into a parallel signal. The purpose is to maximize the use of the large bandwidth of the optical fiber to achieve large flow and high-speed information transmission.

[0042] In the embodiment of the present invention, the information collected by each circuit unit is modulated into the optical fiber medium through digital signal for transmission. Since the link transmits digital signals, it has strong anti-interference ability. In addition, the optical fiber medium has a fast transmission speed and can be applied to long-distance transmission and scenarios with high real-time requirements. The physical electrical isolation between the host and each slave is achieved through the optical fiber module, and the circuit equipment can also be protected.

[0043] In an optional embodiment, the circuit information of each circuit unit includes current value information of the circuit unit;

[0044] The processor of the circuit unit corresponding to each host on the first communication loop also performs a current summary calculation:

[0045] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and adds the current values ​​of all other circuit units to the current value of the circuit unit to obtain the current total current value of the first communication loop.

[0046] In yet another optional embodiment, the processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for current balancing:

[0047] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and finds the target circuit unit corresponding to the minimum current value through a sorting algorithm, calculates the current value difference between the target circuit unit and the current value of the circuit unit corresponding to the host, and determines whether the current value difference exceeds a preset value. If so, a first control signal is generated, and the first control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the voltage according to the first control signal.

[0048] In this embodiment, the host obtains the current data of all slaves and its own host current through the ring optical fiber communication, and the current is summed up in the host processor. All slave currents are sorted by the sorting algorithm to obtain the slave number with the minimum current, which is then compared with the host current, and the voltage of the slave with the minimum current is fine-tuned and increased. After reaching the definition point, the next process is entered again to continue sorting until all slaves have completed a sorting. If the minimum value is within the defined range, the next condition is interrupted and waits for the next condition to be triggered.

[0049] In yet another optional embodiment, the circuit information of each of the circuit units includes voltage value information of the circuit unit;

[0050] The processor of the circuit unit corresponding to each host on the first communication loop also outputs a control signal for voltage balancing:

[0051] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the voltage value information sent by all other circuit units on the first communication loop, finds the target circuit unit corresponding to the minimum voltage value through a sorting algorithm, calculates the voltage value difference between the target circuit unit and the circuit unit corresponding to the host, determines whether the voltage value difference exceeds a preset value, generates a second control signal if it exceeds, and outputs the second control signal to the target circuit unit through the first communication loop so that the target circuit unit increases the current threshold according to the first control signal.

[0052] In this embodiment, if the output mode of the parallel system is voltage, it is determined whether to enter the constant current mode. If entered, all slave voltages here are sorted by the algorithm to obtain the slave number of the minimum voltage, which is then compared with the host voltage, and the current limit of the slave with the minimum voltage is fine-tuned and increased. After reaching the definition point, the next process is entered again to continue sorting until all slaves have completed a sorting. If the minimum value is already within the defined range, an interrupt is issued to wait for the next condition to be triggered.

[0053] In another optional embodiment, the circuit information on the first communication loop includes at least one of a current value of each circuit unit on the first communication loop, a total value of current values ​​of all circuit units on the first communication loop, and a voltage value of each circuit unit on the first communication loop.

[0054] In yet another optional embodiment, the number of slaves does not exceed 255.

[0055] In the embodiment of the present invention, the circuit information transmitted by the last circuit unit module includes the global control information of the system and the current information uploaded by the previous circuit unit modules, and the current information includes the independent current information of all the previous circuit units.

[0056] The fiber-optic ring communication parallel system of the embodiment of the present invention uses multiple circuit units with fiber-optic modules to form a high-speed ring communication structure, divides the digital reference source of the host to 2 times or more of the system output stage PWM drive frequency, generates a phase synchronization clock pulse, and couples it to the high-bandwidth fiber-optic ring communication line through a two-way signal conversion module (parallel to LVDS circuit or chip logic algorithm). The slave decouples the phase synchronization clock from the fiber-optic ring communication line through the two-way signal conversion module, and after frequency multiplication, it is used as the clock of the slave, and so on. Finally, the host also uses the same method to obtain the same synchronization clock pulse of the last slave as the clock of the host. Because the coupling / decoupling can usually be performed at a speed of tens of MHZ or higher, the execution time is a few us, and the delay of the optical fiber is extremely small, various types of synchronous control of the system and synchronous measurement of instantaneous quantities can be completed in real time.

[0057] In an embodiment of the present invention, control instructions and phase synchronization pulses are sent to all slaves in a broadcast manner, reach the slaves via optical fiber ring communication, and are finally transmitted to the host. After the slave is connected to the optical fiber, it is transmitted to the slave processor via an optical fiber module and a bidirectional signal conversion module, executes the control parameters, and synchronously decouples the phase synchronization clock as the digital reference source of the slave. By analogy, the last slave sends the broadcast control instruction from the optical fiber sending module to an optical fiber receiving module of the host, and transmits it to the host processor via the host LVDS to parallel module for execution, and synchronously decouples the phase synchronization clock as the digital reference source of the host. The time error of this execution is t=N*((T1+T2)*2), where T1 is the parallel to LVDS or LVDS to parallel data cycle, T2 is the conversion time of LVDS and optical signal, and N is the number of circuit unit modules in the entire system. The optical fiber module adopts an optical fiber communication port. The circuit unit realizes real-time transmission of data through a loop communication structure.

[0058] Embodiment 2

[0059] See also Figures 2 to 4 The embodiment of the present invention discloses a parallel system with ring communication, which can realize a parallel system on a larger scale than the first embodiment, and the embodiment also has the following features:

[0060] The number of the first communication loops is at least two, and the communication nodes where the hosts on each of the first communication loops are located are sequentially connected through an optical fiber transmission channel to form a second communication loop, and the circuit unit corresponding to each of the hosts on the first communication loop serves as a communication node on the second communication loop;

[0061] The host on the first communication loop is any circuit unit on the first communication loop, wherein the circuit unit further includes a second optical fiber module, and the processor of the circuit unit obtains circuit information on the first communication loop in real time;

[0062] For each circuit unit corresponding to the host on the first communication loop, the second optical fiber module of the circuit unit receives the optical signal emitted by the previous communication node on the second communication loop, and converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor of the circuit unit; the processor integrates the circuit information on the first communication loop into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the second optical fiber module of the circuit unit; the second optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node on the second communication loop through the second communication loop.

[0063] This embodiment realizes dual communication loops by adding a second communication loop. Compared with the single communication loop of the first embodiment, it only needs to add a pair of optical fiber modules to the host of each first communication loop, which can achieve a power-order expansion of the number of parallel systems and greatly improve the scope of application.

[0064] In an embodiment of the present invention, control instructions and phase synchronization pulses are sent to all slaves in a broadcast manner, reach the slaves via optical fiber ring communication, and are finally transmitted to the host. After the slave is connected to the optical fiber, it is transmitted to the processor of the slave via an optical fiber module and a bidirectional signal conversion module, executes the control parameters, and synchronously decouples the phase synchronization clock as the digital reference source of the slave. By analogy, the last slave sends the broadcast control instruction from the optical fiber sending module to an optical fiber receiving module of the host, and transmits it to the processor of the host via the host LVDS to parallel module for execution, and synchronously decouples the phase synchronization clock as the digital reference source of the host. The time error of this execution is t=N*((T1+T2)*2), where T1 is the parallel to LVDS or LVDS to parallel data cycle, T2 is the conversion time between LVDS and optical signal, and N is the number of circuit unit modules in the entire system. The optical fiber module adopts an optical fiber communication port.

[0065] Among them, after the number of circuit unit modules is expanded through the second ring communication structure, the execution time error is t = (N + 1) * ((T1 + T2) * 2). Under higher timing synchronization requirements, or this time error can be fixed in the slave and host algorithms, and the error is fixed and deducted by the known number of units, which can reduce the time error more accurately. For example: 100 circuit unit modules form a 10x10 matrix, then the execution time error is t = (10 + 1) * ((T1 + T2) * 2), and the execution time error only increases the conversion time of one unit.

[0066] In an optional embodiment, the circuit information of each circuit unit includes current value information of the circuit unit;

[0067] The processor of the circuit unit corresponding to each host on the first communication loop also performs a current summary calculation:

[0068] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and adds the current values ​​of all other circuit units to the current value of the circuit unit to obtain the current total current value of the first communication loop.

[0069] In yet another optional embodiment, the processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for current balancing:

[0070] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and finds the target circuit unit corresponding to the minimum current value through a sorting algorithm, calculates the current value difference between the target circuit unit and the current value of the circuit unit corresponding to the host, and determines whether the current value difference exceeds a preset value. If so, a first control signal is generated, and the first control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the voltage according to the first control signal.

[0071] In yet another optional embodiment, the circuit information of each of the circuit units includes voltage value information of the circuit unit;

[0072] The processor of the circuit unit corresponding to each host on the first communication loop also outputs a control signal for voltage balancing:

[0073] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the voltage value information sent by all other circuit units on the first communication loop, finds the target circuit unit corresponding to the minimum voltage value through a sorting algorithm, calculates the voltage value difference between the target circuit unit and the circuit unit corresponding to the host, determines whether the voltage value difference exceeds a preset value, generates a second control signal if it exceeds, and outputs the second control signal to the target circuit unit through the first communication loop so that the target circuit unit increases the current threshold according to the first control signal.

[0074] In another optional embodiment, the circuit information on the first communication loop includes at least one of a current value of each circuit unit on the first communication loop, a total value of current values ​​of all circuit units on the first communication loop, and a voltage value of each circuit unit on the first communication loop.

[0075] In yet another optional embodiment, the number of slaves does not exceed 255.

[0076] The contents disclosed in the embodiments of the present invention only disclose the preferred embodiments of the present invention, which are only used to illustrate the technical solutions of the present invention rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A parallel system with ring communication, comprising a host and a plurality of slaves, wherein the host and the slaves are each a circuit unit, connected in series or in parallel; the circuit unit is a power supply, a load or a source-load; It is characterized in that Each circuit unit is provided with a first optical fiber module, a bidirectional signal conversion module and a processor; the processor acquires circuit information of the circuit unit in real time; Each of the circuit units is connected in sequence through an optical fiber transmission channel to form a first communication loop, and each of the circuit units serves as a communication node on the first communication loop; For each of the circuit units, the first optical fiber module of the circuit unit receives an optical signal emitted by a previous communication node on the first communication loop, and converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor; the processor integrates the circuit information of the circuit unit into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the first optical fiber module; the first optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node through the first communication loop.

2. The parallel system according to claim 1, characterized in that: The number of the first communication loops is at least two, and the communication nodes where the hosts on each of the first communication loops are located are sequentially connected through an optical fiber transmission channel to form a second communication loop, and the circuit unit corresponding to each of the hosts on the first communication loop serves as a communication node on the second communication loop; The host on the first communication loop is any circuit unit on the first communication loop, wherein the circuit unit further includes a second optical fiber module, and the processor of the circuit unit obtains circuit information on the first communication loop in real time; For each circuit unit corresponding to the host on the first communication loop, the second optical fiber module of the circuit unit receives the optical signal emitted by the previous communication node on the second communication loop, and converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor of the circuit unit; the processor integrates the circuit information on the first communication loop into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the second optical fiber module of the circuit unit; the second optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node on the second communication loop through the second communication loop.

3. The parallel system according to claim 1 or 2, characterized in that: The circuit information of each circuit unit includes current value information of the circuit unit; The processor of the circuit unit corresponding to each host on the first communication loop also performs a current summary calculation: After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and adds the current values ​​of all other circuit units to the current value of the circuit unit to obtain the current total current value of the first communication loop.

4. The parallel system according to claim 3, characterized in that: The processor of the circuit unit corresponding to each host on the first communication loop also outputs a control signal for current balancing: After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and finds the target circuit unit corresponding to the minimum current value through a sorting algorithm, calculates the current value difference between the target circuit unit and the current value of the circuit unit corresponding to the host, and determines whether the current value difference exceeds a preset value. If so, a first control signal is generated, and the first control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the voltage according to the first control signal.

5. The parallel system according to claim 1 or 2, characterized in that: The circuit information of each circuit unit includes voltage value information of the circuit unit; The processor of the circuit unit corresponding to each host on the first communication loop also outputs a control signal for voltage balancing: After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the voltage value information sent by all other circuit units on the first communication loop, finds the target circuit unit corresponding to the minimum voltage value through a sorting algorithm, calculates the voltage value difference between the target circuit unit and the circuit unit corresponding to the host, determines whether the voltage value difference exceeds a preset value, generates a second control signal if it exceeds, and outputs the second control signal to the target circuit unit through the first communication loop so that the target circuit unit increases the current threshold according to the first control signal.

6. The parallel system according to claim 1 or 2, characterized in that: The circuit information on the first communication loop includes at least one of a current value of each circuit unit on the first communication loop, a total value of current values ​​of all circuit units on the first communication loop, and a voltage value of each circuit unit on the first communication loop.

7. The parallel system according to claim 1 or 2, characterized in that: The number of the slaves does not exceed 255.

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