A timing system with nanosecond synchronization error

Abstract

The present invention discloses a timing system with nanosecond synchronization error, including a main controller card and a functional subcard that is timed by the main controller card, wherein the main controller card and the functional subcard are connected via a backplane timing bus; the main controller card includes a first IRIG‑G (DC) decoder and a first MLVDS transceiver, and the functional subcard includes a second automatic event trigger, a second soft-core CPU, a second IRIG‑G (DC) decoder, a second MLVDS transceiver, and a second local clock; latching the current time point includes latching the coarse time information of the functional subcard and the fine time information counted by the second local clock in each first cycle; the synchronization error is calculated using the crystal oscillator accuracy of the second local clock and the time length of the first cycle. The synchronization error of the present invention is only accumulated in the first cycle, the synchronization error is very low, and the backplane timing bus adopts an MLVDS differential pair for transmission, so the error in the signal transmission process can be ignored.

Description

Technical Field

[0001] The invention relates to the field of signal acquisition, and in particular to a timing system with nanosecond-level synchronization error. Background Art

[0002] Function cards, also commonly called industrial control cards or data acquisition / output cards, play an important role in the field of industrial automation and process control. One of their main functions is to be applied to event timestamps and event synchronization, ensuring that multiple acquisition devices can accurately record the time when an event occurs and achieve high-precision synchronization. For example: a switch quantity refers to a signal with two states (such as on / off, high / low, 1 / 0). In industrial automation, switch signals are often used to represent the state of a device or control instructions. Through function cards, accurate timing and synchronization of switch events can be achieved. When the switch signal changes, the function card records the timestamp of the event and synchronizes with other acquisition devices to ensure that all devices can accurately record the time of the same event. Analog refers to continuously changing physical quantities such as voltage, current, temperature, pressure, etc. These signals are common in industrial processes and usually need to be accurately measured and recorded. Function cards can collect analog signals and process them to obtain accurate timestamps. Similarly, they can also synchronize with other acquisition devices to ensure that the timestamps of all related events are consistent.

[0003] When the same event occurs and multiple data needs to be collected, each functional card needs to use the architecture system of multiple functional cards to obtain the corresponding type of event data and time data when the event occurs. However, it is important to accurately record the time of event occurrence and reduce the "synchronization error" of multiple devices collecting events:

[0004] (1) During the signal acquisition process, synchronization errors can lead to inconsistent data between different acquisition points, thus affecting the accuracy of data analysis. Through precise timing, it can be ensured that each acquisition point performs data acquisition under the same time reference, thereby eliminating the error caused by time differences and improving the accuracy of signal acquisition. This is especially important for fields that require high-precision data acquisition, such as nuclear power research, aerospace, and intelligent manufacturing.

[0005] (2) Synchronization errors may also cause system instability and affect the normal operation of the system. In a data acquisition system, time synchronization between various acquisition points is the basis for ensuring stable operation of the system. If the time between acquisition points is not synchronized, it may cause data confusion, loss or errors, which in turn affects the stability and reliability of the entire system. Through precise timing, it can be ensured that each acquisition point works under the same time reference, thereby ensuring the stability and reliability of the system.

[0006] (3) In some specific industries and applications, such as power systems and financial trading systems, the requirements for time synchronization are very high. In these fields, even a small synchronization error can lead to serious consequences. For example, in power systems, inaccurate time synchronization may cause protection devices to malfunction or refuse to operate, affecting the safe operation of the power system; in financial trading systems, inaccurate time synchronization may lead to inconsistent or delayed transaction data, affecting the fairness and accuracy of transactions. Therefore, in these fields, accurate timing is crucial to reducing synchronization errors and ensuring stable system operation.

[0007] However, the existing technology usually uses timing equipment and related protocols to achieve this, and not only the synchronization error can only reach the millisecond level, but also the event collection accuracy is not high. Summary of the invention

[0008] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a timing system with nanosecond-level synchronization error.

[0009] The objective of the present invention is achieved through the following technical solutions:

[0010] A first aspect of the present invention provides a timing system with nanosecond synchronization error, comprising a main controller card and a functional daughter card whose timing is served by the main controller card, wherein the main controller card and the functional daughter card are connected via a backplane timing bus;

[0011] The main controller card includes a first IRIG-G (DC) decoder, a first MLVDS transceiver, and the functional daughter card includes a second automatic event trigger, a second soft-core CPU, a second IRIG-G (DC) decoder, a second MLVDS transceiver, and a second local clock;

[0012] For the main controller card, the first IRIG-G (DC) decoder extracts the timestamp of the main controller card coarse time information refreshed in each first cycle to form a G code pulse and sends it to the backplane timing bus through the first MLVDS transceiver; the first cycle corresponds to the IRIG-G (DC) protocol;

[0013] For the functional daughter card, the second MLVDS transceiver receives the G code pulse from the backplane timing bus every first cycle and sends it to the second IRIG-G (DC) decoder, and the second IRIG-G (DC) decoder decodes the received G code pulse to obtain the coarse time information of the functional daughter card; the second automatic event trigger receives the external trigger signal, encapsulates it into a first code, and then sends it to the second IRIG-G (DC) decoder through the AVALON bus, and the second IRIG-G (DC) decoder receives the first code and triggers the time latch to latch the current time point, and re-encodes the current time point and the first code to form a second code; the second soft core CPU obtains the current time point to obtain the current event triggering situation and / or obtains the second code to obtain the historical event triggering situation;

[0014] The latching of the current time point includes latching the coarse time information of the functional daughter card and the fine time information of the count of the second local clock in each first cycle;

[0015] The synchronization error is calculated using the crystal oscillator accuracy of the second local clock and the time length of the first cycle.

[0016] Further, the main controller card also includes a first automatic event trigger, a first soft-core CPU and a first local clock;

[0017] For the main controller card, the first automatic event trigger receives an external trigger signal, encapsulates it into a first code, and then sends it to the first IRIG-G (DC) decoder through the AVALON bus. The first IRIG-G (DC) decoder receives the first code and triggers the time latch to latch the current time point, and re-encodes the current time point and the first code to form a second code; the first soft-core CPU obtains the current time point to obtain the current event triggering situation and / or obtains the second code to obtain the historical event triggering situation;

[0018] The latching of the current time point includes latching the coarse time information of the main controller card and the fine time information of the count of the first local clock in each first cycle.

[0019] Furthermore, the fine time information is obtained by refreshing the fine time every second cycle and extracting the time difference, and the second cycle corresponds to the local clock frequency;

[0020] The fine time information is specifically the time difference information generated by the local clock in each first cycle. The local clock includes a counter unit and a fine time calculation unit. The maximum count number of the counter unit is the first cycle divided by the second cycle. The counter unit performs an addition operation every second cycle until the maximum count number is reached and a reset operation is performed. When the time latch is triggered, the fine time calculation unit multiplies the count value of the counter unit by the second cycle to obtain the time difference information as the fine time information.

[0021] Furthermore, the synchronization error is calculated as follows:

[0022] Calculate the proportional relationship between the duration corresponding to the crystal oscillator accuracy of the local clock and the first cycle;

[0023] The synchronization error in the first cycle is calculated using the proportional relationship.

[0024] Furthermore, the main controller card further includes a time information generator and a bus signal distributor, and the first IRIG-G (DC) decoder further includes a code element extraction module and a timing information pulse extraction module; the main controller card coarse time is updated once every third period, and the update mode includes:

[0025] The time information generator sends the generated covering time pulse to the bus signal distributor every third cycle, and the bus signal distributor sends the covering time pulse to the first IRIG-G (DC) decoder;

[0026] The first IRIG-G (DC) decoder processes the received coverage time pulse to obtain coverage time information, where the coverage time information includes extracting the code element of the coverage time pulse by using the code element extraction module and extracting the timing information and pulse of the coverage time pulse by using the timing information pulse extraction module;

[0027] The overlay time information is used to overlay and update the main controller card rough time information.

[0028] Further, the coverage time pulse generated by the time information generator is a relative coverage time pulse, the time information generator includes an IRIG-G (DC) encoder, and the IRIG-G (DC) encoder includes a codeword generator, a time extraction pre-carry processing module and a time synchronizer;

[0029] The time information generator generates relative coverage time pulses, including:

[0030] The first soft-core CPU sends the initial time information to the IRIG-G (DC) encoder via the AVALON bus, and the IRIG-G (DC) encoder starts timing based on the initial time information to obtain relative coverage time information;

[0031] The code element generator of the IRIG-G (DC) encoder converts the relative coverage time information into code elements, and then the time extraction pre-carry processing module and the time synchronizer convert the code elements into relative coverage time pulses, and send the relative coverage time pulses to the bus signal distributor.

[0032] Further, the coverage time pulse generated by the time information generator is a real coverage time pulse, and the time information generator includes a second CAT5e network port and a fourth MLVDS transceiver;

[0033] The time information generator generates real coverage time pulses, including:

[0034] The second CAT5e network port receives the real coverage time pulse sent by the external high-precision timing module, and forwards it to the bus signal distributor through the fourth MLVDS transceiver.

[0035] Furthermore, the automatic event trigger includes a signal preprocessing module, a multi-channel data source module, a data filter module, a threshold discrimination module and an event pulse generator; the signal preprocessing module of the automatic event trigger receives an external trigger signal for digital quantity processing, and sends it to the data filter module and the threshold discrimination module in sequence through the multi-channel data source module for filtering and threshold screening, and the screened data source directly triggers the event pulse generator to form a first code including a trigger channel and a trigger event;

[0036] The IRIG-G (DC) decoder includes a DMA data transmission module, a time latch, and a time information register group; the DMA data transmission module of the IRIG-G (DC) decoder receives the first code through the AVALON bus and triggers the time latch at the same time, and the time latch puts the decoded current time point into the time information register group.

[0037] Further, the soft-core CPU reads the current time point data from the time information register group of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the current trigger event; and / or:

[0038] The IRIG-G (DC) decoder also includes an event FIFO module; the DMA data transmission module re-encodes the current time point and the first code taken out from the time information register group to form a second code including the trigger channel, trigger time and trigger event; the second code is placed in the event FIFO module for storage; the soft-core CPU reads the second code from the event FIFO module of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the historical event trigger.

[0039] Further, the main controller card also includes a third MLVDS transceiver and a first CAT5e network port;

[0040] The bus signal distributor sends the coverage time pulse to the outside through the third MLVDS transceiver and the first CAT5e network port every third cycle.

[0041] The beneficial effects of the present invention are:

[0042] In an exemplary embodiment of the present invention, the main controller card is used to send G code pulses to the function sub-card used for event triggering collection every first cycle to perform timing operation, so that each function sub-card uses the coarse time obtained by decoding the G code pulse by the decoder to perform coarse time latching when the event is triggered; at the same time, in order to improve the latching accuracy, each function sub-card is provided with a second local clock, which is used to count in each first cycle, so as to obtain fine time information with higher accuracy than the coarse time information of the function sub-card for fine time latching. Since the second local clock counts only in each first cycle (zeroing is performed when the maximum count number is reached in each first cycle), the generated synchronization error is only accumulated in the last first cycle, and the synchronization error is very low (usually nanosecond level). In addition, the backplane timing bus adopts MLVDS differential pairs for transmission, and the error in the signal transmission process can be ignored. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A structural block diagram of a timing system with nanosecond-level synchronization error provided in an exemplary embodiment of the present invention;

[0044] Figure 2 A structural block diagram of a timing system with a nanosecond-level synchronization error after a main controller card is added with an event trigger provided in another exemplary embodiment of the present invention;

[0045] Figure 3 A structural block diagram of a timing system with a nanosecond synchronization error in which a time information generator is added to a main controller card provided in another exemplary embodiment of the present invention;

[0046] Figure 4 A schematic diagram of a covering time pulse provided in an exemplary embodiment of the present invention;

[0047] Figure 5 A schematic diagram of a time information generator generating a relative coverage time pulse provided by an exemplary embodiment of the present invention;

[0048] Figure 6 A schematic diagram of a time information generator generating a real coverage time pulse provided by an exemplary embodiment of the present invention;

[0049] Figure 7A schematic diagram of the specific structure of an automatic event trigger and an IRIG-G (DC) decoder provided by an exemplary embodiment of the present invention;

[0050] Figure 8 A flow chart of an event triggering mechanism provided for an exemplary embodiment of the present invention;

[0051] Fig. 9 A schematic diagram of the specific structure of an automatic event trigger and an IRIG-G (DC) decoder provided for another exemplary embodiment of the present invention;

[0052] Fig.10 A flow chart of an event reading mechanism provided for an exemplary embodiment of the present invention;

[0053] Fig.11 A structural block diagram of a timing system in which a main controller card provided in another exemplary embodiment of the present invention adds a nanosecond synchronization error to an external chassis;

[0054] Fig.12 An exemplary embodiment of the present invention is provided based on Figure 7 or Fig. 9 A schematic diagram of the architecture of the main controller card latching relative time;

[0055] Fig.13 An exemplary embodiment of the present invention is provided based on Figure 7 or Fig. 9 A schematic diagram of the architecture of the main controller card latching the real time;

[0056] Fig.14 An exemplary embodiment of the present invention is provided based on Figure 7 or Fig. 9 A schematic diagram of the architecture of the functional daughter card latch time;

[0057] Fig.15 A schematic diagram of an architecture for latching relative time in a chassis of a main controller card and a functional daughter card provided by an exemplary embodiment of the present invention;

[0058] Fig.16 A schematic diagram of an architecture for locking real time in a chassis of a main controller card and a functional daughter card provided by an exemplary embodiment of the present invention;

[0059] Fig.17 A schematic diagram of a structure for relative time locks of multiple chassis provided by an exemplary embodiment of the present invention;

[0060] Fig.18 A schematic diagram of an architecture for multiple chassis to lock real time is provided as an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0061] The technical solution of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] In the description of the present invention, it should be noted that the directions or positional relationships indicated by "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are directions or positional relationships based on the drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0063] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0064] IRIG-G(DC): The full name is Inter Range Instrumentation Group-G(DC) or IRIG-G(DC), which is a time code format commonly used for time synchronization and timestamp recording.

[0065] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0066] See also Figure 1 , Figure 1 A structural block diagram of a timing system with nanosecond-level synchronization error provided in an exemplary embodiment of the present invention is shown, comprising a main controller card and a functional daughter card whose timing is served by the main controller card, wherein the main controller card and the functional daughter card are connected via a backplane timing bus;

[0067] The main controller card includes a first IRIG-G (DC) decoder, a first MLVDS transceiver, and the functional daughter card includes a second automatic event trigger, a second soft-core CPU, a second IRIG-G (DC) decoder, a second MLVDS transceiver, and a second local clock;

[0068] For the main controller card, the first IRIG-G (DC) decoder extracts the timestamp of the main controller card coarse time information refreshed in each first cycle to form a G code pulse and sends it to the backplane timing bus through the first MLVDS transceiver; the first cycle corresponds to the IRIG-G (DC) protocol;

[0069] For the functional daughter card, the second MLVDS transceiver receives the G code pulse from the backplane timing bus every first cycle and sends it to the second IRIG-G (DC) decoder, and the second IRIG-G (DC) decoder decodes the received G code pulse to obtain the coarse time information of the functional daughter card; the second automatic event trigger receives the external trigger signal, encapsulates it into a first code, and then sends it to the second IRIG-G (DC) decoder through the AVALON bus, and the second IRIG-G (DC) decoder receives the first code and triggers the time latch to latch the current time point, and re-encodes the current time point and the first code to form a second code; the second soft core CPU obtains the current time point to obtain the current event triggering situation and / or obtains the second code to obtain the historical event triggering situation;

[0070] The latching of the current time point includes latching the coarse time information of the functional daughter card and the fine time information of the count of the second local clock in each first cycle;

[0071] The synchronization error is calculated using the crystal oscillator accuracy of the second local clock and the time length of the first cycle.

[0072] Specifically, in this exemplary embodiment, the main controller card is the transmitter of the IRIG-G (DC) code (hereinafter referred to as the G code), the function sub-card is the receiver of the G code, and is also the event signal trigger acquisition end. The main controller card extracts the timestamp of the refreshed main controller card coarse time information through each first cycle (corresponding to the IRIG-G (DC) protocol, for example, 0.1ms), and forms a G code pulse as the coarse time of the function sub-card, and sends the G code pulse to the backplane timing bus through the first MLVDS transceiver; each function sub-card connected to the backplane timing bus will receive the G code pulse sent by the main controller card through the second MLVDS transceiver in each first cycle, and decode the G code pulse through the second IRIG-G (DC) decoder to obtain the coarse time information of the function sub-card, and obtain the coarse time information of the function sub-card corresponding to the time when the event is triggered. In addition, the function sub-card itself is also provided with a second local clock, and the second local clock is used to count in each first cycle, so as to obtain fine time information with higher accuracy than the coarse time information of the function sub-card. Due to the accuracy limitation of the second local clock, synchronization errors will occur, but the fine time counting method only accumulates synchronization errors in each first cycle (because the fine time information in the latched time point is the count of the second local clock in each first cycle), so that the synchronization error is reduced to the nanosecond level (subsequent exemplary embodiments will be demonstrated). At the same time, the backplane timing bus in the chassis uses MLVDS differential pairs for transmission, and the phase accuracy is much higher than the TTL level. The error generated during signal transmission is negligible compared to the nanosecond error of the above-mentioned clock synchronization delay.

[0073] At the same time, for the event triggering of the functional sub-card, the second automatic event trigger of the functional sub-card receives the external trigger signal, encapsulates it into a first code, and then sends it to the second IRIG-G (DC) decoder through the AVALON bus. The second IRIG-G (DC) decoder receives the first code and triggers the time latch to latch the current time point, and re-encodes the current time point and the first code to form a second code; the second soft-core CPU obtains the current time point to obtain the current event triggering situation and / or obtains the second code to obtain the historical event triggering situation.

[0074] In summary, in this exemplary embodiment, the main controller card is used to send G-code pulses to the function sub-card used for event triggering collection every first cycle to perform timing operation, so that each function sub-card uses the coarse time obtained by decoding the G-code pulse by the decoder to perform coarse time latching when the event is triggered; at the same time, in order to improve the latching accuracy, each function sub-card is provided with a second local clock, which is used to count in each first cycle, so as to obtain fine time information with higher accuracy than the coarse time information of the function sub-card for fine time latching. Since the second local clock counts only in each first cycle (zeroing is performed when the maximum count number is reached in each first cycle), the synchronization error generated is only accumulated in the last first cycle, and the synchronization error is very low (usually nanosecond level). In addition, the backplane timing bus adopts MLVDS differential pairs for transmission, and the error in the signal transmission process can be ignored.

[0075] More preferably, in an exemplary embodiment, if Figure 2 As shown, the main controller card also includes a first automatic event trigger, a first soft-core CPU and a first local clock;

[0076] For the main controller card, the first automatic event trigger receives an external trigger signal, encapsulates it into a first code, and then sends it to the first IRIG-G (DC) decoder through the AVALON bus. The first IRIG-G (DC) decoder receives the first code and triggers the time latch to latch the current time point, and re-encodes the current time point and the first code to form a second code; the first soft-core CPU obtains the current time point to obtain the current event triggering situation and / or obtains the second code to obtain the historical event triggering situation;

[0077] The latching of the current time point includes latching the coarse time information of the main controller card and the fine time information of the count of the first local clock in each first cycle.

[0078] Specifically, in this exemplary embodiment, the main controller card not only serves as a G-code generating end, but also can perform event-triggered acquisition, that is, a first automatic event trigger, a first soft-core CPU and a first local clock are added to the main controller card. The event triggering method is the same as the triggering method of the functional daughter card, and the counting method of the fine time information is also the same as the counting method of the fine time information of the functional daughter card. The only difference is that the coarse time information is directly acquired rather than obtained through decoding of the G-code pulse sent from the outside.

[0079] More preferably, in an exemplary embodiment, the fine time information is obtained by refreshing the fine time every second cycle and extracting the time difference, and the second cycle corresponds to the local clock frequency;

[0080] The fine time information is specifically the time difference information generated by the local clock in each first cycle. The local clock includes a counter unit and a fine time calculation unit. The maximum count number of the counter unit is the first cycle divided by the second cycle. The counter unit performs an addition operation every second cycle until the maximum count number is reached and a reset operation is performed. When the time latch is triggered, the fine time calculation unit multiplies the count value of the counter unit by the second cycle to obtain the time difference information as the fine time information.

[0081] Specifically, in this exemplary embodiment, a specific calculation method of fine time information (functional daughter card and main controller card (if any)) is disclosed, and the coarse time information and the fine time information are compared and explained in detail here:

[0082] For the coarse time information (functional daughter card or main controller card), it refers to obtaining the timestamp of the coarse time refreshed based on the first cycle (preferably 0.1ms, i.e. 100us) corresponding to the IRIG-G (DC) protocol, wherein the coarse time (the coarse time refresh module storage can be set separately) is refreshed every first cycle (the specific refresh method is detailed in the subsequent exemplary embodiments); when the time latch latches the current time point, the timestamp of the coarse time is obtained to obtain the coarse time information at the current time point; at this time, the event synchronization time of the functional daughter card and the main controller card can be accurate to microseconds, for example: XXyears:XXdays:XXhours:XXminutes:XXseconds+100us.

[0083] The fine time information refers to the fine time obtained by counting the second cycle (for example, when the local clock frequency is 100Mhz, the clock cycle of the local clock, that is, the second cycle, is 10ns) corresponding to the local clock frequency of the functional daughter card and the main controller card (if any). The time difference information and counting related contents are explained by taking the first cycle of 0.1ms (when matching the second cycle unit, the corresponding is 100000ns) and the second cycle of 10ns as an example (other first cycles and second cycles are analogous): the maximum number of counts of the counter unit is the first cycle divided by the second cycle, that is, 100000ns / 10ns=10000 (times), that is, 10000 counts can be performed in each first cycle (coarse time), and the counter unit performs an increment operation every 10ns until the count reaches 10000. The counting starts again in the next second cycle; when the time latch latches the current time point, the count value of the counter unit is obtained. For example, if the count value is 351, the fine time calculation unit calculates the time difference information of 351*10ns=3510ns (i.e., the count value of the above-mentioned counter unit multiplied by the second cycle) generated by the local clock operation of the function daughter card and the main controller card (if any) within a first cycle (0.1ms) after the current coarse time, and uses this information as the fine time information; at this time, the synchronization time of the function daughter card and the main controller card (if any) (based on the microsecond level of the coarse time information) can be accurate to the nanosecond level, for example: XXyears:XXdays:XXhours:XXminutes:XXseconds+100us+3510ns.

[0084] In summary, in this exemplary embodiment, on top of the basic protocol time accuracy (coarse time accuracy, microsecond level) based on the protocol transmission process, the local clock is used for fine time calculation, an independent counter is set inside the clock of each functional card component and an innovative counter reset command design is used. The use of nanosecond refresh count can greatly reduce errors and further improve the time accuracy of the time latch when an event occurs (i.e., to the nanosecond level), which is particularly suitable for technical fields that require very high time accuracy.

[0085] More preferably, in an exemplary embodiment, the synchronization error is calculated as follows:

[0086] Calculate the proportional relationship between the duration corresponding to the crystal oscillator accuracy of the local clock and the first cycle;

[0087] The synchronization error in the first cycle is calculated using the proportional relationship.

[0088] Specifically, in this exemplary embodiment, a specific calculation method of the synchronization error is disclosed. When the functional daughter card uses a crystal oscillator with an accuracy of ±20PPM (the clock is generated by the crystal oscillator, which is the crystal oscillator deviation in the worst case, and the crystal oscillator deviation is very small in actual circumstances), the clock frequency is 50Mhz, and the clock period (the inverse of the clock frequency) is 1*10 9 / (50*10 6 ) = 20ns. The frequency deviation of the clock (clock frequency * crystal oscillator accuracy) is approximately: 50*10 6 * (20 / 10 6 ) = 1000Hz, then in 1 second, the accumulated error is 1000Hz * 20ns = 20us (frequency deviation * clock period). If a high-precision crystal with temperature compensation is selected, the error will be further reduced.

[0089] In this exemplary embodiment, the crystal oscillator accuracy of ±20PPM corresponds to a duration of 1 second and an accumulated error of 20us. Then, in the first cycle of 0.1ms, an error of 2ns is accumulated. The calculation formula is: 20*10 3 *0.1*10 6 / (1*10 9 ) = 2ns.

[0090] More preferably, in an exemplary embodiment, if Figure 3 As shown, the main controller card also includes a time information generator and a bus signal distributor, and the first IRIG-G (DC) decoder also includes a code element extraction module and a timing information pulse extraction module; the main controller card coarse time is updated once every third period, and the coverage update method includes:

[0091] The time information generator sends the generated covering time pulse to the bus signal distributor every third cycle, and the bus signal distributor sends the covering time pulse to the first IRIG-G (DC) decoder;

[0092] The first IRIG-G (DC) decoder processes the received coverage time pulse to obtain coverage time information, where the coverage time information includes extracting the code element of the coverage time pulse by using the code element extraction module and extracting the timing information and pulse of the coverage time pulse by using the timing information pulse extraction module;

[0093] The overlay time information is used to overlay and update the main controller card rough time information.

[0094] Specifically, in this exemplary embodiment, with respect to the coarse time information of the main controller card, in order to make the coarse time more accurate (reduce the error in the internal time calculation), a coverage update is performed using a coverage time pulse generated by the time information generator every third cycle (for example, 0.01s, corresponding to 10ms), wherein the coverage time pulse generated by the time information generator is accurate time information.

[0095] Specifically, the time information generator sends the generated covering time pulse to the bus signal distributor every third cycle, the bus signal distributor sends the covering time pulse to the first IRIG-G (DC) decoder, the first IRIG-G (DC) decoder processes the received covering time pulse to obtain covering time information, and finally uses the covering time information to cover and update the coarse time. The covering time information includes the code element of the covering time pulse extracted by the code element extraction module, and the timing information and pulse of the covering time pulse extracted by the timing information pulse extraction module.

[0096] In a specific exemplary embodiment, the coverage time pulse is as follows Figure 4 As shown, specifically: each frame pulse includes 100 bits of data, which are respectively allocated as year, day, hour, minute, second, 0.1 second, and 0.01 second as timing information; each bit of data is represented by 0 code element, 1 code element or P code element, 0 code element and 1 code element represent 0 and 1 in binary respectively, and P code element represents the cutoff of the corresponding bit. Among them, the 1st to 10th bits represent seconds, the 11th to 20th bits represent minutes, the 21st to 30th bits represent hours, the 31st to 45th bits represent days, the 46th to 50th bits represent 0.1 seconds, the 51st to 60th bits represent 0.01 seconds, the 61st to 70th bits represent years, and the 71st to 100th bits represent control functions. Figure 4 The coverage time pulses in represent: 24 years, 304 days, 11 hours, 15 minutes, and 30.26 seconds. Figure 4 The “TIME FRAME” in the table means that the third period is 0.01 seconds, and the “INDEX COUNT” means that the first period is 0.1 ms.

[0097] More preferably, in an exemplary embodiment, if Figure 5As shown, the coverage time pulse generated by the time information generator is a relative coverage time pulse, the time information generator includes an IRIG-G (DC) encoder, and the IRIG-G (DC) encoder includes a codeword generator, a time extraction pre-carry processing module and a time synchronizer;

[0098] The time information generator generates relative coverage time pulses, including:

[0099] The first soft-core CPU sends the initial time information to the IRIG-G (DC) encoder via the AVALON bus, and the IRIG-G (DC) encoder starts timing based on the initial time information to obtain relative coverage time information;

[0100] The code element generator of the IRIG-G (DC) encoder converts the relative coverage time information into code elements, and then the time extraction pre-carry processing module and the time synchronizer convert the code elements into relative coverage time pulses, and send the relative coverage time pulses to the bus signal distributor.

[0101] Specifically, in this exemplary embodiment, the coverage time pulse generated by the time information generator of the main controller card is a relative coverage time pulse, that is, when synchronization with the external real time is not required, the relative time is for the entire system, and at this time the coverage time of the main controller card and the coverage time sent by the main controller card to the functional daughter card are both relative coverage times. The specific generation process of relative time is as follows:

[0102] The first soft-core CPU sends the initial time information to the IRIG-G (DC) encoder via the AVALON bus. The IRIG-G (DC) encoder will start timing based on the initial time to obtain the relative time information, and the soft-core CPU will no longer be required to participate. However, during the process, the first soft-core CPU can obtain the current time of the IRIG-G (DC) encoder and correct it (the correction operation itself may introduce errors, so the correction operation should be a slow operation, such as once an hour or a day, or even no correction, because the accumulation of errors will not affect the accuracy of the relative time).

[0103] After the initial time information enters the IRIG-G (DC) encoder, the symbol generator converts the initial time information into a symbol, and then the time extraction / pre-carry processing module and the time synchronizer convert the symbol into a relative coverage time pulse, and then the relative coverage time pulse is transmitted to the bus signal distributor, and the relative coverage time pulse is generated. Subsequently, the bus signal distributor transmits the relative coverage time pulse to the first IRIG-G (DC) decoder for decoding to obtain the relative coverage time information (to achieve relative time acquisition within the board), or transmits it to the third MLVDS transceiver and the first CAT5e network port to transmit pulses externally (to achieve coarse time synchronization of other chassis, such as the subsequent cross-chassis exemplary embodiment).

[0104] More preferably, in an exemplary embodiment, if Figure 6 As shown, the coverage time pulse generated by the time information generator is a real coverage time pulse, and the time information generator includes a second CAT5e network port and a fourth MLVDS transceiver;

[0105] The time information generator generates real coverage time pulses, including:

[0106] The second CAT5e network port receives the real coverage time pulse sent by the external high-precision timing module, and forwards it to the bus signal distributor through the fourth MLVDS transceiver.

[0107] Specifically, in this exemplary embodiment, the coverage time pulse generated by the time information generator of the main controller card is a real coverage time pulse, that is, if synchronization with external real time is required, an external high-precision timing module (which can be a GPS / 5G / PTP high-precision timing module) needs to be connected, and the high-precision timing module sends the real coverage time pulse to the main controller card, specifically, the second CAT5e network port of the main controller card receives the external real coverage time pulse and transmits it to the fourth MLVDS transceiver, and the fourth MLVDS transceiver transmits the real coverage time pulse to the bus signal distributor, so that the real coverage time pulse is generated. Subsequently, the bus signal distributor sends the real coverage time pulse to the first IRIG-G (DC) decoder for decoding to obtain the real coverage time information (to achieve relative time acquisition within the board), or transmits it to the third MLVDS transceiver and the first CAT5e network port to transmit pulses externally (to achieve coarse time synchronization of other chassis, such as the subsequent cross-chassis exemplary embodiment).

[0108] It should be noted that the latching process for latching real time and relative time is the same, which mainly depends on whether the main controller card uses an external high-precision timing module.

[0109] More preferably, in an exemplary embodiment, if Figure 7As shown, the automatic event trigger includes a signal preprocessing module, a multi-channel data source module, a data filter module, a threshold discrimination module and an event pulse generator; the signal preprocessing module of the automatic event trigger receives an external trigger signal for digital quantity processing, and sends it to the data filter module and the threshold discrimination module in sequence through the multi-channel data source module for filtering and threshold screening, and the screened data source directly triggers the event pulse generator to form a first code including a trigger channel and a trigger event;

[0110] The IRIG-G (DC) decoder includes a DMA data transmission module, a time latch, and a time information register group; the DMA data transmission module of the IRIG-G (DC) decoder receives the first code through the AVALON bus and triggers the time latch at the same time, and the time latch puts the decoded current time point into the time information register group. (In addition, in Figure 7 In the figure, the code element extraction module and the timing information pulse extraction module in the aforementioned exemplary embodiment are also shown, and the coarse time refresh module and the fine time refresh module correspond to the coarse time information extraction and the fine time information extraction in the aforementioned exemplary embodiment, respectively.

[0111] Specifically, in this exemplary embodiment, an event triggering mechanism applicable to both the main controller card and the function daughter card is disclosed, such as Figure 8 As shown:

[0112] S1: The external trigger signal (switch quantity, analog quantity, level signal or pulse, not limited) is transmitted to the signal preprocessing module of the automatic event trigger through the input terminal of the function card (converting the analog quantity into digital quantity);

[0113] S2: After preprocessing, a multi-channel data source module is connected to an automatic event trigger. The multi-channel data source module is divided into multiple data source channels (the number of channels is limited by the system's own internal resources). In one exemplary embodiment (such as Fig. 9 As shown in the figure, 32 data source channels are set, namely CH1 data source, CH2 data source, CH3 data source..........CH32 data source;

[0114] S3: Transfer the data sources of different channels to the data filter module, and perform technical filtering according to the filtering rules set by the data filter module. The filtering length is adjustable. Specifically, when the input data is a switch quantity, the filtering rule is an "anti-jitter" filter. For example, when the input data is continuously collected as N 1s, the filter stage will output 1. The same is true when the input data is 0. The N value here can be set. When the input data is an analog quantity, the filtering rule is a "sliding average filter". For example, a 5-point sliding filter is performed on the input data to eliminate peak jitter and prevent false threshold judgment.

[0115] S4: The data source filtered by the data filter is transmitted to the threshold discrimination module. The threshold parameters of the threshold discrimination module are set by the soft-core CPU (transmitted through the AVALON bus). The determined value or upper and lower limits of the threshold parameters are set to filter the data source that meets the parameter setting.

[0116] S5: The data source screened by the threshold discrimination module directly triggers the event pulse generator. The event pulse generator encodes different data sources to form a first code. The encoding rule of the first code is: 1: trigger event; 2: trigger event; 3: trigger event........32: trigger event (different serial numbers represent different channel names. The trigger event refers to what rule triggers it, for example: rising edge or falling edge);

[0117] The above steps (S1~S5) are all executed in sequence by automatic event triggers.

[0118] S6: The event pulse generator sends the first code to the DMA data transmission module of the IRIG-G (DC) decoder through the AVALON bus. The DMA data transmission module triggers the time latch at the same time when receiving the code. After the time latch performs the latching step, the decoded current time point is placed in the time information register group.

[0119] The above steps (S6) are performed sequentially by the IRIG-G (DC) decoder.

[0120] The specific benefits achieved by the DMA data transmission module in this exemplary embodiment include: greatly improving time accuracy: if DMA is not used and a soft-core CPU is used for latching, a random error (ranging from a few microseconds to a few milliseconds) will be introduced, which will have a great impact on the system synchronization accuracy and cannot be eliminated; while using DMA will only introduce a fixed error at the nanosecond level, which can be easily eliminated in later applications.

[0121] More preferably, in an exemplary embodiment, the soft-core CPU reads the current time point data from the time information register group of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the current trigger event; and / or:

[0122] like Fig. 9 As shown, the IRIG-G (DC) decoder also includes an event FIFO module; the DMA data transmission module re-encodes the current time point and the first code taken out from the time information register group to form a second code including a trigger channel, a trigger time and a trigger event; the second code is placed in the event FIFO module for storage; the soft-core CPU reads the second code from the event FIFO module of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the historical event trigger.

[0123] Specifically, it is disclosed in Fig. 9 The event reading mechanism based on the event trigger mechanism is applicable to both the main controller card and the function daughter card, such as Fig.10 As shown:

[0124] S7: The DMA data transmission module combines the current time point stored in the time information register group and the first code sent by the event pulse generator into a set of data for re-encoding to form a second code including the trigger channel, trigger time and trigger event. The second code setting rule is: trigger channel (serial number): trigger time (time): trigger event (trigger rule), for example 1: time: rising edge; 2: time: falling edge.......... (wherein the serial number represents the channel name, which is represented bit by bit in binary conversion; time represents the latched instantaneous time corresponding to the channel name, that is, the current time point; the trigger rule represents which rule triggers, for example: rising edge or falling edge)

[0125] S8: Put the second code into the event FIFO module for storage.

[0126] The above step (S6) is performed in sequence by the IRIG-G (DC) decoder. The corresponding time points of subsequent data sources are deduced in the same way, so that the specific time points when different data sources enter the input end of the function card can be obtained.

[0127] S9: The soft-core CPU reads the current time point data from the time information register group of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the current trigger event;

[0128] S10: The soft-core CPU reads the second code from the event FIFO module of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the historical event triggering.

[0129] The above steps (S9 and S10) are selected and executed by the soft-core CPU according to actual needs.

[0130] Among them, it should be noted that:

[0131] (1) The reason for storing the data group, i.e., the second code, in the event FIFO module is that the time information register group can only store the latest time data information, and the subsequent new time data information will overwrite the previous time data information. Therefore, only by storing the data group obtained in step S6 in the event FIFO module can the saving and reading of the historical time information in step S10 be realized; on the other hand, if only the time information of the current triggering event is needed, the soft-core CPU can directly read the latest data from the time information register group through the AVALON bus (as described in step S9).

[0132] (2) As a coprocessor, the DMA data transmission module can bypass the soft-core CPU and operate independently when it needs to read the time point information of historical trigger events, thus reducing the burden on the soft-core CPU. It can independently handle the work of the soft-core CPU, allowing it to handle other tasks, speeding up the system operation efficiency and thus improving the overall system performance.

[0133] (3) The event FIFO module can cache the latched historical instantaneous time information, making it convenient for the soft-core CPU to read it at any time.

[0134] More preferably, in an exemplary embodiment, if Fig.11 As shown, the main controller card also includes a third MLVDS transceiver and a first CAT5e network port;

[0135] The bus signal distributor sends the coverage time pulse to the outside through the third MLVDS transceiver and the first CAT5e network port every third cycle.

[0136] Specifically, this exemplary embodiment is applicable to application scenarios that require multiple groups of chassis, each group of chassis includes a main controller card and an external functional daughter card. No matter how many chassis there are in the entire system, only one chassis acts as a time generator to provide timing information for the entire system. The limitation of this exemplary embodiment corresponds to the main controller card of the chassis as a time generator. The bus signal distributor uses the coverage time pulse as the cross-chassis coarse time synchronization information, and sends it to other external chassis through the third MLVDS transceiver and the first CAT5e network port. The third CAT5e network port of the main controller card in the other chassis receives the time information pulse every third cycle, and sends it to the third IRIG-G (DC) decoder through the fifth MLVDS transceiver to obtain the cross-chassis coverage time information. The coverage method of the coverage time information is the same as the coverage time information in the box; the subsequent cross-chassis coarse time calculation refers to the coverage time information.

[0137] In addition, this exemplary embodiment also provides high stability and long-distance timing capabilities: the timing bus uses MLVDS differential pairs for transmission, and the timing between chassis uses standard CAT5e interfaces and cables, which can improve the reliability of long-distance timing and further reduce errors. By reducing the pulse rising and falling edge times, the path is steeper and the slope is larger, reducing the error caused by the edge. Especially when the transmission path is very long, the error reduction is very considerable.

[0138] Figure 12 to Figure 18 A schematic diagram of a functional card architecture and a chassis architecture obtained by combining the above exemplary embodiments is shown, specifically:

[0139] Fig.12 Shown based on Figure 7 or Fig. 9 FIG. 1 is a schematic diagram of the architecture of the main controller card latching relative time. The relevant process of the main controller card latching relative time includes: the first soft-core CPU sends the initial time information to the IRIG-G (DC) encoder through the AVALON bus, and the IRIG-G (DC) encoder starts timing itself based on the initial time; after the initial time information enters the IRIG-G (DC) encoder, the code element generator inside the IRIG-G (DC) encoder converts the initial time information into code elements, and then the time extraction pre-carry processing module and the time synchronizer convert the code elements into relative coverage time pulses, and the coverage time pulses are transmitted to the bus signal distributor every third cycle (0.01s), and the bus signal distributor transmits the pulse signal to the first IRIG-G (DC) decoder for decoding or to the third MLVDS transceiver and the first CAT5e network port to transmit pulses externally. When transmitted to the first IRIG-G (DC) decoder, the first IRIG-G (DC) decoder obtains the coarse time of the coverage update by performing code element extraction, timing information, and pulse extraction on the relative coverage time pulse, and then refreshes the extracted timestamp information once every first cycle (0.1ms) through the timing time (coarse time), and sends it to the backplane timing bus through the first MLVDS transceiver as the G code pulse of the coarse time timing information of the functional daughter card, and then sends it to the functional daughter card. The timing time (fine time) is refreshed once every second cycle (10ns) to extract the time difference information generated by the first local clock. The coarse time + fine time = current time point (the absolute time point of the current moment), and the time point immediately latched after the time latch is triggered is this time point.

[0140] Fig.13 Shown based on Figure 7 or Fig. 9 The main controller card latches the real time. The relevant process of the main controller card latching the real time includes: the high-precision timing module sends the real coverage time pulse to the main controller card, the second CAT5e network port of the main controller card receives the external pulse and transmits it to the bus signal distributor through the fourth MLVDS transceiver, and the bus signal distributor sends the real coverage time pulse to the first IRIG-G (DC) decoder or transmits it to the outside through the third MLVDS transceiver and the first CAT5e network port. The rest of the time latch content is the same as Fig.12 The relevant processes described are the same and will not be repeated here.

[0141] Fig.14 Shown based on Figure 7 or Fig. 9The schematic diagram of the functional daughter card latching time of the functional card structure is shown in Figure 1. The relevant process of the functional daughter card latching time includes: receiving the G code pulse sent by the main controller card through the second MLVDS transceiver connected to the backplane timing bus, and sending the G code pulse to the second IRIG-G (DC) decoder for decoding to complete the coarse time synchronization of the functional daughter card. The rest of the time latch content is the same as Fig.12 The relevant processes described are the same and will not be repeated here.

[0142] Fig.15 and Fig.16 The schematic diagram of the architecture of latching relative time and real time in a chassis including a main controller card and a functional daughter card is shown, wherein Fig.15 The logic of Fig.12 Overlay Fig.14 The relevant logic is the same as Fig.16 The logic of Fig.13 Overlay Fig.14 The relevant logic is the same and will not be repeated here.

[0143] Fig.17 and Fig.18 The schematic diagram of the architecture of multiple chassis latching relative time and real time is shown. The functional daughter card is not shown in the figure. If there is a need, it can be used according to Fig.15 and Fig.16 The relevant contents are superimposed. Among them, the time information generator (relative time is generated by the IRIG-G (DC) encoder, and the real time is sent by the external high-precision timing module) sends the generated time information pulse to the bus signal distributor every third cycle. The bus signal distributor sends the coverage time pulse as the cross-box coarse time synchronization information through the third MLVDS transceiver and the first CAT5e network port to the main controller card of the cross-box device. The main controller card of the cross-box device receives the coverage time pulse sent externally as the cross-box coarse time synchronization information through the third CAT5e network port every third cycle, and sends it to its own third IRIG-G (DC) decoder through the fifth MLVDS transceiver and the bus signal distributor. The third IRIG-G (DC) decoder decodes and obtains the cross-box coverage update time synchronization information ( Fig. 9 ). The rest of the time the contents are latched and Fig.12 The relevant processes described are the same and will not be repeated here.

[0144] Obviously, the above embodiments are merely examples for clear explanation, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from them are still within the protection scope of the invention.

Claims

1. A timing system with nanosecond synchronization error, characterized in that: It includes a main controller card and a functional sub-card whose timing is authorized by the main controller card, wherein the main controller card and the functional sub-card are connected via a backplane timing bus; The main controller card includes a first IRIG-G (DC) decoder, a first MLVDS transceiver, and the functional daughter card includes a second automatic event trigger, a second soft-core CPU, a second IRIG-G (DC) decoder, a second MLVDS transceiver, and a second local clock; For the main controller card, the first IRIG-G (DC) decoder extracts the timestamp of the main controller card coarse time information refreshed in each first cycle to form a G code pulse and sends it to the backplane timing bus through the first MLVDS transceiver; the first cycle corresponds to the IRIG-G (DC) protocol; For the functional daughter card, the second MLVDS transceiver receives the G code pulse from the backplane timing bus every first period and sends it to the second IRIG-G (DC) decoder, and the second IRIG-G (DC) decoder decodes the received G code pulse to obtain the coarse time information of the functional daughter card; The second automatic event trigger receives an external trigger signal, encapsulates it into a first code, and then sends it to the second IRIG-G (DC) decoder through the AVALON bus. The second IRIG-G (DC) decoder receives the first code and triggers the time latch to latch the current time point, and re-encodes the current time point and the first code to form a second code; the second soft-core CPU obtains the current time point to obtain the current event triggering situation and / or obtains the second code to obtain the historical event triggering situation; The latching of the current time point includes latching the coarse time information of the functional daughter card and the fine time information of the count of the second local clock in each first cycle; The synchronization error is calculated using the crystal oscillator accuracy of the second local clock and the time length of the first cycle.

2. A timing system with nanosecond synchronization error according to claim 1, characterized in that: The main controller card also includes a first automatic event trigger, a first soft-core CPU and a first local clock; For the main controller card, the first automatic event trigger receives an external trigger signal, encapsulates it into a first code, and then sends it to the first IRIG-G (DC) decoder through the AVALON bus. The first IRIG-G (DC) decoder receives the first code and triggers the time latch to latch the current time point, and re-encodes the current time point and the first code to form a second code; the first soft-core CPU obtains the current time point to obtain the current event triggering situation and / or obtains the second code to obtain the historical event triggering situation; The latching of the current time point includes latching the coarse time information of the main controller card and the fine time information of the count of the first local clock in each first cycle.

3. A timing system with nanosecond synchronization error according to claim 1 or 2, characterized in that: The fine time information is obtained by refreshing the fine time and extracting the time difference every second cycle, and the second cycle corresponds to the local clock frequency; The fine time information is specifically the time difference information generated by the local clock in each first cycle. The local clock includes a counter unit and a fine time calculation unit. The maximum count number of the counter unit is the first cycle divided by the second cycle. The counter unit performs an addition operation every second cycle until the maximum count number is reached and a reset operation is performed. When the time latch is triggered, the fine time calculation unit multiplies the count value of the counter unit by the second cycle to obtain the time difference information as the fine time information.

4. A timing system with nanosecond synchronization error according to claim 1, characterized in that: The synchronization error is calculated as follows: Calculate the proportional relationship between the duration corresponding to the crystal oscillator accuracy of the local clock and the first cycle; The synchronization error in the first cycle is calculated using the proportional relationship.

5. A timing system with nanosecond synchronization error according to claim 1 or 2, characterized in that: The main controller card further includes a time information generator and a bus signal distributor, and the first IRIG-G (DC) decoder further includes a code element extraction module and a timing information pulse extraction module; the main controller card coarse time is updated once every third period, and the update mode includes: The time information generator sends the generated covering time pulse to the bus signal distributor every third cycle, and the bus signal distributor sends the covering time pulse to the first IRIG-G (DC) decoder; The first IRIG-G (DC) decoder processes the received coverage time pulse to obtain coverage time information, where the coverage time information includes extracting the code element of the coverage time pulse by using the code element extraction module and extracting the timing information and pulse of the coverage time pulse by using the timing information pulse extraction module; The overlay time information is used to overlay and update the main controller card rough time information.

6. A timing system with nanosecond synchronization error according to claim 5, characterized in that: The covering time pulse generated by the time information generator is a relative covering time pulse, the time information generator comprises an IRIG-G (DC) encoder, and the IRIG-G (DC) encoder comprises a code element generator, a time extraction pre-carry processing module and a time synchronizer; The time information generator generates relative coverage time pulses, including: The first soft-core CPU sends the initial time information to the IRIG-G (DC) encoder via the AVALON bus, and the IRIG-G (DC) encoder starts timing based on the initial time information to obtain relative coverage time information; The code element generator of the IRIG-G (DC) encoder converts the relative coverage time information into code elements, and then the time extraction pre-carry processing module and the time synchronizer convert the code elements into relative coverage time pulses, and send the relative coverage time pulses to the bus signal distributor.

7. A timing system with nanosecond synchronization error according to claim 5, characterized in that: The coverage time pulse generated by the time information generator is a real coverage time pulse, and the time information generator includes a second CAT5e network port and a fourth MLVDS transceiver; The time information generator generates real coverage time pulses, including: The second CAT5e network port receives the real coverage time pulse sent by the external high-precision timing module, and forwards it to the bus signal distributor through the fourth MLVDS transceiver.

8. A timing system with nanosecond synchronization error according to claim 1 or 2, characterized in that: The automatic event trigger includes a signal preprocessing module, a multi-channel data source module, a data filter module, a threshold discrimination module and an event pulse generator; the signal preprocessing module of the automatic event trigger receives an external trigger signal for digital quantity processing, and sends it to the data filter module and the threshold discrimination module in sequence through the multi-channel data source module for filtering and threshold screening, and the screened data source directly triggers the event pulse generator to form a first code including a trigger channel and a trigger event; The IRIG-G (DC) decoder includes a DMA data transmission module, a time latch, and a time information register group; the DMA data transmission module of the IRIG-G (DC) decoder receives the first code through the AVALON bus and triggers the time latch at the same time, and the time latch puts the decoded current time point into the time information register group.

9. A timing system with nanosecond synchronization error according to claim 8, characterized in that: The soft-core CPU reads the current time point data from the time information register group of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the current trigger event; and / or: The IRIG-G (DC) decoder also includes an event FIFO module; the DMA data transmission module re-encodes the current time point and the first code taken out from the time information register group to form a second code including the trigger channel, trigger time and trigger event; the second code is placed in the event FIFO module for storage; the soft-core CPU reads the second code from the event FIFO module of the IRIG-G (DC) decoder through the AVALON bus to obtain the time information of the historical event trigger.

10. A timing system with nanosecond synchronization error according to claim 5, characterized in that: The main controller card also includes a third MLVDS transceiver and a first CAT5e network port; The bus signal distributor sends the coverage time pulse to the outside through the third MLVDS transceiver and the first CAT5e network port every third cycle.

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