Circuit board and method of manufacturing the same

Abstract

A circuit board includes a main substrate, a thermistor layer, and a plurality of N-type semiconductor units and a plurality of P-type semiconductor units. The main substrate includes a first external structure, a second external structure, and an internal structure disposed between the first external structure and the second external structure. The internal structure includes a first internal circuit layer, a second internal circuit layer, and an insulating layer disposed between the first internal circuit layer and the second internal circuit layer. The thermistor layer is disposed on the insulating layer and the first internal circuit layer. The plurality of N-type semiconductor units and the plurality of P-type semiconductor units are electrically connected to the second internal circuit layer and the second external structure, wherein the plurality of N-type semiconductor units and the plurality of P-type semiconductor units are arranged in a staggered manner. The circuit board has a refrigeration structure, and the cold end of the refrigeration structure can remove the heat energy of the image sensor, so that the heat energy of the circuit board can be effectively discharged.

Description

Technical Field

[0001] The present invention relates to a circuit board and a manufacturing method thereof, and in particular to a circuit board with a cooling structure and a manufacturing method thereof. Background Art

[0002] With the advancement of semiconductor technology, image sensor image quality is improving, but the power consumption required is also increasing, and therefore the energy required for heat dissipation is also increasing. If the heat dissipation problem of image sensors cannot be effectively solved, hot pixels may appear, which will further affect the image quality.

[0003] If heat is dissipated only through the metal layer below the image sensor, it will not be able to effectively dissipate the power consumption of the image sensor when the image sensor is working for a long time or providing higher quality images. In view of the above, there is an urgent need to develop a circuit board that can effectively dissipate heat to overcome the above shortcomings. Summary of the Invention

[0004] At least one embodiment of the present invention provides a circuit board with a cooling structure and a manufacturing method thereof, wherein the cooling structure can provide a cold end to remove heat energy from an image sensor, thereby effectively dissipating heat energy from the circuit board.

[0005] At least one embodiment of the present invention provides a circuit board comprising a main substrate, a first adhesive layer, a second adhesive layer, a thermistor layer, and a plurality of N-type semiconductor units and a plurality of P-type semiconductor units. The main substrate comprises a first external structure, a second external structure, and an internal structure. The internal structure is disposed between the first external structure and the second external structure, wherein the internal structure, the first external structure, and the second external structure are stacked along a first direction. The internal structure comprises a first internal wiring layer, a second internal wiring layer, and an insulating layer. The insulating layer is disposed between the first internal wiring layer and the second internal wiring layer, wherein the insulating layer, the first internal wiring layer, and the second internal wiring layer are stacked along the first direction. The first adhesive layer is disposed between the internal structure and the first external structure and connects the internal structure and the first external structure. The second adhesive layer is disposed between the internal structure and the second external structure and connects the internal structure and the second external structure. The thermistor layer is embedded in the first adhesive layer and disposed on the insulating layer and the first internal wiring layer. A plurality of N-type semiconductor units and a plurality of P-type semiconductor units are embedded in the second adhesive layer and electrically connected to the second internal circuit layer and the second external structure, wherein the plurality of N-type semiconductor units and the plurality of P-type semiconductor units are staggered along a second direction perpendicular to the first direction, and orthographic projections of the plurality of N-type semiconductor units and the plurality of P-type semiconductor units on the insulating layer overlap with orthographic projections of the thermistor layer on the insulating layer.

[0006] In at least one embodiment of the present invention, the second internal circuit layer includes multiple cold ends, and the second external structure includes multiple hot ends, wherein the i-th N-type semiconductor unit is adjacent to the i-th P-type semiconductor unit, the i-th N-type semiconductor unit and the i-th P-type semiconductor unit are connected to the same cold end, and the i-th P-type semiconductor unit and the i+1-th N-type semiconductor unit are connected to the same hot end, where i is a positive integer.

[0007] In at least one embodiment of the present invention, the plurality of N-type semiconductor units and the plurality of P-type semiconductor units are electrically connected to the second external structure.

[0008] In at least one embodiment of the present invention, the circuit board further includes a heat-conducting layer and a heat-dissipating reinforcement layer. The heat-conducting layer is disposed on the second external structure and connects the second external structure to the second adhesive layer. The heat-dissipating reinforcement layer is disposed on the heat-conducting layer.

[0009] In at least one embodiment of the present invention, the circuit board further includes a heat-conducting layer and an image sensor. The heat-conducting layer is disposed on the thermistor layer. The image sensor is disposed on the heat-conducting layer.

[0010] In at least one embodiment of the present invention, the protruding portion of the internal structure protrudes from the sidewalls of the first external structure and the sidewalls of the second external structure, wherein the main substrate further includes a first covering layer and a second covering layer. The first covering layer covers the protruding portion of the internal structure. The second covering layer covers the protruding portion of the internal structure. The circuit board further includes an extension substrate, wherein the extension substrate is electrically connected to the protruding portion of the internal structure.

[0011] At least one embodiment of the present invention provides a method for manufacturing a circuit board, comprising the following operations: providing an internal structure, wherein the internal structure comprises a first internal circuit layer, a second internal circuit layer, and an insulating layer disposed between the first internal circuit layer and the second internal circuit layer, wherein the insulating layer, the first internal circuit layer, and the second internal circuit layer are stacked along a first direction; forming a thermistor layer on the first internal circuit layer, and connecting the insulating layer and the first internal circuit layer; forming a first peelable adhesive layer on the thermistor layer; forming a first adhesive layer on the first internal circuit layer, and covering the first peelable adhesive layer and the thermistor layer; and forming a second adhesive layer on the second internal circuit layer, wherein the second adhesive layer comprises a plurality of grooves, and the plurality of grooves expose the second internal circuit layer. The orthographic projections of the plurality of grooves on the insulating layer overlap with the orthographic projections of the thermistor layer on the insulating layer; filling the plurality of grooves with N-type semiconductor material and P-type semiconductor material to form a plurality of N-type semiconductor units and a plurality of P-type semiconductor units, wherein the N-type semiconductor units and the P-type semiconductor units are staggered along a second direction perpendicular to the first direction; forming a first external structure on the first adhesive layer; forming a second external structure on the second adhesive layer, such that the second external structure electrically connects the N-type semiconductor units and the plurality of P-type semiconductor units; and removing the first peelable adhesive layer and a portion of the first adhesive layer above the first peelable adhesive layer to expose the thermistor layer.

[0012] In at least one embodiment of the present invention, the method for manufacturing a circuit board further includes: forming a heat-conducting layer on the thermistor layer after forming the image sensor on the thermistor layer.

[0013] In at least one embodiment of the present invention, the method for manufacturing a circuit board further includes: disposing an image sensor on the thermistor layer; forming a thermal conductive layer on the second external structure, wherein the thermal conductive layer connects the second external structure and the second adhesive layer; and forming a heat dissipation reinforcement layer on the thermal conductive layer.

[0014] In at least one embodiment of the present invention, the method for manufacturing a circuit board further includes: forming a first covering layer on the first inner circuit layer, wherein the first covering layer is spaced apart from the thermistor layer; forming a second covering layer on the second inner circuit layer, wherein the second covering layer is spaced apart from the plurality of grooves, and an orthographic projection of the first covering layer on the insulating layer overlaps an orthographic projection of the second covering layer on the insulating layer; forming a second peelable adhesive layer on the first covering layer, wherein during the operation of forming the first adhesive layer, the first adhesive layer further covers the second peelable adhesive layer and the first covering layer; forming a third peelable adhesive layer on the second covering layer, wherein during the operation of forming the second adhesive layer, the second adhesive layer further covers the third peelable adhesive layer and the second covering layer; removing the second peelable adhesive layer to expose the first covering layer; and removing the third peelable adhesive layer to expose the second covering layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The various aspects of the present application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be understood that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity.

[0016] Figures 1 to 8 Schematic cross-sectional views of a circuit board in various stages of the manufacturing process according to at least one embodiment of the present invention are shown. DETAILED DESCRIPTION

[0017] In the following text, in order to clearly present the technical features of this case, the dimensions (such as length, width, thickness and depth) of the elements (such as insulating layers, circuit layers and through holes, etc.) in the drawings will be enlarged in a non-proportional manner, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes of the elements, but should cover the dimensions, shapes and deviations thereof caused by actual processes and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, and the sharp angles shown in the drawings may be rounded. Therefore, the elements shown in the drawings of this case are mainly for illustration and are not intended to accurately depict the actual shape of the elements, nor are they used to limit the claims of this case.

[0018] In addition, spatially relative terms such as "below," "beneath," "below," "above," and similar terms are used to facilitate describing the relationship of one element or feature to another element or feature in the figures. Spatially relative terms encompass not only the orientation depicted in the figures, but also other orientations of the device during use or operation. That is, when the device is oriented differently from the figures (rotated 90 degrees or in other orientations), the spatially relative terms used in this disclosure should be interpreted accordingly.

[0019] It will be understood that although terms such as "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] As used herein, the terms "approximately," "substantially," or "substantially" may be used to select a more acceptable range of deviations or standard deviations based on the optical, etching, mechanical, measurement, coating, or other properties, and may not apply to all properties in a single standard deviation. It should be noted that the first direction D1 and the second direction D2 are marked in the drawings of this application to illustrate the configuration relationship of the various components in the drawings. The first direction D1 and the second direction D2 are substantially perpendicular to each other.

[0021] Figures 1 to 8 Schematic diagram of the cross section of the circuit board 800 in various stages of the process of at least one embodiment of the present invention. Figure 1 The internal structure 100 includes a first internal circuit layer 110, a second internal circuit layer 120, and an insulating layer 130 disposed between the first internal circuit layer 110 and the second internal circuit layer 120. The insulating layer 130, the first internal circuit layer 110, and the second internal circuit layer 120 are stacked along a first direction D1.

[0022] like Figure 1 As shown, the first internal circuit layer 110 includes electrodes 111 and 112, which are spaced apart from each other. The second internal circuit layer 120 includes a plurality of cold ends 121, 122, and 123, which are spaced apart from each other. Electrodes 111 and 112 and cold ends 121, 122, and 123 are respectively disposed on opposite sides of the insulating layer 130. It will be understood that electrodes 111 and 112 are, at this stage, metal pads (or metal layers) of the first internal circuit layer 110 and the first internal circuit layer 110, while cold ends 121, 122, and 123 are metal pads of the second internal circuit layer 120.

[0023] In some embodiments, the material of the insulating layer 130 may be an insulating material such as polyimide (PI), glass fiber epoxy resin (FR4), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethylene (PE), but is not limited thereto.

[0024] In this embodiment, the first inner wiring layer 110 and the second inner wiring layer 120 are formed by first forming a dry film, then exposing and developing the film. Therefore, the first inner wiring layer 110 and the second inner wiring layer 120 are formed using a subtractive process. However, in other embodiments, the first inner wiring layer 110 and the second inner wiring layer 120 can be formed using a semi-additive process or an additive process. In some embodiments, the material of the first inner wiring layer 110 and / or the second inner wiring layer 120 can be a conductive material such as copper, gold, or silver, but is not limited thereto.

[0025] Please refer to Figure 2 Thermistor layer 210 is formed on first inner circuit layer 110 and connects electrodes 111 and 112 of first inner circuit layer 110 and insulating layer 130. In some embodiments, thermistor layer 210 may be made of a negative temperature coefficient thermistor (NTC) material or a positive temperature coefficient thermistor (PTC) material.

[0026] like Figure 2 As shown, a first adhesive layer 220 and a first cover layer 230 are further disposed on the first internal circuit layer 110, wherein the first cover layer 230 is spaced apart from the thermistor layer 210. A second adhesive layer 240 and a second cover layer 250 are further disposed on the second internal circuit layer 120. Because the first cover layer 230 and the second cover layer 250 are disposed on opposite sides of the insulating layer 130, the orthographic projection of the first cover layer 230 on the insulating layer 130 overlaps the orthographic projection of the second cover layer 250 on the insulating layer 130. In this embodiment, the first cover layer 230 and the second cover layer 250 are disposed by laminating.

[0027] Please refer to Figure 3 , the first peelable adhesive layer 310 is formed on the thermistor layer 210, the second peelable adhesive layer 320 is formed on the first covering layer 230, and the third peelable adhesive layer 330 is formed on the second covering layer 250. In the present embodiment, the first peelable adhesive layer 310, the second peelable adhesive layer 320 and the third peelable adhesive layer 330 are provided by laminating. In the present embodiment, the width of the first peelable adhesive layer 310 in the second direction D2 is substantially equal to the width of the thermistor layer 210 in the second direction D2. In the present embodiment, the width of the second peelable adhesive layer 320 in the second direction D2 is smaller than the width of the first covering layer 230 in the second direction D2, and the width of the third peelable adhesive layer 330 in the second direction D2 is smaller than the width of the second covering layer 250 in the second direction D2.

[0028] Please refer to Figure 4 The first adhesive layer 410 is formed on the first internal circuit layer 110 and covers the first peelable adhesive layer 310 and the thermistor layer 210. The second adhesive layer 420 is formed on the second internal circuit layer 120, wherein the second adhesive layer 420 includes a plurality of grooves 422 arranged along the second direction D2, and the plurality of grooves 422 expose the plurality of cold ends 121, 122 and 123 of the second internal circuit layer 120. Figure 4 As shown, since the plurality of grooves 422 are disposed on the plurality of cold ends 121 , 122 and 123 of the second inner circuit layer 120 , the orthographic projections of the plurality of grooves 422 on the insulation layer 130 overlap with the orthographic projections of the thermistor layer 210 on the insulation layer 130 .

[0029] like Figure 4 As shown, the first adhesive layer 410 further covers the second peelable adhesive layer 320 and the first cover layer 230, and the second adhesive layer 420 further covers the third peelable adhesive layer 330 and the second cover layer 250. In this embodiment, the first adhesive layer 410 and the second adhesive layer 420 are arranged by laminating and pressing. In this embodiment, the material of the first adhesive layer 410 and the second adhesive layer 420 can be a low-flow prepreg or a non-flow prepreg.

[0030] like Figure 4 As shown, a metal layer 440 is formed on the first adhesive layer 410, and a metal layer 450 is formed on the second adhesive layer 420. After forming the first adhesive layer 410, the second adhesive layer 420, the metal layer 440, and the metal layer 450, a plurality of through holes 430 are formed. In this embodiment, the through holes 430 can be formed by mechanical drilling or laser drilling.

[0031] Please refer to Figure 5 , N-type semiconductor material and P-type semiconductor material are filled in a plurality of grooves 422 (please refer to Figure 4 ) to form a plurality of N-type semiconductor units 510a, 510b and 510c and a plurality of P-type semiconductor units 520a, 520b and 520c, wherein the orthographic projections of the plurality of P-type semiconductor units 520a, 520b and 520c on the insulating layer 130 overlap the orthographic projection of the thermistor layer 210 on the insulating layer 130.

[0032] The N-type semiconductor units 510a, 510b and 510c and the P-type semiconductor units 520a, 520b and 520c are alternately arranged along the second direction D2. Figure 5For example, the first N-type semiconductor cell 510a is adjacent to the first P-type semiconductor cell 520a, the second N-type semiconductor cell 510b is adjacent to the second P-type semiconductor cell 520b, and the third N-type semiconductor cell 510c is adjacent to the third P-type semiconductor cell 520c. Similarly, the i-th N-type semiconductor cell (e.g., the first N-type semiconductor cell 510a) is adjacent to the i-th P-type semiconductor cell (e.g., the first P-type semiconductor cell 520a), where i is a positive integer.

[0033] In this embodiment, a printing process is used to first fill a portion of the recess 422 with an N-type semiconductor material, and then the N-type semiconductor material is baked to form a plurality of N-type semiconductor units 510a, 510b, and 510c. Subsequently, a printing process is used to fill the remaining recess 422 with a P-type semiconductor material, and then the P-type semiconductor material is baked to form a plurality of P-type semiconductor units 520a, 520b, and 520c. An N-type semiconductor is a semiconductor in which the electron density in the conduction band is greater than the hole density in the valence band. N-type semiconductor materials are formed by adding acceptor impurities (e.g., arsenic or phosphorus) to the silicon crystal structure. A P-type semiconductor is a semiconductor in which the hole density in the conduction band exceeds the electron density in the valence band. P-type semiconductor materials are formed by adding acceptor impurities (e.g., boron) to the silicon crystal structure. In some embodiments, the N-type semiconductor material and the P-type semiconductor material can be bismuth-antimony-telluride alloy, bismuth telluride, lead telluride, silicon-germanium, or skutterudite. In the embodiment of this case, the N-type semiconductor material is Bi2Sb 2.7 Te 0.3 , and the P-type semiconductor material is BiSbTe.

[0034] It can be understood that an N-type semiconductor unit and an adjacent P-type semiconductor unit form a pair of thermocouples. Figure 5 Three pairs of thermocouples are shown (i.e., one pair of N-type semiconductor unit 510a and P-type semiconductor unit 520a, one pair of N-type semiconductor unit 510b and P-type semiconductor unit 520b, and one pair of N-type semiconductor unit 510c and P-type semiconductor unit 520c). The N-type semiconductor unit 510a and the P-type semiconductor unit 520a are disposed on the cold end 121, the N-type semiconductor unit 510b and the P-type semiconductor unit 520b are disposed on the cold end 122, and the N-type semiconductor unit 510c and the P-type semiconductor unit 520c are disposed on the cold end 123. It should be noted that the number of thermocouples can be adjusted according to actual cooling needs and is not limited to Figure 5 The number in .

[0035] Please refer to Figure 6A first external structure 610 is formed on metal layer 440, and a second external structure 620 is formed on metal layer 450. The second external structure 620 electrically connects the plurality of N-type semiconductor units 510a, 510b, and 510c and the plurality of P-type semiconductor units 520a, 520b, and 520c. It will be appreciated that the first external structure 610 is electroplated on metal layer 440 using metal layer 440 as a seed layer. Similarly, the second external structure 620 is electroplated on metal layer 450 using metal layer 450 as a seed layer.

[0036] It is noteworthy that the second external structure 620 includes hot ends 621 and 622. It is understood that at this stage, hot ends 621 and 622 are both metal pads of the second external structure 620. Specifically, the P-type semiconductor unit 520a and the N-type semiconductor unit 510b are connected to the same hot end 621, while the P-type semiconductor unit 520b and the N-type semiconductor unit 510c are connected to the same hot end 622. Hot ends 621 and 622 are spaced apart from each other. In other words, the multiple N-type semiconductor units 510a, 510b, and 510c and the multiple P-type semiconductor units 520a, 520b, and 520c form a series structure between the cold ends 121, 122, and 123 and the hot ends 621 and 622.

[0037] like Figure 6 As shown, in this embodiment, the first outer structure 610 , the second outer structure 620 , and the plated through hole 630 may be formed by copper electroplating to form a metal copper layer.

[0038] Please refer to Figure 7 , forming a solder mask (SM) 710 on the plated through hole 630 (please refer to Figure 6 ), and on the first outer structure 610 and the second outer structure 620. In the embodiment of the present case, the solder mask 710 is formed by a printing process and baking.

[0039] like Figure 7 As shown, after forming the solder mask layer 710, the exposed first external structure 610 is surface treated to form a protective layer 720. In the embodiment of this case, the protective layer 720 includes a nickel-gold layer. The protective layer 720 can electrically connect the first external structure 610 and the second external structure 620 below.

[0040] like Figure 7As shown, after forming the protective layer 720, the first peelable adhesive layer 310 and the portion of the first adhesive layer 410 above the first peelable adhesive layer 310 are removed to expose the thermistor layer 210. The second peelable adhesive layer 320 and the portion of the first adhesive layer 410 above the second peelable adhesive layer 320 are removed to expose the first covering layer 230. The third peelable adhesive layer 330 and the portion of the second adhesive layer 420 above the third peelable adhesive layer are removed to expose the second covering layer 250.

[0041] In this embodiment, the first peelable adhesive layer 310, the second peelable adhesive layer 320, and the third peelable adhesive layer 330 are removed by routing. It is understood that the material of the peelable adhesive layer has a certain degree of stickiness, and when the peelable adhesive layer is removed, it is difficult to leave residual adhesive on the film layer below.

[0042] like Figure 7 As shown, after the thermistor layer 210, the first cover layer 230, and the second cover layer 250 are exposed, a thermal conductive layer 730 is formed on the second external structure 620, wherein the second external structure 620 covers a portion of the solder mask 710. It can be understood that since the second external structure 620 has hot ends 621 and 622, the thermal conductive layer 730 covers and connects the hot ends 621 and 622 and the second adhesive layer 420 adjacent to the hot ends 621 and 622.

[0043] In this embodiment, the material of the heat-conducting layer 730 can be silicone. In this embodiment, the heat-conducting layer 730 is formed by laminating.

[0044] exist Figure 7 In the embodiment, after forming the heat conducting layer 730, the heat dissipation reinforcement layer 740 is formed on the heat conducting layer 730. In this embodiment, the heat dissipation reinforcement layer 740 is formed by lamination.

[0045] Please refer to Figure 8 A thermal conductive layer 810 is formed on the thermistor layer 210, and an image sensor 820 is disposed on the thermal conductive layer 810. In this embodiment, the material and formation method of the thermal conductive layer 810 can be the same as or similar to the material and formation method of the thermal conductive layer 730. In this embodiment, the image sensor 820 is disposed by wire bonding. After the image sensor 820 is disposed, bonding wires are formed above the image sensor 820 to electrically connect the image sensor 820 to the first external structure 610.

[0046] Please refer again Figure 8, the circuit board 800 includes a main substrate MB and an extended substrate EB. The internal structure 100 of the main substrate MB includes a protruding portion 100p, which is covered by the first covering layer 230 and the second covering layer 250. The protruding portion 100p protrudes from the side wall ss1 of the first external structure 610 and the side wall ss2 of the second external structure 620. The extended substrate EB is electrically connected to the protruding portion 100p of the internal structure 100. It should be noted that the main substrate MB and the extended substrate EB are integrally formed substrates, which are formed by the above-mentioned Figures 1 to 8 In the embodiment of the present case, the extended substrate EB includes a data processor and a driving circuit.

[0047] like Figure 8 As shown, the main substrate MB includes a thermistor layer 210, an image sensor 820, and a cooling structure. It is understood that electrodes 111 and 112 serve as electrodes for the thermistor layer 210. The "cooling structure" herein includes a plurality of N-type semiconductor units 510a, 510b, and 510c, a plurality of P-type semiconductor units 520a, 520b, and 520c, cold ends 121, 122, and 123, and hot ends 621 and 622.

[0048] The plurality of N-type semiconductor units 510a, 510b and 510c and the plurality of P-type semiconductor units 520a, 520b and 520c are electrically connected to the cold ends 121 and 122 of the second inner circuit layer 120 and the hot ends 621 and 622 of the second outer structure 620, so that the cooling structure is a series structure. Figure 8 For example, the first N-type semiconductor unit 510a and the first P-type semiconductor unit 520a are connected to the same cold end 121, and the first P-type semiconductor unit 520a and the second N-type semiconductor unit 510b are connected to the same hot end 621. Similarly, the i-th N-type semiconductor unit (e.g., the first N-type semiconductor unit 510a) and the i-th P-type semiconductor unit (e.g., the first P-type semiconductor unit 520a) are connected to the same cold end (e.g., cold end 121), and the i-th P-type semiconductor unit (e.g., the first P-type semiconductor unit 520a) and the i+1-th N-type semiconductor unit (e.g., the second N-type semiconductor unit 510b) are connected to the same hot end (e.g., hot end 621), where i is a positive integer.

[0049] The extended substrate EB of the present invention can be used as a central controller, which can determine the current flowing through the cooling structure according to temperature information (eg, the temperature of the image sensor 820 measured by the thermistor layer 210 ).

[0050] In this embodiment, thermistor layer 210 is embedded in first adhesive layer 410, and the cooling structure is embedded in second adhesive layer 420. Thermistor layer 210 is connected to cold terminals 121 and 122. Thermistor layer 210 monitors the temperature of the image sensor 820 above and transmits this temperature information to the extended substrate EB. The extended substrate EB then uses a data processor to determine the current flowing through the cooling structure.

[0051] Please refer to Figure 8 The arrows in the cooling structure indicate the flow of current within the cooling structure. When current flows from N-type semiconductor units 510a, 510b, and 510c to P-type semiconductor units 520a, 520b, and 520c, the upper junctions become cold ends 121, 122, and 123. When current flows from P-type semiconductor units 520a, 520b, and 520c to N-type semiconductor units 510a, 510b, and 510c, the lower junctions become hot ends 621 and 622. Cold ends 121, 122, and 123 transfer heat energy from image sensor 820 via conduction through insulating layer 130, thermistor layer 210, and thermally conductive layer 810. Thermally conductive layer 730 and heat dissipation reinforcement layer 740 remove heat energy from hot ends 621 and 622 via conduction.

[0052] In summary, the circuit board provided by the present invention has a cooling structure that can adjust the cooling effect according to demand. The cold end of the cooling structure can remove heat energy from the image sensor, thereby effectively dissipating heat energy from the circuit board.

[0053] The features of the various embodiments are summarized above so that those skilled in the art can better understand the aspects of the present application. Those skilled in the art will appreciate that this application can be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present application, and that various variations, substitutions, and modifications may be made herein without departing from the spirit and scope of the present application.

[0054]

Explanation of symbols

[0055] 100: Internal structure

[0056] 100p: convex part

[0057] 110: First internal circuit layer

[0058] 111, 112: Electrodes

[0059] 120: Second internal circuit layer

[0060] 121, 122, 123: Cold junction

[0061] 130: Insulation layer

[0062] 210: Thermistor layer

[0063] 220: First bonding layer

[0064] 230: First covering layer

[0065] 240: Second bonding layer

[0066] 250: Second cover layer

[0067] 310: First peelable adhesive layer

[0068] 320: Second peelable adhesive layer

[0069] 330: The third peelable adhesive layer

[0070] 410: First adhesive layer

[0071] 420: Second adhesive layer

[0072] 422: Groove

[0073] 430: Through hole

[0074] 510a, 510b, 510c: N-type semiconductor unit

[0075] 520a, 520b, 520c: P-type semiconductor units

[0076] 610: First external structure

[0077] 620: Second external structure

[0078] 621, 622: hot end

[0079] 630: Plated through hole

[0080] 710: solder mask

[0081] 720: Protective layer

[0082] 730: Thermal conductive layer

[0083] 740: Heat dissipation reinforcement layer

[0084] 800: Circuit board

[0085] 810: Thermal conductive layer

[0086] 820: Image sensor

[0087] MB: main substrate

[0088] EB: Extended Base Plate

[0089] ss1, ss2: side walls

[0090] D1: First direction

[0091] D2: Second direction.

Claims

1. A circuit board, characterized in that: Include: The main substrate includes: First external structure; second external structure; and an internal structure disposed between the first external structure and the second external structure, wherein the internal structure, the first external structure, and the second external structure are stacked along a first direction; The internal structure includes: a first inner circuit layer; a second inner wiring layer; and an insulating layer disposed between the first internal circuit layer and the second internal circuit layer, wherein the insulating layer, the first internal circuit layer, and the second internal circuit layer are stacked along the first direction; a first adhesive layer, disposed between the internal structure and the first external structure, and connecting the internal structure and the first external structure; a second adhesive layer, disposed between the internal structure and the second external structure, and connecting the internal structure and the second external structure; a thermistor layer embedded in the first adhesive layer and disposed on the insulating layer and the first internal circuit layer; and A plurality of N-type semiconductor units and a plurality of P-type semiconductor units are embedded in the second adhesive layer and electrically connected to the second internal circuit layer and the second external structure, wherein the plurality of N-type semiconductor units and the plurality of P-type semiconductor units are staggered along a second direction perpendicular to the first direction, and the orthographic projections of the plurality of N-type semiconductor units and the plurality of P-type semiconductor units on the insulating layer overlap with the orthographic projection of the thermistor layer on the insulating layer, the second internal circuit layer includes a plurality of cold ends, and the second external structure includes a plurality of hot ends, wherein the i-th N-type semiconductor unit is adjacent to the i-th P-type semiconductor unit, the i-th N-type semiconductor unit and the i-th P-type semiconductor unit are connected to the same cold end, and the i-th P-type semiconductor unit and the i+1-th N-type semiconductor unit are connected to the same hot end, where i is a positive integer. 2 . The circuit board according to claim 1 , wherein the plurality of N-type semiconductor units and the plurality of P-type semiconductor units are electrically connected to the second external structure.

3. The circuit board according to claim 2, wherein: Also includes: a heat-conducting layer disposed on the second external structure and connecting the second external structure and the second adhesive layer; and The heat dissipation reinforcement layer is arranged on the heat conducting layer.

4. The circuit board according to claim 1, wherein Also includes: a heat-conducting layer, disposed on the thermistor layer; and The image sensor is disposed on the heat-conducting layer.

5. The circuit board according to claim 1 , wherein the protruding portion of the internal structure protrudes from the sidewall of the first external structure and the sidewall of the second external structure, and wherein the main substrate further comprises: a first covering layer covering the protruding portion of the internal structure; and a second covering layer covering the protruding portion of the internal structure; The circuit board further comprises: An extension substrate is provided, wherein the extension substrate is electrically connected to the protruding portion of the internal structure.

6. A method for manufacturing a circuit board, characterized in that: Include: An internal structure is provided, wherein the internal structure comprises: a first inner circuit layer; a second inner wiring layer; and an insulating layer disposed between the first internal circuit layer and the second internal circuit layer, wherein the insulating layer, the first internal circuit layer, and the second internal circuit layer are stacked along a first direction; forming a thermistor layer on the first internal circuit layer and connecting the insulating layer and the first internal circuit layer; forming a first peelable adhesive layer on the thermistor layer; forming a first adhesive layer on the first internal circuit layer and covering the first peelable adhesive layer and the thermistor layer; forming a second adhesive layer on the second inner circuit layer, wherein the second adhesive layer comprises a plurality of grooves, the plurality of grooves exposing the second inner circuit layer, and orthographic projections of the plurality of grooves on the insulating layer overlap with orthographic projections of the thermistor layer on the insulating layer; Filling N-type semiconductor material and P-type semiconductor material in the plurality of grooves to form a plurality of N-type semiconductor units and a plurality of P-type semiconductor units, wherein the N-type semiconductor units and the P-type semiconductor units are alternately arranged along a second direction perpendicular to the first direction; forming a first external structure on the first adhesive layer; forming a second external structure on the second adhesive layer, such that the second external structure electrically connects the plurality of N-type semiconductor units and the plurality of P-type semiconductor units; and The first peelable adhesive layer and a portion of the first adhesive layer located above the first peelable adhesive layer are removed to expose the thermistor layer, the second internal circuit layer includes multiple cold ends, and the second external structure includes multiple hot ends, wherein the i-th N-type semiconductor unit is adjacent to the i-th P-type semiconductor unit, the i-th N-type semiconductor unit and the i-th P-type semiconductor unit are connected to the same cold end, and the i-th P-type semiconductor unit and the i+1-th N-type semiconductor unit are connected to the same hot end, where i is a positive integer.

7. The method for manufacturing a circuit board according to claim 6, wherein: Also includes: After forming the image sensor on the thermistor layer, a heat conducting layer is formed on the thermistor layer.

8. The method for manufacturing a circuit board according to claim 6, wherein: Also includes: Disposing an image sensor on the thermistor layer; forming a heat-conducting layer on the second external structure, wherein the heat-conducting layer connects the second external structure and the second adhesive layer; and A heat dissipation reinforcement layer is formed on the heat conducting layer.

9. The method for manufacturing a circuit board according to claim 6, wherein: Also includes: forming a first covering layer on the first inner circuit layer, wherein the first covering layer is spaced apart from the thermistor layer; forming a second covering layer on the second inner circuit layer, wherein the second covering layer is spaced apart from the plurality of grooves, and an orthographic projection of the first covering layer on the insulating layer overlaps an orthographic projection of the second covering layer on the insulating layer; forming a second peelable adhesive layer on the first covering layer, wherein during the operation of forming the first adhesive layer, the first adhesive layer also covers the second peelable adhesive layer and the first covering layer; forming a third peelable adhesive layer on the second covering layer, wherein during the operation of forming the second adhesive layer, the second adhesive layer also covers the third peelable adhesive layer and the second covering layer; removing the second peelable adhesive layer to expose the first covering layer; and The third peelable adhesive layer is removed to expose the second covering layer.

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