Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure. The cell structure includes: a plurality of gate electrodes spaced apart from each other in a vertical direction; the channel structure penetrates through the gate electrodes and extends in the vertical direction, and the channel structure is provided with a first end close to the peripheral circuit structure and a second end opposite to the first end; and a common source layer covering the second end of the channel structure. The channel structure includes a channel layer extending in a vertical direction, the common source layer includes a first region and a second region, the first region and the second region contain impurities of different conductivity types, and the first region of the common source layer is connected to at least a portion of the channel layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0096406 filed in the Korean Intellectual Property Office on July 24, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having memory strings structured in a vertical direction. Background Art

[0003] In electronic systems that require data storage, semiconductor devices that can store large amounts of data are required. In order to achieve the excellent performance and affordable prices required by consumers while increasing the data storage capacity, it is necessary to increase the integration of semiconductor devices. In the case of two-dimensional or planar semiconductor devices, the integration is determined by the area occupied by the unit memory cell and is affected by the level of fine pattern forming technology. However, very expensive equipment is required to manufacture fine patterns. Therefore, although the integration of two-dimensional semiconductor devices is increasing, the increase in integration is still limited. Therefore, a three-dimensional semiconductor memory device with a three-dimensionally arranged memory cell has been proposed. Summary of the invention

[0004] In general, in some aspects, the present disclosure relates to a semiconductor device having improved electrical characteristics and reliability and improved integration.

[0005] According to some aspects of the present disclosure, a semiconductor device includes: a peripheral circuit structure; and a unit structure, stacked on the peripheral circuit structure and including a unit region, a connection region positioned adjacent to the unit region in a first horizontal direction, and a peripheral circuit connection region surrounding the unit region and the connection region, wherein the unit structure includes a gate electrode, a channel structure, and a common source layer, the gate electrodes are arranged in the unit region and spaced apart from each other in a vertical direction, the channel structure passes through the gate electrode in the unit region and extends in a vertical direction, the channel structure has a first end close to the peripheral circuit structure and a second end opposite to the first end, the common source layer is arranged above the gate electrode and covers the second end of the channel structure, wherein the channel structure includes a channel layer extending in the vertical direction, the common source layer includes a first region and a second region, the first region and the second region contain impurities of different conductivity types, and the first region of the common source layer is connected to at least a portion of the channel layer.

[0006] According to some aspects of the present disclosure, a semiconductor device includes: a peripheral circuit structure; and a unit structure stacked on the peripheral circuit structure, wherein the unit structure includes a gate electrode, a channel structure and a common source layer, the gate electrodes are spaced apart from each other in a vertical direction, the channel structure passes through the gate electrode and extends in the vertical direction, the channel structure has a first end close to the peripheral circuit structure and a second end opposite to the first end, the common source layer is arranged above the gate electrode and covers the second end of the channel structure, wherein the common source layer includes a plurality of first regions and a plurality of second regions, each first region has a first conductivity type and extends in a first horizontal direction, each second region has a second conductivity type and extends in the first horizontal direction, the second conductivity type is different from the first conductivity type, wherein the first regions and the second regions are alternately arranged in a second horizontal direction intersecting the first horizontal direction.

[0007] According to some aspects of the present disclosure, a semiconductor device includes: a peripheral circuit structure; and a cell structure, which is stacked on the peripheral circuit structure and includes a cell region, a connection region and a peripheral circuit connection region, wherein the cell structure includes a gate electrode, a channel structure, a pad, a first plug, a stacked insulating layer, a second plug and a common source layer, the gate electrode is arranged in the cell region and spaced apart from each other in a vertical direction, the channel structure passes through the gate electrode in the cell region and extends in a vertical direction, the channel structure has a first end close to the peripheral circuit structure and a second end opposite to the first end, the pad has a step shape in the connection region and extends from the gate electrode, the first plug is connected to the pad, passes through the pad and extends in the vertical direction, the stacked insulating layer surrounds the gate electrode in a plan view, the second plug passes through the stacked insulating layer in the peripheral circuit connection region and extends in the vertical direction, the common source layer is located in the cell region and covers the second end of the channel structure, wherein the channel structure includes a channel layer extending in the vertical direction, the common source layer includes a first region and a second region, the first region and the second region contain impurities of different conductivity types, and the first region of the common source layer includes P-type conductivity and is connected to at least a portion of the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram of an exemplary semiconductor device according to some embodiments.

[0010] Figure 2 is a circuit diagram illustrating an exemplary memory block according to some embodiments.

[0011] Figure 3 is a perspective view illustrating an exemplary configuration of a semiconductor device according to some embodiments.

[0012] Figure 4 yes Figure 3 A planar layout diagram of a semiconductor device.

[0013] Figure 5 yes Figure 4 An enlarged layout diagram of area A.

[0014] Fig. 6A It is along Figure 5 A cross-sectional view taken along line B1-B1' and line B2-B2'.

[0015] Figure 6B It is along Figure 5 A cross-sectional view taken along line B3-B3'.

[0016] Figure 6C It is along Figure 5 A cross-sectional view taken along line B4-B4'.

[0017] Fig.6D yes Fig. 6A Magnified view of the area PP.

[0018] Figure 7 yes Figure 4 An enlarged layout diagram of area A.

[0019] Fig. 8A It is along Figure 7 A cross-sectional view taken along line C1-C1' and line C2-C2'.

[0020] Figure 8B yes Fig. 8A A magnified view of the area QQ.

[0021] Fig. 9 yes Figure 4 An enlarged layout diagram of area A.

[0022] FIG. 10A to FIG. 15C is a schematic diagram illustrating an exemplary method of manufacturing a semiconductor device according to some embodiments.

[0023] Fig.16 is a schematic diagram illustrating an exemplary data storage system including a semiconductor device according to some embodiments.

[0024] Fig.17 is a perspective view illustrating an exemplary data storage system according to some embodiments.

[0025] Fig.18 FIG. 2 is a diagram showing an exemplary semiconductor package according to some embodiments. Fig.17 A cross-sectional view taken along line II-II'. DETAILED DESCRIPTION

[0026] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram of an exemplary semiconductor device according to some embodiments. Figure 1 , the semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 includes a plurality of memory cell blocks BLK1, BLK2, ..., BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ..., BLKn may include a plurality of memory cells. The memory cell blocks BLK1, BLK2, ..., BLKn may be connected to the peripheral circuit 30 via a bit line BL, a word line WL, a string selection line SSL, and a ground selection line GSL.

[0028] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output circuit 36, and a control logic 38. Figure 1 Although not shown, the peripheral circuit 30 may also include an input / output interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, and the like.

[0029] The memory cell array 20 may be connected to the page buffer 34 via the bit line BL, and connected to the row decoder 32 via the word line WL, the string selection line SSL, and the ground selection line GSL. In the memory cell array 20, the plurality of memory cells of the plurality of memory cell blocks BLK1, BLK2, ..., BLKn may each include a flash memory cell. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of negative-AND (NAND) strings, each NAND string may include a plurality of memory cells connected to a plurality of word lines WL vertically stacked on a substrate.

[0030] The peripheral circuit 30 may be configured to receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor device 10 , and may transmit or receive data DATA to or from a device outside the semiconductor device 10 .

[0031] The row decoder 32 may be configured to select at least one of the plurality of memory cell blocks BLK1, BLK2, ..., BLKn and may select a word line WL, a string selection line SSL, and a ground selection line GSL of the selected memory cell block in response to an address ADDR from outside the row decoder 32. The row decoder 32 may be configured to transmit a voltage for performing a memory operation to the word line WL of the selected memory cell block.

[0032] The page buffer 34 may be connected to the memory cell array 20 via the bit line BL. The page buffer 34 may be configured to operate as a write driver during a program operation and apply a voltage to the bit line BL according to the data DATA to be stored in the memory cell array 20, and the page buffer 34 may be configured to operate as a sense amplifier during a read operation and sense the data stored in the memory cell array 20. The page buffer 34 may be configured to operate according to the control signal PCTL provided from the control logic 38.

[0033] The data input / output circuit 36 ​​may be connected to the page buffer 34 via the data lines DLs. The data input / output circuit 36 ​​may be configured to receive data DATA from a memory controller (not shown) during a program operation, and may provide the programmed data DATA to the page buffer 34 based on the column address C_ADDR provided from the control logic 38. The data input / output circuit 36 ​​may be configured to provide the read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided from the control logic 38 during a read operation.

[0034] The data input / output circuit 36 ​​may be configured to transfer an input address or command to the control logic 38 or the row decoder 32. The peripheral circuit 30 may further include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0035] The control logic 38 may be configured to receive a command CMD and a control signal CTRL from a memory controller. The control logic 38 may be configured to provide a row address R_ADDR to the row decoder 32, and provide a column address C_ADDR to the data input / output circuit 36. In response to the control signal CTRL, the control logic 38 may be configured to generate various internal control signals used inside the semiconductor device 10. For example, when performing a memory operation such as a program operation or an erase operation, the control logic 38 may adjust the voltage levels provided to the word line WL and the bit line BL.

[0036] Figure 2 is a circuit diagram showing an exemplary memory cell block BLK according to some embodiments. Figure 2 In the embodiment, the memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL (BL1, BL2, ..., BLm), a plurality of word lines WL (WL1, WL2, ..., WLn-1 and WLn), at least one string selection line SSL, at least one ground selection line GSL and a common source line CSL. A plurality of memory cell strings MS may be formed between a plurality of bit lines BL (BL1, BL2, ..., BLm) and a common source line CSL. Although Figure 2A case where each of the plurality of memory cell strings MS includes two string selection lines SSL is shown, but some embodiments are not limited thereto. For example, each of the plurality of memory cell strings MS may include one string selection line SSL.

[0037] Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1, MC2, ..., MCn-1, and MCn. The drain region of the string selection transistor SST may be connected to a bit line BL (BL1, BL2, ..., BLm), and the source region of the ground selection transistor GST may be connected to a common source line CSL. The common source line CSL may have a region to which the source regions of the plurality of ground selection transistors GST are commonly connected.

[0038] The string selection transistor SST may be connected to the string selection line SSL, and the ground selection transistor GST may be connected to the ground selection line GSL. A plurality of memory cell transistors MC1, MC2, ..., MCn-1, and MCn may be connected to a plurality of word lines WL (WL1, WL2, ..., WLn-1, and WLn), respectively.

[0039] Figure 3 is a perspective view of an exemplary configuration of a semiconductor device according to some embodiments. Figure 4 yes Figure 3 FIG. 1 is a plan layout diagram of a semiconductor device 100 . Figure 5 yes Figure 4 An enlarged layout diagram of area A. Fig. 6A It is along Figure 5 A cross-sectional view taken along line B1-B1' and line B2-B2'. Figure 6B It is along Figure 5 A cross-sectional view taken along line B3-B3'. Figure 6C It is along Figure 5 A cross-sectional view taken along line B4-B4'. Fig.6D yes Fig. 6A Magnified view of the area PP.

[0040] Reference Figures 3 to 6D , the semiconductor device 100 includes a cell structure CS and a peripheral circuit structure PS stacked on each other in a vertical direction Z. The cell structure CS may include Figure 1 The memory cell array 20 described above, the peripheral circuit structure PS may include the following Figure 1 The peripheral circuit 30 is described. Figures 3 to 6D , the first horizontal direction X is defined as a direction parallel to the upper surface of the substrate 50, the second horizontal direction Y is defined as a direction parallel to the upper surface of the substrate 50 and intersecting the first horizontal direction X, and the vertical direction Z is defined as a direction perpendicular to the upper surface of the substrate 50.

[0041] The cell structure CS may include a plurality of memory cell blocks BLK1 , BLK2 , . . . , BLKn. Each of the plurality of memory cell blocks BLK1 , BLK2 , . . . , BLKn may include three-dimensionally arranged memory cells.

[0042] exist Fig. 6A , the peripheral circuit structure PS may include a peripheral circuit transistor 60TR and a peripheral circuit wiring structure 70 arranged on a substrate 50. An active region AC may be defined in the substrate 50 by an element isolation film 52, and a plurality of peripheral circuit transistors 60TR may be formed on the active region AC. The plurality of peripheral circuit transistors 60TR may each include a peripheral circuit gate 60G and a source / drain region 62, and the source / drain region 62 is arranged in a portion of the substrate 50 on both sides of the peripheral circuit gate 60G.

[0043] The substrate 50 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or silicon germanium. The substrate 50 may be provided as a bulk wafer or an epitaxial layer. In some embodiments, the substrate 50 may include a silicon on insulator (SOI) substrate or a germanium on insulator (GeOI) substrate.

[0044] The peripheral circuit wiring structure 70 includes a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit wiring layers 74. A first interlayer insulating film 80 may be provided on the substrate 50 to cover the peripheral circuit transistor 60TR and the peripheral circuit wiring structure 70. The plurality of peripheral circuit wiring layers 74 may have a multilayer structure including a plurality of metal layers arranged at different vertical levels. A connection pad (pad, or "pad" or "pad") 90 may be provided in the first interlayer insulating film 80, and the peripheral circuit structure PS and the cell structure CS may be electrically connected and bonded to each other through the connection pad 90.

[0045] The cell structure CS may include a cell region MCR, a connection region CON, and a peripheral circuit connection region PRC. Figure 4 In the embodiment, the connection region CON may be adjacent to the cell region MCR in the first horizontal direction X, and the peripheral circuit connection region PRC may surround the cell region MCR and the connection region CON. The cell region MCR may include a region in which a memory cell block BLK is located, and the memory cell block BLK includes a plurality of memory cell strings extending in the vertical direction Z. Fig. 6A, the cell region MCR may include a common source layer 110, a gate electrode 120, and a channel structure 130, the channel structure 130 passes through the gate electrode 120, extends in the vertical direction Z, and is connected to the common source layer 110. The connection region CON may include an extension portion 120E and a pad portion 120P connected to the plurality of gate electrodes 120, and a first plug CP1 passing through the extension portion 120E and the pad portion 120P and electrically connected to the pad portion 120P. The peripheral circuit connection region PRC may include a second plug CP2 extending in the vertical direction Z and electrically connected to the peripheral circuit wiring structure 70.

[0046] The cell structure CS may include a first surface CS_1 connected to the peripheral circuit structure PS and a second surface CS_2 opposite to the first surface CS_1. Fig. 6A , the first surface CS_1 of the unit structure CS is shown on the lower side of the unit structure CS, and the second surface CS_2 of the unit structure CS is shown on the upper side of the unit structure CS. Here, the portion of the unit structure CS close to the first surface CS_1 is referred to as the portion at the lower vertical level, and the portion of the unit structure CS close to the second surface CS_2 is referred to as the portion at the higher vertical level.

[0047] The gate electrodes 120 may be spaced apart from each other in the vertical direction Z in the cell region MCR, and the gate electrodes 120 may be arranged alternately with the mold insulating layer 122. The gate electrode 120 may extend to the connection region CON, and the portion of the gate electrode 120 located in the connection region CON may be referred to as an extension 120E. The extension 120E may have a horizontal length that gradually increases in the direction toward the second surface CS_2 of the cell structure CS (i.e., in the upward direction). The extensions 120E may each have a stepped shape, and the pad 120P may be connected to the end of the extension 120E. In the vertical direction Z, the thickness of the pad 120P may be greater than the thickness of the extension 120E.

[0048] Although not shown, the gate electrode 120 may include a buried conductive layer and a conductive barrier layer, the conductive barrier layer surrounding the top surface, bottom surface and side surface of the buried conductive layer. For example, the buried conductive layer may include a metal (such as tungsten, nickel, cobalt and tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide and tantalum silicide), doped polysilicon, or a combination thereof. In some embodiments, the conductive barrier layer may include titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0049] In some embodiments, the gate electrode 120 may correspond to a cell constituting the memory cell string MS (see Figure 2), a ground selection line GSL, word lines WL (WL1, WL2, ..., WLn-1 and WLn) and at least one string selection line SSL. For example, the topmost gate electrode 120 can be used as a ground selection line GSL, the two bottom gate electrodes 120 can be used as string selection lines SSL, and the remaining gate electrodes 120 can be used as word lines WL. Therefore, a memory cell string MS can be provided, in which a ground selection transistor GST, a string selection transistor SST, and memory cell transistors MC1, MC2, ..., MCn-1 and MCn between the ground selection transistor GST and the string selection transistor SST are connected in series with each other. In some embodiments, at least one of the gate electrodes 120 can be used as a dummy word line, but in some embodiments, it is not limited thereto.

[0050] exist Figure 5 and Fig. 6A , the stack separation insulating layer WLI may be located inside the stack separation opening WLH that passes through the gate electrode 120 and the mold insulating layer 122 and extends in the vertical direction Z. Although not shown, the stack separation insulating layer WLI may have an upper surface at a higher vertical level than the uppermost gate electrode 120 and may protrude upward from the uppermost gate electrode 120. Figure 5 As shown in , the gate electrode 120 arranged between a pair of stack separation openings WLH can form a memory cell block BLK. In addition, at least one gate electrode 120 (e.g., the lowermost gate electrode 120) inside a memory cell block BLK can be separated into two gate electrodes 120 by the string separation opening SSLH. The string separation insulating layer SSLI can be located inside the string separation opening SSLH.

[0051] In the connection region CON and the peripheral circuit connection region PRC, the stacked insulating layer 124 may be provided to surround the gate electrode 120, the extension 120E, and the pad portion 120P. In a plan view, the stacked insulating layer 124 may surround the gate electrode 120. In the peripheral circuit connection region PRC, the upper surface of the stacked insulating layer 124 may be at the same level as the upper surface of the uppermost mold insulating layer among the mold insulating layers 122.

[0052] exist Fig. 6A , the channel structure 130 may include a first end 130x close to the peripheral circuit structure PS and a second end 130y opposite to the first end 130x. In some embodiments, the channel structure 130 may have an inclined sidewall so that the width of the first end 130x is greater than the width of the second end 130y. The bit line BL may be electrically connected to the first end 130x of the channel structure 130 via the bit line contact BLC, and the common source layer 110 may be connected to the second end 130y of the channel structure 130.

[0053] exist Fig.6D , the channel structure 130 may be located in a channel hole 130H that passes through the gate electrode 120 and the mold insulating layer 122 and extends in a vertical direction, and may include a gate insulating layer 132, a channel layer 134, a buried insulating layer 136, and a drain region 138. The channel layer 134 may have a cylindrical shape, the gate insulating layer 132 may be located on an outer wall of the channel layer 134, and the buried insulating layer 136 may be located on an inner wall of the channel layer 134. The gate insulating layer 132 may not be disposed on the uppermost surface of the channel layer 134, for example, not disposed on the upper surface of the channel layer 134 located at the second end 130y of the channel structure 130.

[0054] exist Fig.6D In the embodiment, the gate insulating layer 132 may have a structure including a tunneling dielectric layer 132A, a charge storage layer 132B, and a blocking dielectric layer 132C, which are arranged in this order on the outer wall of the channel layer 134. The relative thicknesses of the tunneling dielectric layer 132A, the charge storage layer 132B, and the blocking dielectric layer 132C constituting the gate insulating layer 132 are not limited to Fig.6D The relative thicknesses are shown and may be modified.

[0055] The tunneling dielectric layer 132A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer 132B may have a region capable of storing electrons passing through the tunneling dielectric layer 132A from the channel layer 134, and may include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric layer 132C may include silicon oxide, silicon nitride, or a metal oxide having a dielectric constant greater than that of silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0056] exist Fig. 6A , a common source layer 110 may be disposed on the uppermost molded insulating layer 122. The common source layer 110 may be conformally formed and connected to the second end 130y of the channel structure 130. Although not shown, the common source layer 110 may cover the upper surface of the stacked separation insulating layer WLI. In a plan view, the common source layer 110 may be disposed in the entire cell region MCR. The common source layer 110 may not be disposed on the connection region CON. The common source layer 110 extends in the second horizontal direction Y and may be disposed to at least a portion of the peripheral circuit connection region PRC. A portion of the common source layer 110 may have an upper surface at a vertical level different from the vertical level of another portion of the common source layer 110 that contacts the second end 130y of the channel structure 130.

[0057] In some embodiments, Fig.6DAs shown in , the common source layer 110 may conformally cover the upper surface of the channel layer 134 and the upper surface of the gate insulating layer 132. For example, the gate insulating layer 132 may be at a level lower than the upper surface of the channel layer 134, wherein the upper surface and a portion of the sidewall of the channel layer 134 are covered by the common source layer 110, so that a sufficient contact area between the channel layer 134 and the common source layer 110 may be obtained. In some embodiments, as Fig.6D As shown in FIG. 1 , the upper surface of the charge storage layer 132B may protrude upward from the upper surface of the tunnel dielectric layer 132A and the upper surface of the blocking dielectric layer 132C. However, the shape of the gate insulating layer 132 is not limited to Fig.6D In some embodiments, the upper surface of the charge storage layer 132B may be at the same level as the upper surface of the tunneling dielectric layer 132A and the upper surface of the blocking dielectric layer 132C, so that the upper surface of the gate insulating layer 132 may have a flat level.

[0058] The common source layer 110 may have a first region 110A and a second region 110B. The first region 110A and the second region 110B may include portions of the common source layer 110 doped with impurities of different conductivity types. For example, the first region 110A may be doped with impurities of a first conductivity type (e.g., boron (B) atoms), and the first conductivity type may include a P type. The second region 110B may be doped with impurities of a second conductivity type (e.g., phosphorus (P) atoms), and the second conductivity type may include an N type. For example, the first region 110A may include or have a first conductivity (e.g., P type conductivity), and the second region 110B may include or have a second conductivity (e.g., N type conductivity). Figure 5 As shown in FIG. 1 , each of the first region 110A and the second region 110B may extend in the second horizontal direction Y. As shown in FIG.

[0059] Each of the first region 110A and the second region 110B may be provided in plural. The plurality of first regions 110A and the plurality of second regions 110B may be alternately arranged in the first horizontal direction X. Two first regions 110A may be adjacent to each other in the first horizontal direction X, with at least one second region 110B located between the two first regions 110A. Two second regions 110B may be adjacent to each other in the first horizontal direction X, with at least one first region 110A located between the two second regions 110B.

[0060] The first region 110A may contact the channel layer 134 at the second end 130y of the channel structure 130. The first region 110A may cover at least a portion of an upper surface and at least a portion of a sidewall of the channel layer 134 at the second end 130y of the channel structure 130.

[0061] The second region 110B may be in contact with the channel layer 134 located at the second end 130y of the channel structure 130. The second region 110B may cover at least a portion of the upper surface and at least a portion of the sidewall of the channel layer 134 located at the second end 130y of the channel structure 130. Therefore, the channel layer 134 of the channel structure 130 may be connected to both the first region 110A and the second region 110B. In some embodiments, the physical boundary between the first region 110A and the second region 110B may not be observed.

[0062] In some embodiments, the common source layer 110 may include polysilicon. A laser annealing process may be performed on the common source layer 110, wherein the common source layer 110 may have a relatively large grain size and exhibit relatively excellent crystal quality.

[0063] In the connection region CON, a first plug CP1 may be provided passing through the extension 120E and the pad 120P extending from the gate electrode 120. An insulating pattern 126 may be formed at a position vertically overlapping the pad 120P connected to the first plug CP1. The insulating pattern 126 may be provided between the first plug CP1 and the extension 120E.

[0064] In some embodiments, Fig. 6A As shown in , the third end CP1x of the first plug CP1 may be adjacent to the peripheral circuit structure PS, and the fourth end CP1y of the first plug CP1 may be opposite to the third end CP1x. The first plug CP1 may have an inclined sidewall so that the width of the third end CP1x is greater than the width of the fourth end CP1y. The fourth end CP1y of the first plug CP1 may extend through the uppermost mold insulation layer 122, and the upper surface of the fourth end CP1y of the first plug CP1 may be covered by the first upper interlayer insulation film 161.

[0065] Although not shown, in some embodiments, the first plug CP1 may include a conductive buried layer and a barrier layer, the barrier layer having a small thickness and surrounding the upper surface and sidewalls of the conductive buried layer. For example, the conductive buried layer may include a metal (such as tungsten, nickel, cobalt, and tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, and tantalum silicide), doped polysilicon, or a combination thereof. The barrier layer may include titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0066] like Figure 6BAs shown in the figure, in the peripheral circuit connection region PRC, a second plug CP2 passing through the stacked insulating layer 124 may be provided. The fifth end CP2x of the second plug CP2 may be adjacent to the peripheral circuit structure PS, and the sixth end CP2y of the second plug CP2 may be opposite to the fifth end CP2x. The second plug CP2 may have an inclined sidewall so that the width of the fifth end CP2x is greater than the width of the sixth end CP2y. The sixth end CP2y of the second plug CP2 may extend through the uppermost mold insulating layer 122, and the upper surface of the sixth end CP2y of the second plug CP2 may be covered by the first upper interlayer insulating film 161.

[0067] like Figure 6C As shown in , in the peripheral circuit connection region PRC, a third plug CP3 passing through the stacked insulating layer 124 may be provided. The third plug CP3 may be spaced apart from the common source layer 110 in the first horizontal direction X. The seventh end CP3x of the third plug CP3 may be adjacent to the peripheral circuit structure PS, and the eighth end CP3y of the third plug CP3 may be opposite to the seventh end CP3x. The third plug CP3 may have an inclined sidewall so that the width of the seventh end CP3x is greater than the width of the eighth end CP3y. The eighth end CP3y of the third plug CP3 may extend through the uppermost mold insulating layer 122, and the upper surface of the eighth end CP3y of the third plug CP3 may be covered by the first upper interlayer insulating film 161.

[0068] exist Fig. 6A In the embodiment, the connection via 152, the connection wiring layer 154, and the second interlayer insulating film 156 surrounding the connection via 152 and the connection wiring layer 154 may be arranged between the stacked insulating layer 124 and the peripheral circuit structure PS. The connection via 152 and the connection wiring layer 154 may be formed in a plurality of layers arranged at a plurality of vertical levels, and the bit line BL, the first plug CP1, the second plug CP2, and the third plug CP3 may be electrically connected to the peripheral circuit structure PS via the connection pad 90.

[0069] In the peripheral circuit connection region PRC, the first conductive line CL1 and the second conductive line CL2 may be arranged on the first upper interlayer insulating film 161. The vertical level of the first conductive line CL1 and the second conductive line CL2 may be higher than the vertical level of the channel layer 134. The first conductive line CL1 and the second conductive line CL2 may extend in the first horizontal direction X. The first conductive line CL1 may be connected to at least one of the plurality of first regions 110A of the common source layer 110 through a first conductive via CL1V passing through the first upper interlayer insulating film 161. The second conductive line CL2 may be connected to at least one of the plurality of second regions 110B of the common source layer 110 through a second conductive via CL2V passing through the first upper interlayer insulating film 161. One first conductive line CL1 may be connected to at least one first region 110A, and one second conductive line CL2 may be connected to at least one second region 110B.

[0070] The first conductive line CL1 and the second conductive line CL2 may be spaced apart from each other in the second horizontal direction Y. Each of the first conductive line CL1 and the second conductive line CL2 may be provided in one or more. When a plurality of first conductive lines CL1 and a second conductive line CL2 are provided, the plurality of first conductive lines CL1 and the plurality of second conductive lines CL2 may be alternately arranged in the second horizontal direction Y. However, in some embodiments, the plurality of first conductive lines CL1 may be arranged successively in the second horizontal direction Y, and the plurality of second conductive lines CL2 may be arranged successively in the second horizontal direction Y.

[0071] exist Fig. 6A and Figure 6C In the embodiment, each of the first conductive line CL1 and the second conductive line CL2 may be connected to one of the plurality of third plugs CP3 through a third conductive via VC passing through the first upper interlayer insulating film 161. Each of the first conductive line CL1 and the second conductive line CL2 may be electrically connected to the peripheral circuit structure PS via one of the third plugs CP3. Fig. 6A and Fig. 9 In the embodiment, a first conductive via CL1V connecting the first conductive line CL1 to the first region 110A may be located in the cell region MCR. A second conductive via CL2V connecting the second conductive line CL2 to the second region 110B may be located in the cell region MCR.

[0072] exist Figure 6C and Fig. 9 In the embodiment, the third plug CP3 and the third conductive via VC may be spaced apart from the common source layer 110 in the second horizontal direction Y, but may not be spaced apart from the common source layer 110 in the second horizontal direction Y. Figure 5 and Figure 7, as shown in , the third plugs CP3 and the third conductive vias VC are spaced apart from the common source layer 110 in the first horizontal direction X. However, in some embodiments, when the first conductive line CL1 and the second conductive line CL2 are further extended in the first horizontal direction X in the peripheral circuit connection region PRC, the third plugs CP3 and the third conductive vias VC may be spaced apart from the common source layer 110 in the first horizontal direction X.

[0073] In some embodiments, the memory cell string MS (in the embodiment of FIG. 1 ) composed of the channel structure 130 may be erased by applying an erase voltage to the first region 110A of the common source layer 110 through the first conductive line CL1. Figure 2 In addition, by applying a program voltage or a read voltage to the second region 110B of the common source layer 110 via the second conductive line CL2, the memory cell string MS (in Figure 2 ) for programming or reading operations.

[0074] exist FIG. 6A to FIG. 6D In the embodiment, the second upper interlayer insulating film 162 may be disposed on the first upper interlayer insulating film 161. The second upper interlayer insulating film 162 may cover the first upper interlayer insulating film 161, the first conductive line CL1, and the second conductive line CL2.

[0075] exist Figure 6B , the backside via 164 may pass through the second upper interlayer insulating film 162. The backside via 164 may further extend in the vertical direction Z and then be inserted into the first upper interlayer insulating film 161. Each of the backside vias 164 may be connected to one of the plurality of second plugs CP2.

[0076] exist Figure 6B In the embodiment, the backside pad 166 may be disposed on the second upper interlayer insulating film 162. The backside pad 166 may be connected to the backside via 164. The passivation layer 168 may be disposed on the second upper interlayer insulating film 162, and the opening OP of the passivation layer 168 may expose the upper surface of the backside pad 166.

[0077] Typically, the peripheral circuit structure PS and the cell structure CS are attached to each other by a bonding process, and a common source layer 110 is formed on the upper surface of the cell structure CS by deposition, and the common source layer 110 is doped with N-type impurities (e.g., phosphorus (P) atoms). During the erase operation of the semiconductor device 100, the gate-induced drain leakage (GIDL) phenomenon is utilized with the help of the common source layer 110 doped with N-type impurities to perform the erase operation. However, when the erase operation of the semiconductor device 100 is performed using the GIDL phenomenon in the case of a large number of gate electrodes 120 and a mold insulating layer 122, a relatively high erase voltage (Vers) is applied to the common source layer 110. Therefore, the channel structure 130 may be adversely affected, and the data retention and durability of the channel structure 130 may be degraded. Therefore, the reliability of the semiconductor device 100 may be degraded.

[0078] However, according to the above-described embodiment, the common source layer 110 may include a first region 110A and a second region 110B, wherein the first region 110A may be doped with impurities of a first conductivity type, and the second region 110B may be doped with impurities of a second conductivity type. The first conductivity type may include a P type, and the second conductivity type may include an N type. Both the first region 110A and the second region 110B may be connected to a channel layer 134 in one channel structure 130. Therefore, when performing a programming operation and a reading operation of the semiconductor device 100, the second region 110B may be used, and when performing an erase operation, the first region 110A may be used. Specifically, when the first region 110A is used during an erase operation, holes may be supplied from the first region 110A to the channel layer 134. Therefore, compared with the erase operation of the GIDL method, an erase operation may be performed even at a relatively low erase voltage. Although not shown, the first region 110A of the common source layer 110 may include N-type conductivity, and the second region 110B of the common source layer 110 may include P-type conductivity. When performing a program operation and a read operation of the semiconductor device 100, the first region 110A may be used, and when performing an erase operation, the second region 110B may be used.

[0079] Figure 7 yes Figure 4 An enlarged layout diagram of area A. Fig. 8A It is along Figure 7 A cross-sectional view taken along line C1-C1' and line C2-C2'. Figure 8B yes Fig. 8A Hereinafter, the differences from the above are described.

[0080] Reference Figure 7 , Fig. 8A and Figure 8B, the first region 110A of the common source layer 110 of the semiconductor device 101 may be in contact with the channel layer 134 of the channel structure 130, and the second region 110B may be spaced apart from the channel layer 134. The width of the first region 110A in the first horizontal direction X may be smaller than the width of the first end 130x of the channel structure 130, and greater than the width of the second end 130y of the channel structure 130. The first region 110A may or may not cover the sidewall and the upper surface of the gate insulating layer 132 at the second end 130y of the channel structure 130. The second region 110B may or may not cover the sidewall and the upper surface of the gate insulating layer 132 at the second end 130y of the channel structure 130.

[0081] Fig. 9 yes Figure 4 The enlarged layout diagram of area A of FIG. In the following, the differences from the above are described. Fig. 9 In the embodiment, the first region 110A and the second region 110B of the common source layer 110 of the semiconductor device 102 may extend in the first horizontal direction X. The two first regions 110A may be adjacent to each other in the second horizontal direction Y, and at least one second region 110B may be located between the two first regions 110A. The two second regions 110B may be adjacent to each other in the second horizontal direction Y, and at least one first region 110A may be located between the two second regions 110B. Fig. 9 In the embodiment, the common source layer 110 is located only in the cell region MCR, but some embodiments are not limited thereto. For example, the common source layer 110 may further extend in the second horizontal direction Y and may be located in the peripheral circuit connection region PRC.

[0082] In the semiconductor device 102, according to some embodiments, the first conductive line CL1 and the second conductive line CL2 may extend in the second horizontal direction Y in the cell region MCR, and may extend to the peripheral circuit connection region PRC. The area occupied by the first conductive line CL1 and the second conductive line CL2 may be small in a plan view compared to when the first conductive line CL1 and the second conductive line CL2 extend in the first horizontal direction X. Therefore, the integration of the semiconductor device 102 may be improved.

[0083] exist Fig. 9 In the cell region MCR, the first conductive line CL1 and the second conductive line CL2 may extend in the second horizontal direction Y. The first conductive line CL1 and the second conductive line CL2 may further extend to the peripheral circuit connection region PRC.

[0084] FIG. 10A to FIG. 15C is a schematic diagram illustrating an exemplary method of manufacturing a semiconductor device according to some embodiments. Specifically, Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14 and Fig.15A It is along Figure 5 A cross-sectional view taken along the line B1-B1' and the line B2-B2', Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 15B It is along Figure 5 A cross-sectional view taken along line B3-B3', Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C and Fig. 15C It is along Figure 5 A cross-sectional view taken along line B4-B4'.

[0085] Reference Fig. 10A , Fig. 10B and Fig. 10C , a carrier substrate 310 including a cell region MCR, a connection region CON, and a peripheral circuit connection region PRC may be provided. The connection region CON may be spaced apart from the cell region MCR in the first horizontal direction X, and the peripheral circuit connection region PRC may surround the cell region MCR and the connection region CON. In some embodiments, the carrier substrate 310 may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof.

[0086] On the carrier substrate 310, a gate electrode 120 and a mold insulating layer 122 may be formed in the cell region MCR and the connection region CON, and an extension portion 120E and a pad portion 120P connected to the gate electrode 120 may be formed in the connection region CON. A channel structure 130 and a bit line BL may be formed in the cell region MCR, the channel structure 130 passes through the gate electrode 120 and extends in the vertical direction Z, and the bit line BL is connected to the channel structure 130. A stacked insulating layer 124 may be formed in the connection region CON and the peripheral circuit connection region PRC, the stacked insulating layer 124 surrounding the gate electrode 120, the extension portion 120E, and the pad portion 120P. A first plug CP1 passing through the extension portion 120E and the pad portion 120P may be formed in the connection region CON, and a second plug CP2 and a third plug CP3 passing through the stacked insulating layer 124 may be formed in the peripheral circuit connection region PRC.

[0087] The channel structure 130, the first plug CP1, the second plug CP2, and the third plug CP3 may further extend in the vertical direction Z and be inserted into the carrier substrate 310. A connection via 152 and a connection wiring layer 154 electrically connected to the bit line BL, the first plug CP1, the second plug CP2, and the third plug CP3 may be provided, and a second interlayer insulating film 156 may be provided.

[0088] Although not shown, the stack separation opening WLH may pass through the gate electrode 120 and the mold insulation layer 122 and extend in the vertical direction Z, and the stack separation insulation layer WLI may be formed inside the stack separation opening WLH. The stack separation insulation layer WLI may further extend in the vertical direction Z and be inserted into the carrier substrate 310 .

[0089] In some embodiments, during the formation of the channel structure 130, as Fig. 10A As shown in , the first end 130 x of the channel structure 130 may be at a higher vertical level than the second end 130 y of the channel structure 130 , and the second end 130 y may extend into the carrier substrate 310 .

[0090] In some embodiments, during the formation of the first plug CP1 , the third end CP1 x of the first plug CP1 may have a greater width than the fourth end CP1 y of the first plug CP1 , and the fourth end CP1 y of the first plug CP1 may extend into the carrier substrate 310 .

[0091] In some embodiments, during the formation of the second plug CP2 , the fifth end CP2 x of the second plug CP2 may have a greater width than the sixth end CP2 y of the second plug CP2 , and the sixth end CP2 y of the second plug CP2 may extend into the carrier substrate 310 .

[0092] In some embodiments, during the formation of the third plug CP3 , the seventh end CP3 x of the third plug CP3 may have a greater width than the eighth end CP3 y of the third plug CP3 , and the eighth end CP3 y of the third plug CP3 may extend into the carrier substrate 310 .

[0093] Reference Fig.11A , Fig. 11B and Fig. 11C, a peripheral circuit structure PS can be prepared. The peripheral circuit structure PS may include a peripheral circuit transistor 60TR and a peripheral circuit wiring structure 70 arranged on the substrate 50. An active region AC may be defined in the substrate 50 by an element isolation film 52, and a plurality of peripheral circuit transistors 60TR may be formed on the active region AC. The plurality of peripheral circuit transistors 60TR may each include a peripheral circuit gate 60G and a source / drain region 62, and the source / drain region 62 is arranged in a portion of the substrate 50 on both sides of the peripheral circuit gate 60G.

[0094] Subsequently, the peripheral circuit structure PS may be attached to the cell structure CS. The peripheral circuit structure PS and the cell structure CS may be attached to each other through the connection pad 90, the first interlayer insulating film 80, and the second interlayer insulating film 156 using a metal-oxide hybrid bonding method.

[0095] Subsequently, the structure in which the peripheral circuit structure PS and the cell structure CS are attached to each other may be turned over so that the carrier substrate 310 is oriented upward.

[0096] Reference Fig. 12A , Fig. 12B and Fig. 12C , the carrier substrate 310 can be removed (in Fig. 12A ). The carrier substrate 310 may be removed by a grinding process and a subsequent etching process, and the second end 130y of the channel structure 130 may be exposed. Similarly, as the carrier substrate 310 is removed, the fourth end CP1y of the first plug CP1, the sixth end CP2y of the second plug CP2, and the eighth end CP3y of the third plug CP3 may be exposed. Although not shown, as the carrier substrate 310 is removed, the upper portion of the stack separation insulating layer WLI may also be exposed.

[0097] Subsequently, a portion of the gate insulating layer 132 exposed at the second end 130y of the channel structure 130 may be removed, and an upper surface of the channel layer 134 may be exposed. In some embodiments, an upper surface of the gate insulating layer 132 may be at a lower level than an upper surface of the channel layer 134, and an upper portion of the gate insulating layer 132 may be further removed to partially expose an upper surface and sidewalls of the channel layer 134.

[0098] Subsequently, an inclined ion implantation process TIIP may be performed on the channel layer 134. In the inclined ion implantation process TIIP, the ion implantation process is performed at an angle inclined relative to the vertical direction Z. In the inclined ion implantation process TIIP, impurities of a first conductivity type may be implanted into the channel layer 134, wherein the first conductivity type may include a P type.

[0099] Reference Fig.13A , Fig. 13B and Fig. 13C , a preliminary common source layer 110p may be formed on the cell region MCR, the connection region CON, and the peripheral circuit connection region PRC. The preliminary common source layer 110p may be formed using polysilicon.

[0100] In the cell region MCR, a preliminary common source layer 110p may be conformally formed on the exposed upper surface of the channel layer 134 and the uppermost mold insulating layer among the mold insulating layers 122. In the connection region CON and the peripheral circuit connection region PRC, a preliminary common source layer 110p may be formed on the stacked insulating layer 124, the first plug CP1, the second plug CP2, and the third plug CP3.

[0101] Reference Fig.14 , a first ion implantation process and a second ion implantation process may be performed on the preliminary common source layer 110p using a first photomask film and a second photomask film, respectively. In the first ion implantation process, a portion of the preliminary common source layer 110p where the second region 110B is to be formed may be covered with the first photomask film, and impurities of the first conductivity type may be implanted into the preliminary common source layer 110p. After the first ion implantation process is completed, a second ion implantation process may be performed. In the second ion implantation process, a portion of the preliminary common source layer 110p where the first region 110A is to be formed may be covered with the second photomask film, and impurities of the second conductivity type may be implanted into the preliminary common source layer 110p. In some embodiments, the order of the first ion implantation process and the second ion implantation process may be changed. Subsequently, the preliminary common source layer 110p disposed on the connection region CON and the peripheral circuit connection region PRC may be removed. Therefore, a common source layer 110 including a first region 110A and a second region 110B may be formed on the cell region MCR.

[0102] Subsequently, laser annealing may be performed on the common source layer 110. In some embodiments, laser annealing may be performed to improve crystallinity of the common source layer 110 in the cell region MCR, increase a grain size of the common source layer 110, or reduce resistance of the common source layer 110. In some embodiments, laser annealing may be performed on the preliminary common source layer 110p before performing the first ion implantation process and the second ion implantation process.

[0103] Reference Fig.15A , Fig. 15B and Fig. 15C, the first upper interlayer insulating film 161 may cover the common source layer 110. The first upper interlayer insulating film 161 may cover the uppermost mold insulating layer among the mold insulating layers 122 and the fourth end CP1y of the first plug CP1 in the connection region CON. The first upper interlayer insulating film 161 may cover the stacked insulating layer 124, the sixth end CP2y of the second plug CP2, and the eighth end CP3y of the third plug CP3 in the peripheral circuit connection region PRC.

[0104] Subsequently, the third conductive via VC may pass through the first upper interlayer insulating film 161 and be connected to the third plug CP3. Then, the first conductive line CL1 and the second conductive line CL2 may be formed on the first upper interlayer insulating film 161. The first conductive line CL1 and the second conductive line CL2 may extend in the first horizontal direction X in the peripheral circuit connection region PRC.

[0105] Return to reference Figure 5 , Fig. 6A , Figure 6B and Figure 6C , a second upper interlayer insulating film 162 may be formed on the first upper interlayer insulating film 161. The second upper interlayer insulating film 162 may cover the first conductive line CL1 and the second conductive line CL2. Subsequently, backside vias 164 may pass through the second upper interlayer insulating film 162, wherein each of the backside vias 164 may be connected to the second plug CP2.

[0106] Backside pads 166 connected to backside vias 164 may be formed on second upper interlayer insulating film 162. Subsequently, a passivation layer 168 covering backside pads 166 is formed on second upper interlayer insulating film 162, and openings OP may be formed in passivation layer 168 and expose upper surfaces of backside pads 166.

[0107] Fig.16 is a schematic diagram illustrating an exemplary data storage system according to some embodiments. Fig.16 , the data storage system 1000 may include one or more semiconductor devices 1100 and a memory controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may include, for example, a solid state drive (SSD) device including at least one semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0108] In some embodiments, the semiconductor device 1100 may include a nonvolatile semiconductor device. For example, the semiconductor device 1100 may include a NAND flash memory semiconductor device including a semiconductor device such as described in reference Figures 1 to 9The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may include a peripheral circuit structure PS (on Figure 3 ), the peripheral circuit structure PS includes a row decoder 1110, a page buffer 1120 and a logic circuit 1130.

[0109] The second structure 1100S may include a unit structure CS (in Figure 3 In the second structure 1100S, the cell structure CS includes a bit line BL, a common source line CSL, a plurality of word lines WL, a first string selection line UL1, a second string selection line UL2, a first ground selection line LL1, a second ground selection line LL2, and a plurality of memory cell strings CSTR located between the bit line BL and the common source line CSL. In the second structure 1100S, each of the plurality of memory cell strings CSTR may include ground selection transistors LT1 and LT2 adjacent to the common source line CSL, string selection transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT arranged between the ground selection transistors LT1 and LT2 and the string selection transistors UT1 and UT2. The number of the ground selection transistors LT1 and LT2 and the number of the string selection transistors UT1 and UT2 may vary.

[0110] In some embodiments, a plurality of ground selection lines LL1 and LL2 may be connected to gate electrodes of ground selection transistors LT1 and LT2, respectively. A word line WL may be connected to gate electrodes of memory cell transistors MCT. A plurality of string selection lines UL1 and UL2 may be connected to gate electrodes of string selection transistors UT1 and UT2, respectively.

[0111] A common source line CSL, a plurality of ground selection lines LL1 and LL2, a plurality of word lines WL, and a plurality of string selection lines UL1 and UL2 may be connected to the row decoder 1110. A plurality of bit lines BL may be electrically connected to the page buffer 1120.

[0112] The semiconductor device 1100 may communicate with the memory controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130.

[0113] The memory controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , wherein the memory controller 1200 may be configured to control the plurality of semiconductor devices 1100 .

[0114] The processor 1210 may be configured to control the overall operation of the data storage system 1000 including the memory controller 1200. The processor 1210 may be configured to operate according to a certain firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 configured to handle communication with the semiconductor device 1100. The control command may be configured to control the semiconductor device 1100, control data to be written into the plurality of memory cell transistors MCT of the semiconductor device 1100, wherein data to be read from the plurality of memory cell transistors MCT of the semiconductor device 1100 may be transmitted via the NAND interface 1221. The host interface 1230 may be configured to provide a communication function between the data storage system 1000 and an external host. When a control command is received from an external host via the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0115] Fig.17 is a perspective view illustrating an exemplary data storage system 2000 according to some embodiments. Fig.17 , a data storage system 2000 may include a main board 2001, a memory controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the memory controller 2002 through a plurality of wiring patterns 2005 formed on the main board 2001.

[0116] The mainboard 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 may be configured to communicate with the external host according to one of the interfaces such as a universal serial bus (USB), a peripheral component interconnect fast (PCI-Express), a serial advanced technology attachment (SATA), and M-Phy for universal flash memory (UFS). In some embodiments, the data storage system 2000 may be operated by power supplied from an external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) configured to distribute power supplied from an external host to the memory controller 2002 and the semiconductor package 2003.

[0117] The memory controller 2002 may be configured to write data to or read data from the semiconductor package 2003. Therefore, the memory controller 2002 may improve the operation speed of the data storage system 2000.

[0118] The DRAM 2004 may include a buffer memory configured to mitigate a speed difference between an external host and the semiconductor package 2003 including a data storage space. The DRAM 2004 included in the data storage system 2000 may be configured to operate as a cache memory and may provide a space for temporarily storing data during the operation of controlling the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the memory controller 2002 may further include a DRAM controller configured to control the DRAM 2004 in addition to the NAND controller configured to control the semiconductor package 2003.

[0119] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package board 2100, a plurality of semiconductor chips 2200 on the package board 2100, an adhesive layer 2300 disposed on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 to the package board 2100, and a mold layer 2500 covering the plurality of semiconductor chips 2200 and the connection structure 2400 on the package board 2100.

[0120] The package board 2100 may include a printed circuit board having a plurality of package upper pads 2130. Each of the plurality of semiconductor chips 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to the input / output pad 1101 (in Fig.16 Each of the plurality of semiconductor chips 2200 may include a reference Figures 1 to 9 At least one of the semiconductor devices 10 , 100 , 101 , and 102 described.

[0121] In some embodiments, the connection structure 2400 may include a bonding wire that electrically connects the input / output pad 2210 to the package upper pad 2130. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other using bonding wires, and may be electrically connected to the package upper pad 2130 of the package board 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through silicon via (TSV, or "Through Silicon Via") instead of using a bonding wire type connection structure 2400.

[0122] In some embodiments, the memory controller 2002 and the plurality of semiconductor chips 2200 may be included in a single package. In some embodiments, the memory controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate interposer board different from the main board 2001, and the memory controller 2002 and the plurality of semiconductor chips 2200 may be connected to each other through wiring formed on the interposer board.

[0123] Fig.18 FIG. 2 is a diagram showing an exemplary semiconductor package according to some embodiments. Fig.17 A cross-sectional view taken along line II-II'. Fig.18 In the semiconductor package 2003, the package board 2100 may include a printed circuit board. The package board 2100 may include a package substrate body 2120, a plurality of package upper pads 2130 arranged on the upper surface of the package substrate body 2120 (in Fig.17 ), a plurality of lower pads 2125 arranged on the lower surface of the package substrate body 2120 or exposed through the lower surface of the package substrate body 2120, and a plurality of package upper pads 2130 (in Fig.17 ) and a plurality of internal wirings 2135 electrically connected to the plurality of lower pads 2125. Fig.17 In the embodiment, the plurality of package upper pads 2130 may be electrically connected to the plurality of corresponding connection structures 2400. Fig.18 As shown in FIG. 1 , the plurality of lower pads 2125 can be respectively connected to the plurality of wiring patterns 2005 (eg, FIG. 2005 ) on the main board 2001 of the data storage system 2000 via the plurality of conductive bumps 2800. Fig.17 Each of the plurality of semiconductor chips 2200 may include a reference Figures 1 to 9 At least one of the semiconductor devices 10 , 100 , 101 , and 102 described.

[0124] Although the present disclosure contains many specific implementation details, these implementation details should not be interpreted as limiting the scope of what can be claimed. Some features described in the context of separate implementations in the present disclosure can also be combined in a single implementation. On the contrary, various features described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. In addition, although features can be described above as working in some combinations, even initially claimed as such, in some cases, one or more features from the combination can be removed from the combination, and the combination can involve sub-combinations or variations of sub-combinations.

Claims

1. A semiconductor device, comprising: Peripheral circuit structure; as well as a cell structure stacked on the peripheral circuit structure, the cell structure comprising a cell region, a connection region positioned adjacent to the cell region in a first horizontal direction, and a peripheral circuit connection region surrounding the cell region and the connection region, The cell structure includes: a plurality of gate electrodes, each of which is arranged in the cell region and spaced apart from each other in the vertical direction; a channel structure, which passes through the gate electrodes in the cell region and extends in the vertical direction, and the channel structure has a first end close to the peripheral circuit structure and a second end opposite to the first end; and a common source layer, which is arranged above the plurality of gate electrodes and covers the second end of the channel structure. Wherein, the channel structure includes a channel layer extending in a vertical direction, The common source layer includes a first region and a second region, the first region and the second region contain impurities of different conductivity types, and The first region of the common source layer is connected to at least a portion of the channel layer.

2. The semiconductor device according to claim 1, wherein The first region of the common source layer includes P-type conductivity.

3. The semiconductor device according to claim 2, in, A first portion of the channel layer is connected to a first region of the common source layer, and The second portion of the channel layer is connected to the second region of the common source layer.

4. The semiconductor device according to claim 2, wherein: The second region of the common source layer is spaced apart from the channel layer.

5. The semiconductor device according to claim 1, wherein The unit structure also includes: a first conductive line electrically connected to a first region of the common source layer; and a second conductive line electrically connected to a second region of the common source layer, Wherein, in the peripheral circuit connection region, the first conductive line and the second conductive line extend in a first horizontal direction.

6. The semiconductor device according to claim 5, wherein: The unit structure also includes: stacking insulating layers surrounding the plurality of gate electrodes in a connection region and a peripheral circuit connection region; and a plug penetrating through the stacked insulating layer and connected to one of the first conductive line and the second conductive line in the peripheral circuit connection region, Wherein, the plug is electrically connected to the peripheral circuit structure.

7. The semiconductor device according to claim 5, in, Each of the first conductive line and the second conductive line is provided in plural numbers, and The plurality of first conductive lines and the plurality of second conductive lines are alternately arranged in at least one of a first horizontal direction and a second horizontal direction, and the second horizontal direction intersects the first horizontal direction.

8. The semiconductor device according to claim 1, wherein The unit structure also includes: a first conductive line electrically connected to a first region of the common source layer; and a second conductive line electrically connected to a second region of the common source layer, The first conductive line and the second conductive line extend in a second horizontal direction crossing the first horizontal direction.

9. The semiconductor device according to claim 8, wherein: The unit structure also includes: stacking insulating layers surrounding the plurality of gate electrodes in a connection region and a peripheral circuit connection region; and a plug penetrating through the stacked insulating layer and connected to one of the first conductive line and the second conductive line in the peripheral circuit connection region, In the plan view, the plug overlaps with the common source layer in the second horizontal direction.

10. The semiconductor device according to claim 1, wherein The unit structure also includes: A first conductive line connected to a first region of the common source layer; and a second conductive line connected to a second region of the common source layer, Wherein, a vertical level of each of the first conductive line and the second conductive line is higher than a vertical level of the channel layer.

11. A semiconductor device, comprising: Peripheral circuit structure; as well as Unit structure, stacked on the peripheral circuit structure, The unit structure includes: a plurality of gate electrodes, each of which is spaced apart from each other in a vertical direction; a channel structure, which passes through the plurality of gate electrodes and extends in a vertical direction, and the channel structure has a first end close to the peripheral circuit structure and a second end opposite to the first end; and a common source layer, which is arranged above the plurality of gate electrodes and covers the second end of the channel structure. The common source layer includes: a plurality of first regions, each of which has a first conductivity type and extends in a first horizontal direction; and a plurality of second regions, each of which has a second conductivity type and extends in the first horizontal direction, and the second conductivity type is different from the first conductivity type. The first regions and the second regions are alternately arranged in a second horizontal direction intersecting the first horizontal direction.

12. The semiconductor device according to claim 11, wherein The unit structure includes: a cell region, wherein the plurality of gate electrodes and the channel structure are arranged in the cell region; a connection region located adjacent to the unit region in a second horizontal direction; and The peripheral circuit connection area surrounds the cell area and the connection area.

13. The semiconductor device according to claim 12, wherein: The unit structure also includes: a first conductive line electrically connected to one of the plurality of first regions of the common source layer in the peripheral circuit connection region; and a second conductive line electrically connected to one of the plurality of second regions of the common source layer in the peripheral circuit connection region, The first conductive line and the second conductive line extend in a second horizontal direction.

14. The semiconductor device according to claim 11, wherein The unit structure includes: a cell region, wherein the plurality of gate electrodes and the channel structure are arranged in the cell region; a connection region located adjacent to the unit region in a first horizontal direction; and The peripheral circuit connection area surrounds the cell area and the connection area.

15. The semiconductor device according to claim 14, wherein: The unit structure also includes: a first conductive line electrically connected to one of the plurality of first regions of the common source layer in the peripheral circuit connection region; and a second conductive line electrically connected to one of the plurality of second regions of the common source layer in the peripheral circuit connection region, The first conductive line and the second conductive line extend from the cell area to the peripheral circuit connection area along a second horizontal direction.

16. The semiconductor device according to claim 11, in, The channel structure includes a channel layer having a cylindrical shape and extending in a vertical direction, wherein a portion of the channel layer located at the second end of the channel structure vertically overlaps with and contacts a first region of the common source layer, and The first conductivity type includes P type.

17. The semiconductor device according to claim 16, in, The width of each first region of the common source layer in the second horizontal direction is defined as a first width, Wherein, the width of the first end of the channel structure is defined as the second width, Wherein, the width of the second end of the channel structure is defined as a third width, wherein the second width is greater than the third width, and The first width is smaller than the second width and larger than the third width.

18. A semiconductor device, comprising: Peripheral circuit structure; as well as a cell structure stacked on the peripheral circuit structure and comprising a cell region, a connection region and a peripheral circuit connection region, The unit structure includes: a plurality of gate electrodes, each gate electrode being arranged in the cell region and spaced apart from each other in a vertical direction; A channel structure, passing through the plurality of gate electrodes in the cell region and extending in a vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end; a pad portion having a stepped shape in a connection region and extending from the plurality of gate electrodes; a first plug connected to the pad portion, passing through the pad portion, and extending in a vertical direction; stacking an insulating layer surrounding the plurality of gate electrodes in a plan view; a second plug penetrating the stacked insulating layer in the peripheral circuit connection region and extending in a vertical direction; and a common source layer, located in the cell region and covering the second end of the channel structure, Wherein, the channel structure includes a channel layer extending in a vertical direction, The common source layer includes a first region and a second region, the first region and the second region contain impurities of different conductivity types, and The first region of the common source layer includes P-type conductivity and is connected to at least a portion of the channel layer.

19. The semiconductor device according to claim 18, in, The common source layer extends from the cell region to the peripheral circuit connection region, and The unit structure also includes: a first conductive line electrically connected to a first region of the common source layer; and a second conductive line electrically connected to a second region of the common source layer, wherein the first plug is spaced apart from the first conductive line and the second conductive line, and The second plug is connected to any one of the first conductive line and the second conductive line.

20. The semiconductor device according to claim 18, wherein A second region of the common source layer is connected to the channel layer.

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