Semiconductor device

Abstract

A semiconductor device includes: a peripheral circuit structure; and a cell structure on the peripheral circuit structure, in which the peripheral circuit structure includes: a substrate including a cell region, a connection region adjacent to the cell region, and a pad region extending around the cell region and the connection region; a first connection structure between the substrate and the cell structure; a first peripheral circuit transistor in the cell region and / or the connection region; and a second peripheral circuit transistor in the pad region, in which the first connection structure includes a first wiring structure and a dummy structure, the first wiring structure is electrically connected to the first peripheral circuit transistor and / or the second peripheral circuit transistor, and the dummy structure is not directly connected to the first peripheral circuit transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0096409 filed in the Korean Intellectual Property Office on July 24, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept of the present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a dummy wiring and a dummy via. Background Art

[0004] In electronic systems that require data storage, semiconductor devices that can store high-capacity data may be required. Semiconductor devices may need to increase integration to meet the excellent performance and low price required by consumers while increasing data storage capacity. Because the integration is mainly determined by the area occupied by the unit storage unit, two-dimensional (2D) or planar semiconductor devices may be greatly affected by the level of micro-patterning technology. However, because the miniaturization of the pattern may require ultra-expensive equipment, the integration of 2D semiconductor devices can be increased, but may still be limited. Therefore, a three-dimensional (3D) semiconductor memory device including a three-dimensionally arranged storage unit has been proposed. Summary of the invention

[0005] The inventive concepts of the present disclosure may provide a semiconductor device having improved electrical characteristics and reliability.

[0006] The inventive concepts of the present disclosure may provide a semiconductor device having an improved degree of integration.

[0007] However, problems to be solved by the inventive concept of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned may be clearly understood by those skilled in the art from the following description.

[0008] According to one aspect of the inventive concept of the present disclosure, a semiconductor device is provided, comprising: a peripheral circuit structure; and a cell structure on the peripheral circuit structure, wherein the peripheral circuit structure comprises: a substrate, comprising a cell area, a connection area adjacent to the cell area, and a pad area extending around the cell area and the connection area; a first connection structure, between the substrate and the cell structure; a first peripheral circuit transistor in the cell area and / or the connection area; and a second peripheral circuit transistor in the pad area, wherein the first connection structure comprises a first wiring structure and a dummy structure, the first wiring structure overlaps with the cell area, the connection area and / or the pad area in a first direction perpendicular to an upper surface of the substrate, the first wiring structure is electrically connected to the first peripheral circuit transistor and / or the second peripheral circuit transistor, the dummy structure overlaps with the cell area and / or the connection area in the first direction, and the dummy structure is not directly connected to the first peripheral circuit transistor.

[0009] According to another aspect of the inventive concept of the present disclosure, a semiconductor device is provided, comprising: a substrate; a peripheral circuit structure in the substrate; a first connection structure on the substrate; and a second connection structure on the first connection structure, wherein the first connection structure comprises a first interlayer insulating layer, a first stop layer on the first interlayer insulating layer, and a first connection wiring and a dummy wiring in the first interlayer insulating layer, the second connection structure comprises a second stop layer, a second interlayer insulating layer on the second stop layer, and a second connection wiring in the second interlayer insulating layer, the first connection wiring is electrically connected to the peripheral circuit structure, the dummy wiring is not directly connected to the peripheral circuit structure, the upper surface of the dummy wiring and the lower surface of the first stop layer are coplanar with each other, and the lower surface of the second connection wiring and the upper surface of the second stop layer are coplanar with each other.

[0010] According to another aspect of the inventive concept of the present disclosure, a semiconductor device is provided, comprising: a peripheral circuit structure; and a cell structure on the peripheral circuit structure, wherein the peripheral circuit structure comprises: a substrate, comprising a cell region, a connection region adjacent to the cell region, and a pad region extending around the cell region and the connection region; and a first connection structure on the substrate, wherein the cell structure comprises: gate electrodes spaced apart from each other along a first direction in the cell region, wherein the first direction is perpendicular to an upper surface of the substrate; a channel structure extending in the gate electrode along the first direction in the cell region, wherein the channel structure comprises a first end and a second end, the first end being closer to the peripheral circuit structure than the second end in the first direction, and the second end being an opposite side of the first end; a pad portion, in the connection region extending from the gate electrode, wherein the pad portion is in a stepped shape; a first vertical conductive structure electrically connected to the pad portion, wherein the first vertical conductive structure extends in the pad portion along a first direction; a stacked insulating layer extending around the gate electrode in a plan view; a second vertical conductive structure in the pad region, wherein the second vertical conductive structure extends in the stacked insulating layer along the first direction; and a common source layer on the second end of the channel structure in the cell region, wherein the first connection structure includes a wiring structure and a dummy structure, the wiring structure overlaps with the cell region, the connection region and / or the pad region in the first direction, the wiring structure is electrically connected to the peripheral circuit structure, the dummy structure overlaps with the cell region and / or the connection region in the first direction, and the dummy structure is not directly connected to the peripheral circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of a semiconductor device according to some embodiments;

[0013] Figure 2 is a circuit diagram illustrating a memory block according to some embodiments;

[0014] Figure 3 is a perspective view showing a representative configuration of a semiconductor device according to some embodiments;

[0015] Figure 4 yes Figure 3 A planar layout diagram of a semiconductor device;

[0016] Figure 5 yes Figure 4 an enlarged layout diagram of part A;

[0017] Figure 6 According to some embodiments, Figure 5 A cross-sectional view taken along the lines B1-B1′ and B2-B2′;

[0018] Fig. 7A yes Figure 6 A magnified view of part PP1 in;

[0019] Figure 7B yes Figure 6 A magnified view of part PP2 in FIG.

[0020] Figure 7C yes Figure 6 A magnified view of part PP3 in FIG.

[0021] Fig. 8A yes Figure 6 A magnified view of part PP1 in;

[0022] Figure 8B yes Figure 6 A magnified view of part PP2 in FIG.

[0023] Fig. 9 According to some embodiments, Figure 5 A cross-sectional view taken along the lines B1-B1′ and B2-B2′;

[0024] Fig.10 yes Fig. 9 A magnified view of a portion of PP4;

[0025] Figures 11 to 15 is a diagram showing a method of manufacturing a semiconductor device according to some embodiments, and specifically along the Figure 5 A cross-sectional view taken along the lines B1-B1′ and B2-B2′;

[0026] Fig.16 is a diagram schematically illustrating a data storage system including a semiconductor device according to some embodiments;

[0027] Fig.17 is a perspective view schematically illustrating a data storage system including a semiconductor device according to some embodiments; and

[0028] Fig.18 is a diagram schematically showing a semiconductor package according to some embodiments, and is a diagram showing a semiconductor package according to some embodiments. Fig.17 A cross-sectional view taken along line II-II′. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 is a block diagram of a semiconductor device 10 according to some embodiments.

[0031] Reference Figure 1, the semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 may include a plurality of memory cell blocks BLK1, BLK2, ..., BLKn. A plurality of memory cell blocks BLK1, BLK2, ..., BLKn may each include a plurality of memory cells. A plurality of memory cell blocks BLK1, BLK2, ..., BLKn may be connected (e.g., electrically connected) to the peripheral circuit 30 via a plurality of bit lines BL, a plurality of word lines WL, a plurality of string selection lines SSL, and a ground selection line GSL. It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly on the other element or layer, directly connected to or coupled to the other element or layer, or one or more intermediate elements or layers may exist. In contrast, when an element is referred to as being "directly coupled", "directly connected", or "directly responsive to" another element, or "directly" "on" another element, there is no intermediate element. In addition, "electrically connected" conceptually includes physical connection and physical disconnection. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0032] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output (I / O) circuit 36, and control logic 38. Figure 1 Although not shown, the peripheral circuit 30 may further include an input / output interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, and the like.

[0033] The memory cell array 20 may be connected (e.g., electrically connected) to the page buffer 34 through a plurality of bit lines BL, and may be connected (e.g., electrically connected) to the row decoder 32 through a plurality of word lines WL, a plurality of string selection lines SSL, and a ground selection line GSL. In the memory cell array 20, the memory cells included in the plurality of memory cell blocks BLK1, BLK2, ..., BLKn may be flash memory cells. The memory cell array 20 may include a three-dimensional (3D) memory cell array. The 3D memory cell array may include a plurality of NAND strings, and each NAND string may include a plurality of memory cells connected (e.g., electrically connected) to a plurality of word lines WL vertically stacked on a substrate.

[0034] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor device 10, and may send data to and receive data from a device outside the semiconductor device 10. As used hereinafter, the terms “external / external configuration,” “external / external device,” “external / external power,” “external / external signal,” or “external” are intended to broadly refer to devices, circuits, blocks, modules, power, and / or signals that reside externally (e.g., outside of a functional or physical boundary) relative to a given circuit, block, module, system, or device.

[0035] The row decoder 32 may select at least one of the plurality of memory cell blocks BLK1, BLK2, ..., BLKn in response to an address ADDR from the outside, and may select a word line WL (among a plurality of word lines WL) of the selected memory cell block (among a plurality of memory cell blocks BLK1, BLK2, ..., BLKn), a string selection line SSL (among a plurality of string selection lines SSL), and a ground selection line GSL. The row decoder 32 may send a voltage for performing a storage operation to the plurality of word lines WL of the selected memory cell block (among a plurality of memory cell blocks BLK1, BLK2, ..., BLKn).

[0036] The page buffer 34 may be connected (e.g., electrically connected) to the memory cell array 20 through the plurality of bit lines BL. The page buffer 34 may operate as a write driver during a program operation to apply voltages to the plurality of bit lines BL according to data to be stored in the memory cell array 20, and may operate as a sense amplifier during a read operation to read data stored in the memory cell array 20. The page buffer 34 may operate in response to a control signal PCTL provided from the control logic 38.

[0037] The data input / output circuit 36 ​​may be connected (e.g., electrically connected) to the page buffer 34 through a plurality of data lines DL. The data input / output circuit 36 ​​may receive data from a memory controller (not shown) during a program operation, and may provide program data to the page buffer 34 based on a column address C_ADDR provided from the control logic 38. During a read operation, the data input / output circuit 36 ​​may provide read data stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided from the control logic 38.

[0038] The data input / output circuit 36 ​​may transmit an address or a command input to the control logic 38 or the row decoder 32. The peripheral circuit 30 may also include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0039] The control logic 38 may receive a command CMD and a control signal CTRL from a memory controller. The control logic 38 may provide a row address R_ADDR to the row decoder 32 and a column address C_ADDR to the data input / output circuit 36. The control logic 38 may generate various internal control signals used in the semiconductor device 10 in response to the control signal CTRL. For example, when performing a memory operation such as a program operation or an erase operation, the control logic 38 may adjust the levels of voltages provided to a plurality of word lines WL and a plurality of bit lines BL.

[0040] Figure 2 is a circuit diagram illustrating a memory block BLK (among a plurality of memory cell blocks BLK1 , BLK2 , . . . , BLKn) according to some embodiments.

[0041] Reference Figure 2 , the memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL (BL1, BL2, ..., BLm), a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. A plurality of memory cell strings MS may be formed between a plurality of bit lines BL (BL1, BL2, ..., BLm) and the common source line CSL. Figure 2 It is shown that each of the plurality of memory cell strings MS includes two string selection lines SSL, but the inventive concept is not limited thereto. For example, each of the plurality of memory cell strings MS may also include one string selection line SSL.

[0042] Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1, MC2, ..., MCn-1, MCn. The drain region of the string selection transistor SST may be connected (e.g., electrically connected) to at least one of the plurality of bit lines BL (BL1, BL2, ..., BLm), and the source region of the ground selection transistor GST may be connected (e.g., electrically connected) to a common source line CSL. The common source line CSL may be commonly connected (e.g., electrically connected) to the source regions of the plurality of ground selection transistors GST.

[0043] The string selection transistor SST may be connected (e.g., electrically connected) to a string selection line SSL, and the ground selection transistor GST may be connected (e.g., electrically connected) to a ground selection line GSL. Each of the plurality of memory cell transistors MC1, MC2, ..., MCn-1, MCn may be connected (e.g., electrically connected) to a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn), respectively.

[0044] Figure 3 is a perspective view illustrating a representative configuration of a semiconductor device 100 according to some embodiments. Figure 4 yes Figure 3 FIG. 1 is a plan layout diagram of a semiconductor device 100 . Figure 5 yes Figure 4 An enlarged layout diagram of portion A. Figure 6 According to some embodiments, Figure 5 Cross-sectional views taken along lines B1-B1′ and B2-B2′. Fig. 7A yes Figure 6 Magnified view of part PP1. Figure 7B yes Figure 6 Magnified view of part PP2. Figure 7C yes Figure 6 Magnified view of part PP3.

[0045] Reference Figures 3 to 7C , the semiconductor device 100 includes a cell structure CS and a peripheral circuit structure PS that overlap each other in a vertical direction Z. The cell structure CS may include a reference Figure 1 The memory cell array 20 described above and the peripheral circuit structure PS may include reference Figure 1 The peripheral circuit 30 is described.

[0046] In this specification, a first horizontal direction X is defined as a direction parallel to an upper surface of a substrate 50 to be described below, a second horizontal direction Y is defined as a direction parallel to the upper surface of the substrate 50 and intersecting the first horizontal direction X, and a vertical direction Z is defined as a direction perpendicular to the upper surface of the substrate 50. The vertical direction Z may intersect the first horizontal direction X and the second horizontal direction Y.

[0047] The cell structure CS may include a plurality of memory cell blocks BLK1, BLK2, ..., BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ..., BLKn may include memory cells arranged three-dimensionally.

[0048] The peripheral circuit structure PS may include a peripheral circuit transistor structure CTR and a first connection structure CNS1 on the peripheral circuit transistor structure CTR. The peripheral circuit transistor structure CTR may include first and second peripheral circuit transistors 60TR and 61TR disposed on (in) a substrate 50 and a peripheral circuit wiring structure 70 .

[0049] The substrate 50 may include a cell region MCR, a connection region CON, and a pad region PRC. Figure 4As shown, the connection region CON may be adjacent to (eg, immediately adjacent to) the cell region MCR (in the first horizontal direction X), and the pad region PRC may extend around (eg, surround) the cell region MCR and the connection region CON.

[0050] The substrate 50 may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, and / or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), and / or silicon germanium. The substrate 50 may be provided as a bulk wafer or an epitaxial layer. In some embodiments, the substrate 50 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0051] An active region AC may be defined in the substrate 50 by a device isolation layer 52, and a plurality of first peripheral circuit transistors 60TR and a plurality of second peripheral circuit transistors 61TR may be formed on (in) the active region AC. The first peripheral circuit transistor 60TR may be formed in the cell region MCR and the connection region CON of the substrate 50. The second peripheral circuit transistor 61TR may be formed in the pad region PRC of the substrate 50. The plurality of first peripheral circuit transistors 60TR and the second peripheral circuit transistor 61TR may each include a peripheral circuit gate 60G and a source / drain region 62 disposed in a portion of the substrate 50 on both (e.g., opposite) sides of the peripheral circuit gate 60G.

[0052] The peripheral circuit wiring structure 70 may include a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit wirings 74. The peripheral circuit transistor structure CTR may include a peripheral circuit insulating layer 80 disposed on the substrate 50. The peripheral circuit insulating layer 80 may be disposed on the first peripheral circuit transistor 60TR and the second peripheral circuit transistor 61TR and the peripheral circuit wiring structure 70 (e.g., covering the first peripheral circuit transistor 60TR and the second peripheral circuit transistor 61TR and the peripheral circuit wiring structure 70). Figure 6 The peripheral circuit wiring 74 is shown as including only one layer, but the peripheral circuit wiring 74 may have a multilayer structure including multiple metal layers arranged at different vertical levels. In this article, vertical level, vertical height, etc. may mean the distance from the upper surface of the substrate 50 in the vertical direction Z.

[0053] The first connection structure CNS1 may include first to fourth stop layers STP1 to STP4, first to fourth interlayer insulating layers ILD1 to ILD4, first to fourth connection vias CNP1 to CNP4, first to third connection wirings CNW1 to CNW3, first to fourth dummy vias DCNP1 to DCNP4, first to third dummy wirings DCNW1 to DCNW3, and first connection pads 90.

[0054] The first to fourth stop layers STP1 to STP4 and the first to fourth interlayer insulating layers ILD1 to ILD4 may be alternately stacked sequentially on the substrate 50. For example, the first interlayer insulating layer ILD1 may be disposed on the first stop layer STP1, and the second stop layer STP2 may be disposed on the first interlayer insulating layer ILD1. In the drawings, only four interlayer insulating layers and four stop layers are shown in the first connection structure CNS1, but the inventive concept is not limited thereto, and four or more or less interlayer insulating layers and four or more or less stop layers may be disposed in the first connection structure CNS1. The thickness of the first to fourth interlayer insulating layers ILD1 to ILD4 (i.e., the length in the vertical direction Z) may be greater than the thickness of the first to fourth stop layers STP1 to STP4, respectively. Each of the first to fourth interlayer insulating layers ILD1 to ILD4 may include a material having an etching selectivity with each of the first to fourth stop layers STP1 to STP4. For example, the first to fourth interlayer insulating layers ILD1 to ILD4 may each include silicon oxide, and the first to fourth stop layers STP1 to STP4 may each include silicon nitride.

[0055] The first connection wiring CNW1 to the third connection wiring CNW3 and the first dummy wiring DCNW1 to the third dummy wiring DCNW3 may be respectively arranged in the first interlayer insulating layer ILD1 to the third interlayer insulating layer ILD3. The first connection wiring CNW1 to the third connection wiring CNW3 may be used as an electrical path in terms of the circuit of the semiconductor device 100. On the other hand, the first dummy wiring DCNW1 to the third dummy wiring DCNW3 may be a dummy portion that is not related to the electrical path in terms of the circuit of the semiconductor device 100. For example, the first connection wiring CNW1 to the third connection wiring CNW3 may be connected (e.g., electrically connected) to the first peripheral circuit transistor 60TR and the second peripheral circuit transistor 61TR. On the other hand, the first dummy wiring DCNW1 to the third dummy wiring DCNW3 may be disconnected from the first peripheral circuit transistor 60TR and the second peripheral circuit transistor 61TR (e.g., electrically disconnected, electrically insulated, or electrically negligible from the first peripheral circuit transistor 60TR and the second peripheral circuit transistor 61TR except for the influence caused by the improved hydrogen supply).

[0056] The first connection wiring CNW1 and the first dummy wiring DCNW1 may be disposed in the first interlayer insulating layer ILD1. The second connection wiring CNW2 and the second dummy wiring DCNW2 may be disposed in the second interlayer insulating layer ILD2. The third connection wiring CNW3 and the third dummy wiring DCNW3 may be disposed in the third interlayer insulating layer ILD3. The first connection wiring CNW1 to the third connection wiring CNW3 may be disposed on all the cell regions MCR, the connection regions CON, and the pad regions PRC of the substrate 50. The first connection wiring CNW1 to the third connection wiring CNW3 may overlap with the cell regions MCR, the connection regions CON, and / or the pad regions PRC of the substrate 50 in the vertical direction Z.

[0057] On the other hand, the first to third dummy wirings DCNW1 to DCNW3 may be disposed on the cell region MCR and the connection region CON of the substrate 50. The first to third dummy wirings DCNW1 to DCNW3 may overlap the cell region MCR and / or the connection region CON of the substrate 50 in the vertical direction Z. The first to third dummy wirings DCNW1 to DCNW3 may not be disposed on the pad region PRC of the substrate 50. For example, the first to third dummy wirings DCNW1 to DCNW3 may not overlap the pad region PRC in the vertical direction Z.

[0058] Each of the first to third connection wirings CNW1 to CNW3 may be spaced apart from each of the first to third dummy wirings DCNW1 to DCNW3. That is, each of the first to third connection wirings CNW1 to CNW3 may be configured to be electrically separated (e.g., electrically disconnected or electrically insulated) from each of the first to third dummy wirings DCNW1 to DCNW3. In some embodiments, the first to fourth dummy vias DCNP1 to DCNP4 and the first to third dummy wirings DCNW1 to DCNW3 may not be directly connected to other components (e.g., a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit wirings 74) in the peripheral circuit wiring structure 70.

[0059] The first connection vias CNP1 to the fourth connection vias CNP4 and the first dummy vias DCNP1 to the fourth dummy vias DCNP4 may be respectively arranged in the first interlayer insulating layer ILD1 to the fourth interlayer insulating layer ILD4. The first connection vias CNP1 to the fourth connection vias CNP4 may be arranged on all the cell regions MCR, the connection regions CON and the pad regions PRC of the substrate 50. The first connection vias CNP1 to the fourth connection vias CNP4 may overlap with the cell regions MCR, the connection regions CON and / or the pad regions PRC of the substrate 50 in the vertical direction Z. The first dummy vias DCNP1 to the fourth dummy vias DCNP4 may be arranged on the cell regions MCR and the connection regions CON of the substrate 50. The first dummy vias DCNP1 to the fourth dummy vias DCNP4 may overlap with the cell regions MCR and / or the connection regions CON of the substrate 50 in the vertical direction Z. The first dummy vias DCNP1 to the fourth dummy vias DCNP4 may not be arranged on the pad regions PRC. For example, the first to fourth dummy via holes DCNP1 to DCNP4 may not overlap with the pad region PRC in the vertical direction Z.

[0060] The first connection via CNP1 may extend in the first stop layer STP1 (e.g., penetrate the first stop layer STP1) to connect (e.g., electrically connect) to the peripheral circuit wiring 74, and may extend in the first interlayer insulating layer ILD1 (e.g., be inserted into the first interlayer insulating layer ILD1) to connect (e.g., electrically connect) to the first connection wiring CNW1. The second connection via CNP2 may extend in the second stop layer STP2 (e.g., penetrate the second stop layer STP2) to connect (e.g., electrically connect) to the first connection wiring CNW1, and may extend in the second interlayer insulating layer ILD2 (e.g., be inserted into the second interlayer insulating layer ILD2) to connect (e.g., electrically connect) to the second connection wiring CNW2. The third connection via CNP3 may extend in the third stop layer STP3 (e.g., penetrate the third stop layer STP3) to connect (e.g., electrically connect) to the second connection wiring CNW2, and may extend in the third interlayer insulating layer ILD3 (e.g., be inserted into the third interlayer insulating layer ILD3) to connect (e.g., electrically connect) to the third connection wiring CNW3. The fourth connection via CNP4 may extend in the fourth stop layer STP4 (e.g., penetrate the fourth stop layer STP4) to connect (e.g., electrically connect) to the third connection wiring CNW3, and may extend in the fourth interlayer insulating layer ILD4 (e.g., be inserted into the fourth interlayer insulating layer ILD4) to connect (e.g., electrically connect) to any one (e.g., at least one) of the first connection pads 90.

[0061] The first dummy via DCNP1 may extend in the first stop layer STP1 (e.g., penetrate the first stop layer STP1), may extend in the first interlayer insulating layer ILD1 (e.g., be inserted into the first interlayer insulating layer ILD1), and may be connected to the first dummy wiring DCNW1. The first dummy via DCNP1 may be spaced apart (e.g., disconnected, electrically disconnected, or electrically insulated) from the peripheral circuit wiring 74. The second dummy via DCNP2 may extend in the second stop layer STP2 (e.g., penetrate the second stop layer STP2) to connect to the first dummy wiring DCNW1, and may extend in the second interlayer insulating layer ILD2 (e.g., be inserted into the second interlayer insulating layer ILD2) to connect to the second dummy wiring DCNW2. The third dummy via DCNP3 may extend in the third stop layer STP3 (e.g., penetrate the third stop layer STP3) to connect to the second dummy wiring DCNW2, and may extend in the third interlayer insulating layer ILD3 (e.g., be inserted into the third interlayer insulating layer ILD3) to connect to the third dummy wiring DCNW3. The fourth dummy via DCNP4 may extend in the fourth stop layer STP4 (e.g., penetrate the fourth stop layer STP4) to connect to the third dummy wiring DCNW3, and may extend in the fourth interlayer insulating layer ILD4 (e.g., be inserted into the fourth interlayer insulating layer ILD4) to connect to any one (e.g., at least one) of the first connection pads 90.

[0062] The first connection wiring CNW1 to the third connection wiring CNW3 and the first connection via CNP1 to the fourth connection via CNP4 may each include, for example, a metal and / or a metal nitride. The metal may include, for example, tungsten, copper, aluminum, titanium, tantalum and / or cobalt. The first dummy wiring DCNW1 to the third dummy wiring DCNW3 and the first dummy via DCNP1 to the fourth dummy via DCNP4 may respectively include, for example, the same material as the first connection wiring CNW1 to the third connection wiring CNW3 and the first connection via CNP1 to the fourth connection via CNP4. In some embodiments, the first dummy wiring DCNW1 to the third dummy wiring DCNW3 and the first dummy via DCNP1 to the fourth dummy via DCNP4 may respectively include, for example, a metal material having a hydrogen diffusion rate greater than the hydrogen diffusion rate of the first stop layer STP1 to the fourth stop layer STP4. For example, the first dummy wiring DCNW1 to the third dummy wiring DCNW3 and the first dummy via DCNP1 to the fourth dummy via DCNP4 may each include tungsten and / or copper.

[0063] The first connection pads 90 may be disposed in the fourth interlayer insulating layer ILD4. An upper surface of each first connection pad 90 may be coplanar with an upper surface of the fourth interlayer insulating layer ILD4. Each first connection pad 90 may be connected to the fourth connection via CNP4 and / or the fourth dummy via DCNP4.

[0064] Reference Fig. 7A and Figure 7B , the first dummy via DCNP1 may have a first width W1. The first width W1 may be the width of the first dummy via DCNP1 in the first horizontal direction X or the second horizontal direction Y. The first connection via CNP1 may have a second width W2. The second width W2 may be the width of the first connection via CNP1 in the first horizontal direction X or the second horizontal direction Y. The first width W1 may be substantially the same as the second width W2. The width of each of the second to fourth dummy vias DCNP2 to DCNP4 in the first horizontal direction X or the second horizontal direction Y may also be substantially the same as the first width W1. The width of each of the second to fourth connection vias CNP2 to CNP4 in the first horizontal direction X or the second horizontal direction Y may also be substantially the same as the second width W2.

[0065] The vertical level of the upper surface DCNW1T of the first dummy wiring DCNW1 may be substantially the same as the vertical level of the lower surface STP2B of the second stop layer STP2. For example, the upper surface DCNW1T of the first dummy wiring DCNW1 may be coplanar with the lower surface STP2B of the second stop layer STP2. The vertical level of the upper surface DCNW2T of the second dummy wiring DCNW2 may be substantially the same as the vertical level of the lower surface STP3B of the third stop layer STP3. For example, the upper surface DCNW2T of the second dummy wiring DCNW2 may be coplanar with the lower surface STP3B of the third stop layer STP3. The vertical level of the upper surface DCNW3T of the third dummy wiring DCNW3 may be substantially the same as the vertical level of the lower surface STP4B of the fourth stop layer STP4. For example, the upper surface DCNW3T of the third dummy wiring DCNW3 may be coplanar with the lower surface STP4B of the fourth stop layer STP4.

[0066] Refer again Figures 3 to 6 , the cell structure CS may be disposed on the peripheral circuit structure PS. The cell structure CS may include a second connection structure CNS2 and a cell array structure CAS on the second connection structure CNS2.

[0067] The second connection structure CNS2 may include second connection pads 92 , fifth to seventh interlayer insulating layers ILD5 to ILD7 , fifth and sixth stop layers STP5 and STP6 , fourth and fifth connection wirings CNW4 and CNW5 , and fifth to seventh connection vias CNP5 to CNP7 .

[0068] The fifth interlayer insulating layer ILD5 may be disposed on the fourth interlayer insulating layer ILD4. The second connection pads 92 may be disposed on the lower portion of the fifth interlayer insulating layer ILD5. The second connection pads 92 may be connected (e.g., electrically connected) to the first connection pads 90, respectively. The fifth interlayer insulating layer ILD5 may be in contact with the fourth interlayer insulating layer ILD4. The peripheral circuit structure PS and the cell structure CS may be electrically connected and bonded to each other through the first connection pads 90 and the second connection pads 92 and the fourth interlayer insulating layer ILD4 and the fifth interlayer insulating layer ILD5.

[0069] The fifth stop layer STP5 and the sixth stop layer STP6 and the sixth interlayer insulating layer ILD6 and the seventh interlayer insulating layer ILD7 may be alternately stacked sequentially on the fifth interlayer insulating layer ILD5. For example, the fifth stop layer STP5 may be disposed on the fifth interlayer insulating layer ILD5, and the sixth interlayer insulating layer ILD6 may be disposed on the fifth stop layer STP5. The sixth stop layer STP6 may be disposed on the sixth interlayer insulating layer ILD6, and the seventh interlayer insulating layer ILD7 may be disposed on the sixth stop layer STP6. The fifth interlayer insulating layer ILD5 to the seventh interlayer insulating layer ILD7 may include, for example, silicon oxide, and the fifth stop layer STP5 and the sixth stop layer STP6 may include, for example, silicon nitride.

[0070] The fourth connection wiring CNW4 and the fifth connection wiring CNW5 may be disposed in the sixth interlayer insulating layer ILD6 and the seventh interlayer insulating layer ILD7, respectively. The fourth connection wiring CNW4 may be disposed in a lower portion of the sixth interlayer insulating layer ILD6. The fifth connection wiring CNW5 may be disposed in a lower portion of the seventh interlayer insulating layer ILD7.

[0071] The fifth connection via CNP5 may extend in the fifth stop layer STP5 (e.g., penetrate the fifth stop layer STP5) to connect (e.g., electrically connect) to the fourth connection wiring CNW4. The fifth connection via CNP5 may extend in the fifth interlayer insulating layer ILD5 (e.g., be inserted into the fifth interlayer insulating layer ILD5) to connect to any one (e.g., at least one) of the second connection pads 92. The sixth connection via CNP6 may extend in the sixth stop layer STP6 (e.g., penetrate the sixth stop layer STP6) to connect (e.g., electrically connect) to the fifth connection wiring CNW5. The sixth connection via CNP6 may extend in the sixth interlayer insulating layer ILD6 (e.g., be inserted into the sixth interlayer insulating layer ILD6) to connect (e.g., electrically connect) to the fourth connection wiring CNW4. The seventh connection via CNP7 may extend in the seventh interlayer insulating layer ILD7 (e.g., be inserted into the seventh interlayer insulating layer ILD7) to connect (e.g., electrically connect) to the fifth connection wiring CNW5.

[0072] In the accompanying drawings, only three interlayer insulating layers, two stop layers, two connection wirings and three connection vias are shown in the second connection structure CNS2, but the inventive concept is not limited to this number, and three or more or less interlayer insulating layers, two or more or less stop layers, two or more or less connection wirings, and three or more or less connection vias can be set in the second connection structure CNS2.

[0073] Reference Figure 7C , the vertical level of the lower surface CNW4B of the fourth connection wiring CNW4 may be substantially the same as the vertical level of the upper surface STP5T of the fifth stop layer STP5. For example, the lower surface CNW4B of the fourth connection wiring CNW4 may be coplanar with the upper surface STP5T of the fifth stop layer STP5. The vertical level of the lower surface CNW5B of the fifth connection wiring CNW5 may be substantially the same as the vertical level of the upper surface STP6T of the sixth stop layer STP6. For example, the lower surface CNW5B of the fifth connection wiring CNW5 may be coplanar with the upper surface STP6T of the sixth stop layer STP6.

[0074] The structure having the first to third connection wirings CNW1 to CNW3 and the first to fourth connection vias CNP1 to CNP4 may be referred to as a first wiring structure. The structure having the first to third dummy wirings DCNW1 to DCNW3 and the first to fourth dummy vias DCNP1 to DCNP4 may be referred to as a dummy structure. The structure having the fourth connection wiring CNW4 and the fifth connection wiring CNW5 and the fifth to seventh connection vias CNP5 to CNP7 may be referred to as a second wiring structure.

[0075] Refer again Figures 3 to 6 , the cell region MCR may be a region in which a memory block BLK (among a plurality of memory cell blocks BLK1, BLK2, ..., BLKn) including a plurality of memory cell strings extending in a vertical direction Z is disposed. A common source layer 110, a gate electrode 120, and a channel structure 130 extending in the gate electrode 120 (e.g., penetrating the gate electrode 120) and connected (e.g., electrically connected) to the common source layer 110 along the vertical direction Z may be disposed in the cell region MCR. An extension portion 120E and a pad portion 120P connected to the gate electrode 120, and a first vertical conductive structure CP1 extending in the extension portion 120E and the pad portion 120P (e.g., penetrating the extension portion 120E and the pad portion 120P) and electrically connected to the pad portion 120P may be disposed in the connection region CON. The first vertical conductive structure CP1 may be connected (e.g., electrically connected) to any one (e.g., at least one) of a plurality of seventh connection vias CNP7. A second vertical conductive structure CP2 extending in the vertical direction Z and electrically connected to the peripheral circuit wiring structure 70 may be disposed in the pad region PRC. The second vertical conductive structure CP2 may be connected (e.g., electrically connected) to any one (e.g., at least one) of a plurality of seventh connection vias CNP7. The second vertical conductive structure CP2 may be electrically connected to any one (e.g., at least one) of the second peripheral circuit transistors 61TR through the seventh connection vias CNP7.

[0076] The unit structure CS may include a first surface CS_1 connected to (e.g., in contact with) the peripheral circuit structure PS and a second surface CS_2 opposite to the first surface CS_1. In the accompanying drawings, the first surface CS_1 of the unit structure CS is shown as being disposed on the lower side of the unit structure CS, and the second surface CS_2 of the unit structure CS is shown as being disposed on the upper side of the unit structure CS. Here, for convenience, as shown in the accompanying drawings, the first surface CS_1 disposed close to the unit structure CS is defined as being disposed at a lower vertical level, and the second surface CS_2 disposed close to the unit structure CS is defined as being disposed at a higher vertical level.

[0077] The gate electrodes 120 may be disposed to be spaced apart from each other in the vertical direction Z in the cell region MCR, and the gate electrodes 120 may be alternately disposed with the mold insulating layer 122. The gate electrode 120 may extend into the connection region CON, and a portion of the gate electrode 120 disposed in the connection region CON may be referred to as an extension 120E. The extension 120E may have a horizontal length that increases (discretely) in a direction toward the second surface CS_2 of the cell structure CS (i.e., in an upward direction in the drawings). The extension 120E may have a stepped shape (e.g., Figure 6The pad portions 120P may each have a thickness in the vertical direction Z greater than that of each extension portion 120E.

[0078] Although not shown, the gate electrode 120 may include a buried conductive layer and a conductive barrier layer extending around the upper surface, lower surface, and side surface of the buried conductive layer (e.g., surrounding the upper surface, lower surface, and side surface of the buried conductive layer). For example, the buried conductive layer may include a metal (e.g., tungsten, nickel, cobalt, tantalum, etc.), a metal silicide (e.g., tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, etc.), doped polysilicon, and / or a combination thereof. In some embodiments, the conductive barrier layer may include, for example, titanium nitride, tantalum nitride, tungsten nitride, and / or a combination thereof.

[0079] In some embodiments, the gate electrode 120 may be connected to a ground selection line GSL, a plurality of word lines WL (WL1, WL2, . . . , WLn-1, WLn), and at least one string selection line SSL (see FIG. 1 ) in a memory cell string MS (among a plurality of memory cell strings MS) (e.g., constituting the memory cell string MS). Figure 2 ) corresponds. For example, the topmost gate electrode 120 may be used as a ground selection line GSL, the bottom two gate electrodes 120 may be used as string selection lines SSL, and the remaining gate electrodes 120 may be used as a plurality of word lines WL. Therefore, a memory cell string MS in which a ground selection transistor GST, a string selection transistor SST, and memory cell transistors MC1, MC2, ..., MCn-1, MCn between the ground selection transistor GST and the string selection transistor SST are connected in series (e.g., electrically connected) may be provided. In some embodiments, at least one gate electrode 120 may be used as a dummy word line, but the inventive concept is not limited thereto.

[0080] The stack separation insulating layer WLI may be disposed in the stack separation opening WLH extending through the gate electrode 120 and the mold insulating layer 122 in the vertical direction Z. Although not shown, the stack separation insulating layer WLI may have an upper surface disposed at a higher vertical level than the uppermost gate electrode 120 and may protrude upward relative to the uppermost gate electrode 120. Figure 5 As shown, the gate electrode 120 disposed between a pair of (adjacent) stack separation openings WLH may form one memory cell block BLK (among a plurality of memory cell blocks BLK1, BLK2, ..., BLKn). In addition, within one memory cell block BLK, at least one gate electrode 120 (e.g., the lowest gate electrode 120) may be divided into two gate electrodes 120 by the string separation opening SSLH. The string separation insulating layer SSLI may be disposed in the string separation opening SSLH.

[0081] The stacked insulating layer 124 may be disposed on the gate electrode 120, the extension 120E, and the pad portion 120P in the connection region CON and the pad region PRC (e.g., may extend around the gate electrode 120, the extension 120E, and the pad portion 120P or may surround the gate electrode 120, the extension 120E, and the pad portion 120P). In a plan view, the stacked insulating layer 124 may be disposed to extend around the gate electrode 120 (e.g., surround the gate electrode 120). In the pad region PRC, the upper surface of the stacked insulating layer 124 may be at the same vertical level as the upper surface of the uppermost mold insulating layer 122.

[0082] The channel structure 130 may include a first end 130x disposed closer to the peripheral circuit structure PS and a second end 130y opposite to the first end 130x. In some embodiments, the channel structure 130 may have an inclined sidewall so that the width of the first end 130x (in the first horizontal direction X and / or the second horizontal direction Y) is greater than the width of the second end 130y (in the first horizontal direction X and / or the second horizontal direction Y). The bit line BL may be electrically connected to the first end 130x of the channel structure 130 through the bit line contact BLC, and the common source layer 110 may be connected (e.g., electrically connected) to the second end 130y of the channel structure 130. The bit line BL may be connected (e.g., electrically connected) to any one (e.g., at least one) of the plurality of seventh connection vias CNP7.

[0083] The channel structure 130 may extend in the gate electrode 120 and the molded insulating layer 122 (e.g., penetrate the gate electrode 120 and the molded insulating layer 122) to be disposed in a channel hole 130H extending in the vertical direction Z. The channel structure 130 may include a gate insulating layer 132, a channel layer 134, a buried insulating layer 136, and a drain region 138. The channel layer 134 may have, for example, a cylindrical shape, and the gate insulating layer 132 may be disposed on an outer wall (e.g., an outer side wall) of the channel layer 134, and the buried insulating layer 136 may be disposed on an inner wall (e.g., an inner side wall) of the channel layer 134. The gate insulating layer 132 may not be disposed on the uppermost surface of the channel layer 134 (e.g., on an upper surface of the channel layer 134 disposed at the second end 130y of the channel structure 130).

[0084] Although not shown, the gate insulating layer 132 may have a structure sequentially including a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer on an outer wall (e.g., an outer sidewall) of the channel layer 134. The relative thicknesses of the tunneling dielectric layer, the charge storage layer, and the blocking dielectric layer in (e.g., constituting) the gate insulating layer 132 may be modified in various ways.

[0085] The tunneling dielectric layer may include, for example, silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer may be a region that stores electrons that pass through the tunneling dielectric layer from the channel layer 134, and may include, for example, silicon nitride, boron nitride, silicon boron nitride, and / or polysilicon doped with impurities. The blocking dielectric layer may include, for example, silicon oxide, silicon nitride, and / or a metal oxide having a dielectric constant greater than that of silicon oxide. The metal oxide may include, for example, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and / or a combination thereof.

[0086] The common source layer 110 may be disposed on the uppermost mold insulating layer 122. The common source layer 110 may be conformally formed to be connected (e.g., electrically connected) to the second end 130y of the channel structure 130. Although not shown, the common source layer 110 may be on the upper surface of the stacked separation insulating layer WLI (e.g., covering the upper surface of the stacked separation insulating layer WLI). In a plan view, the common source layer 110 may be disposed on the entire cell region MCR. The common source layer 110 may not be disposed on the connection region CON.

[0087] The vertical level of the upper surface of a portion of the common source layer 110 (e.g., the portion of the common source layer 110 that does not contact the second end 130y of the channel structure 130) may be different from the vertical level of the upper surface of other portions of the common source layer 110 that contact the second end 130y of the channel structure 130.

[0088] In some embodiments, the common source layer 110 may be disposed on (e.g., conformally covers) the upper surface of the channel layer 134 and the upper surface of the gate insulating layer 132. For example, the gate insulating layer 132 may be disposed at a lower vertical level than the upper surface of the channel layer 134, and thus, a portion of the upper surface and sidewall of the channel layer 134 may be covered by the common source layer 110, so that a sufficient contact area between the channel layer 134 and the common source layer 110 is ensured.

[0089] In some embodiments, the common source layer 110 may include, for example, polysilicon, and a laser annealing process may be performed on the common source layer 110 to have a relatively large grain size and / or relatively good crystal quality.

[0090] The first vertical conductive structure CP1 disposed in the connection region CON may extend in the extension portion 120E and the pad portion 120P (e.g., penetrate the extension portion 120E and the pad portion 120P). The insulating pattern 126 may be formed at a position vertically overlapping the pad portion 120P. The insulating pattern 126 may be connected to the first vertical conductive structure CP1 and may be disposed between the first vertical conductive structure CP1 and the extension portion 120E.

[0091] In some embodiments, the first end CP1x of the first vertical conductive structure CP1 may be disposed closer to the peripheral circuit structure PS, and the second end CP1y of the first vertical conductive structure CP1 may be disposed opposite to the first end CP1x. The first vertical conductive structure CP1 may have an inclined sidewall so that the width of the first end CP1x (in the first horizontal direction X and / or the second horizontal direction Y) is greater than the width of the second end CP1y (in the first horizontal direction X and / or the second horizontal direction Y). The second end CP1y of the first vertical conductive structure CP1 may extend in the uppermost molded insulating layer 122 (e.g., penetrate the uppermost molded insulating layer 122), and the first upper insulating layer 161 may be on the upper surface of the second end CP1y of the first vertical conductive structure CP1 (e.g., cover the upper surface of the second end CP1y of the first vertical conductive structure CP1).

[0092] Although not shown, in some embodiments, the first vertical conductive structure CP1 may include a conductive buried layer and a barrier layer of a smaller thickness extending around the upper surface and sidewalls of the conductive buried layer (e.g., surrounding the upper surface and sidewalls of the conductive buried layer). For example, the conductive buried layer may include, for example, a metal (e.g., tungsten, nickel, cobalt, tantalum, etc.), a metal silicide (e.g., tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, etc.), doped polysilicon, and / or a combination thereof. The barrier layer may include, for example, titanium nitride, tantalum nitride, tungsten nitride, and / or a combination thereof.

[0093] The second vertical conductive structure CP2 may be disposed in the pad region PRC to extend in the stacked insulating layer 124 (e.g., penetrate the stacked insulating layer 124). The third end CP2x of the second vertical conductive structure CP2 may be disposed closer to the peripheral circuit structure PS, and the fourth end CP2y of the second vertical conductive structure CP2 may be disposed opposite to the third end CP2x. The second vertical conductive structure CP2 may have an inclined sidewall so that the width of the third end CP2x (in the first horizontal direction X and / or the second horizontal direction Y) is greater than the width of the fourth end CP2y (in the first horizontal direction X and / or the second horizontal direction Y). The fourth end CP2y of the second vertical conductive structure CP2 may extend in the uppermost molded insulating layer 122 (e.g., penetrate the uppermost molded insulating layer 122). The first upper insulating layer 161 may be disposed on the upper surface of the fourth end CP2y of the second vertical conductive structure CP2 (e.g., cover the upper surface of the fourth end CP2y of the second vertical conductive structure CP2).

[0094] The bit line BL and the first and second vertical conductive structures CP1 and CP2 may be electrically connected to the peripheral circuit structure PS through the first and second connection pads 90 and 92 .

[0095] The second upper insulating layer 162 may be disposed on the first upper insulating layer 161. The second upper insulating layer 162 may cover the first upper insulating layer 161. According to some embodiments, the second upper insulating layer 162 may be omitted.

[0096] A rear via 164 extending in the second upper insulating layer 162 (e.g., penetrating the second upper insulating layer 162) may be provided. The rear via 164 may also extend in the vertical direction Z to be (partially) provided in (e.g., inserted into) the first upper insulating layer 161. The rear vias 164 may be connected (e.g., electrically connected) to the plurality of second vertical conductive structures CP2, respectively.

[0097] The rear pad 166 may be disposed on the second upper insulating layer 162. The rear pad 166 may be connected (eg, electrically connected) to the rear via 164. The passivation layer 168 may be disposed on the second upper insulating layer 162, and an opening OP of the passivation layer 168 may expose at least a portion of an upper surface of the rear pad 166.

[0098] The process of manufacturing the semiconductor device 100 may include a process of injecting hydrogen from the second surface CS_2 of the cell structure CS of the semiconductor device 100. The reason for injecting hydrogen is to improve the operation speed characteristics and reliability of the semiconductor device 100 by eliminating dangling bond defects on the surface of the substrate 50.

[0099] In particular, when the pattern of the semiconductor device 100 is miniaturized and its wiring is stacked, the dark current problem may become worse. The dark current may mean charges accumulated without applying a voltage, and may be generated by defects or dangling bonds present in the substrate 50.

[0100] A dangling bond is a defect that may occur on the surface of substrate 50 when substrate 50 is processed by an oxidation process or an etching process, and may mean a bonding state (-Si-O) and (-Si-) in which the outermost electrons of atoms on the surface of substrate 50 are not completely bonded and are separated (e.g., cut off).

[0101] When electrons are separated from dangling bonds on the surface of substrate 50, various parts of semiconductor device 100 may be in a state where charge may be generated even without applying voltage. When there are a large number of dangling bonds on substrate 50, a large amount of charge may be generated even without applying voltage, and semiconductor device 100 may react as if voltage is applied, and may exhibit abnormal behavior such as noise or dark current. Therefore, it is necessary to remove the dangling bond defects of substrate 50. At this time, the dangling bond defects can be solved by combining with hydrogen. Therefore, it is necessary to fully supply hydrogen into substrate 50 to remove the dangling bond defects on the surface (e.g., upper surface) of substrate 50.

[0102] When hydrogen is injected from the second surface CS_2 of the cell structure CS of the semiconductor device 100, hydrogen can easily reach the substrate 50 (in the pad region PRC) through the second vertical conductive structure CP2, the first connection vias CNP1 to the seventh connection vias CNP7, and the first connection wirings CNW1 to the fifth connection wirings CNW5. On the other hand, in the cell region MCR and the connection region CON, due to the insufficient number of the first connection vias CNP1 to the seventh connection vias CNP7 and the first connection wirings CNW1 to the fifth connection wirings CNW5, the hydrogen transmitted from the first vertical conductive structure CP1 may not (sufficiently) reach the substrate 50. Specifically, the first stop layer STP1 to the sixth stop layer STP6 may each include a material having a low hydrogen diffusion rate. In this case, there is no (or less) medium to diffuse hydrogen through the first stop layer STP1 to the sixth stop layer STP6, so that hydrogen may not (sufficiently) reach the substrate 50. As a result, a problem that the hydrogen concentration in the cell region MCR and the connection region CON is less than the hydrogen concentration in the pad region PRC may occur.

[0103] The peripheral circuit structure PS of the semiconductor device 100 according to the inventive concept of the present disclosure may include the first dummy vias DCNP1 to the fourth dummy vias DCNP4 and the first dummy wirings DCNW1 to the third dummy wirings DCNW3 in the cell region MCR and the connection region CON. The first dummy vias DCNP1 to the fourth dummy vias DCNP4 and the first dummy wirings DCNW1 to the third dummy wirings DCNW3 may each include a material having a greater hydrogen diffusion rate than the first stop layer STP1 to the sixth stop layer STP6. Therefore, hydrogen may be better (more easily) supplied to the substrate 50 in the cell region MCR and the connection region CON. That is, the concentration of hydrogen supplied to the substrate 50 may be uniform in the cell region MCR, the connection region CON, and the pad region PCR. Due to the above reasons, the dangling bond defects (in the cell area MCR, the connection area CON and the pad area PCR) can be effectively solved (through the first dummy via DCNP1 to the fourth dummy via DCNP4 and the first dummy wiring DCNW1 to the third dummy wiring DCNW3), and therefore, the electrical characteristics and reliability of the semiconductor device 100 can be improved.

[0104] Fig. 8A yes Figure 6 Magnified view of part PP1. Figure 8B yes Figure 6 In the following, the reference numerals may be omitted. Figures 3 to 7C Those described are redundant, and only the differences may be described in detail.

[0105] Reference Fig. 8A and Figure 8B, the second dummy via hole DCNP2 may have a third width W3. The third dummy via hole DCNP3 may have a fourth width W4. The fourth dummy via hole DCNP4 may have a fifth width W5. The second connection via hole CNP2 may have a sixth width W6. The third connection via hole CNP3 may have a seventh width W7. The fourth connection via hole CNP4 may have an eighth width W8. The first width W1 to the eighth width W8 may be widths correspondingly arranged in the first horizontal direction X or the second horizontal direction Y, respectively.

[0106] The third width W3, the fourth width W4, and the fifth width W5 may be the same as or different from the first width W1. The sixth width W6, the seventh width W7, and the eighth width W8 may be the same as or different from the second width W2. The first to eighth widths W1 to W8 may be the same as or different from each other.

[0107] In some embodiments, each of the plurality of first connection vias CNP1 may have the same width or different widths. This may also be applied to the second connection vias CNP2 to the fourth connection vias CNP4 and the first dummy vias DCNP1 to the fourth dummy vias DCNP4. That is, the widths of the respective dummy vias may be the same or different from each other, and the widths of the respective connection vias may be the same or different from each other.

[0108] According to the inventive concept of the present disclosure, the first width W1, the third width W3, the fourth width W4 and the fifth width W5 of the first dummy via DCNP1 to the fourth dummy via DCNP4 and the second width W2, the sixth width W6, the seventh width W7 and the eighth width W8 of the first connection via CNP1 to the fourth connection via CNP4 may be the same or different from each other. Thus, the width of each of the first dummy via DCNP1 to the fourth dummy via DCNP4 and the first connection via CNP1 to the fourth connection via CNP4 may be increased in the portion where the hydrogen concentration is insufficient, and may be reduced in the portion where the hydrogen concentration is sufficient to meet the process margin (e.g., excessive). The width of each of the first dummy via DCNP1 to the fourth dummy via DCNP4 and the first connection via CNP1 to the fourth connection via CNP4 may be selectively adjusted only in the portion where the hydrogen concentration is insufficient, and therefore, the semiconductor device 100 may not require additional space. Thus, the integration of the semiconductor device 100 may be improved.

[0109] Fig. 9 According to some embodiments, Figure 5 Cross-sectional views taken along lines B1-B1′ and B2-B2′. Fig.10 yes Fig. 9 Magnified view of a portion of PP4. Fig. 9 The semiconductor device 101 in FIG. Figures 1 to 8BIn the following, the semiconductor device 100 may be omitted. Figures 3 to 7C Those described are redundant, and only the differences may be described in detail.

[0110] Reference Fig. 9 and Fig.10 , at least one of the first to fourth dummy vias DCNP1 to DCNP4 may be connected to a corresponding one of the first to third connection wirings CNW1 to CNW3. Fig.10 As shown, the second dummy via DCNP2 may be connected to the second connection wiring CNW2. However, this corresponds only to an embodiment, and the first dummy via DCNP1 may be connected to the first connection wiring CNW1, for example. This may vary depending on the design of the semiconductor device 101 to be implemented. Fig.10 In the embodiment of the present invention, the second dummy via DCNP2 may be connected to the first dummy wiring DCNW1, and the first dummy wiring DCNW1 may be connected to the first dummy via DCNP1. At this time, the first dummy via DCNP1 may be separated from the peripheral circuit wiring 74. Therefore, the second dummy via DCNP2, the first dummy wiring DCNW1, and the first dummy via DCNP1 may be electrically connected to the first peripheral circuit transistor 60TR through the second connection wiring CNW2. However, even in this case, the second dummy via DCNP2, the first dummy wiring DCNW1, and the first dummy via DCNP1 may not change the electrical path through the second connection wiring CNW2 as expected in the design of the semiconductor device 101. That is, the first to fourth dummy vias DCNP1 to DCNP4 and the first to third dummy wirings DCNW1 to DCNW3 (e.g., the second dummy via DCNP2, the first dummy wiring DCNW1, and the first dummy via DCNP1) may be connected only to the first to third connection wirings CNW1 to CNW3 (e.g., the second connection wiring CNW2), and may not be directly connected to other components (e.g., the plurality of peripheral circuit contacts 72 and the plurality of peripheral circuit wirings 74) in the peripheral circuit wiring structure 70. For example, the second dummy vias DCNP2, the first dummy wiring DCNW1, and the first dummy vias DCNP1 may be electrically negligible for the operation of the semiconductor device 101, except for the effect caused by the improved hydrogen supply through the second dummy vias DCNP2, the first dummy wiring DCNW1, and the first dummy vias DCNP1 (improved reliability or performance of the semiconductor device 101).

[0111] Figures 11 to 15 is a diagram showing a method of manufacturing a semiconductor device according to some embodiments, and specifically along the Figure 5 Cross-sectional views taken along lines B1-B1′ and B2-B2′.

[0112] Reference Fig.11 , a carrier substrate 310 including a cell region MCR, a connection region CON, and a pad region PRC may be provided. The connection region CON may be spaced apart from (or adjacent to) the cell region MCR in the first horizontal direction X, and the pad region PRC may extend around (e.g., surround) the cell region MCR and the connection region CON.

[0113] In some embodiments, the carrier substrate 310 may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and / or mixtures thereof.

[0114] On the carrier substrate 310, a gate electrode 120 and a mold insulating layer 122 may be formed in the cell region MCR and the connection region CON, and an extension portion 120E and a pad portion 120P connected to the gate electrode 120 may be formed in the connection region CON. In addition, a channel structure 130 extending in the gate electrode 120 (e.g., penetrating the gate electrode 120) along a vertical direction Z and a bit line BL connected (e.g., electrically connected) to the channel structure 130 may be formed in the cell region MCR. In addition, a stacked insulating layer 124 may be formed on (e.g., extending around or surrounding the gate electrode 120, the extension portion 120E, and the pad portion 120P) the gate electrode 120, the extension portion 120E, and the pad portion 120P in the connection region CON and the pad region PRC. In addition, a first vertical conductive structure CP1 extending in the extension portion 120E and the pad portion 120P along the vertical direction Z (for example, penetrating the extension portion 120E and the pad portion 120P) may be formed in the connection area CON, and a second vertical conductive structure CP2 extending in the stacked insulation layer 124 along the vertical direction Z (for example, penetrating the stacked insulation layer 124) may be formed in the pad area PRC.

[0115] The channel structure 130, the first vertical conductive structure CP1, and the second vertical conductive structure CP2 may further extend in the vertical direction Z to be inserted into the carrier substrate 310. For example, the channel structure 130, the first vertical conductive structure CP1, and the second vertical conductive structure CP2 may at least partially penetrate the carrier substrate 310. In addition, a seventh interlayer insulating layer ILD7 may be formed on the bit line BL, the first vertical conductive structure CP1, and the second vertical conductive structure CP2. A seventh connection via CNP7 and a fifth connection wiring CNW5 electrically connected to the bit line BL, the first vertical conductive structure CP1, and the second vertical conductive structure CP2 may be formed. A fifth stop layer STP5 and a sixth stop layer STP6, a fifth interlayer insulating layer ILD5 and a sixth interlayer insulating layer ILD6, a fourth connection wiring CNW4, a fifth connection via CNP5 and a sixth connection via CNP6, and a second connection pad 92 may be formed on the seventh interlayer insulating layer ILD7.

[0116] Although not shown, a stack separation opening WLH extending in the gate electrode 120 and the mold insulating layer 122 (e.g., penetrating the gate electrode 120 and the mold insulating layer 122) along the vertical direction Z may be formed, and a stack separation insulating layer WLI may be formed within the stack separation opening WLH. The stack separation insulating layer WLI may further extend in the vertical direction Z to be inserted into the carrier substrate 310. For example, the stack separation insulating layer WLI may at least partially penetrate the carrier substrate 310.

[0117] In some embodiments, in the process of forming the channel structure 130, the first end 130x of the channel structure 130 can be set at a higher vertical level than the second end 130y, and the second end 130y can be formed to extend in the carrier substrate 310 (e.g., at least partially penetrate the carrier substrate 310).

[0118] In some embodiments, in the process of forming the first vertical conductive structure CP1, the first end CP1x of the first vertical conductive structure CP1 can be formed to have a width greater than a width of the second end CP1y of the first vertical conductive structure CP1, and the second end CP1y of the first vertical conductive structure CP1 can be formed to extend in the carrier substrate 310 (for example, at least partially penetrate the carrier substrate 310).

[0119] In some embodiments, in the process of forming the second vertical conductive structure CP2, the third end CP2x of the second vertical conductive structure CP2 can be formed to have a width greater than the fourth end CP2y of the second vertical conductive structure CP2, and the fourth end CP2y of the second vertical conductive structure CP2 can be formed to extend in the carrier substrate 310 (for example, at least partially penetrate the carrier substrate 310).

[0120] Reference Fig.12 , a peripheral circuit structure PS can be prepared. The peripheral circuit structure PS may include a peripheral circuit transistor structure CTR and a first connection structure CNS1 on the peripheral circuit transistor structure CTR. The peripheral circuit transistor structure CTR may include a substrate 50, a first peripheral circuit transistor 60TR and a second peripheral circuit transistor 61TR disposed in (on) the substrate 50, and a peripheral circuit wiring structure 70. An active area AC may be defined in the substrate 50 by a device isolation layer 52, and a plurality of first peripheral circuit transistors 60TR and a plurality of second peripheral circuit transistors 61TR may be formed in (on) the active area AC. The plurality of first peripheral circuit transistors 60TR and the second peripheral circuit transistor 61TR may each include a peripheral circuit gate 60G and a source / drain region 62 disposed in portions of the substrate 50 on both (e.g., opposite) sides of the peripheral circuit gate 60G. The first connection structure CNS1 may include a first connection structure CNS1 formed in reference to Figures 3 to 6 The components included in the first connection structure CNS1 are described.

[0121] At this time, when the first to third dummy wirings DCNW1 to DCNW3 and the first to fourth dummy vias DCNP1 to DCNP4 include the same material as the first to third connection wirings CNW1 to CNW3 and the first to fourth connection vias CNP1 to CNP4, no additional process is required and only the layout may be changed. Therefore, the process may be simplified.

[0122] Thereafter, the peripheral circuit structure PS may be attached to the cell structure CS. The peripheral circuit structure PS and the cell structure CS may be attached to each other via the first and second connection pads 90 and 92, the fourth and fifth interlayer insulating layers ILD4 and ILD5 by using a metal oxide hybrid bonding method, but are not limited thereto.

[0123] Thereafter, the structure in which the peripheral circuit structure PS and the cell structure CS are attached to each other may be flipped so that the carrier substrate 310 faces upward. The carrier substrate 310 may be removed by, for example, a grinding process and a subsequent etching process. The second end 130y of the channel structure 130 may be exposed. Likewise, when the carrier substrate 310 is removed, the second end CP1y of the first vertical conductive structure CP1 and the fourth end CP2y of the second vertical conductive structure CP2 may be exposed. Although not shown, when the carrier substrate 310 is removed, the upper portion of the stacked separation insulating layer WLI may also be exposed.

[0124] Reference Fig.13, the upper surface of the channel layer 134 can be exposed by removing the portion of the gate insulating layer 132 exposed at the second end 130y of the channel structure 130. In some embodiments, the upper side of the gate insulating layer 132 can be further removed so that the upper surface of the gate insulating layer 132 is disposed at a lower level than the upper surface of the channel layer 134, and a portion of the upper surface and sidewalls of the channel layer 134 are exposed.

[0125] Thereafter, a tilted ion implantation process (TIIP) may be performed on the channel layer 134. TIIP means performing an ion implantation process at an angle tilted relative to the vertical direction Z. In TIIP, impurities of a first conductivity type may be implanted into the channel layer 134. For example, the first conductivity type may include a P type, but is not limited thereto.

[0126] Reference Fig.14 , a preliminary common source layer 110p may be formed on the cell region MCR, the connection region CON, and the pad region PRC. The preliminary common source layer 110p may include polysilicon.

[0127] In the cell region MCR, a preliminary common source layer 110p may be conformally formed on the exposed upper surfaces of the uppermost mold insulation layer 122 and the channel layer 134 among the mold insulation layers 122. The preliminary common source layer 110p may be formed on the stack insulation layer 124, the first vertical conductive structure CP1, and the second vertical conductive structure CP2 in the connection region CON and the pad region PRC.

[0128] Reference Fig.15 , an ion implantation process may be performed on the preliminary common source layer 110p by using a photomask layer. Thereafter, the preliminary common source layer 110p may be removed from the connection region CON and the pad region PRC. Thus, the common source layer 110 may be formed on the cell region MCR.

[0129] Thereafter, a laser annealing process may be performed on the common source layer 110. In some embodiments, the laser annealing process may be performed to improve the crystallinity of the common source layer 110 disposed in the cell region MCR, increase the grain size of the common source layer 110, or reduce the resistance (and / or resistivity) of the common source layer 110. In some embodiments, the laser annealing process may be performed on the preliminary common source layer 110p before performing the ion implantation process.

[0130] Refer again Figure 5 and Figure 6, a first upper insulating layer 161 may be formed on the common source layer 110 (e.g., covering the common source layer 110). The first upper insulating layer 161 may be on the connector CON on the uppermost molded insulating layer 122 among the molded insulating layers 122 and the second end CP1y of the first vertical conductive structure CP1 (e.g., covering the uppermost molded insulating layer 122 among the molded insulating layers 122 and the second end CP1y of the first vertical conductive structure CP1). The first upper insulating layer 161 may cover the stacked insulating layer 124 and the fourth end CP2y of the second vertical conductive structure CP2 on the pad region PRC.

[0131] The second upper insulating layer 162 may be formed on the first upper insulating layer 161. The formation of the second upper insulating layer 162 may be omitted. The second upper insulating layer 162 may cover the first upper insulating layer 161. Thereafter, a rear via 164 extending in the second upper insulating layer 162 (e.g., penetrating the second upper insulating layer 162) may be formed. Each rear via 164 may be provided to be connected (e.g., electrically connected) to the second vertical conductive structure CP2.

[0132] A rear pad 166 connected (e.g., electrically connected) to the rear via 164 may be formed on the second upper insulating layer 162. Thereafter, a passivation layer 168 on (e.g., at least partially covering) the rear pad 166 may be formed on the second upper insulating layer 162, and an opening OP may be formed in the passivation layer 168 to expose the upper surface of the rear pad 166 (a portion of the upper surface of the rear pad 166). Thus, the semiconductor device 100 may be manufactured.

[0133] Fig.16 is a diagram schematically illustrating a data storage system 1000 including a semiconductor device according to some embodiments.

[0134] Reference Fig.16 , the data storage system 1000 may include one or more semiconductor devices 1100 and a storage controller 1200 electrically connected to the semiconductor device 1100. For example, the data storage system 1000 may be, for example, a solid state drive (SSD) device including at least one semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0135] The semiconductor device 1100 may be a nonvolatile memory device. For example, the semiconductor device 1100 may include the Figures 1 to 9 The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may be Figure 3The peripheral circuit structure PS includes a row decoder 1110, a page buffer 1120 and a logic circuit 1130.

[0136] The second structure 1100S may be Figure 3 The storage cell structure CS includes multiple bit lines BL, a common source line CSL, multiple word lines WL, a first string selection line UL1 and a second string selection line UL2, a first ground selection line LL1 and a second ground selection line LL2, and a storage cell structure CS of multiple storage cell strings CSTR between the multiple bit lines BL and the common source line CSL.

[0137] In the second structure 1100S, the plurality of memory cell strings CSTR may each include ground selection transistors LT1 and LT2 adjacent to the common source line CSL, string selection transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the ground selection transistors LT1 and LT2 and the string selection transistors UT1 and UT2. The number of the ground selection transistors LT1 and LT2 and the number of the string selection transistors UT1 and UT2 may be modified in various ways according to the embodiment.

[0138] In some embodiments, a plurality of first ground selection lines LL1 and a plurality of second ground selection lines LL2 may be connected (e.g., electrically connected) to gate electrodes of ground selection transistors LT1 and LT2, respectively. A word line WL may be connected (e.g., electrically connected) to a gate electrode of a memory cell transistor MCT. A plurality of first string selection lines UL1 and a plurality of second string selection lines UL2 may be connected (e.g., electrically connected) to gate electrodes of string selection transistors UT1 and UT2, respectively.

[0139] Common source lines CSL, first and second ground selection lines LL1 and LL2, word lines WL, and first and second string selection lines UL1 and UL2 may be connected (eg, electrically connected) to a row decoder 1110. Bit lines BL may be electrically connected to a page buffer 1120.

[0140] The semiconductor device 1100 may communicate with the memory controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130.

[0141] The memory controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the memory controller 1200 may control the plurality of semiconductor devices 1100 .

[0142] The processor 1210 may control all operations of the data storage system 1000 including the storage controller 1200. The processor 1210 may operate according to a specific firmware and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 for communicating with the semiconductor device 1100. A control command for controlling the semiconductor device 1100, data to be written into a plurality of memory cell transistors MCT of the semiconductor device 1100, and data to be read from a plurality of memory cell transistors MCT of the semiconductor device 1100, etc. may be sent through the NAND interface 1221. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0143] Fig.17 is a perspective view schematically illustrating a data storage system 2000 including a semiconductor device according to some embodiments.

[0144] Reference Fig.17 , a data storage system 2000 according to some embodiments may include a main substrate 2001, a memory controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004. The one or more semiconductor packages 2003 and the DRAM 2004 may be connected (e.g., electrically connected) to the memory controller 2002 through a plurality of wiring patterns 2005 formed on the main substrate 2001.

[0145] The main substrate 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 may communicate with the external host according to any one of the interfaces (e.g., Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Memory (UFS), etc.). In some embodiments, the data storage system 2000 may be operated by power supplied from an external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from an external host to the storage controller 2002 and one or more semiconductor packages 2003.

[0146] The memory controller 2002 may write data to or read data from the one or more semiconductor packages 2003 , and may increase the operation speed of the data storage system 2000 .

[0147] The DRAM 2004 may be a buffer memory that reduces the speed difference between the one or more semiconductor packages 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a cache memory and may provide a space for temporarily storing data in a control operation on the one or more semiconductor packages 2003. When the data storage system 2000 includes the DRAM 2004, the storage controller 2002 may further include a DRAM controller that controls the DRAM 2004 in addition to the NAND controller that controls the one or more semiconductor packages 2003.

[0148] The one or more semiconductor packages 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b separated from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 on a lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a mold layer 2500 disposed on the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100 (e.g., covering the plurality of semiconductor chips 2200 and the connection structure 2400).

[0149] The package substrate 2100 may be a printed circuit board including a plurality of package pads 2130. Each of the plurality of semiconductor chips 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.16 Each of the plurality of semiconductor chips 2200 may include the input / output pads 1101 described above. Figures 1 to 9 At least one of the semiconductor devices 10 , 100 , and 101 is described.

[0150] In some embodiments, the connection structure 2400 may include bonding wires that electrically connect the input / output pads 2210 to the package pads 2130, respectively. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by using a bonding wire method, and may be electrically connected to the package pads 2130 of the package substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of a connection structure 2400 of a bonding wire type.

[0151] In some embodiments, the memory controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In some embodiments, the memory controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the memory controller 2002 may be connected (e.g., electrically connected) to the plurality of semiconductor chips 2200 through wiring formed on the interposer substrate.

[0152] Fig.18 is a diagram schematically illustrating a semiconductor package 2003 according to some embodiments, and is a diagram along Fig.17 A cross-sectional view taken along line II-II′.

[0153] Reference Fig.18 The package substrate 2100 of the semiconductor package 2003 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, a plurality of package upper pads 2130 (see FIG. 213 ) on the upper surface of the package substrate body 2120, and a plurality of package upper pads 2130 (see FIG. 213 ). Fig.17 ), a plurality of package lower pads 2125 arranged on or exposed through the lower surface of the package substrate body 2120, and a plurality of package upper pads 2130 (see Fig.17 ) are electrically connected to a plurality of internal wirings 2135 of the plurality of package lower pads 2125. Fig.17 As shown, the plurality of package upper pads 2130 may be electrically connected to the plurality of connection structures 2400, respectively. Fig.18 As shown, the plurality of package lower pads 2125 may be connected (eg, electrically connected) to the plurality of conductive connecting portions 2800. Fig.17 The data storage system 2000 shown in FIG. 2000 includes a plurality of wiring patterns 2005 on the main substrate 2001. Each of the plurality of semiconductor chips 2200 may include the plurality of wiring patterns 2005 on the main substrate 2001. Figures 1 to 9 At least one of the semiconductor devices 10 , 100 , and 101 is described.

[0154] While the inventive concept of the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device, comprising: Peripheral circuit structure; as well as a cell structure on said peripheral circuit structure, Wherein, the peripheral circuit structure includes: A substrate comprising a cell region, a connection region adjacent to the cell region, and a pad region extending around the cell region and the connection region; a first connection structure, between the substrate and the unit structure; a first peripheral circuit transistor in the cell region and / or the connection region; and a second peripheral circuit transistor in the pad region, Wherein, the first connection structure includes a first wiring structure and a dummy structure, The first wiring structure overlaps the cell area, the connection area and / or the pad area in a first direction perpendicular to the upper surface of the substrate, the first wiring structure is electrically connected to the first peripheral circuit transistor and / or the second peripheral circuit transistor, The dummy structure overlaps the cell region and / or the connection region in the first direction, and The dummy structure is not directly connected to the first peripheral circuit transistor.

2. The semiconductor device according to claim 1, wherein The unit structure includes a vertical conductive structure in the pad region, and The vertical conductive structure is electrically connected to the second peripheral circuit transistor through the first wiring structure.

3. The semiconductor device according to claim 1, wherein The dummy structure and the first wiring structure are spaced apart from and electrically insulated from each other.

4. The semiconductor device according to claim 1, wherein: The dummy structure is connected to the first wiring structure.

5. The semiconductor device according to claim 1, wherein The unit structure comprises: gate electrodes spaced apart from each other along the first direction on the upper surface of the substrate; and a channel structure extending in said gate electrode, The channel structure includes a first end and a second end opposite to the first end. The first end is closer to the peripheral circuit structure than the second end in the first direction, The width of the first end in the second direction is greater than the width of the second end in the second direction, and The second direction is parallel to the upper surface of the substrate.

6. The semiconductor device according to claim 1, wherein The first connection structure further includes a first connection pad, and The unit structure includes second connection pads on the first connection structure that are in contact with the first connection pads, respectively.

7. The semiconductor device according to claim 6, wherein: The dummy structure is connected to the first connection pad.

8. The semiconductor device according to claim 7, wherein: The unit structure further includes: a second wiring structure electrically connected to the second connection pad, and The first wiring structure is electrically connected to the first connection pad.

9. The semiconductor device according to claim 1, wherein: The first wiring structure comprises: a first connection wiring extending in a second direction parallel to the upper surface of the substrate; and a first connection via electrically connected to the first connection wiring and extending in the first direction, and Wherein, the virtual structure includes: a dummy wiring extending in the second direction; and A dummy via is connected to the dummy wiring and extends in the first direction.

10. The semiconductor device according to claim 9, wherein A width of the first connection via in the second direction and a width of the dummy via in the second direction are different from each other.

11. The semiconductor device according to claim 9, wherein: The first wiring structure further includes: a second connection wiring extending in the second direction and electrically connected to the first connection via; and a second connection via extending in the first direction and electrically connected to the second connection wiring, and Wherein, a width of the first connection via in the second direction and a width of the second connection via in the second direction are different from each other.

12. The semiconductor device according to claim 9, wherein The dummy vias include multiple layers of dummy vias. The multi-layer dummy vias are at different distances from the upper surface of the substrate, and The widths of the multiple layers of dummy vias in the second direction are different from each other.

13. A semiconductor device comprising: substrate; a peripheral circuit structure in the substrate; a first connection structure on the substrate; as well as a second connecting structure on the first connecting structure, The first connection structure includes a first interlayer insulating layer, a first stop layer on the first interlayer insulating layer, and a first connection wiring and a dummy wiring in the first interlayer insulating layer. The second connection structure includes a second stop layer, a second interlayer insulating layer on the second stop layer, and a second connection wiring in the second interlayer insulating layer, The first connection wiring is electrically connected to the peripheral circuit structure, The dummy wiring is not directly connected to the peripheral circuit structure, An upper surface of the dummy wiring and a lower surface of the first stop layer are coplanar with each other, and A lower surface of the second connection wiring and an upper surface of the second stop layer are coplanar with each other.

14. The semiconductor device according to claim 13, wherein: The dummy wiring includes a first material having a greater hydrogen diffusion rate than second materials of the first stop layer and the second stop layer.

15. The semiconductor device according to claim 13, wherein: The dummy wiring and the first connection wiring include the same material.

16. The semiconductor device according to claim 13, wherein: The first connection structure further includes: a dummy via connected to the dummy wiring and extending in the first stop layer; and A connection via is electrically connected to the first connection wiring and extends in the first stop layer.

17. The semiconductor device according to claim 16, wherein: The width of the dummy via in the first direction and the width of the connection via in the first direction are different from each other, and The first direction is parallel to the upper surface of the substrate.

18. The semiconductor device according to claim 13, wherein: The dummy wiring is connected to the first connection wiring.

19. A semiconductor device comprising: Peripheral circuit structure; as well as a cell structure on said peripheral circuit structure, Wherein, the peripheral circuit structure includes: A substrate comprising a cell region, a connection region adjacent to the cell region, and a pad region extending around the cell region and the connection region; and a first connection structure on the substrate, Wherein, the unit structure comprises: gate electrodes spaced apart from each other along a first direction in the cell region, wherein the first direction is perpendicular to an upper surface of the substrate; a channel structure extending in the gate electrode along the first direction in the cell region, wherein the channel structure includes a first end and a second end, the first end is closer to the peripheral circuit structure than the second end in the first direction, and the second end is an opposite side of the first end; a pad portion extending from the gate electrode in the connection region, wherein the pad portion is in a stepped shape; a first vertical conductive structure electrically connected to the pad portion, wherein the first vertical conductive structure extends in the pad portion along the first direction; A stacked insulating layer extending around the gate electrode in a plan view; a second vertical conductive structure in the pad region, wherein the second vertical conductive structure extends in the stacked insulating layer along the first direction; and a common source layer on the second end of the channel structure in the cell region, Wherein, the first connection structure includes a wiring structure and a dummy structure, The wiring structure overlaps the cell area, the connection area and / or the pad area in the first direction, The wiring structure is electrically connected to the peripheral circuit structure, The dummy structure overlaps the cell region and / or the connection region in the first direction, and The dummy structure is not directly connected to the peripheral circuit structure.

20. The semiconductor device according to claim 19, wherein The wiring structure is electrically connected to the second vertical conductive structure in the pad area, and The dummy structure and the wiring structure are spaced apart from each other and are electrically separated.

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