Multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction

Abstract

According to the multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction provided by the invention, an N-pole drift region and a P-pole drift region are introduced on the basis of a traditional LIGBT device to form a super junction structure, so that the breakdown voltage of the device is improved, and the conduction voltage drop is reduced; a collector N-buffer region, a collector P region, a collector metal electrode and a collector gate oxide layer are introduced to form an electron extraction structure, when the device is turned off, forward voltage of a collector enables a conducting channel to appear in the collector P region, electrons can flow through the conducting channel and then directly flow into the collector metal electrode without penetrating through a p region barrier, and therefore the electron extraction efficiency is improved. Compared with the prior art, the semiconductor device has the advantages that electron dissociation is accelerated, turn-off time and turn-off loss of the device are effectively reduced, an N-buffer layer 1 region, an N-buffer layer 2 region and an N-buffer layer 3 region are introduced to form an auxiliary depletion region, the breakdown voltage of the device is improved, and a path is provided for electron dissociation when the device is turned off.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and in particular relates to a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction. Background Art

[0002] LIGBT (Lateral Insulated Gate Bipolar Transistor) is a bipolar power semiconductor device with the characteristics of large breakdown voltage, small on-state voltage drop, and high operating frequency. It is widely used in various electronic fields such as transportation and communication. IGBT can be roughly regarded as a combination of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and BJT (Bipolar junction transistor). Therefore, it has the characteristics of gate voltage control of MOSFET and dual-carrier conduction of BJT.

[0003] SJ (Super-Junction) is an emerging structure that can be applied to devices such as MOS and IGBT. It was first proposed by Academician Chen Xingbi. SJ changes the n-type drift region in MOS and IGBT into a structure in which n-pillar and p-pillar alternate with each other, and introduces a lateral electric field inside the device without affecting the longitudinal electric field of the device, thereby increasing the breakdown voltage of the device without affecting the on-state voltage drop: when the device is turned off, the n-pillar and p-pillar deplete each other, and the drift region of the device can be approximately regarded as an intrinsic semiconductor, thereby increasing the breakdown voltage of the device and optimizing the ratio of breakdown voltage to on-state voltage drop from 2.52 to 1.3, successfully breaking through the traditional "silicon limit".

[0004] In order to completely deplete the drift region and achieve the maximum breakdown voltage, the n-pillar and the p-pillar often have the same doping concentration. However, in LIGBT, since the substrate is a low-doped p-type substrate, there is a parasitic pn junction between the n-pillar and the substrate. The p-type substrate causes the n-pillar to be completely depleted before the p-pillar, and at the same time makes the p-pillar unable to be completely depleted. Therefore, how to control the synchronous depletion of the p-pillar and the n-pillar has become a problem that still needs to be solved.

[0005] In addition, IGBT is a gate voltage controlled power device, so IGBT has a large breakdown voltage and a high operating frequency; and because IGBT is a bipolar conduction device, the IGBT has a small on-state voltage drop. However, bipolar conduction also has defects. When the device is turned off, the residual carriers in the drift region will cause a certain tail current, increasing the turn-off loss of the device. This is because there is a p-region in the collector of the device, which will act as a barrier to hinder the extraction of electrons when the device is turned off. Therefore, the excess carriers in the drift region of the device need to disappear through recombination, resulting in a longer turn-off time and tail current, which greatly increases the turn-off loss of the device. Therefore, how to reduce the turn-off loss of IGBT has become an urgent problem to be solved. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a multi-layer N-buffer structure SJ-LIGBT device that accelerates electron extraction. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] The present invention provides a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction, comprising: an emitter P+ region 1, an emitter N+ region 2, an emitter P-well region 3, a P-type substrate region 4, an emitter metal electrode 5, a gate oxide layer 6, a gate metal electrode 7, an N-pillar drift region 8, a P-pillar drift region 9, a collector N-buffer region 10, a collector P region 11, an N-bufferlayer1 region 12, an N-bufferlayer2 region 13, an N-bufferlayer3 region 14, a collector metal electrode 15 and a collector gate oxide layer 16;

[0008] Among them, the P-type substrate region 4 is located at the bottom of the multi-layer N-buffer structure SJ-LIGBT device, and one end is a trapezoidal structure; the emitter P-well region 3, the emitter P+ region 1, the emitter N+ region 2, and the emitter metal electrode 5 together constitute the emitter region located at one end of the top of the device; the gate oxide layer 6 and the gate metal electrode 7 constitute the gate metal region, which is arranged closely to the emitter region; the N-pillar drift region 8 and the P-pillar drift region 9 are arranged laterally and staggered in the middle position of the top of the device to form a drift region; the collector N-buffer region 10, the collector P region 11, the N-bufferlayer1 region 12, the N-bufferlayer2 region 13, the N-bufferlayer3 region 14, the collector metal electrode 15, and the collector gate oxide layer 16 together constitute the collector region, and are placed at the other end of the top of the multi-layer N-buffer structure SJ-LIGBT device opposite to the emitter region.

[0009] Beneficial effects:

[0010] The present invention provides a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction. On the basis of a traditional LIGBT device, an N-pillar drift region 8 and a P-pillar drift region 9 are introduced to form a super junction structure, thereby increasing the breakdown voltage of the device and reducing the on-state voltage drop; a collector N-buffer region 10, a collector P region 11, a collector metal electrode 15, and a collector gate oxide layer 16 are introduced to form an electron extraction structure. When the device is turned off, the collector forward voltage causes a conductive channel to appear in the collector P region 11, and electrons can flow through the conductive channel and directly flow into the collector metal electrode 15, without passing through the collector p region like a traditional LIGBT, and without passing through the p region potential barrier, thereby accelerating the extraction of electrons and effectively reducing the turn-off time and turn-off loss of the device. N-bufferlayer1 region 12, N-bufferlayer2 region 13, and N-bufferlayer3 region 14 are introduced to form an auxiliary depletion region, thereby increasing the breakdown voltage of the device and providing a path for the extraction of electrons when the device is turned off.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the three-dimensional structure of a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction provided by the present invention;

[0013] Figure 2 It is a cross-sectional view of a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction provided by the present invention. DETAILED DESCRIPTION

[0014] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0015] The object of the present invention is to provide a multi-layer n-buffer structure SJ-LIGBT device that accelerates electron extraction. The multi-layer n-buffer structure can assist the depletion of the P-type substrate, thereby improving the device breakdown voltage. In addition, the multi-layer n-buffer structure combined with the collector gate oxide structure can assist in extracting electrons when the device is turned off to accelerate the device's turn-off speed and reduce the turn-off loss.

[0016] Combination Figure 1 and Figure 2The present invention provides a multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction, comprising: an emitter P+ region 1, an emitter N+ region 2, an emitter P-well region 3, a P-type substrate region 4, an emitter metal electrode 5, a gate oxide layer 6, a gate metal electrode 7, an N-pillar drift region 8, a P-pillar drift region 9, a collector N-buffer region 10, a collector P region 11, an N-bufferlayer1 region 12, an N-bufferlayer2 region 13, an N-bufferlayer3 region 14, a collector metal electrode 15 and a collector gate oxide layer 16;

[0017] Among them, the P-type substrate region 4 is located at the bottom of the multi-layer N-buffer structure SJ-LIGBT device, and one end is in a stepped structure; the emitter P-well region 3, the emitter P+ region 1, the emitter N+ region 2, and the emitter metal electrode 5 together constitute the emitter region located at one end of the top of the device; the gate oxide layer 6 and the gate metal electrode 7 constitute the gate metal region, which is arranged closely to the emitter region; the N-pillar drift region 8 and the P-pillar drift region 9 are arranged laterally and staggered in the middle position of the top of the device to form a drift region; the collector N-buffer region 10, the collector P region 11, the N-bufferlayer1 region 12, the N-bufferlayer2 region 13, the N-bufferlayer3 region 14, the collector metal electrode 15, and the collector gate oxide layer 16 together constitute the collector region, and are placed at the other end of the top of the multi-layer N-buffer structure SJ-LIGBT device opposite to the emitter region.

[0018] The N-pillar drift region 8 and the P-pillar drift region 9 have the same shape and size, and the thickness thereof is the same as that of the emitter P-well region 3 .

[0019] It is worth noting that: N-bufferlayer1 region 12, N-bufferlayer2 region 13, and N-bufferlayer3 region 14 constitute an auxiliary depletion region. The auxiliary depletion region composed of a multi-layer n-buffer structure can assist the P-type substrate in depletion, thereby increasing the device breakdown voltage. The collector N-buffer region 10, the collector P region 11, the collector metal electrode 15, and the collector gate oxide layer 16 constitute an electron extraction structure, and the multi-layer n-buffer structure combined with the collector electron extraction structure can assist in extracting electrons when the device is turned off to speed up the device's turn-off speed and reduce turn-off losses.

[0020] refer to Figure 1 and Figure 2In the emitter region, the emitter P-well region 3 is located at the other end of the P-type substrate region 4, and surrounds the emitter P+ region 1 and the emitter N+ region 2 in an inverted L shape; the emitter P+ region 1 and the emitter N+ region 2 are adjacent to each other and are both located above the emitter P-well region 3; the emitter metal electrode 5 is located to cover the emitter P+ region 1 and the emitter N+ region 2.

[0021] refer to Figure 1 and Figure 2 In the gate metal region, the gate oxide layer 6 covers the end of the emitter P-well region 3 that is protruding in the reverse L shape, and the gate metal electrode 7 covers the gate oxide layer 6 .

[0022] refer to Figure 1 and Figure 2 In the collector region, the N-bufferlayer3 region 14 is arranged at the bottom step of the emitter P+ region 1; the N-bufferlayer2 region 13 is located above the N-bufferlayer3 region 14; the N-bufferlayer1 region 12 is located above the N-bufferlayer2 region 13; the collector gate oxide layer 16 is located outside the device, and the collector metal electrode 15 is located above the collector P region 11 and the collector gate oxide layer 16 and to the right of the collector gate oxide layer 16, surrounding the collector P region 11 and the collector gate oxide layer 16 in an inverted L shape.

[0023] The directions in the embodiment of the present invention are: "up", "down", "thickness" and "height" are from top to bottom along the direction from the emitter P+ region 1 to the P-type substrate region 4; "length", "left" and "right" are from left to right along the direction from the emitter P+ region 1 to the collector P region 11; and "width", "front" and "back" are from front to back along the direction from the N-pillar drift region 8 to the P-pillar drift region 9.

[0024] In a specific embodiment of the present invention, the length of the emitter P+ region 1 is 2μm, the length of the emitter N+ region 2 is 2μm, the length of the emitter P-well region 3 is 6μm, the length of the P-type substrate region 4 is 74μm, the length of the emitter metal electrode 5 is 4μm, the length of the gate oxide layer 6 and the gate metal electrode 7 is 2μm, the length of the N-pillar drift region 8 and the P-pillar drift region 9 are both 60μm, the length of the collector N-buffer region 10 is 5μm, the length of the collector P region 11 is 4.5μm, the length of the N-bufferlayer1 region 12 is 8μm, the length of the N-bufferlayer2 region 13 is 6μm, the length of the N-bufferlayer3 region 14 is 4μm, the length of the collector metal electrode 15 is 4.6μm, and the length of the collector gate oxide layer 16 is 0.1μm.

[0025] In a specific embodiment of the present invention, without considering the metal electrode, the overall thickness of the multi-layer N-buffer structure SJ-LIGBT device is 100 μm, the thickness of the emitter P+ region 1 is 0.2 μm, the thickness of the emitter N+ region 2 is 0.2 μm, the thickness of the emitter P-well region 3 is 0.6 μm, and the thickness of the P-type substrate region 4 is 99.4 μm; the thickness of the emitter metal electrode 5, the collector metal electrode 15, the gate oxide layer 6 and the gate metal electrode 7 are all 0.1 μm; the thickness of the N-pillar drift region 8 and the P-pillar drift region 9 are both 0.2 μm, the thickness of the collector N-buffer region 10 is 0.6 μm, the thickness of the collector P region 11 is 0.3 μm, the thickness of the N-bufferlayer1 region 12, the N-bufferlayer2 region 13 and the N-bufferlayer3 region 14 are all 0.5 μm, and the thickness of the collector gate oxide layer 16 is 0.3 μm;

[0026] Among them, except for the N-pillar drift region 8 and the P-pillar drift region 9, the width of other regions of the multi-layer N-buffer structure SJ-LIGBT device is 2μm, and the width of the N-pillar drift region 8 and the P-pillar drift region 9 is 1μm.

[0027] In a specific embodiment of the present invention, the emitter P+ region 1 is P-type doped with a doping concentration of 1e19 cm -3 , the emitter N+ region 2 is N-type doped with a doping concentration of 1e19cm -3 , the emitter P-well region 3 is P-type doped with a doping concentration of 1e16cm -3 , the P-type substrate region 4 is P-type doped, with a doping concentration of 1e14cm -3 , N-pillar drift region 8 and P-pillar drift region 9 are N-type doped and P-type doped respectively, and the doping concentration is 1e16cm -3 The collector N-buffer region 10 is N-type doped with a doping concentration of 5e16cm -3 , the collector P region 11 is P-type doped with a doping concentration of 1e17cm -3 , the length of N-bufferlayer1 region 12 is 8 μm, the length of N-bufferlayer2 region 13 is 6 μm, and the N-bufferlayer3 region 14 is N-type doped, and the doping concentration is 1e16 cm -3 .

[0028] The working principle of the device of the present invention is as follows:

[0029] When the device is forward-conducted, the gate metal electrode 7 is connected to a positive voltage, the emitter metal electrode 5 is connected to a negative voltage, and the collector metal electrode 15 is connected to a positive voltage. There is an electron extraction structure, namely the collector gate oxide layer 16 and the collector metal electrode 15, on the right side of the collector P region 11. Since a positive voltage is applied to the collector contact metal electrode 13, the holes in the part of the collector p region 11 that contacts the collector gate oxide layer 16 are repelled, thereby generating a conductive channel. Electrons flow through the conductive channel generated in the collector P region 11 and flow into the collector metal electrode 15 without passing through the PN junction barrier generated by the collector N-buffer region 10 and the collector P region 11, thereby reducing the conduction voltage drop.

[0030] When the device withstands voltage, the gate metal electrode 7 is connected to a negative voltage, the emitter metal electrode 5 is connected to a negative voltage, and the collector metal electrode 15 is connected to a positive voltage. Since there are multiple layers of N-buffer structures in the P-type substrate region 4, the multiple layers of N-buffer structures and the P-type substrate region 4 are mutually depleted, which can effectively prevent the device from undergoing longitudinal breakdown, thereby improving the longitudinal withstand voltage capability of the device and achieving full utilization of the substrate. In addition, the mutual depletion of the multiple layers of N-buffer structures and the P-type substrate region 4 can also prevent the P-type substrate region 4 from affecting the mutual depletion between the N-pillar drift region 8 and the P-pillar drift region 9, thereby improving the lateral withstand voltage capability of the device.

[0031] At the moment of device shutdown, the gate metal electrode 7 changes from positive voltage to negative voltage, the emitter metal electrode 5 is connected to negative voltage, and the collector metal electrode 15 is connected to positive voltage. On the right side of the collector P region 11, there is an electron extraction structure, namely the collector gate oxide layer 16 and the collector metal electrode 15. Since a positive voltage is applied to the collector contact metal electrode 13, the holes in the part of the collector p region 11 contacting the collector gate oxide layer 16 are repelled, thereby generating a conductive channel. At the moment of device shutdown, the remaining electrons remaining in the drift region can flow through the collector n-buffer region and this conductive channel and flow into the collector metal electrode 15 without passing through the PN junction barrier generated by the collector N-buffer region 10 and the collector P region 11. Compared with the traditional SJ-LIGBT structure, this structure provides a conductive channel for electron extraction when the device is turned off, which reduces the turn-off time and the turn-off loss when the device is turned off.

[0032] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components or steps.

[0033] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction, characterized in that: include: Emitter P+ region (1), emitter N+ region (2), emitter P-well region (3), P-type substrate region (4), emitter metal electrode (5), gate oxide layer (6), gate metal electrode (7), N-pillar drift region (8), P-pillar drift region (9), collector N-buffer region (10), collector P region (11), N-bufferlayer1 region (12), N-bufferlayer2 region (13), N-bufferlayer3 region (14), collector metal electrode (15) and collector gate oxide layer (16); The P-type substrate region (4) is located at the bottom of the multi-layer N-buffer structure SJ-LIGBT device, and one end is in a trapezoidal structure; the emitter P-well region (3), the emitter P+ region (1), the emitter N+ region (2), and the emitter metal electrode (5) together constitute the emitter region located at one end of the top of the device; the gate oxide layer (6) and the gate metal electrode (7) constitute the gate metal region, which is arranged adjacent to the emitter region; the N-pillar drift region (8) and the P-pillar drift region ( 9) are arranged in a staggered manner in a horizontal direction in the middle of the top of the device to form a drift region; the collector N-buffer region (10), the collector P region (11), the N-bufferlayer1 region (12), the N-bufferlayer2 region (13), the N-bufferlayer3 region (14), the collector metal electrode (15), and the collector gate oxide layer (16) together form a collector region and are placed at the other end of the top of the multi-layer N-buffer structure SJ-LIGBT device opposite to the emitter region.

2. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, characterized in that: In the emitter region, the emitter P-well region (3) is located at the other end of the P-type substrate region (4), and surrounds the emitter P+ region (1) and the emitter N+ region (2) in an inverted L shape; the emitter P+ region (1) and the emitter N+ region (2) are adjacent to each other and are both located above the emitter P-well region (3); the emitter metal electrode (5) is located to cover the emitter P+ region (1) and the emitter N+ region (2).

3. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, characterized in that: In the gate metal region, the gate oxide layer (6) covers an end of the emitter P-well region (3) that is protruding in an L shape, and the gate metal electrode (7) covers the gate oxide layer (6).

4. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, characterized in that: In the collector region, the N-bufferlayer3 region (14) is arranged at the bottommost step of the emitter P+ region (1); the N-bufferlayer2 region (13) is located above the N-bufferlayer3 region (14); the N-bufferlayer1 region (12) is located above the N-bufferlayer2 region (13); the collector gate oxide layer (16) is located outside the device, and the collector metal electrode (15) is located above the collector P region (11) and the collector gate oxide layer (16) and to the right of the collector gate oxide layer (16), and surrounds the collector P region (11) and the collector gate oxide layer (16) in an inverse L shape.

5. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, characterized in that: The length of the emitter P+ region (1) is 2 μm, the length of the emitter N+ region (2) is 2 μm, the length of the emitter P-well region (3) is 6 μm, the length of the P-type substrate region (4) is 74 μm, the length of the emitter metal electrode (5) is 4 μm, the length of the gate oxide layer (6) and the gate metal electrode (7) are 2 μm, the length of the N-pillar drift region (8) and the P-pillar drift region (9) are both 60 μm, and the length of the collector The length of the electrode N-buffer region (10) is 5 μm, the length of the collector P region (11) is 4.5 μm, the length of the N-bufferlayer1 region (12) is 8 μm, the length of the N-bufferlayer2 region (13) is 6 μm, the length of the N-bufferlayer3 region (14) is 4 μm, the length of the collector metal electrode (15) is 4.6 μm, and the length of the collector gate oxide layer (16) is 0.1 μm.

6. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, characterized in that: Without considering the metal electrodes, the overall thickness of the multi-layer N-buffer structure SJ-LIGBT device is 100 μm, the thickness of the emitter P+ region (1) is 0.2 μm, the thickness of the emitter N+ region (2) is 0.2 μm, the thickness of the emitter P-well region (3) is 0.6 μm, and the thickness of the P-type substrate region (4) is 99.4 μm; the thickness of the emitter metal electrode (5), the collector metal electrode (15), the gate oxide layer (6) and the gate metal electrode (7) are all 0.1 μm; the thickness of the N-pillar drift region (8) and the P-pillar drift region (9) are both 0.2 μm, the thickness of the collector N-buffer region (10) is 0.6 μm, the thickness of the collector P region (11) is 0.3 μm, the thickness of the N-bufferlayer1 region (12), the N-bufferlayer2 region (13) and the N-bufferlayer3 region (14) are all 0.5 μm, and the thickness of the collector gate oxide layer (16) is 0.3 μm; Except for the N-pillar drift region (8) and the P-pillar drift region (9), the widths of other regions of the multi-layer N-buffer structure SJ-LIGBT device are all 2 μm, and the widths of the N-pillar drift region (8) and the P-pillar drift region (9) are all 1 μm.

7. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, characterized in that: The emitter P+ region (1) is P-type doped with a doping concentration of 1e19 cm -3 , the emitter N+ region (2) is N-type doped with a doping concentration of 1e19cm -3 The emitter P-well region (3) is P-type doped with a doping concentration of 1e16 cm -3 The P-type substrate region (4) is P-type doped with a doping concentration of 1e14 cm -3 The N-pillar drift region (8) and the P-pillar drift region (9) are N-type doped and P-type doped, respectively, with doping concentrations of 1e16 cm -3 The collector N-buffer region (10) is N-type doped with a doping concentration of 5e16 cm -3 , the collector P region (11) is P-type doped with a doping concentration of 1e17cm -3 , the length of N-bufferlayer1 region (12) is 8 μm, the length of N-bufferlayer2 region (13) is 6 μm, and N-bufferlayer3 region (14) is N-type doped, and the doping concentration is 1e16 cm -3 .

8. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, characterized in that: The N-bufferlayer1 region (12), the N-bufferlayer2 region (13), and the N-bufferlayer3 region (14) constitute an auxiliary depletion region.

9. The multi-layer N-buffer structure SJ-LIGBT device for accelerating electron extraction according to claim 1, characterized in that: The collector N-buffer region (10), the collector P region (11), the collector metal electrode (15), and the collector gate oxide layer (16) constitute an electron extraction structure.

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