Floating gate type flash memory unit and manufacturing method thereof

Abstract

The invention discloses a floating gate type flash memory unit and a manufacturing method thereof. The invention relates to a floating gate type flash memory unit, which comprises a substrate, a source electrode and a drain electrode are formed in the substrate; a floating gate bottom tunneling oxide layer is arranged above the center of the substrate; an inverted T-shaped floating gate is arranged at the upper part of the floating gate bottom tunneling oxide layer and is used for enlarging a storage window; the upper part of the floating gate is an erasing gate, and the inverted T-shaped structure of the floating gate enhances the electric field of an erasing area. The manufacturing process is simple, the control gate and the selection gate can be formed together through deposition, chemical mechanical grinding, etching and other processes, and the number of photomasks is reduced. The floating gate structure with the tip enhances the electric field of the erasure area, so that FN tunneling is easier to occur, and the erasure efficiency and reliability of the flash memory unit are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, in particular to a floating gate flash memory unit and a manufacturing method thereof. Background Art

[0002] The current mainstream floating gate flash memory cell has a stacked gate structure, including a tunneling oxide layer, a floating gate, a coupling dielectric layer and a control gate sequentially arranged on a substrate. When programming or erasing such a flash memory cell, appropriate voltages are applied to the source region, the drain region and the control gate, respectively, so that electrons are injected into the floating gate or pulled out of the floating gate. However, during programming or erasing operations, electrons must flow through the tunneling oxide layer under the floating gate to be injected into the floating gate or pulled out of the floating gate. This process usually damages the structure of the tunneling oxide layer, thereby reducing the reliability of the flash memory. Summary of the invention

[0003] In view of the deficiencies of the prior art, the present invention provides a floating gate flash memory unit and a manufacturing method thereof.

[0004] One aspect of the present invention provides a floating gate flash memory cell, comprising a substrate;

[0005] A source and a drain are formed inside the substrate; a floating gate bottom tunnel oxide layer is formed above the center of the substrate; an inverted T-shaped floating gate is formed above the floating gate bottom tunnel oxide layer to increase the storage window;

[0006] The upper portion of the floating gate is an erase gate, and the inverted T-shaped structure of the floating gate enhances the electric field of the erase region.

[0007] Another aspect of the present invention provides a method for manufacturing a floating gate flash memory cell, specifically:

[0008] S1: depositing a tunneling oxide layer at the bottom of the floating gate and depositing polysilicon on the substrate;

[0009] S2: forming an inverted T-shaped floating gate structure by photolithography and etching;

[0010] S3: Deposition of ON structure sidewalls;

[0011] S4: removing the ON structure deposited under one side of the floating gate by photolithography and etching, the side corresponding to the selection gate;

[0012] S5: growing an oxide layer at the ON structure removed above;

[0013] S6: depositing polysilicon to cover the sidewalls and oxide layer of the ON structure, thereby forming a select gate and a control gate;

[0014] S7: forming a self-oxide layer around the select gate and the control gate;

[0015] S8: removing the SIN layer on the top of the floating gate by photolithography and etching;

[0016] S9: growing the oxide layer on the top of the floating gate and its surroundings;

[0017] S10: depositing polysilicon to form an erase gate;

[0018] S11: forming sidewalls, photolithography, and ion implantation to form LDD regions;

[0019] S12: Deposit a SIN layer and implant ions into the substrate to form source and drain regions.

[0020] Beneficial effects of the present invention:

[0021] 1. A flash memory cell with an inverted "T"-shaped floating gate structure is proposed for the first time. The inverted "T"-shaped floating gate is beneficial for increasing the storage window.

[0022] 2. The manufacturing process is simple. The control gate and the select gate can be formed together through deposition, chemical mechanical polishing, etching and other processes, reducing the number of masks.

[0023] 3. The floating gate structure with a sharp tip enhances the electric field in the erase area, making FN tunneling more likely to occur, thereby improving the erase efficiency and reliability of the flash memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural diagram of the device of the present invention;

[0025] Figure 2 It is a schematic diagram of the manufacturing process of the present invention;

[0026] Figure 3 This is a diagram of the current-voltage characteristics simulation of a floating gate flash memory cell using TCAD software. DETAILED DESCRIPTION

[0027] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0028] like Figure 1 As shown, the embodiment of the present application provides a flash memory cell. The Si substrate 101 includes a drain 103-1 on the left and a source 103-2 on the right, and both electrodes have respective NLDD doped layers 102-1 and 102-2.

[0029] The inverted T-shaped floating gate 104 in the embodiment of the present application is located on the Si substrate 101 and in the middle, and a floating gate bottom tunneling oxide layer 105 is arranged between the substrate.

[0030] In the embodiment of the present application, the left side of the floating gate 104 is the selection gate 108, and the right side is the control gate 106; a selection gate dielectric layer 109 is arranged between the selection gate 108 and the substrate; and a control gate dielectric layer 107 is arranged between the control gate 106 and the substrate.

[0031] The selection gate 108 also has a selection gate sidewall 111 , and the control gate 106 also has a control gate sidewall 112 .

[0032] The top of the inverted T-shaped floating gate 104 is an erase gate 113 , and between the two is an erase gate bottom oxide layer 114 . Both sides of the erase gate 113 are provided with erase gate sidewalls 115 .

[0033] The select gate and the floating gate, and the control gate and the floating gate are isolated by a dielectric layer 110 .

[0034] The present application also provides a process for manufacturing the above-mentioned floating gate flash memory unit:

[0035] S1: Deposit the tunnel oxide layer at the bottom of the floating gate, through 20-30 RTO and 60-80 HTO process is used to form polysilicon. Polysilicon is deposited and As ions are implanted. Figure 2 As shown in (a).

[0036] S2: An inverted “T” floating gate structure is formed by photolithography, etching and other processes, such as Figure 2 As shown in (b).

[0037] S3: Deposition of ON structure sidewalls, 20-30 RTO, 120-150 SIN process formation, such as Figure 2 As shown in (c).

[0038] S4: Remove the ON deposited below the left side of the floating gate by photolithography, etching, etc. Figure 2 As shown in (d).

[0039] S5: 20-30 growth by ISSG method Oxide layer, such as Figure 2 As shown in (e).

[0040] S6: Deposit polysilicon and perform P ion implantation. Then, chemical mechanical polishing is performed to form Figure 2 Middle (f) structure.

[0041] S7: Form a self-oxide layer around the select gate and the control gate by the ISSG method, such as Figure 2 As shown in (g).

[0042] S8: Remove the SIN layer on the top of the floating gate by photolithography and etching, such as Figure 2 As shown in (h).

[0043] S9: Growth of 80-100 by HTO method Oxide layer, such as Figure 2 As shown in (i).

[0044] S10: Deposit polysilicon, perform photolithography, etching, etc. to form an erase gate, such as Figure 2 As shown in (j).

[0045] S11: RTO method formation 10-30 Sidewall, photolithography, ion implantation to form LDD region, such as Figure 2 As shown in (k).

[0046] S12: SIN is deposited by the sidewall process. P ion implantation forms the source and drain regions, such as Figure 2 As shown in (l).

[0047] The current-voltage characteristics of the above devices were simulated by TCAD software, such as Figure 3 As shown, the memory has distinct erase and program performance and a large storage window.

[0048] The above are preferred embodiments of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications are also considered to be within the protection scope of the present invention.

Claims

1. A floating gate flash memory cell, characterized in that: including a substrate; A source and a drain are formed inside the substrate; a tunnel oxide layer at the bottom of the floating gate is formed above the center of the substrate; an inverted T-shaped floating gate is formed above the tunnel oxide layer at the bottom of the floating gate, which is used to increase the storage window; The upper portion of the floating gate is an erase gate, and the inverted T-shaped structure of the floating gate enhances the electric field of the erase region.

2. A floating gate flash memory cell according to claim 1, characterized in that: One side of the floating gate is a control gate, and a control gate dielectric layer is arranged between the floating gate and the substrate; the other side is a selection gate, and a selection gate dielectric layer is arranged between the floating gate and the substrate.

3. A floating gate flash memory cell according to claim 1, characterized in that: The selection gate is also provided with a selection gate side wall.

4. A floating gate flash memory cell according to claim 1, characterized in that: The control grid is also provided with a control grid side wall.

5. A floating gate flash memory cell according to any one of claims 1 to 4, characterized in that: The erase gate has an erase gate sidewall.

6. A method for manufacturing a floating gate flash memory cell, characterized in that The method comprises the following steps: S1: depositing a tunneling oxide layer at the bottom of the floating gate and depositing polysilicon on the substrate; S2: forming an inverted T-shaped floating gate structure by photolithography and etching; S3: Deposition of ON structure sidewalls; S4: removing the ON structure deposited under one side of the floating gate by photolithography and etching, the side corresponding to the selection gate; S5: growing an oxide layer at the ON structure removed above; S6: depositing polysilicon to cover the sidewalls and oxide layer of the ON structure, thereby forming a select gate and a control gate; S7: forming a self-oxide layer around the select gate and the control gate; S8: removing the SIN layer on the top of the floating gate by photolithography and etching; S9: growing the oxide layer on the top of the floating gate and its surroundings; S10: depositing polysilicon to form an erase gate; S11: forming sidewalls, photolithography, and ion implantation to form LDD regions; S12: Deposit a SIN layer and implant ions into the substrate to form source and drain regions.

7. A method for manufacturing a floating gate flash memory cell according to claim 6, characterized in that: The bottom tunnel oxide layer of the floating gate deposited in S1 is formed by 20-30 Å RTO and 60-80 Å HTO process.

8. The method for manufacturing a floating gate flash memory cell according to claim 7, characterized in that: The deposition process also includes an As ion implantation step.

9. The method for manufacturing a floating gate flash memory cell according to claim 6, characterized in that: The ON structure sidewalls are deposited in S3 and formed by 20-30 Å RTO and 120-150 Å SIN processes.

10. The method for manufacturing a floating gate flash memory cell according to claim 6, characterized in that: The oxide layer growth in S5 and S7 was performed using the ISSG method, where the oxide layer thickness in S5 was 20-30 Å.

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