Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. The semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, and a source and drain structure on the barrier layer. The source structure includes a horizontal source portion extending in a first direction and at least one vertical source portion extending in a second direction perpendicular to the first direction. The drain structure includes a horizontal drain portion extending in a first direction and at least one vertical drain portion extending in a second direction, wherein each of the at least one vertical drain portion includes a tip drain portion and a flat end drain portion connecting the horizontal drain portion and the tip drain portion. The semiconductor device also includes a gate structure disposed on the barrier layer and between the source and drain structures, and a field plate structure disposed on the barrier layer, wherein the field plate structure contacts and surrounds the drain structure.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and is related to a semiconductor device and a method for forming the same, and in particular, to a semiconductor device with a stepped field plate structure and a method for forming the same. Background Art

[0002] With the development of semiconductor technology, the market is no longer satisfied with traditional silicon transistors. In high-power and high-frequency applications, compound semiconductors of Group III and V have shown the potential to replace silicon transistors. In recent years, high electron mobility transistors (HEMTs) made of gallium nitride (GaN) have attracted particular attention.

[0003] When operating a current GaN HEMT, the tip portion (commonly known as the fingertip) of the vertical portion (commonly known as the finger) of the drain structure will generate more hot carriers due to the higher electric field. Once the operation time is prolonged, the accumulated hot carriers will degrade the performance of the HEMT device or even destroy the HEMT device. Therefore, a novel HEMT structure is needed to prevent the high electric field at the tip portion of the drain structure from damaging the HEMT device. Summary of the invention

[0004] An embodiment of the present application provides a semiconductor device. The semiconductor device includes a substrate, a channel layer disposed above the substrate, a barrier layer disposed above the channel layer, and a source structure and a drain structure disposed above the barrier layer. The source structure includes a horizontal source portion extending along a first direction, and at least one vertical source portion extending along a second direction perpendicular to the first direction. The drain structure includes a horizontal drain portion extending along the first direction and at least one vertical drain portion extending along the second direction, wherein each of the at least one vertical drain portion includes a tip drain portion and a flat-end drain portion connecting the horizontal drain portion and the tip drain portion. The semiconductor device also includes a gate structure disposed above the barrier layer and between the source structure and the drain structure, and a field plate structure disposed above the barrier layer, wherein the field plate structure contacts and surrounds the drain structure.

[0005] An embodiment of the present application provides a method for forming a semiconductor device. The method for forming a semiconductor device includes providing an epitaxial structure, the epitaxial structure including a substrate, a channel layer above the substrate, and a barrier layer above the channel layer; forming a passivation layer above the barrier layer; patterning the passivation layer to form a source trench and a drain trench exposing the barrier layer; forming an insulating layer on a portion of the barrier layer in the drain trench and on a portion of the passivation layer, wherein the insulating layer includes a first insulating portion in the drain trench and a second insulating portion on the passivation layer; forming a source structure in the source trench and a drain structure in the drain trench, wherein the drain structure includes a horizontal drain portion extending along a first direction and a vertical drain portion extending along a second direction perpendicular to the first direction, and the vertical drain portion includes a tip drain portion and a flat-end drain portion connecting the horizontal drain portion and the tip drain portion, and at least a portion of the tip drain portion is formed on the first insulating portion; and forming a field plate structure on the insulating layer and the passivation layer, wherein the field plate structure includes a first field plate portion in contact with the tip drain portion, and a second field plate portion in contact with the flat-end drain portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present application can be better understood from the following embodiments and the accompanying drawings. It should be emphasized that, according to the standard practice of the industry, various features are not drawn to scale and are only for illustration purposes.

[0007] Figure 1 FIG. 1 is a partial or entire top view of an exemplary semiconductor device according to some embodiments of the present application.

[0008] Figure 2A According to some embodiments of the present application, the semiconductor device is arranged along Figure 1 Cross-sectional view of line segment AA'.

[0009] Figure 2B According to some embodiments of the present application, the semiconductor device is arranged along Figure 1 Cross-sectional view of line segment BB'.

[0010] Figure 2C According to some embodiments of the present application, the semiconductor device is arranged along Figure 1 Cross-sectional view of line segment C-C'.

[0011] Figure 2D According to some embodiments of the present application, the semiconductor device is arranged along Figure 1 Cross-sectional view of line segment D-D'.

[0012] Figure 3 According to other embodiments of the present application, the semiconductor device is arranged along Figure 1 Schematic cross-sectional view of line segment CC'.

[0013] Figure 4 is a flow chart of a method for forming a semiconductor device according to some embodiments of the present application.

[0014] [Explanation of symbols]

[0015] 100:Semiconductor device

[0016] 101: Epitaxial structure

[0017] 102:Substrate

[0018] 103: Buffer layer

[0019] 104: Channel layer

[0020] 105: Barrier layer

[0021] 106: passivation layer

[0022] 110: Source structure

[0023] 112: horizontal source portion

[0024] 114: Flat-end source part

[0025] 116: Tip source portion

[0026] 120: Drain structure

[0027] 122: horizontal drain portion

[0028] 124: Flat end drain part

[0029] 126: Tip drain part

[0030] 130: Gate structure

[0031] 132: first gate portion

[0032] 134: Second gate portion

[0033] 136: Third gate portion

[0034] 140: Insulation layer

[0035] 142: first insulating part

[0036] 144: Second insulating part

[0037] 146: The third insulating part

[0038] 150: Field plate structure

[0039] 152: First board section

[0040] 154: Second field board part

[0041] 156: The third board part

[0042] 400:Method

[0043] 402-416: Operation DETAILED DESCRIPTION

[0044] The following application provides many different embodiments or examples for implementing different features of the present application. Specific examples of the various components and arrangements of the present application are described below to simplify the description. Of course, these examples are not intended to limit the present application. For example, if the description has a first feature formed on or above a second feature, it may include an embodiment in which the first feature and the second feature are formed in direct contact, and it may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact. In addition, the present application may repeat reference numbers and / or letters in multiple examples. The purpose of this repetition is to simplify and clarify, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0045] Further, this application may use spatially relative terms, such as "below," "below," "below," "above," "above," and the like, to describe the relationship of one element or feature to other elements or features in the drawings. Spatially relative terms may also encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in different orientations (rotated 90 degrees or at other orientations), and the spatially relative terms used herein shall be interpreted accordingly.

[0046] Further, unless specifically denied, singular words include plural words and vice versa. In addition, the present application is not limited to the order of operations or events shown, as some operations can occur in different orders and / or simultaneously with other operations or events. In addition, not all operations or events shown are necessary to implement the methods of the present application.

[0047] Generally speaking, in a GaN high electron mobility transistor (HEMT) having an aluminum gallium nitride / gallium nitride (AlGaN / GaN) heterostructure, the source structure and the drain structure are finger-shaped structures in a top view, and the vertical portion of the finger structure of the source structure (also referred to as the finger portion) and the vertical portion of the finger structure of the drain structure are alternately arranged. However, the tip portion of the vertical portion of the drain structure has a higher electric field and thus generates a high concentration of hot carriers. After accumulation, these hot carriers caused by the high electric field may cause degradation of the performance of the HEMT device or even damage the HEMT device.

[0048] In order to solve the above problems, the present application provides a semiconductor device and a manufacturing method thereof to adjust the electric field at the tip portion of the drain structure. In this way, the peak value of the electric field can be reduced, so that the rising curve of the electric field becomes gentle to avoid a sharp change (sudden rise) of the electric field, and the electric field strength at the tip portion of the drain structure can be reduced to a level close to the electric field at the flat portion of the drain structure, so as to avoid creating an obvious weak point in the HEMT device. In this way, the performance of the HEMT device can be further avoided from being reduced or the HEMT device can be damaged, and the robustness and reliability of the HEMT device can be increased.

[0049] Figure 1 1 is a partial or entire top view of an exemplary semiconductor device 100 according to some embodiments of the present application. The semiconductor device 100 may be a single transistor device or an array of multiple transistor devices, wherein the transistor device is, for example, a GaN HEMT. In some embodiments, the semiconductor device 100 includes a source structure 110, a drain structure 120, and a gate structure 130 disposed above an epitaxial structure (e.g., the epitaxial structure 101 described below).

[0050] In some embodiments, the source structure 110 includes a horizontal source portion 112 extending along the X direction, and a vertical source portion (which may be referred to as a finger portion of the source structure) extending along the Y direction. In the Y direction, the vertical source portion includes a tip source portion 116 (which may be referred to as a fingertip portion of the source structure) away from the horizontal source portion 112, and a flat-end source portion 114 connecting the horizontal source portion 112 and the tip source portion 116.

[0051] In some embodiments, the drain structure 120 includes a horizontal drain portion 122 extending along the X direction, and a vertical drain portion (which may be referred to as a finger portion of the drain structure) extending along the Y direction perpendicular to the X direction. In the Y direction, the vertical drain portion includes a tip drain portion 126 (which may be referred to as a finger tip portion of the drain structure) away from the horizontal drain portion 122, and a flat-end drain portion 124 connecting the horizontal drain portion 122 and the tip drain portion 126.

[0052] In some embodiments, the horizontal source portion 112 and the horizontal drain portion 122 are spaced apart from each other along the Y direction, and the vertical source portion (including the flat-end source portion 114 and the pointed source portion 116) and the vertical drain portion (including the flat-end drain portion 124 and the pointed drain portion 126) are alternately disposed along the X direction, such as Figure 1The pointed source portion 116 of the source structure 110 points toward the horizontal drain portion 122 along the Y direction, while the pointed drain portion 126 of the drain structure 124 points toward the horizontal source portion 112 along the Y direction.

[0053] In some embodiments, the gate structure 130 is disposed between the source structure 110 and the drain structure 120, and surrounds at least a portion of the source structure 110 and the drain structure 120. For example, the gate structure 130 surrounds the vertical source portion (including the flat-end source portion 114 and the pointed source portion 116) and the vertical drain portion (including the flat-end drain portion 124 and the pointed drain portion 126), such as Figure 1 As shown. The gate structure 130 can be a continuous whole and continuously extends to be shared by multiple transistor devices. In some embodiments, the distance between the gate structure 130 and the source structure 110 is smaller than the distance between the gate structure 130 and the drain structure 120. For the sake of clarity, the gate structure 130 is divided into a first gate portion 132, a second gate portion 134, and a third gate portion 136 having the same stacking structure.

[0054] exist Figure 1 In the illustrated embodiment, the first gate portion 132 is located between the two flat-ended source portions 114 in the X direction, and between the pointed drain portion 126 and the horizontal source portion 112 in the Y direction. The second gate portion 134 is located between the two flat-ended drain portions 124 in the X direction, and between the pointed source portion 116 and the horizontal drain portion 122 in the Y direction. The third gate portion 136 is located between a vertical source portion (including the flat-ended source portion 114 and the pointed source portion 116) and a vertical drain portion (including the flat-ended drain portion 124 and the pointed drain portion 126) in the X direction, and between the horizontal source portion 112 and the horizontal drain portion 122 in the Y direction. The third gate portion 136 is connected to each other through the first gate portion 132 and the second gate portion 134, or the first gate portion 132 and the second gate portion 134 are connected to each other through the third gate portion 136. In some embodiments, the first gate portion 132 and the second gate portion 134 are located in a top view (e.g., Figure 1 ) is arc-shaped.

[0055] In some embodiments, the semiconductor device 100 further includes an insulating layer 140. The insulating layer 140 is disposed above the epitaxial structure (e.g., the epitaxial structure 101 described below) and below the tip drain portion 126 of the drain structure 120. In some embodiments, an end of the insulating layer 140 close to the first gate portion 132 has an arc-shaped profile, such as Figure 1 shown.

[0056] In some embodiments, the semiconductor device 100 further includes a field plate structure 150. The field plate structure 150 surrounds and contacts the drain structure 120. For example, the field plate structure 150 includes a first field plate portion 152 in contact with the tip drain portion 126, and a second field plate portion 154 in contact with the flat-end drain portion 124 and the horizontal drain portion 122. In some embodiments, the first field plate portion 152 in contact with the tip drain portion 126 is disposed on the insulating layer 140, while the second field plate portion 154 is not disposed on the insulating layer 140, so that the first field plate portion 152 and the second field plate portion 154 form a stepped structure, which will be described in more detail below. In some embodiments, an end of the first field plate portion 152 close to the first gate portion 132 has an arc-shaped profile, such as Figure 1 shown.

[0057] According to some embodiments, Figure 2A The semiconductor device 100 is Figure 1 The cross-sectional view of the line segment A-A', and Figure 2B The semiconductor device 100 is Figure 1 Cross-sectional view of line segment BB'. Figure 2A A cross-sectional view including the flat-ended drain portion 124 and the second field plate portion 154 along the X direction is shown, and Figure 2B A cross-sectional view including the tip drain portion 126 , the insulating layer 140 , and the first field plate portion 152 along the X direction is shown.

[0058] Reference Figure 2A and Figure 2B , the semiconductor device 100 includes an epitaxial structure 101, wherein the epitaxial structure 101 includes a substrate 102, a buffer layer 103 above the substrate 102, a channel layer 104 above the buffer layer 103, and a barrier layer 105 above the channel layer 104. In some embodiments, the buffer layer 103 and the channel layer 104 may be combined together and collectively referred to as a buffer layer or a channel layer.

[0059] In some embodiments, the material of the channel layer 104 is GaN, and the material of the barrier layer 105 is AlGaN. A GaN / AlGaN heterojunction formed by stacking the channel layer 104 and the barrier layer 105 forms a two-dimensional electron gas (2DEG) between the channel layer 104 and the barrier layer 105, which serves as a channel of the semiconductor device 100 (drawn by dotted lines). In some embodiments, the semiconductor device 100 further includes a passivation layer 106 disposed on the barrier layer 105, wherein the material of the passivation layer 106 is, for example, silicon nitride (SiN). It should be noted that, in order to simplify the description, the passivation layer 106 is not shown in FIG. Figure 1 The passivation layer 106 is shown in the top view of FIG.

[0060] The source structure 110, the drain structure 120 and the gate structure 130 are disposed above the epitaxial structure 101, for example, above the barrier layer 105, and are disposed in the trench of the passivation layer 106. The gate structure 130 is disposed between the source structure 110 and the drain structure 120. Figure 2A As shown, the third gate portion 136 of the gate structure 130 is disposed between the flat-end source portion 114 of the source structure 110 and the flat-end drain portion 124 of the drain structure 120 along the X direction. Figure 2B As shown, the third gate portion 136 is disposed between the flat-ended source portion 114 and the pointed drain portion 126 of the drain structure 120 along the X direction.

[0061] Reference Figure 2A The flat-end drain portion 124 is disposed on the barrier layer 105 in the trench of the passivation layer 106 , and the second field plate portion 154 in contact with the flat-end drain portion 124 is disposed on the passivation layer 106 . Figure 2A In the illustrated embodiment, the second field plate portion 154 contacts the sidewalls of the flat end drain portion 124. In some embodiments, the top surface of the second field plate portion 154 is coplanar with the top surface of the flat end drain portion 124. In other embodiments, the top surface of the second field plate portion 154 can be higher or lower than the top surface of the flat end drain portion 124. In further embodiments, the second field plate portion 154 can partially cover the top surface of the flat end drain portion 124.

[0062] Reference Figure 2B In the region where the tip drain portion 126 belongs, the semiconductor device 100 includes an insulating layer 140. The insulating layer 140 includes a first insulating portion 142 directly disposed on the barrier layer 105 in the trench of the passivation layer 106, and a second insulating portion 144 directly disposed on the passivation layer 106. Figure 2B In the illustrated embodiment, a portion of the tip drain portion 126 is disposed on the first insulating portion 142, such that the tip drain portion 126 is Figure 2B In these embodiments, because the insulating layer 140 does not fill the bottom of the tip drain portion 126, the insulating layer 140 is U-shaped in a top view.

[0063] In other embodiments, the insulating layer 140 includes only the second insulating portion 144 but not the first insulating portion 142, so that the entire tip drain portion 126 is directly disposed on the barrier layer 105 and in contact with the passivation layer 106, similar to Figure 2AIn some other embodiments, in the region where the tip drain portion 126 belongs, the first insulating portion 142 of the insulating layer 140 extends and covers the entire barrier layer 105 in the trench of the passivation layer 106, so that the entire tip drain portion 126 is disposed on the first insulating portion 142 of the insulating layer 140.

[0064] Still refer to Figure 2B , a first field plate portion 152 in contact with the tip drain portion 126 is disposed on the second insulating portion 144. Figure 2B In the illustrated embodiment, the first field plate portion 152 contacts the sidewalls of the tip drain portion 126. In some embodiments, the top surface of the first field plate portion 152 is coplanar with the top surface of the tip drain portion 126. In other embodiments, the top surface of the first field plate portion 152 can be higher or lower than the top surface of the tip drain portion 126. In further embodiments, the first field plate portion 152 can partially cover the top surface of the tip drain portion 126.

[0065] like Figure 2A as well as Figure 2B As shown, due to the presence of the insulating layer 140, the first field plate portion 152 disposed on the second insulating portion 144 is higher than the second field plate portion 154 disposed on the passivation layer 106, so that the first field plate portion 152 and the second field plate portion 154 form a stepped structure. In other words, the field plate structure 150 has a stepped structure.

[0066] In other embodiments, the semiconductor device 100 may not include the passivation layer 106. In these embodiments, the insulating layer 140 may be directly disposed on the blocking layer 105, the second field plate portion 154 may be directly disposed on the blocking layer 106, and the first field plate portion 152 may also be disposed on the second insulating portion 144. In this way, the first field plate portion 152 disposed on the second insulating portion 144 is also higher than the second field plate portion 154 disposed on the blocking layer 105, so that the first field plate portion 152 and the second field plate portion 154 also form a stepped structure.

[0067] According to some embodiments, Figure 2C The semiconductor device 100 is Figure 1 The cross-sectional view of the line segment C-C', and Figure 2D The semiconductor device 100 is Figure 1 Cross-sectional view of line segment D-D'. Figure 2C A cross-sectional view including the insulating layer 140, the first field plate portion 152, the tip drain portion 126 and the flat end drain portion 124 along the Y direction is shown. Figure 2DA cross-sectional view including the insulating layer 140 , the first field plate portion 152 , and the second field plate portion 154 along the Y direction is shown.

[0068] Reference Figure 2C , the first gate portion 132 of the gate structure 130 is disposed along the Y direction between the horizontal source portion 112 of the source structure 110 and the tip drain portion 126 of the drain structure 120. As described above, a portion of the tip drain portion 126 is disposed on the first insulating portion 142 of the insulating layer 140, and the first field plate portion 152 in contact with the tip drain portion 126 is disposed on the second insulating portion 144 of the insulating layer 140. Also as described above, in other embodiments, the insulating layer 140 includes only the second insulating portion 144 and the tip drain portion 126 is directly disposed on the blocking layer 105, and in still other embodiments, the first insulating portion 142 extends so that the entire tip drain portion 126 is disposed on the first insulating portion 142.

[0069] exist Figure 2C In the illustrated embodiment, the vertical drain portion (including the tip drain portion 126 and the flat end drain portion 124) has a stepped top surface. In other embodiments, more drain material may be deposited to make the vertical drain portion have a substantially flat top surface. Since the insulating layer 140 includes a first insulating portion 142 disposed on the barrier layer 105 and a second insulating portion 144 disposed on the passivation layer 106, Figure 2B and Figure 2C In the cross-sectional view, the insulating layer 140 also has a stepped structure.

[0070] Reference Figure 2D , a first field plate portion 152 in contact with the tip drain portion 126 is disposed on the second insulating portion 144, and a second field plate portion 154 in contact with the flat end drain portion 124 is disposed on the passivation layer 106. Figure 2D As shown, the first field plate portion 152 and the second field plate portion 154 form a stepped structure. In other words, the field plate structure 150 has a stepped structure. Figure 2D As shown, the top surface of the first field plate portion 152 is higher than the top surface of the second field plate portion 154 .

[0071] As described above, the present application provides a stepped field plate structure having a higher first field plate portion in contact with the tip drain portion, and a lower second field plate portion in contact with the flat end drain portion. The field plate structure can be used to adjust the electric field strength, such as reducing the peak value of the electric field, and making the rising curve of the electric field become gentle to avoid a sharp rise in the electric field. In this way, the high electric field of the drain structure can be prevented from causing damage to the semiconductor device.

[0072] Furthermore, by using an insulating layer to pad the field plate structure at the tip drain portion, a multi-stage first field plate portion with better effect can be formed. In this way, the electric field at the tip drain portion that is subjected to the highest electric field can be adjusted more effectively. At the same time, the present application uses a single-stage second field plate portion that is not padded by the insulating layer in the flat end drain portion. That is to say, the present application uses a multi-stage first field plate portion with better effect in the tip drain portion with the highest electric field, and uses a single-stage second field plate portion that is not as effective as the multi-stage field plate in the flat end drain portion with a relatively low electric field. In this way, the electric field of the tip drain portion and the electric field of the flat end drain portion can be reduced to a similar level, while avoiding the tip drain portion still having a relatively highest electric field due to the use of the same field plate structure with similar effects in the entire drain structure. In this way, in addition to reducing the electric field of the overall drain structure, it is also possible to avoid leaving a relatively high electric field weakness in the drain structure, thereby avoiding damage to the performance or structure of the semiconductor device, and increasing the robustness and reliability of the semiconductor device. In addition, the insulating layer used to raise the second field plate portion can also be used to reduce leakage at the tip drain portion.

[0073] Figure 3 According to other embodiments of the present application, the semiconductor device 100 is arranged along Figure 1 Schematic cross-sectional view of line segment CC'. Figure 3 Similar to Figure 2C , the difference is that, Figure 3 The third insulating portion 146 and the third field plate portion 156 are further included. As shown in the figure, the third insulating portion 146 and the first field plate portion 152 are disposed on the second insulating portion 144, and the third field plate portion 156 is disposed on the third insulating portion 146 and the first field plate portion 152. In some embodiments, the third field plate portion 156 does not overlap with the first field plate portion 152, but is only disposed on the third insulating portion 146.

[0074] By disposing the third field plate portion 156 on the third insulating portion 146, a field plate structure 150 with more steps can be formed. For example, the third field plate portion 156, the first field plate portion 152, the second insulating portion 144, and the third insulating portion 146 form a stepped structure with more steps. At the same time, the third field plate portion 156, the first field plate portion 152, and the second field plate portion 154 also form a stepped structure with more steps. By forming a field plate structure with more steps (for example, the third field plate portion 156 and the first field plate portion 152) on the tip drain portion 126, the electric field at the tip drain portion can be adjusted more effectively.

[0075] In a further embodiment, a ratio Figure 3In other embodiments, a field plate structure with more levels can also be formed in the region where the flat drain portion 124 belongs (but the number of levels is less than the field plate structure in the region where the tip drain portion 126 belongs) to more effectively adjust the electric field of the drain structure.

[0076] Figure 4 is a flowchart of a method 400 for forming a semiconductor device 100 according to some embodiments of the present application. Figures 1 to 3 To Figure 4 Provide explanation.

[0077] In operation 402, the method 400 provides or receives an epitaxial structure, such as the epitaxial structure 101 described above. The epitaxial structure 101 includes a substrate 102, a buffer layer 103 on the substrate 102, a channel layer 104 on the buffer layer 103, and a barrier layer 105 on the channel layer 104. In some embodiments, the buffer layer 103 and the channel layer 104 may be combined and collectively referred to as a buffer layer or a channel layer.

[0078] In operation 404, the method 400 forms a passivation layer 106 on the epitaxial structure 101, for example, by forming the passivation layer 106 on the barrier layer 105 of the epitaxial structure 101 through a suitable deposition process. The material of the passivation layer 106 is, for example, silicon nitride (SiN) or silicon oxynitride (SiON). Suitable deposition processes may include physical vapor deposition (PVD), chemical vapor deposition (CVD), coating processes, other suitable processes, or combinations thereof. The PVD process may include sputtering, evaporation, and / or pulsed laser deposition. The CVD process may include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), atomic layer deposition (ALD) process, electroplating, other suitable processes, and / or combinations thereof.

[0079] In operation 406, the method 400 patterns the passivation layer 106 to form source trenches and drain trenches that expose the blocking layer 105. For example, the patterning of the passivation layer 106 can be performed by suitable photolithography and etching processes. In some embodiments, the photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). In other embodiments, the photolithography process can be performed by other suitable methods, such as maskless lithography, electron beam (e-beam) writing, and ion beam writing. In some embodiments, the etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0080] In operation 408, method 400 forms an insulating layer 140 on a portion of barrier layer 105 in the drain trench and on a portion of passivation layer 106. In some embodiments, insulating layer 140 includes a first insulating portion 142 disposed directly on barrier layer 105 in the drain trench and a second insulating portion 144 disposed directly on passivation layer 106, such as Figure 2B and Figure 2C In some embodiments, the insulating layer 140 only includes a second insulating portion 144 disposed on the passivation layer 106 . In other embodiments, the insulating layer 140 also includes a third insulating portion 146 disposed on the second insulating portion 144 .

[0081] In some embodiments, an insulating material may be first deposited on the passivation layer 106 and the barrier layer 105 in the source trench and the drain trench by a suitable deposition process, and then patterned by a suitable photolithography and etching process to form the insulating layer 140. For example, the insulating material may include silicon nitride, silicon oxide, silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), other suitable insulating materials, or combinations thereof.

[0082] In operation 410, the method 400 forms a source structure 110 in a source trench and forms a drain structure 120 in a drain trench. Figure 1 As shown, the source structure 110 includes a horizontal source portion 112 extending along the X direction and a vertical source portion extending along the Y direction (including a flat-end source portion 114 and a pointed source portion 116), while the drain structure 120 includes a horizontal drain portion 122 extending along the X direction and a vertical drain portion extending along the Y direction (including a flat-end drain portion 124 and a pointed drain portion 126).

[0083] In some embodiments, a portion of the tip drain portion 126 is disposed on the first insulating portion 142, and the remaining portion of the tip drain portion 126 is disposed on the barrier layer 105 together with the flat end drain portion 124 and the horizontal drain portion 122, such as Figure 2B and Figure 2C In the embodiment where the insulating layer 140 only includes the second insulating portion 144 , the entire tip drain portion 126 is disposed on the barrier layer 105 . In some other embodiments, the entire tip drain portion 126 is disposed on the first insulating portion 142 of the insulating layer 140 .

[0084] In some embodiments, operation 410 forms a patterned photoresist layer including openings over the passivation layer 106 and the insulating layer 140 by a photolithography process, wherein the openings expose regions (e.g., source and drain trenches) where the source structure 110 and the drain structure 120 are to be formed. Next, a conductive material is deposited over the patterned photoresist layer by a deposition process, and then the patterned photoresist layer and the conductive material on the patterned photoresist layer are removed by a photoresist lift-off process, so as to leave the conductive material in the openings as the source structure 110 and the drain structure 120.

[0085] In other embodiments, operation 410 may first deposit a conductive material on the barrier layer 105 and the insulating layer 140 through a deposition process, and then pattern the deposited conductive material through photolithography and etching processes to form the source structure 110 and the drain structure 120. The conductive material used for the source structure 110 and the drain structure 120 may include aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), ruthenium (Ru), palladium (Pd), platinum (Pt), manganese (Mn), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), tungsten silicide (WSi), titanium silicide (TiSi2), other suitable conductive materials or combinations thereof.

[0086] In operation 412, the method 400 forms a field plate structure 150 on the passivation layer 106 and the insulating layer 140. The field plate structure 150 includes a first field plate portion 152 disposed on the second insulating portion 144 of the insulating layer 140 and in contact with the tip drain portion 126 (see FIG. Figure 2B and Figure 2C ), and a second field plate portion 154 disposed on the passivation layer 105 and in contact with the flat-ended drain portion 124 (see Figure 2A ). The first field plate portion 152 and the second field plate portion 154 form a stepped structure, such as Figure 2D shown.

[0087] In other embodiments, the field plate structure 150 further includes a third field plate portion 156 disposed on the third insulating portion 146 on the second insulating portion 144, such as Figure 3 The third field plate portion 156, the first field plate portion 152 and the second field plate portion 154 form a stepped structure. In further embodiments, more layers of insulating portions and field plate structures may be formed to form a stepped field plate structure with more levels.

[0088] In some embodiments, operation 410 and operation 412 are performed simultaneously, and the field plate structure 150 includes the same material as the source structure 110 and the drain structure 120. In other embodiments, operation 410 and operation 412 are performed separately. In these embodiments, operation 412 includes a process similar to operation 410, and the field plate structure 150 may include the same or different conductive material as the source structure 110 and the drain structure 120. In some embodiments, an annealing process may be performed after operation 410 and / or operation 412.

[0089] In operation 414, the method 400 forms a gate trench in the passivation layer 106. Operation 414 may form a gate trench in the passivation layer 106 by the same or similar method as operation 406.

[0090] In operation 416, method 400 forms a gate structure 130 in the gate trench. Operation 416 may form the gate structure 130 in the gate trench by the same or similar method as operation 410. The gate structure 130 may include a conductive material, such as Al, Cu, Au, Ag, W, Ti, Ta, Ni, Co, Ru, Pd, Pt, Mn, WN, TiN, TaN, MoN, WSi, TiSi2, other suitable conductive materials, or combinations thereof.

[0091] like Figure 1 As shown, the gate structure 130 includes a first gate portion 132, a second gate portion 134, and a third gate portion 136. The first gate portion 132 is located between the tip drain portion 126 and the horizontal source portion 112 in the Y direction. The second gate portion 134 is located between the tip source portion 116 and the horizontal drain portion 122 in the Y direction. The third gate portion 136 is located between a vertical source portion and a vertical drain portion in the X direction.

[0092] It should be noted that additional operations may be provided before, during, or after the method 400, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of the method 400. For example, a gate dielectric layer may be deposited to form a metal insulator semiconductor (MIS) structure, a gate recess or p-type gallium nitride epitaxial layer may be formed to form an enhancement mode (E-mode) device, and various interlayer dielectric (ILD) layers and interconnect structures may be formed.

[0093] The foregoing text summarizes the features of multiple embodiments or examples so that those skilled in the art can better understand the present application. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the present application to achieve the same purpose and / or achieve the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present application, and various changes, substitutions and modifications can be made to the present application without departing from the spirit and scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: a substrate; a channel layer disposed above the substrate; a barrier layer disposed above the channel layer; a source structure disposed above the barrier layer, the source structure comprising a horizontal source portion extending along a first direction, and at least one vertical source portion extending along a second direction perpendicular to the first direction; a drain structure disposed above the barrier layer, the drain structure comprising a horizontal drain portion extending along the first direction and at least one vertical drain portion extending along the second direction, wherein each of the at least one vertical drain portion comprises a tip drain portion and a flat-end drain portion connecting the horizontal drain portion and the tip drain portion; a gate structure disposed above the barrier layer and between the source structure and the drain structure; as well as A field plate structure is disposed above the barrier layer, wherein the field plate structure contacts and surrounds the drain structure.

2. The semiconductor device according to claim 1, wherein: It also includes an insulating layer, which is arranged above the blocking layer, wherein at least a portion of the tip drain portion is arranged above the insulating layer, and a first field plate portion of the field plate structure that contacts the tip drain portion is also arranged above the insulating layer, while a second field plate portion of the field plate structure that contacts the flat end drain portion is not arranged above the insulating layer.

3. The semiconductor device according to claim 2, wherein: The invention also comprises a passivation layer, wherein the passivation layer is arranged above the blocking layer, wherein the insulating layer comprises a first insulating portion directly arranged on the blocking layer and a second insulating portion directly arranged on the passivation layer.

4. The semiconductor device according to claim 3, wherein: The at least a portion of the tip drain portion is disposed on the first insulating portion, and the first field plate portion is disposed on the second insulating portion.

5. The semiconductor device according to claim 4, wherein: The second field plate portion is directly disposed on the passivation layer, so that the first field plate portion and the second field plate portion form a stepped structure.

6. The semiconductor device according to claim 5, wherein: The insulating layer further includes a third insulating portion disposed on the second insulating portion; and The field plate structure further includes a third field plate portion disposed on the third insulating portion, such that the third field plate portion, the first field plate portion and the second field plate portion form a stepped structure.

7. A method for forming a semiconductor device, characterized in that: include: Providing an epitaxial structure, the epitaxial structure comprising a substrate, a channel layer above the substrate, and a barrier layer above the channel layer; forming a passivation layer over the barrier layer; Patterning the passivation layer to form a source trench and a drain trench exposing the barrier layer; forming an insulating layer on a portion of the barrier layer in the drain trench and on a portion of the passivation layer, wherein the insulating layer comprises a first insulating portion in the drain trench and a second insulating portion on the passivation layer; forming a source structure in the source trench and forming a drain structure in the drain trench, wherein the drain structure comprises a horizontal drain portion extending along a first direction and a vertical drain portion extending along a second direction perpendicular to the first direction, and the vertical drain portion comprises a tip drain portion and a flat-end drain portion connecting the horizontal drain portion and the tip drain portion, and at least a portion of the tip drain portion is formed on the first insulating portion; as well as A field plate structure is formed on the insulating layer and the passivation layer, wherein the field plate structure includes a first field plate portion contacting the tip drain portion and a second field plate portion contacting the flat end drain portion.

8. The method for forming a semiconductor device according to claim 7, wherein: The first field plate portion of the field plate structure is disposed on the second insulating portion, and the second field plate portion of the field plate structure is disposed on the passivation layer, so that the first field plate portion and the second field plate form a stepped structure.

9. The method for forming a semiconductor device according to claim 8, wherein: The insulating layer further includes a third insulating portion disposed on the second insulating portion; and The field plate structure further includes a third field plate portion disposed on the third insulating portion, such that the third field plate portion, the first field plate portion and the second field plate portion form a stepped structure.

10. The method for forming a semiconductor device according to claim 7, wherein: The source structure includes a horizontal source portion extending along the first direction and a vertical source portion extending along the second direction, and the method for forming the semiconductor device further includes: forming a gate trench in the passivation layer; and A gate structure is formed in the gate trench, wherein the gate structure includes a first gate portion between the horizontal source portion and the tip drain portion of the vertical drain portion, and a second gate portion between the vertical source portion and the vertical drain portion.

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