Semiconductor device and radio frequency module
By designing the drainage injection area of the gradient in semiconductor device, optimize the distribution of electric field between the drain and the gate, solve the problem of uneven distribution of electric field, and improve the power level and overall performance of HEMT.
Patent Information
- Application Number
- CN202411226655.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-03
- Publication Date
- 2025-01-24
AI Technical Summary
In semiconductor devices, the semiconductor material below the drain forms local charge accumulation through ion implantation, resulting in uneven electric field distribution, which in turn reduces the operating voltage and affects device performance.
Design a semiconductor device in which the drain ion implantation region extends from the bottom of the drain toward the gate, and gradient regions with different ion doping concentrations are set up at different locations to ensure that the ion doping concentration of the drain ion implantation region is within the range of the drain. The area between the gate and the gate is larger, optimizing the electric field distribution.
By optimizing the distribution of electric field between the drain and the gate, the power level of HEMT is improved, the peak value of the electric field is reduced, and the more uniform electric field distribution is achieved, thereby improving the overall performance of semiconductor devices.
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Figure CN119364797A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a radio frequency module. Background Art
[0002] In semiconductor devices, the source and drain are key parts of the semiconductor device, and their ohmic contact resistance with the semiconductor material has a crucial impact on the overall performance of the device. In order to improve the performance of semiconductor devices, ion implantation is usually performed under the source and drain to reduce the ohmic contact resistance between the source, drain and epitaxial structure. However, ion implantation will cause local charge accumulation in the semiconductor material under the drain, resulting in uneven electric field distribution, which in turn reduces the operating voltage and affects the performance of the device.
[0003] Therefore, how to optimize the electric field distribution on the drain side is a problem that those skilled in the art currently need to solve. Summary of the invention
[0004] The present invention provides a semiconductor device, which can solve at least one problem in the background technology to effectively optimize the electric field distribution and improve the electrical characteristics of HEMT.
[0005] In a first aspect, the present invention provides a semiconductor device, comprising a substrate, an epitaxial structure, a source, a drain, a gate and a drain ion implantation region.
[0006] The epitaxial structure is located on the substrate; the epitaxial structure at least includes a channel layer located on the substrate and a barrier layer located on the channel layer; the source electrode covers the epitaxial structure; the drain electrode covers the epitaxial structure; the gate electrode is located between the source electrode and the drain electrode; the drain ion implantation region extends from the surface of the epitaxial structure close to the drain electrode side to the substrate direction to the channel layer, and the drain ion implantation region is located below the drain electrode and extends in the direction close to the gate electrode side;
[0007] The ion doping concentration of the drain ion implantation region located in the orthographic projection region of the drain on the substrate is greater than the ion doping concentration of the drain ion implantation region on the side closest to the gate.
[0008] Furthermore, in the gate length direction, the distance from the drain to the gate is Lgd, and the distance from the drain to the edge of the drain ion implantation region closest to the gate is L1, wherein 0.005≤L1 / Lgd≤0.5.
[0009] Furthermore, a distance L1 from the drain to an edge of the drain ion implantation region closest to the gate is between 0.1 μm and 1 μm.
[0010] Furthermore, the thickness of the barrier layer is d1, the depth of the drain ion implantation region is H, and H≥2*d1.
[0011] Furthermore, the thickness d1 of the barrier layer is between 5 and 30 nm; the thickness d2 of the channel layer is between 50 and 800 nm.
[0012] Furthermore, the drain ion implantation region has a peak implantation concentration, and a distance D1 from a depth position where the peak implantation concentration is located to a surface of the epitaxial structure away from the substrate is between 5 and 50 nm.
[0013] Furthermore, the drain ion implantation region has a peak implantation concentration, and a distance D2 from a depth position where the peak implantation concentration is located to an interface between the barrier layer and the channel layer is between 0 and 10 nm.
[0014] Furthermore, the peak implantation concentration of the drain ion implantation region decreases from the bottom of the drain toward the gate.
[0015] Furthermore, the surface of the epitaxial structure includes a first table in contact with the drain and a second table not in contact with the source, drain or gate; looking down at the epitaxial structure from the semiconductor device, the drain ion implantation region includes a contact doping region located within the first table and an extended doping region located within the second table, and the peak implantation concentration of the contact doping region is greater than the peak implantation concentration of the extended doping region.
[0016] Furthermore, the ion doping concentration of the contact doping region is between 10 17 ~10 22 cm -3 ; The ion doping concentration of the extended doping region is between 10 15 ~10 21 cm -3 .
[0017] Furthermore, the drain ion implantation region includes a plurality of gradient regions arranged in sequence from the bottom of the drain to the side close to the gate, and the peak implantation concentration of each gradient region increases step by step from the side close to the gate to the side far from the gate.
[0018] Furthermore, the drain ion injection region includes a first gradient region, a second gradient region and a third gradient region arranged in sequence from the bottom of the drain toward the gate side; the ion doping concentration of the first gradient region is greater than the ion doping concentration of the second gradient region, and the ion doping concentration of the second gradient region is greater than the ion doping concentration of the third gradient region.
[0019] Furthermore, the peak injection concentration in the first gradient zone is between 10 18 ~10 22 cm -3 The ratio of the peak injection concentration in the first gradient zone to the peak injection concentration in the second gradient zone is between 2 and 100, and the ratio of the peak injection concentration in the second gradient zone to the peak injection concentration in the third gradient zone is between 2 and 100.
[0020] Furthermore, the width of the first gradient region is greater than the width of the second gradient region, and / or the width of the first gradient region is greater than the width of the third gradient region.
[0021] Furthermore, the depth of the first gradient zone is greater than the depth of the second gradient zone, and the depth of the second gradient zone is greater than the depth of the third gradient zone.
[0022] Furthermore, an orthographic projection area of the first gradient region on the substrate at least partially overlaps with an orthographic projection area of the drain on the substrate.
[0023] Furthermore, the semiconductor device also includes a source ion implantation region extending from the surface of the epitaxial structure close to the source toward the substrate to the channel layer, and the orthographic projection area of the source ion implantation region on the substrate at least partially overlaps with the orthographic projection area of the source on the substrate.
[0024] Furthermore, the thickness of the barrier layer is d1, the depth of the source ion implantation region is h, h≥2*d1; the ion doping concentration of the source ion implantation region is between 10 15 ~10 22 cm -3 .
[0025] In a second aspect, the present invention further provides a radio frequency module, comprising the above-mentioned semiconductor device.
[0026] The semiconductor device provided by the present invention can effectively optimize the electric field distribution between the drain and the gate and improve the power level of the HEMT by designing the drain ion implantation region.
[0027] Other features and advantages of the present invention will be set forth in the following description, and in part will be apparent from the description, or may be learned by practicing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0029] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor device provided by an embodiment of the present invention;
[0030] Figure 2 is a schematic diagram of the change in ion doping concentration in the drain ion implantation region along the depth direction in one embodiment of the present invention;
[0031] Figure 3 , Figure 4 , Figure 5 , Figure 8 is a schematic cross-sectional structural diagram of a semiconductor device provided by another embodiment of the present invention;
[0032] Figure 6 It is a schematic diagram of the electric field distribution of the conventional drain ion implantation region in the prior art;
[0033] Figure 7 Schematic diagram of electric field distribution in the drain ion implantation region in an embodiment of the present invention.
[0034] Reference numerals:
[0035] 10-substrate; 20-epitaxial structure; 21-channel layer; 22-barrier layer; 23-buffer layer; 30-drain ion implantation region; 41-drain; 42-source; 43-gate; 50-source ion implantation region; S1-first table; S2-second table; 31'-contact doping region; 32'-extended doping region; 31-first gradient region; 32-second gradient region; 33-third gradient region. DETAILED DESCRIPTION
[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0037] See also Figure 1 , Figure 1 1 is a cross-sectional view of a semiconductor device provided by an embodiment of the present invention. To achieve at least one of the advantages or other advantages, the present invention provides a semiconductor device including at least a substrate 10, an epitaxial structure 20, a source 42, a drain 41, a gate 43 and a drain ion implantation region 30.
[0038] The epitaxial structure 20 is located on the substrate 10; wherein the substrate 10 can be a base material for carrying semiconductor integrated circuit components that is well known to those skilled in the art, usually a heterogeneous substrate such as silicon (Si), silicon carbide (SiC), sapphire (Saphhire), gallium nitride (GaN), etc., which is not limited here.
[0039] The epitaxial structure 20 may be grown on the substrate 10 by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other processes, which are not limited in this embodiment and may be reasonably selected according to actual needs.
[0040] The epitaxial structure 20 includes a group III nitride heterojunction. In some embodiments, the epitaxial structure 20 includes at least a channel layer 21 located on the substrate 10 and a barrier layer 22 located on the channel layer 21; a heterojunction is formed between the channel layer 21 and the barrier layer 22 to form a two-dimensional electron gas. As an example, the barrier layer 22 can be a layer or a stack of aluminum nitride, aluminum indium nitride, aluminum gallium nitride, indium gallium nitride or aluminum indium gallium nitride. Preferably, the thickness d1 of the barrier layer 22 is between 5nm and 30nm. The material of the channel layer 21 can be gallium nitride or aluminum gallium nitride. Preferably, the thickness d2 of the channel layer 21 is between 50 and 800nm.
[0041] It should be noted that, according to the actual needs of the semiconductor device, the epitaxial structure 20 can also be provided with at least one of the functional layers (not shown in the figure) such as a nucleation layer, a transition layer, an insertion layer, and a cap layer, which are not limited here. For example, an AlN insertion layer is provided between the channel layer 21 and the barrier layer 22. The thickness of the AlN insertion layer can be in the range of 0.5nm to 2nm. The AlN insertion layer can increase the channel electron density and electron mobility, and improve the effect of the heterogeneous interface. For another example, a nucleation layer is provided between the substrate 10 and the channel layer 21. As an example, the material of the nucleation layer is AlN, and the thickness is 10nm to 50nm; the nucleation layer can release the mismatch stress caused by the lattice mismatch between the buffer layer 23 and the substrate 10 and the thermal stress caused by the thermal expansion coefficient, optimize the flatness of the surface of the nucleation layer, and make the growth of the epitaxial layer have lower defects.
[0042] The source 42 and the drain 41 are covered on the epitaxial structure 20. The structure, size, and material of the source 42 and the drain 41 can be the same or different, and are specifically set according to actual working requirements, and are not limited here. As an example, the material of the source 42 and the drain 41 can be nickel, gold, titanium, aluminum, platinum, chromium or other metals or their alloys or stacks, such as Ti / Au metal stacks, so as to form ohmic contact with the epitaxial structure 20 through high temperature annealing.
[0043] The gate 43 covers the epitaxial structure 20 and is located between the source 42 and the drain 41. The gate 43 can be designed into a T-type gate or a groove gate according to the needs to effectively reduce the short channel effect of the device. The specific structure is not limited here. The material of the gate 43 can be a metal such as Ni, Ag, Cu, Co, Pu, Ni, Pt, Au, or its alloy or its stack. It is generally made by electrochemical deposition, electron beam evaporation or sputtering process. The Schottky contact is not annealed. The Schottky contact can be formed after the gate 43 is made.
[0044] In this embodiment, the semiconductor device further includes a passivation dielectric layer (not shown in the figure), and the passivation dielectric layer covers part of the barrier layer 22. The material of the passivation dielectric layer can be selected from one or a combination of SiO2, SiN, Al2O3, and SiON, which is not limited in the embodiment of the present invention. By designing the passivation dielectric layer, it is possible to effectively prevent external charged particles or debris from affecting the normal operation of the HEMT. More preferably, a passivation protection layer (not shown in the figure) is deposited on the passivation dielectric layer to protect the gate 43, the drain 41 and the source 42. Among them, the passivation protection layer is preferably a SiN layer to isolate water vapor and protect the device. According to requirements, other passivation structures can be provided on the outside of the passivation protection layer.
[0045] In order to improve the performance of the semiconductor device, the semiconductor device of this embodiment further includes a drain ion implantation region 30. Among them, the implanted ions in the drain ion implantation region 30 preferably include silicon. The angle of ion implantation from the surface of the epitaxial structure 20 can be vertical implantation or implantation at a certain angle, which is specifically designed according to actual needs and is not limited here. The drain ion implantation region 30 extends from the surface of the epitaxial structure 20 close to the drain 41 side toward the substrate 10 to the channel layer 21 to further reduce the sheet resistance and optimize the ohmic contact.
[0046] The drain ion implantation region 30 is located below the drain 41 and extends toward the side close to the gate 43, and the ion doping concentration of the drain ion implantation region 30 located in the orthogonal projection region of the drain 41 on the substrate 10 is greater than the ion doping concentration of the drain ion implantation region 30 closest to the gate 43. Specifically, the drain ion implantation region 30 includes a portion located in the orthogonal projection region of the drain 41 on the substrate 10 and a portion located outside the orthogonal projection region of the drain 41 on the substrate 10. Among them, the ion doping concentration of the portion located in the orthogonal projection region of the drain 41 on the substrate 10 is greater than the ion doping concentration of the portion located in the region outside the orthogonal projection region of the drain 41 on the substrate 10 closest to the gate 43. It should be noted that the ion doping concentration of the drain ion injection region 30 is greater than the ion doping concentration of the drain ion injection region 30 on the side closest to the gate 43. The peak injection concentration of the drain ion injection region 30 is greater than the peak injection concentration of the drain ion injection region 30 on the side closest to the gate 43, or the average ion doping concentration of the drain ion injection region 30 is greater than the average ion doping concentration of the drain ion injection region 30 on the side closest to the gate 43.
[0047] Compared with the traditional ion implantation region with the same ion doping concentration, the design of different ion doping concentrations at different positions of the drain ion implantation region 30 in this embodiment can effectively weaken the dense electric field distribution near the drain ion implantation region 30 closest to the gate 43, reduce the electric field peak, and make the electric field more evenly distributed in the channel, thereby achieving a higher operating voltage and improving the power level of the semiconductor device. In addition, compared with the traditional ion implantation region that is only located below the drain 41 and does not extend toward the gate 43, in this embodiment, the drain ion implantation region 30 extends and distributes toward the gate 43 and is designed with different ion doping concentrations at different positions, which can avoid the design from not working due to the different electric field peaks of different epitaxial structures 20, so that the application range of different epitaxial structures 20 is wider and the applicability of semiconductor devices is improved.
[0048] In an optional embodiment, in the gate length direction, the distance from the drain 41 to the gate 43 is Lgd, and the distance from the drain 41 to the edge of the drain ion implantation region 30 closest to the gate 43 is L1, wherein 0.005≤L1 / Lgd≤0.5. In this embodiment, by setting L1 / Lgd to be greater than or equal to 0.005, the semiconductor device can obtain a sufficiently long depletion region widening when it is in a high-voltage off state, which is beneficial to improving the withstand voltage capability of the semiconductor device. By setting L1 / Lgd to be less than or equal to 0.5, the length of the drain ion implantation region 30 with a low ion doping concentration is limited, and the on-state resistance of the semiconductor device will not be greatly improved. That is, this range can greatly improve the off-state withstand voltage capability of the drain ion implantation region 30 with a low ion doping concentration while ensuring that the on-state performance of the device is not greatly damaged. Preferably, the distance L1 from the drain 41 to the edge of the drain ion implantation region 30 closest to the gate 43 is between 0.1 and 1 μm.
[0049] Preferably, the thickness of the barrier layer 22 is d1, and the depth of the drain ion implantation region 30 is H, H≥2*d1, that is, by limiting the depth H of the drain ion implantation region 30 to be greater than or equal to twice the thickness d1 of the barrier layer 22, it is possible to ensure that the depth of the drain ion implantation region 30 is near the channel layer 21 area, and there are enough carriers, thereby ensuring that the ohmic contact resistance is small enough.
[0050] In order to further reduce the overall resistivity of the device, the drain ion implantation region 30 has a peak implantation concentration. It should be noted that the peak implantation concentration refers to the maximum ion concentration in the drain ion implantation region 30 along the depth direction. Figure 2, the ordinate is the depth position of the drain ion implantation region 30, and the abscissa is the ion doping concentration value. As the ion implantation deepens from the surface of the epitaxial structure 20 away from the substrate 10 to the substrate 10, the ion doping concentration first increases and then decreases, and a peak implantation concentration is formed near the interface between the barrier layer 22 and the channel layer 21. In a preferred embodiment, the distance D1 from the depth position where the peak implantation concentration is located to the surface of the epitaxial structure 20 away from the substrate 10 is between 5 and 50 nm. In another preferred embodiment, the drain ion implantation region 30 has a peak implantation concentration, and the distance D2 from the depth position where the peak implantation concentration is located to the interface between the barrier layer 22 and the channel layer 21 is between 0 and 10 nm. That is, the depth position where the peak implantation concentration is located can be located in the channel layer 21 or in the barrier layer 22 or at the interface between the channel layer 21 and the barrier layer 22, and is generally arranged near the two-dimensional electron gas, which can significantly reduce the contact resistance and improve the electrical performance of the device.
[0051] Preferably, the peak injection concentration of the drain ion injection region 30 decreases from the bottom of the drain 41 toward the side close to the gate 43. That is, the peak injection concentration of the drain ion injection region 30 located below the drain 41 is greater than the peak injection concentration of the drain ion injection region 30 close to the gate 43, thereby further optimizing the electric field concentration at the position of the drain ion injection region 30 close to the gate 43 and realizing electric field modulation.
[0052] It should be noted that the method of performing ion implantation on the drain ion implantation region 30 in the above-mentioned embodiment can select a suitable implantation dose and energy for single implantation or multiple implantations according to actual needs. Preferably, when performing ion implantation to form the drain ion implantation region 30, the implantation energy of the ion implantation changes from large to small. That is, the implantation energy is first high-energy implanted and then changed to low-energy implantation. Specifically, high-energy implantation is first used to make the implanted ion concentration deeper and the concentration distribution deeper, so as not to constitute a blocking effect on the subsequent low-energy implantation, thereby achieving the desired preset implantation depth and avoiding the low-energy injected ions from hindering the subsequent high-energy injected ions.
[0053] See also Figure 3, the surface of the epitaxial structure 20 includes a first table S1 in contact with the drain 41 and a second table S2 that is not in contact with the source 42, the drain 41 or the gate 43; looking down at the epitaxial structure 20 from the semiconductor device, the ion implantation region includes a contact doping region 31' located within the first table S1 and an extended doping region 32' located within the second table S2, and the peak implantation concentration of the contact doping region 31' is greater than the peak implantation concentration of the extended doping region 32'. That is, the maximum value of the ion concentration implanted into the contact doping region 31' is greater than the maximum value of the ion concentration implanted into the extended doping region 32', so that the peak value of the electric field at the extended doping region 32' is reduced, making the electric field distribution more dispersed. As an example, the ion doping concentration of the contact doping region 31' is between 10 17 ~10 22 cm -3 The ion doping concentration of the extended doping region 32' is between 10 15 ~10 21 cm -3 Of course, the specific value of the ion doping concentration can be reasonably set according to actual needs, and this embodiment is not limited thereto.
[0054] In an optional embodiment, the drain ion implantation region 30 includes a plurality of gradient regions arranged in sequence from the bottom of the drain 41 to the side close to the gate 43, and the peak injection concentration of each gradient region increases step by step from the side close to the gate 43 to the side away from the gate 43. That is, the drain ion implantation region 30 includes a plurality of different gradient regions with different peak injection concentrations, wherein the peak injection concentration of the gradient region closer to the gate 43 side is lower, and the peak injection concentration of the gradient region farther away from the gate 43 side is higher, thereby achieving the purpose of reducing the ohmic contact resistance and optimizing the electric field. It should be noted that the gradient region can be set to 2, 3, 4, etc., and is reasonably designed according to actual needs.
[0055] Take the example of 3 gradient zones, please refer to Figure 4 The drain ion implantation region 30 includes a first gradient region 31, a second gradient region 32, and a third gradient region 33 arranged in sequence from the bottom of the drain 41 to the side close to the gate 43; the ion doping concentration of the first gradient region 31 is greater than the ion doping concentration of the second gradient region 32, and the ion doping concentration of the second gradient region 32 is greater than the ion doping concentration of the third gradient region 33. By limiting the ion doping concentrations of the first gradient region 31, the second gradient region 32, and the third gradient region 33, the withstand voltage can be further enhanced, the peak electric field on the side of the drain 41 close to the gate 43 can be reduced, and the electric field distribution of the drain 41 can be optimized.
[0056] In this embodiment, it is preferred that the orthographic projection area of the first gradient region 31 on the substrate 10 at least partially overlaps with the orthographic projection area of the drain 41 on the substrate 10. Figure 4 The orthographic projection area of the middle drain 41 on the substrate 10 is located within the range of the orthographic projection area of the first gradient region 31 on the substrate 10, thereby ensuring that the first gradient region 31 with a higher ion doping concentration has sufficient position to achieve relatively uniform low-ohmic contact, reduce the risk of current leakage, and improve current transmission efficiency.
[0057] Preferably, please continue to see Figure 4 , the width of the first gradient region 31 is greater than the width of the second gradient region 32, and / or, the width of the first gradient region 31 is greater than the width of the third gradient region 33. By setting the widths of the second gradient region 32 and the third gradient region 33 to be smaller than the width of the first gradient region 31, the widths of the second gradient region 32 and the third gradient region 33 with low ion doping concentration can be limited, ensuring that the on-state performance of the device is not significantly damaged, and at the same time, the off-state withstand voltage capability can be improved.
[0058] See also Figure 5 , the depth of the first gradient region 31 is greater than the depth of the second gradient region 32, and the depth of the second gradient region 32 is greater than the depth of the third gradient region 33. Compared with the same ion implantation depth, the structure with different ion implantation depths in the drain ion implantation region 30 can increase the concentration difference between the vertical interior and the epitaxial surface, thereby improving the degree of freedom of electric field modulation optimization and adapting to different electric field distributions corresponding to more epitaxial structures 20 and barrier layers 22.
[0059] Of course, the depths of the first gradient region 31 , the second gradient region 32 , and the third gradient region 33 may be equal or unequal, and the present embodiment is not limited thereto.
[0060] It should be understood that, for the ion implantation method of the drain ion implantation region 30, on the one hand, ion implantation can be performed on each gradient region separately, for example, firstly the third gradient region 33 is implanted with ions of lower implantation dose and energy, then the second gradient region 32 is implanted with ions of higher implantation dose and energy, and finally the first gradient region 31 is implanted with ions of the highest implantation dose and energy, so as to achieve different ion doping concentrations and peak implantation concentrations in different gradient regions. On the other hand, multiple superimposed implantations can be performed on each gradient region, for example, firstly the first gradient region 31, the second gradient region 32, and the third gradient region 33 are implanted with ions of appropriate implantation dose and energy, then the first gradient region 31 and the second gradient region 32 are implanted with ions of appropriate implantation dose and energy, and finally the first gradient region 31 is implanted with ions of appropriate implantation dose and energy; in this way, the first gradient region 31 is superimposed with three ion implantations, and its ion doping concentration is higher, the second gradient region 32 is superimposed with two ion implantations, and its ion doping concentration is lower, and the third gradient region 33 is superimposed with only one ion implantation, and its ion doping concentration is the lowest, thereby achieving a gradient distribution of ion doping concentration.
[0061] As an example, the peak implant concentration of the first gradient region 31 is between 10 18 ~10 22 cm -3 , the ratio of the peak injection concentration of the first gradient region 31 to the peak injection concentration of the second gradient region 32 is between 2 and 100, and the ratio of the peak injection concentration of the second gradient region 32 to the peak injection concentration of the third gradient region 33 is between 2 and 100. By limiting the peak injection concentration and the ion doping concentration as described above, the electric field modulation can be further optimized and the performance of the semiconductor device can be improved.
[0062] Furthermore, the drain ion implantation region 30 has a valley implantation concentration, wherein the valley implantation concentration refers to the minimum ion concentration along the depth direction in the drain ion implantation region 30. In a preferred embodiment of the present embodiment, in the first gradient region 31, the ratio of the peak implantation concentration of the first gradient region 31 to the valley implantation concentration of the first gradient region 31 is between 1 and 10; in the second gradient region 32, the ratio of the peak implantation concentration of the second gradient region 32 to the valley implantation concentration of the second gradient region 32 is between 1 and 10; in the third gradient region 33, the ratio of the peak implantation concentration of the third gradient region 33 to the valley implantation concentration of the third gradient region 33 is between 1 and 10.
[0063] In this embodiment, after forming the above-mentioned drain ion implantation region 30, a high temperature activation process can be combined to form an ohmic contact with the drain 41. Optionally, a groove with an opening toward the surface of the epitaxial structure 20 away from the substrate 10 is also opened in the drain ion implantation region 30, and the drain 41 is formed in the groove. That is, the drain 41 is formed in the groove of the drain ion implantation region 30, rather than on the surface of the epitaxial structure 20 at the drain ion implantation region 30, so as to further reduce the ohmic contact resistance.
[0064] In other optional embodiments, the semiconductor device further includes a buffer layer 23 between the channel layer 21 and the substrate 10 to relieve stress caused by lattice mismatch between the substrate 10 and the epitaxial structure 20. As an example, the buffer layer 23 includes one or more combinations of AlN, AlGaN, and GaN.
[0065] Preferably, the buffer layer 23 is doped with iron and / or carbon, which can not only effectively adjust the carrier concentration and improve the crystal quality, but also effectively suppress the current collapse. The peak concentration of the doping of iron and / or carbon in the buffer layer 23 is between 10 10 ~10 18 cm -3In this embodiment, the buffer layer 23 is preferably a thin buffer layer 23 (the thickness of the buffer layer 23 is about tens of nanometers). Compared with the traditional thick buffer layer 23 (the thickness of the buffer layer 23 is between hundreds of nanometers and several microns), the thin buffer layer 23 has a lower resistance, can reduce RF loss, improve the performance of semiconductor devices, and is suitable for applications with high-performance RF characteristics.
[0066] However, in actual applications, the above-mentioned thin buffer layer 23 has a large difference in impurity concentration and thickness from the traditional thick buffer layer 23, which causes the electric field peak distribution of the semiconductor device under high pressure stress to be concentrated at the boundary of the ohmic contact area of the drain 41, thereby causing the problem of uneven electric field distribution and reduced voltage resistance. In particular, as the thickness of the buffer layer 23 gradually decreases, the electric field peak in the channel will gradually shift from the gate foot close to the drain 41 to the vicinity of the boundary of the ion implantation area of the drain 41, thereby causing the electric field peak to be concentrated at the boundary of the ion implantation area of the drain 41.
[0067] Based on the above, while applying the thin buffer layer 23 technology to meet the application of high-performance RF characteristics, the present embodiment designs the drain ion injection region 30 on the drain 41 side in the above-mentioned embodiments to reduce the electric field peak and optimize the electric field distribution, thereby effectively solving the problem of uneven electric field distribution in the application of the thin buffer layer 23 and improving the electrical properties and voltage resistance of the semiconductor device.
[0068] In order to effectively illustrate the function of the drain ion implantation region 30 in the embodiment of the present invention, the present invention compares the conventional drain ion implantation region 30 in the prior art and the drain ion implantation region 30 in the embodiment of the present invention. Figure 4 The drain ion implantation region 30 of the embodiment of the present invention is subjected to TCAD simulation verification under the same conditions. Among them, the conventional drain ion implantation region 30 in the prior art is characterized by a consistent ion doping concentration in the drain ion implantation region 30. Figure 4 The drain ion implantation region 30 shows that the ion doping concentration of the three gradient regions gradually decreases from the side away from the gate 43 to the side close to the gate 43. In this TCAD simulation verification, the ion doping concentration of the conventional drain ion implantation region 30 in the prior art is set to 1E20 / cm 3 In the embodiment of the present invention, the ion doping concentrations of the first gradient region 31, the second gradient region 32, and the third gradient region 33 are set to 1E20 / cm 3 , 1E19 / cm 3 , 1E18 / cm 3 After TCAD simulation verification, we can get the following Figure 6 Schematic diagram of the electric field distribution of the conventional drain ion implantation region 30 in the prior art and Figure 7 Schematic diagram of the electric field distribution of the drain ion implantation region 30 in an embodiment of the present invention. Figure 6 , Figure 7It can be seen that the design of the conventional drain ion injection region 30 in the prior art makes the electric field peak higher and the high field area is distributed more densely; while the design of the drain ion injection region 30 according to the embodiment of the present invention effectively reduces the electric field peak and the high field area is distributed dispersedly, which greatly optimizes the electric field distribution.
[0069] See also Figure 8 The semiconductor device provided by the embodiment of the present invention further includes a source ion implantation region 50, which extends from the surface of the epitaxial structure 20 near the source 42 side toward the substrate 10 to the channel layer 21, wherein the orthogonal projection area of the source ion implantation region 50 on the substrate 10 at least partially overlaps with the orthogonal projection area of the source 42 on the substrate 10. Through the above-mentioned design of the source ion implantation region 50, the ohmic contact effect of the source 42 can be effectively improved, and the ohmic contact resistance between the source 42 and the epitaxial structure 20 can be reduced.
[0070] The source ion implantation region 50 is highly doped with Si ions. Preferably, the thickness of the barrier layer 22 is d1, and the depth of the source ion implantation region 50 is h, where h≥2*d1, to further optimize the ohmic contact effect and improve the current level of the semiconductor device. The ion implantation conditions of the source ion implantation region 50 can be the same as the ion implantation conditions of the first gradient region 31. As an example, the ion doping concentration of the source ion implantation region 50 is between 10 15 ~10 22 cm -3 .
[0071] The embodiment of the present invention further provides a radio frequency module, including a semiconductor device. The radio frequency module can be applied to communication terminal equipment such as base stations and mobile phones. The semiconductor device is a gallium nitride semiconductor device, which adopts the semiconductor device provided by the above embodiments, and this embodiment will not be repeated here.
[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; An epitaxial structure located on the substrate; the epitaxial structure at least comprises a channel layer located on the substrate and a barrier layer located on the channel layer; A source electrode covering the epitaxial structure; A drain electrode covering the epitaxial structure; A gate electrode, located between the source electrode and the drain electrode; A drain ion implantation region extends from the surface of the epitaxial structure close to the drain side toward the substrate to the channel layer, and the drain ion implantation region is located below the drain and extends toward the side close to the gate; the ion doping concentration of the drain ion implantation region located within the positive projection area of the drain on the substrate is greater than the ion doping concentration of the drain ion implantation region closest to the gate.
2. The semiconductor device according to claim 1, wherein: In the gate length direction, the distance from the drain to the gate is Lgd, and the distance from the drain to the edge of the drain ion implantation region closest to the gate is L1, wherein 0.005≤L1 / Lgd≤0.
5.
3. The semiconductor device according to claim 2, wherein: A distance L1 from the drain to an edge of the drain ion implantation region closest to the gate is between 0.1 μm and 1 μm.
4. The semiconductor device according to claim 1, wherein: The thickness of the barrier layer is d1, and the depth of the drain ion implantation region is H, where H≥2*d1.
5. The semiconductor device according to claim 1, wherein: The thickness d1 of the barrier layer is between 5 and 30 nm; the thickness d2 of the channel layer is between 50 and 800 nm.
6. The semiconductor device according to claim 1, wherein: The drain ion implantation region has a peak implantation concentration, and a distance D1 from a depth position where the peak implantation concentration is located to a surface of the epitaxial structure away from the substrate is between 5 and 50 nm.
7. The semiconductor device according to claim 1, wherein: The drain ion implantation region has a peak implantation concentration, and a distance D2 from a depth position where the peak implantation concentration is located to an interface between the barrier layer and the channel layer is between 0 and 10 nm.
8. The semiconductor device according to any one of claims 1 to 7, characterized in that: The peak implantation concentration of the drain ion implantation region decreases from the bottom of the drain toward the gate.
9. The semiconductor device according to any one of claims 1 to 7, characterized in that: The surface of the epitaxial structure includes a first table in contact with the drain and a second table not in contact with the source, drain or gate; when looking down at the epitaxial structure from the semiconductor device, the drain ion implantation region includes a contact doping region located within the first table and an extended doping region located within the second table, and the peak implantation concentration of the contact doping region is greater than the peak implantation concentration of the extended doping region.
10. The semiconductor device according to claim 9, wherein: The ion doping concentration of the contact doping region is between 10 17 ~10 22 cm -3 ; The ion doping concentration of the extended doping region is between 10 15 ~10 21 cm -3 .
11. The semiconductor device according to any one of claims 1 to 7, characterized in that: The drain ion implantation region includes a plurality of gradient regions sequentially arranged from the bottom of the drain toward the gate side, and the peak implantation concentration of each gradient region increases step by step from the gate side toward the gate side.
12. The semiconductor device according to any one of claims 1 to 7, characterized in that: The drain ion injection region includes a first gradient region, a second gradient region and a third gradient region arranged in sequence from the bottom of the drain toward the gate side; the ion doping concentration of the first gradient region is greater than the ion doping concentration of the second gradient region, and the ion doping concentration of the second gradient region is greater than the ion doping concentration of the third gradient region.
13. The semiconductor device according to claim 12, wherein: The peak injection concentration in the first gradient zone is between 10 18 ~10 22 cm -3 , the ratio of the peak injection concentration in the first gradient zone to the peak injection concentration in the second gradient zone is between 2 and 100, and the ratio of the peak injection concentration in the second gradient zone to the peak injection concentration in the third gradient zone is between 2 and 100.
14. The semiconductor device according to claim 12, wherein: The width of the first gradient region is greater than the width of the second gradient region, and / or the width of the first gradient region is greater than the width of the third gradient region.
15. The semiconductor device according to claim 12, wherein: The depth of the first gradient zone is greater than the depth of the second gradient zone, and the depth of the second gradient zone is greater than the depth of the third gradient zone.
16. The semiconductor device according to claim 12, wherein: An orthographic projection area of the first gradient region on the substrate at least partially overlaps with an orthographic projection area of the drain on the substrate.
17. A radio frequency module, characterized in that: A semiconductor device comprising any one of claims 1 to 16.