Transistor and manufacturing method thereof
By opening the groove and setting the dielectric layer and grid in the power barrier layer of the high -electrical migration rate crystal tube, using the dielectric layer stress to adjust the two -dimensional electronic gas concentration, solving the difficulty type and enhanced type in the existing technology. The problem of the transistor realizes the production of transistor with different threshold voltage under the same structure, which reduces the difficulty of process.
Patent Information
- Application Number
- CN202411247778.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-06
- Publication Date
- 2025-01-24
AI Technical Summary
The prior art is difficult to realize depletion-type and enhanced high-electron mobility transistors through the same structure, and the process is difficult.
On the substrate layer layer layer and the potential layer in turn, the groove is opened in the band layer, the first medium layer and the second medium layer are set in the groove, and a gate is set in the groove. By adjusting the stress of the media layer, the concentration of the two -dimensional electronic gas is adjusted to adjust the threshold voltage of the transistor.
It is possible to grow transistors with different threshold voltages through the same structure, and both depletion-mode transistors and enhancement-mode transistors can be obtained, which reduces the difficulty of the manufacturing process.
Smart Images
Figure CN119364798A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a transistor and a method for manufacturing the same. Background Art
[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor that is widely used in various electrical appliances.
[0003] The related technology provides a transistor structure, which includes a channel layer and a barrier layer stacked in sequence on a substrate, a source and a drain penetrating the barrier layer and connected to the channel layer, and a gate located in the barrier layer and arranged between the source and the drain.
[0004] The above structure is a depletion-mode HEMT. If an enhancement-mode HEMT is to be realized, an additional P-type GaN layer needs to be provided in the above transistor structure, which makes the process difficult. Summary of the invention
[0005] The disclosed embodiment provides a transistor and a method for manufacturing the same transistor, which can realize a depletion-mode HEMT and an enhancement-mode HEMT using the same structure, and the manufacturing process is easy. The technical solution is as follows:
[0006] In one aspect, a transistor is provided, comprising:
[0007] A substrate, a channel layer and a barrier layer sequentially stacked on the substrate; the barrier layer has a groove extending into the channel layer;
[0008] A dielectric layer, comprising a first dielectric sub-layer and a second dielectric sub-layer, wherein the first dielectric sub-layer and the second dielectric sub-layer sequentially cover the bottom of the groove;
[0009] a source electrode and a drain electrode, the source electrode penetrates the barrier layer and is connected to the channel layer, the drain electrode penetrates the barrier layer and is connected to the channel layer; the groove is located between the source electrode and the drain electrode;
[0010] The gate is located in the groove.
[0011] Optionally, along a direction perpendicular to the substrate, a width A of the groove cross section is greater than a depth B of the groove cross section.
[0012] Optionally, the width A is 1000 to 20000 times the depth B.
[0013] Optionally, the gate includes a main body, a first extension portion, and a second extension portion; the main body, the first extension portion, and the second extension portion are arranged in sequence between the source and the drain, at least part of the main body is located in the groove, the first extension portion and the second extension portion are located outside the groove, and the second extension portion, the first extension portion, and the main body are in a two-step structure.
[0014] Optionally, along a direction perpendicular to the substrate,
[0015] The width C of the cross section of the first extension portion is greater than the width A of the cross section of the groove;
[0016] A width D of a cross section of the second extension portion is greater than a width A of a cross section of the groove.
[0017] Optionally, the width C is 2 to 3 times the width A;
[0018] The width D is 2 to 3 times the width A.
[0019] Optionally, a threshold voltage of the transistor is related to stress levels of the first dielectric sublayer and the second dielectric sublayer.
[0020] Optionally, the threshold voltage of the transistor is greater than 0 in any of the following cases:
[0021] The first dielectric sublayer is under compressive stress C1, the second dielectric sublayer is under tensile stress T2, and C1≥T2;
[0022] The first dielectric sublayer is under tensile stress T1, the second dielectric sublayer is under compressive stress C2, and T1≤C2;
[0023] The first dielectric sublayer has a compressive stress C1, and the second dielectric sublayer has a compressive stress C2.
[0024] Optionally, the threshold voltage of the transistor is less than 0 in any of the following cases:
[0025] The first dielectric sublayer is under tensile stress T1, the second dielectric sublayer is under compressive stress C2, and T1>C2;
[0026] The first dielectric sublayer is in tensile stress T1, and the second dielectric sublayer is in tensile stress T2.
[0027] In another aspect, a method for manufacturing a transistor is provided, the method comprising:
[0028] forming a channel layer on a substrate;
[0029] forming a barrier layer on the channel layer, wherein the barrier layer has a groove extending into the channel layer;
[0030] Fabricating a dielectric layer on the barrier layer, wherein the dielectric layer includes a first dielectric sub-layer and a second dielectric sub-layer, wherein the first dielectric sub-layer and the second dielectric sub-layer sequentially cover the bottom of the groove;
[0031] Making a source electrode and a drain electrode, wherein the source electrode penetrates the barrier layer and is connected to the channel layer, and the drain electrode penetrates the barrier layer and is connected to the channel layer;
[0032] A gate is manufactured, wherein the gate is located in the groove.
[0033] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0034] In the disclosed embodiment, a channel layer and a barrier layer are sequentially formed on the substrate, wherein a groove extending to the channel layer is provided in the barrier layer, a first dielectric sublayer and a second dielectric sublayer are provided in the groove, and then a gate is provided in the groove. By providing a groove, the concentration of the two-dimensional electron gas (2DEG) can be changed, and the first dielectric sublayer and the second dielectric sublayer are provided in the groove. The first dielectric sublayer and the second dielectric sublayer will introduce stress during the growth process, and the stress will change the degree of polarization of the heterojunction and change the 2DEG concentration, thereby being able to adjust the threshold voltage of the transistor. Therefore, this method can use the same structure to grow transistors with different threshold voltages. By adjusting the threshold voltage, both depletion-type transistors and enhancement-type transistors can be obtained, which reduces the difficulty of the transistor manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0036] Figure 1 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure;
[0037] Figure 2 A schematic diagram of the structure of another transistor provided in an embodiment of the present disclosure;
[0038] Figure 3 is a schematic diagram of a transistor package provided by an embodiment of the present disclosure;
[0039] Figure 4 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure;
[0040] Figure 5 It is a flow chart of another method for manufacturing a transistor provided in an embodiment of the present disclosure.
[0041] The reference numerals are as follows:
[0042] 100: substrate; 101: channel layer; 102: barrier layer; 120: groove; 103: dielectric layer; 131: first dielectric sublayer; 132: second dielectric sublayer; 104: source; 105: drain; 106: gate; 107: nucleation layer; 108: buffer layer; 109: interlayer insulating layer; 1040: source pin; 1050: drain pin; 1060: gate pin; 2000: epitaxial structure. DETAILED DESCRIPTION
[0043] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0044] Figure 1 A schematic diagram of a transistor structure provided by an embodiment of the present disclosure. Figure 1 The transistor includes: a substrate 100 , a channel layer 101 , a barrier layer 102 , a dielectric layer 103 , a source 104 , a drain 105 and a gate 106 .
[0045] Among them, the channel layer 101 and the barrier layer 102 are stacked on the substrate 100 in sequence, and the barrier layer 102 has a groove 120 extending into the channel layer 101; the dielectric layer 103 includes a first dielectric sublayer 131 and a second dielectric sublayer 132, and the first dielectric sublayer 131 and the second dielectric sublayer 132 cover the bottom of the groove 120 in sequence; the source 104 passes through the barrier layer 102 and is connected to the channel layer 101, and the drain 105 passes through the barrier layer 102 and is connected to the channel layer 101; the groove 120 is located between the source 104 and the drain 105; and the gate 106 is located in the groove 120.
[0046] In the disclosed embodiment, a channel layer and a barrier layer are sequentially formed on the substrate, wherein a groove extending to the channel layer is provided in the barrier layer, a first dielectric sublayer and a second dielectric sublayer are provided in the groove, and then a gate is provided in the groove. The 2DEG concentration can be changed by providing a groove, and the first dielectric sublayer and the second dielectric sublayer are provided in the groove. The first dielectric sublayer and the second dielectric sublayer will introduce stress during the growth process, and the stress will change the degree of polarization of the heterojunction and change the 2DEG concentration, thereby being able to adjust the threshold voltage of the transistor. Therefore, this method can use the same structure to grow transistors with different threshold voltages. By adjusting the threshold voltage, both depletion-type transistors and enhancement-type transistors can be obtained, which reduces the difficulty of the transistor manufacturing process.
[0047] Among them, stress is introduced during the growth process of the first dielectric sublayer and the second dielectric sublayer, which can make the threshold voltage greater than 0. Moreover, even for a P-type transistor, the threshold voltage can be greatly increased by introducing stress.
[0048] Furthermore, the transistor provided in the embodiment of the present disclosure utilizes the gate in the groove and the dielectric layer stress modulation to realize the depletion mode / enhancement mode device, so that the transistor threshold withstand voltage reaches -30V to +30V and the collapse voltage is greater than 1200V. That is, the adjustable threshold voltage>5V can realize the enhancement mode transistor (E-mode), and the adjustable threshold voltage<-20V can realize the depletion mode transistor (D-mode).
[0049] In the disclosed embodiment, in addition to changing the threshold voltage through stress, the dielectric layer also serves to isolate the gate metal and semiconductor, forming a Metal Insulation Semiconductor Field Effect Transistor (MISFET) structure, which can increase the gate's ability to withstand breakdown.
[0050] In the embodiment of the present disclosure, the substrate 100 may be a Si substrate, a SiC substrate, a sapphire substrate, or the like.
[0051] In the embodiment of the present disclosure, the channel layer 101 may be a non-doped GaN channel layer.
[0052] The thickness of the channel layer 101 may be 1-5 μm.
[0053] Exemplarily, the thickness of the channel layer 101 is 3 μm.
[0054] In the embodiment of the present disclosure, the barrier layer 102 may be Al x Ga 1-x N barrier layer, the barrier layer 102 and the channel layer 101 form a two-dimensional electron gas (2DEG), wherein the value of x is 0.1-0.3.
[0055] The barrier layer 102 may have a thickness of 3-30 nm.
[0056] Exemplarily, the thickness of the barrier layer 102 is 20 nm.
[0057] It can be seen that the transistor is a GaN / AlGaN device. Based on the characteristics of GaN / AlGaN devices, it can also achieve zero hysteresis and enhance transistor sensitivity.
[0058] In the embodiment of the present disclosure, along a direction perpendicular to the substrate 100 , a width A of a cross section of the groove 120 is greater than a depth B of the cross section of the groove 120 .
[0059] In the embodiment of the present disclosure, the width A is 1000 to 20000 times the depth B. It is worth noting that the drawings are only structural examples and do not show the size multiples between the film layers.
[0060] Exemplarily, the width A is 10,000 times the depth B.
[0061] In this implementation, a groove with a relatively large width is provided, thereby avoiding the short channel effect caused by a gate length that is too small.
[0062] For example, the width of the groove 120 may be 1-3 μm.
[0063] In the embodiment of the present disclosure, the depth of the groove 120 can be opened to the channel layer, so that the 2DEG is etched through, so that the threshold voltage of the transistor can be adjusted to a positive voltage.
[0064] In the embodiment of the present disclosure, the dielectric layer 103 can be manufactured by a chemical vapor deposition (CVD) process. For example, the dielectric layer 103 can be manufactured by a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure chemical vapor deposition (LPCVD) process, an atomic layer deposition (ALD) process, a metal organic chemical vapor deposition (MOCVD) process, or a molecular beam epitaxy (MBE) process.
[0065] In the embodiment of the present disclosure, the thickness of the first dielectric sublayer 131 and the second dielectric sublayer 132 may be 20 nm to 60 nm, and the specific value may be selected according to the threshold voltage requirement.
[0066] In the embodiment of the present disclosure, the material of the dielectric layer 103 can be silicon nitride, silicon oxide, aluminum oxide, P-type gallium nitride or N-type gallium nitride. That is, the materials of the first dielectric sublayer 131 and the second dielectric sublayer 132 are silicon nitride, silicon oxide, aluminum oxide, P-type gallium nitride or N-type gallium nitride.
[0067] It should be noted that the P-type gallium nitride here has a different function from the P-type GaN layer in the related technology, and therefore is easier to implement.
[0068] Furthermore, the materials of the first dielectric sub-layer 131 and the second dielectric sub-layer 132 in the dielectric layer 103 can be the same, for example, both are silicon nitride materials; the materials of the first dielectric sub-layer 131 and the second dielectric sub-layer 132 in the dielectric layer 103 can also be different, for example, the first dielectric sub-layer 131 is silicon nitride, and the second dielectric sub-layer 132 is silicon oxide material.
[0069] In the embodiment of the present disclosure, the threshold voltage of the transistor is related to the stress levels of the first dielectric sublayer 131 and the second dielectric sublayer 132 .
[0070] In the disclosed embodiment, the formation principle of 2DEG between the barrier layer 102 and the channel layer 101 is the mixed effect of spontaneous polarization and piezoelectric polarization. The stress of the dielectric layer is equivalent to regulating the degree of piezoelectric polarization, which can control the concentration of 2DEG and thus change the threshold voltage.
[0071] The dielectric layer acts as a field effect control layer, reduces gate leakage and increases gate withstand voltage. The barrier layer is affected by applying internal stress during the growth of the dielectric layer, thereby achieving the purpose of adjusting the threshold voltage in a small range.
[0072] In the embodiments of the present disclosure, the threshold voltage of the transistor is greater than 0 in any of the following cases, that is, an enhancement mode transistor (E-mode) is implemented:
[0073] The first dielectric sublayer 131 is under compressive stress C1, the second dielectric sublayer 132 is under tensile stress T2, and C1≥T2 (the equality here only refers to the equality of stress values);
[0074] The first dielectric sublayer 131 is under tensile stress T1, the second dielectric sublayer 132 is under compressive stress C2, and T1≤C2;
[0075] The first dielectric sublayer 131 has a compressive stress C1, and the second dielectric sublayer 132 has a compressive stress C2. In this case, the threshold voltage is much greater than zero.
[0076] In the embodiment of the present disclosure, the threshold voltage of the transistor is less than 0 in any of the following cases, that is, a depletion mode transistor (D-mode) is implemented:
[0077] The first dielectric sublayer 131 is under tensile stress T1, the second dielectric sublayer 132 is under compressive stress C2, and T1>C2;
[0078] The first dielectric sublayer 131 is under tensile stress T1, and the second dielectric sublayer 132 is under tensile stress T2. In this case, the threshold voltage is much smaller than zero.
[0079] Among them, compressive stress will cause the threshold voltage to shift positively, while tensile stress will cause the threshold voltage to shift negatively.
[0080] In the embodiment of the present disclosure, when the above groove depth and dielectric layer thickness are used, the corresponding relationship between the stress and threshold voltage of the two dielectric sublayers can be experimentally determined first. During manufacturing, the required stress can be determined based on the target threshold voltage and the corresponding relationship.
[0081] In the embodiments of the present disclosure, the stress of the dielectric layer is introduced during the growth process. For example, when making a dielectric sublayer, the stress can be controlled by controlling the frequency of the deposition equipment and / or the ratio of elements. For example, when the dielectric sublayer is a silicon nitride material, controlling the ratio of Si and N can change the silicon nitride composition and the size of the optical band gap, thereby adjusting the stress applied by the dielectric sublayer during the growth process. The process is convenient and easy to implement.
[0082] During the experiment, dielectric layer stress can be measured by mechanical method, interference method, diffraction method, etc. Among them, mechanical method and interference method indirectly infer stress by measuring the bending degree of the substrate, while diffraction method obtains stress information by measuring the change of film lattice constant. In addition, X-ray diffraction method can also characterize internal stress.
[0083] In the embodiment of the present disclosure, the source electrode 104 and the drain electrode 105 may each include a Ti sublayer, an Al sublayer, a Ni sublayer and an Au sublayer stacked in sequence.
[0084] In the embodiment of the present disclosure, the Ti sublayer and the Ni sublayer in the source and the drain are used to improve the adhesion between the sublayers and between the sublayers and the barrier layer, the Al sublayer is used to ensure the conductivity of the electrode, and the Au sublayer is used to protect the other sublayers to prevent the source and the drain from being oxidized or corroded.
[0085] In the source electrode 104 and the drain electrode 105 , the thickness of the Ti sublayer may be 5 to 30 nm, the thickness of the Al sublayer may be 100 to 200 nm, the thickness of the Ni sublayer may be 30 to 80 nm, and the thickness of the Au sublayer may be 30 to 80 nm.
[0086] Exemplarily, in the source 104 and the drain 105 , the thickness of the Ti sublayer is 20 nm, the thickness of the Al sublayer is 120 nm, the thickness of the Ni sublayer is 40 nm, and the thickness of the Au sublayer is 50 nm.
[0087] In the embodiment of the present disclosure, the gate 106 includes a Ni sublayer and an Au sublayer, wherein the Ni sublayer is used to improve the adhesion between the sublayers, and the Au sublayer is used to protect the other sublayers from being oxidized or corroded.
[0088] In the gate 106 , the thickness of the Ni sub-layer may be 10 to 50 nm, and the thickness of the Au sub-layer may be 10 to 50 nm.
[0089] Exemplarily, in the gate 106 , the thickness of the Ni sub-layer is 40 nm, and the thickness of the Au sub-layer is 50 nm.
[0090] Figure 2 FIG. 1 is a schematic diagram of another transistor structure provided by an embodiment of the present disclosure. Figure 2 As shown, the transistor may further include a nucleation layer 107 and a buffer layer 108 , wherein the nucleation layer 107 and the buffer layer 108 are sequentially stacked between the substrate 100 and the channel layer 101 .
[0091] In the embodiment of the present disclosure, the nucleation layer 107 may be an AlN nucleation layer.
[0092] The thickness of the nucleation layer 107 may be 100-300 nm.
[0093] Exemplarily, the thickness of the nucleation layer 107 is 200 nm.
[0094] In the embodiment of the present disclosure, the buffer layer 108 may be a GaN buffer layer and / or an AlGaN buffer layer.
[0095] The thickness of the buffer layer 108 is 500-2000 nm.
[0096] Exemplarily, the thickness of the buffer layer 108 is 1000 nm.
[0097] In the embodiment of the present disclosure, if the thickness of the buffer layer is too thick, it will lead to an increase in the production cost. If the thickness of the buffer layer is too thin, it will be detrimental to the buffering effect of the buffer layer, and a good growth interface cannot be formed on the surface of the buffer layer, which is not conducive to the growth of subsequent device layers.
[0098] Alternatively, if Figure 2 As shown, the transistor may further include an interlayer insulating layer 109 , wherein the interlayer insulating layer 109 is located between the source and the drain and covers the gate.
[0099] In the embodiment of the present disclosure, the interlayer insulating layer 109 may be a SiN layer, a SiO 2 layer or an Al 2 O 3 layer.
[0100] In the embodiment of the present disclosure, the thickness of the interlayer insulating layer 109 may be 0.1-10 μm.
[0101] Illustratively, the thickness of the interlayer insulating layer 109 is 5 μm.
[0102] See again Figure 2The gate 106 includes a main body 161, a first extension portion 162 and a second extension portion 163; the main body 161, the first extension portion 162 and the second extension portion 163 are arranged in sequence between the source 104 and the drain 105, at least part of the main body 161 is located in the groove 120, the first extension portion 162 and the second extension portion 163 are located outside the groove 120, and the second extension portion 163, the first extension portion 162 and the main body 161 present a two-step structure.
[0103] By providing the first extension portion 162 and the second extension portion 163, a field plate structure design is formed, so that the electric field is distributed around the field plate rather than at a single point, that is, the electric field strength is sequentially transferred to the first extension portion 162 and the second extension portion 163, so that the high-voltage electric field of the drain is evenly distributed around the field plate, thereby increasing the breakdown voltage and making the maximum collapse voltage of the device greater than 1200V (4*300V / 1μm gallium nitride material characteristics).
[0104] Optionally, the source electrode may also pass through the semiconductor structure layer (insulation penetration) to connect to the substrate, so that the source electrode and the substrate are at the same potential. Alternatively, the source electrode and the substrate are connected during packaging.
[0105] In the embodiment of the present disclosure, along a direction perpendicular to the substrate 100,
[0106] The width C of the cross section of the first extension portion 162 is greater than the width A of the cross section of the groove 120;
[0107] A width D of a cross section of the second extension portion 163 is greater than a width A of a cross section of the groove 120 .
[0108] In the embodiment of the present disclosure, the width C is 2 to 3 times the width A;
[0109] The width D is 2 to 3 times the width A.
[0110] For example, the width C is twice the width A;
[0111] The width D is twice the width A.
[0112] Since the field plate design is related to the height and length of the field plate, the use of the above dimensions can better achieve the transfer of electric field strength and improve the voltage resistance, breakdown voltage and other performance of the transistor.
[0113] Figure 3 Schematic diagram of transistor packaging provided by an embodiment of the present disclosure. Figure 3When the transistors provided in the embodiments of the present disclosure are packaged, multiple transistors can be packaged on the same circuit board, wherein reference numerals 1040, 1050 and 1060 are source pins, drain pins and gate pins on the circuit board, respectively. Figure 3 As shown, the gates, sources, drains, etc. of multiple transistor epitaxial structures 2000 are connected together and then connected together to the pins of the circuit board. Figure 3 The multiple epitaxial structures 2000 may be epitaxial structures using the groove plus dielectric layer method in the embodiment of the present disclosure, or may be epitaxial structures using other methods.
[0114] Figure 4 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure, which is used to manufacture the transistor described above. Figure 4 The method steps include:
[0115] S11. Fabricating a channel layer on a substrate.
[0116] S12, forming a barrier layer on the channel layer, wherein the barrier layer has a groove extending into the channel layer.
[0117] S13, manufacturing a dielectric layer on the barrier layer, wherein the dielectric layer includes a first dielectric sub-layer and a second dielectric sub-layer, and the first dielectric sub-layer and the second dielectric sub-layer sequentially cover the bottom of the groove.
[0118] S14, manufacturing a source electrode and a drain electrode, wherein the source electrode penetrates the barrier layer and is connected to the channel layer, and the drain electrode penetrates the barrier layer and is connected to the channel layer.
[0119] S15, manufacturing a gate, wherein the gate is located in the groove.
[0120] In the disclosed embodiment, a channel layer and a barrier layer are sequentially formed on the substrate, wherein a groove extending to the channel layer is provided in the barrier layer, a first dielectric sublayer and a second dielectric sublayer are provided in the groove, and then a gate is provided in the groove. The 2DEG concentration can be changed by providing a groove, and the first dielectric sublayer and the second dielectric sublayer are provided in the groove. The first dielectric sublayer and the second dielectric sublayer will introduce stress during the growth process, and the stress will change the degree of polarization of the heterojunction and change the 2DEG concentration, thereby being able to adjust the threshold voltage of the transistor. Therefore, this method can use the same structure to grow transistors with different threshold voltages. By adjusting the threshold voltage, both depletion-type transistors and enhancement-type transistors can be obtained, which reduces the difficulty of the transistor manufacturing process.
[0121] Figure 5 is a flow chart of another method for manufacturing a transistor provided by an embodiment of the present disclosure, which is used to manufacture the transistor described above. Figure 5 The method steps include:
[0122] S21. Growing a nucleation layer on the substrate.
[0123] In the embodiment of the present disclosure, the substrate is one of a Si substrate, a SiC substrate, a sapphire substrate and the like.
[0124] In the embodiment of the present disclosure, the nucleation layer 107 may be an AlN nucleation layer.
[0125] The thickness of the nucleation layer 107 may be 100-300 nm.
[0126] Exemplarily, the thickness of the nucleation layer 107 is 200 nm.
[0127] In the embodiments of the present disclosure, high-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixed gas of high-purity H2 and high-purity N2 is used as a carrier gas, high-purity NH3 is used as a nitrogen source, trimethylgallium (TMGa) and triethylgallium (TEGa) are used as gallium sources, trimethylindium (TMIn) is used as an indium source, silane (SiH4) is used as an N-type dopant, trimethylaluminum (TMAl) is used as an aluminum source, and bis(cyclopentadienyl)magnesium (CP2Mg) is used as a P-type dopant.
[0128] S22. Growing a buffer layer on the nucleation layer.
[0129] In the embodiment of the present disclosure, the buffer layer 108 may be a GaN buffer layer and / or an AlGaN buffer layer.
[0130] The thickness of the buffer layer 108 is 500-2000 nm.
[0131] Exemplarily, the thickness of the buffer layer 108 is 1000 nm.
[0132] In the embodiment of the present disclosure, if the thickness of the buffer layer is too thick, it will lead to an increase in the production cost. If the thickness of the buffer layer is too thin, it will be detrimental to the buffering effect of the buffer layer, and a good growth interface cannot be formed on the surface of the buffer layer, which is not conducive to the growth of subsequent device layers.
[0133] S23 . Growing a channel layer on the buffer layer.
[0134] In the embodiment of the present disclosure, the channel layer 101 may be a non-doped GaN channel layer.
[0135] The thickness of the channel layer 101 may be 1-5 μm.
[0136] Exemplarily, the thickness of the channel layer 101 is 3 μm.
[0137] S24 . Growing a barrier layer on the channel layer, wherein the barrier layer has a groove extending into the channel layer.
[0138] In the embodiment of the present disclosure, the barrier layer 102 may be Al x Ga 1-x N barrier layer, the barrier layer 102 and the channel layer 101 form a two-dimensional electron gas (2DEG), wherein the value of x is 0.1-0.3.
[0139] The barrier layer 102 may have a thickness of 3-30 nm.
[0140] Exemplarily, the thickness of the barrier layer 102 is 20 nm.
[0141] It can be seen that the transistor is a GaN / AlGaN device. Based on the characteristics of GaN / AlGaN devices, it can also achieve zero hysteresis and enhance transistor sensitivity.
[0142] In the embodiment of the present disclosure, along a direction perpendicular to the substrate 100 , a width A of a cross section of the groove 120 is greater than a depth B of the cross section of the groove 120 .
[0143] In the embodiment of the present disclosure, the width A is 1000 to 20000 times the depth B.
[0144] Exemplarily, the width A is 10,000 times the depth B.
[0145] In this implementation, a groove with a relatively large width is provided, thereby avoiding the short channel effect caused by a gate length that is too small.
[0146] For example, the width of the groove 120 may be 1-3 μm.
[0147] In the embodiment of the present disclosure, the depth of the groove 120 can be opened to the channel layer, so that the 2DEG is etched through, so that the threshold voltage of the transistor can be adjusted to a positive voltage.
[0148] S25, manufacturing a dielectric layer on the barrier layer, wherein the dielectric layer includes a first dielectric sub-layer and a second dielectric sub-layer, and the first dielectric sub-layer and the second dielectric sub-layer sequentially cover the bottom of the groove.
[0149] In the embodiment of the present disclosure, in the embodiment of the present disclosure, the dielectric layer 103 can be manufactured by using a CVD process. For example, the dielectric layer 103 can be manufactured by using a PECVD process, a LPCVD process, an ALD process, a MOCVD process, or an MBE process.
[0150] In the embodiment of the present disclosure, the thickness of the first dielectric sublayer 131 and the second dielectric sublayer 132 may be 20 nm to 60 nm, and the specific value may be selected according to the threshold voltage requirement.
[0151] In the embodiment of the present disclosure, the material of the dielectric layer 103 can be silicon nitride, silicon oxide, aluminum oxide, P-type gallium nitride or N-type gallium nitride. That is, the materials of the first dielectric sublayer 131 and the second dielectric sublayer 132 are silicon nitride, silicon oxide, aluminum oxide, P-type gallium nitride or N-type gallium nitride.
[0152] It should be noted that the P-type gallium nitride here has a different function from the P-type GaN layer in the related technology, and therefore is easier to implement.
[0153] Furthermore, the materials of the first dielectric sub-layer 131 and the second dielectric sub-layer 132 in the dielectric layer 103 can be the same, for example, both are silicon nitride materials; the materials of the first dielectric sub-layer 131 and the second dielectric sub-layer 132 in the dielectric layer 103 can also be different, for example, the first dielectric sub-layer 131 is silicon nitride, and the second dielectric sub-layer 132 is silicon oxide material.
[0154] In the embodiment of the present disclosure, the threshold voltage of the transistor is related to the stress levels of the first dielectric sublayer 131 and the second dielectric sublayer 132 .
[0155] In the disclosed embodiment, the formation principle of 2DEG between the barrier layer 102 and the channel layer 101 is the mixed effect of spontaneous polarization and piezoelectric polarization. The stress of the dielectric layer is equivalent to regulating the degree of piezoelectric polarization, which can control the concentration of 2DEG and thus change the threshold voltage.
[0156] The dielectric layer acts as a field effect control layer, reduces gate leakage and increases gate withstand voltage. The barrier layer is affected by applying internal stress during the growth of the dielectric layer, thereby achieving the purpose of adjusting the threshold voltage in a small range.
[0157] In the embodiments of the present disclosure, the threshold voltage of the transistor is greater than 0 in any of the following cases, that is, an enhancement mode transistor (E-mode) is implemented:
[0158] The first dielectric sublayer 131 is in compressive stress (compressive) C1, the second dielectric sublayer 132 is in tensile stress (tensile) T2, and C1 ≥ T2;
[0159] The first dielectric sublayer 131 is under tensile stress T1, the second dielectric sublayer 132 is under compressive stress C2, and T1≤C2;
[0160] The first dielectric sublayer 131 has a compressive stress C1, and the second dielectric sublayer 132 has a compressive stress C2. In this case, the threshold voltage is much greater than zero.
[0161] In the embodiment of the present disclosure, the threshold voltage of the transistor is less than 0 in any of the following cases, that is, a depletion mode transistor (D-mode) is implemented:
[0162] The first dielectric sublayer 131 is under tensile stress T1, the second dielectric sublayer 132 is under compressive stress C2, and T1>C2;
[0163] The first dielectric sublayer 131 is under tensile stress T1, and the second dielectric sublayer 132 is under tensile stress T2. In this case, the threshold voltage is much smaller than zero.
[0164] Among them, compressive stress will cause the threshold voltage to shift positively, while tensile stress will cause the threshold voltage to shift negatively.
[0165] In the embodiment of the present disclosure, when the above groove depth and dielectric layer thickness are used, the corresponding relationship between the stress and threshold voltage of the two dielectric sublayers can be experimentally determined first. During manufacturing, the required stress can be determined based on the target threshold voltage and the corresponding relationship.
[0166] In the embodiments of the present disclosure, the stress of the dielectric layer is introduced during the growth process. For example, when making a dielectric sublayer, the stress can be controlled by controlling the frequency of the deposition equipment and / or the ratio of elements. For example, when the dielectric sublayer is a silicon nitride material, controlling the ratio of Si and N can change the silicon nitride composition and the size of the optical band gap, thereby adjusting the stress applied by the dielectric sublayer during the growth process. The process is convenient and easy to implement.
[0167] During the experiment, dielectric layer stress can be measured by mechanical method, interference method, diffraction method, etc. Among them, mechanical method and interference method indirectly infer stress by measuring the bending degree of the substrate, while diffraction method obtains stress information by measuring the change of film lattice constant. In addition, X-ray diffraction method can also characterize internal stress.
[0168] S26, manufacturing a gate, wherein the gate is located in the groove.
[0169] In the embodiment of the present disclosure, the gate 106 includes a Ni sublayer and an Au sublayer, wherein the Ni sublayer is used to improve the adhesion between the sublayers, and the Au sublayer is used to protect the other sublayers from being oxidized or corroded.
[0170] In the gate 106 , the thickness of the Ni sub-layer may be 10 to 50 nm, and the thickness of the Au sub-layer may be 10 to 50 nm.
[0171] Exemplarily, in the gate 106 , the thickness of the Ni sub-layer is 40 nm, and the thickness of the Au sub-layer is 50 nm.
[0172] See again Figure 2The gate 106 includes a main body 161, a first extension portion 162 and a second extension portion 163; the main body 161, the first extension portion 162 and the second extension portion 163 are arranged in sequence between the source 104 and the drain 105, at least part of the main body 161 is located in the groove 120, the first extension portion 162 and the second extension portion 163 are located outside the groove 120, and the second extension portion 163, the first extension portion 162 and the main body 161 present a two-step structure.
[0173] By providing the first extension portion 162 and the second extension portion 163, a field plate structure design is formed, so that the electric field is distributed around the field plate rather than at a single point, that is, the electric field strength is sequentially transferred to the first extension portion 162 and the second extension portion 163, so that the high-voltage electric field of the drain is evenly distributed around the field plate, thereby increasing the breakdown voltage and making the maximum collapse voltage of the device greater than 1200V (4*300V / 1μm gallium nitride material characteristics).
[0174] Optionally, the source electrode may also pass through the semiconductor structure layer (insulation penetration) to connect to the substrate, so that the source electrode and the substrate are at the same potential. Alternatively, the source electrode and the substrate are connected during packaging.
[0175] In the embodiment of the present disclosure, along a direction perpendicular to the substrate 100,
[0176] The width C of the cross section of the first extension portion 162 is greater than the width A of the cross section of the groove 120;
[0177] A width D of a cross section of the second extension portion 163 is greater than a width A of a cross section of the groove 120 .
[0178] In the embodiment of the present disclosure, the width C is 2 to 3 times the width A;
[0179] The width D is 2 to 3 times the width A.
[0180] For example, the width C is twice the width A;
[0181] The width D is twice the width A.
[0182] Since the field plate design is related to the height and length of the field plate, the use of the above dimensions can better achieve the transfer of electric field strength and improve the voltage resistance, breakdown voltage and other performance of the transistor.
[0183] S27, making an interlayer insulating layer, wherein the interlayer insulating layer covers the gate.
[0184] In the embodiment of the present disclosure, the interlayer insulating layer 109 may be a SiN layer, a SiO 2 layer or an Al 2 O 3 layer.
[0185] In the embodiment of the present disclosure, the thickness of the interlayer insulating layer 109 may be 0.1-10 μm.
[0186] Illustratively, the thickness of the interlayer insulating layer 109 is 5 μm.
[0187] S28, making a source and a drain, wherein the source sequentially penetrates the interlayer insulating layer, the barrier layer and is connected to the channel layer, and the drain sequentially penetrates the interlayer insulating layer, the barrier layer and is connected to the channel layer.
[0188] Figure 2 The figure shows only a cross-sectional view of the transistor. Figure 2 The portion of the drain electrode extending out of the interlayer insulating layer is not shown in the cross section.
[0189] In the embodiment of the present disclosure, the source electrode 104 and the drain electrode 105 may each include a Ti sublayer, an Al sublayer, a Ni sublayer and an Au sublayer stacked in sequence.
[0190] In the embodiment of the present disclosure, the Ti sublayer and the Ni sublayer in the source and the drain are used to improve the adhesion between the sublayers and between the sublayers and the barrier layer, the Al sublayer is used to ensure the conductivity of the electrode, and the Au sublayer is used to protect the other sublayers to prevent the source and the drain from being oxidized or corroded.
[0191] In the source electrode 104 and the drain electrode 105 , the thickness of the Ti sublayer may be 5 to 30 nm, the thickness of the Al sublayer may be 100 to 200 nm, the thickness of the Ni sublayer may be 30 to 80 nm, and the thickness of the Au sublayer may be 30 to 80 nm.
[0192] Exemplarily, in the source 104 and the drain 105 , the thickness of the Ti sublayer is 20 nm, the thickness of the Al sublayer is 120 nm, the thickness of the Ni sublayer is 40 nm, and the thickness of the Au sublayer is 50 nm.
[0193] The transistor manufactured by the solution provided in the embodiment of the present disclosure may be a MISFET, and the threshold voltage can be regulated by controlling the stress of the dielectric layer 103 therein, thereby realizing an enhanced transistor and a normally-off safety device.
[0194] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A transistor, characterized in that: The transistor comprises: A substrate (100), a channel layer (101) and a barrier layer (102) sequentially stacked on the substrate (100); the barrier layer (102) having a groove (120) extending into the channel layer (101); A dielectric layer (103), comprising a first dielectric sublayer (131) and a second dielectric sublayer (132), wherein the first dielectric sublayer (131) and the second dielectric sublayer (132) sequentially cover the bottom of the groove (120); a source electrode (104) and a drain electrode (105), wherein the source electrode (104) penetrates the barrier layer (102) and is connected to the channel layer (101), and the drain electrode (105) penetrates the barrier layer (102) and is connected to the channel layer (101); and the groove (120) is located between the source electrode (104) and the drain electrode (105); The gate (106) is located in the groove (120).
2. The transistor according to claim 1, characterized in that Along a direction perpendicular to the substrate (100), a width A of a cross section of the groove (120) is greater than a depth B of the cross section of the groove (120).
3. The transistor according to claim 2, characterized in that The width A is 1000 to 20000 times the depth B.
4. The transistor according to any one of claims 1 to 3, characterized in that: The gate (106) comprises a main body (161), a first extension part (162) and a second extension part (163); the main body (161), the first extension part (162) and the second extension part (163) are arranged in sequence between the source (104) and the drain (105); at least part of the main body (161) is located in the groove (120); the first extension part (162) and the second extension part (163) are located outside the groove (120); and the second extension part (163), the first extension part (162) and the main body (161) present a two-step structure.
5. The transistor according to claim 4, characterized in that In a direction perpendicular to the substrate (100), The width C of the cross section of the first extension portion (162) is greater than the width A of the cross section of the groove (120); The width D of the cross section of the second extension portion (163) is greater than the width A of the cross section of the groove (120).
6. The transistor according to claim 5, characterized in that The width C is 2 to 3 times the width A; the width D is 2 to 3 times the width A.
7. The transistor according to any one of claims 1 to 3, characterized in that: The threshold voltage of the transistor is related to the stress magnitude of the first dielectric sublayer (131) and the second dielectric sublayer (132).
8. The transistor according to claim 7, characterized in that The threshold voltage of the transistor is greater than 0 in any of the following cases: The first dielectric sublayer (131) is in compressive stress C1, the second dielectric sublayer (132) is in tensile stress T2, and C1≥T2; The first dielectric sublayer (131) is in tensile stress T1, the second dielectric sublayer (132) is in compressive stress C2, and T1≤C2; The first dielectric sublayer (131) has a compressive stress C1, and the second dielectric sublayer (132) has a compressive stress C2.
9. The transistor according to claim 7, characterized in that The threshold voltage of the transistor is less than 0 in any of the following cases: The first dielectric sublayer (131) is under tensile stress T1, the second dielectric sublayer (132) is under compressive stress C2, and T1>C2; The first dielectric sublayer (131) is under tensile stress T1, and the second dielectric sublayer (132) is under tensile stress T2.
10. A method for manufacturing a transistor, characterized in that: The method comprises: Fabricating a channel layer (101) on a substrate (100); Fabricating a barrier layer (102) on the channel layer (101), wherein the barrier layer (102) has a groove (120) extending into the channel layer (101); A dielectric layer (103) is fabricated on the barrier layer (102), wherein the dielectric layer (103) comprises a first dielectric sublayer (131) and a second dielectric sublayer (132), wherein the first dielectric sublayer (131) and the second dielectric sublayer (132) sequentially cover the bottom of the groove (120); A source electrode (104) and a drain electrode (105) are fabricated, wherein the source electrode (104) penetrates the barrier layer (102) and is connected to the channel layer (101), and the drain electrode (105) penetrates the barrier layer (102) and is connected to the channel layer (101); A gate (106) is manufactured, and the gate (106) is located in the groove (120).