Power semiconductor device

Abstract

A power semiconductor device includes a semiconductor substrate, a drift layer, a well region, a doped region, two dummy trenches, a gate structure and a dielectric layer. The semiconductor substrate is doped to have a first conductive channel. The drift layer is located on the semiconductor substrate and is doped to have a first conductive channel. The well region is located on the drift layer and doped to have a second conductive channel opposite to the first conductive channel in polarity. The doped region is located on the well region and is doped to have a first conductive channel. The two virtual trenches penetrate through the doped region and the well region, and each virtual trench is provided with a virtual grid electrode. The gate structure is located between the two virtual trenches, and the gate structure is provided with a real gate. The dielectric layer isolates the dummy gate in the doped region, the well region and the drift layer, and isolates the real gate in the doped region, the well region and the drift layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a power semiconductor device. Background Art

[0002] Compared to Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) made of silicon (Si)-based materials, MOSFET made of silicon carbide (SiC) materials has higher carrier mobility, faster switching speed and smaller switching loss. Compared to vertical double-diffused MOSFET (VD-MOSFET), vertical trench MOSFET (TrenchMOSFET, also known as Trench Gate MOSFET, or UMOSFET) has smaller on-resistance and smaller switching loss.

[0003] However, due to the structural design, whether it is a vertical double diffused MOSFET or a vertical trench MOSFET, the electric field will be concentrated on the boundary of the well region (for example, the well region of a P-type semiconductor) or the corner of the gate trench, causing the vertical double diffused MOSFET and the vertical trench MOSFET to undergo avalanche breakdown early (for example, the bottom of the well region or the bottom of the gate trench is broken down by the electric field), thereby making the vertical double diffused MOSFET and the vertical trench MOSFET have a lower voltage resistance (that is, a smaller breakdown voltage). Summary of the invention

[0004] The present invention provides a power semiconductor device. The power semiconductor device includes a semiconductor substrate, a drift layer, a well region, a doped region, two dummy grooves, a gate structure and a dielectric layer. The semiconductor substrate is doped with a first element in a first element group and has a first conductive channel. The drift layer is located on the semiconductor substrate, and the drift layer is doped with a second element in the first element group and has a first conductive channel. The well region is located on the drift layer, and the well region is doped with a third element in the second element group and has a second conductive channel. The polarity of the second conductive channel is opposite to that of the first conductive channel. The doped region is located on the well region, and the doped region is doped with a fourth element in the first element group and has a first conductive channel. Two dummy grooves penetrate the doped region and the well region, and each dummy groove has a dummy gate. The gate structure is located between the two dummy grooves, and the gate structure has a real gate. The dielectric layer isolates each dummy gate from the doped region, the well region and the drift layer, and isolates the real gate from the doped region, the well region and the drift layer.

[0005] According to some embodiments, the present invention can balance the charges and evenly disperse the electric field through the virtual trench and its virtual gate, so that the electric field will not be concentrated at the bottom of the well region or the bottom of the gate structure (such as the bottom of the gate trench). In this way, the voltage resistance of the power semiconductor device can be improved (i.e., the breakdown voltage is increased), so that the power semiconductor device will have a later avalanche breakdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram of the component structure of a power semiconductor device according to a first embodiment of the present invention;

[0007] Figure 2 A partial schematic diagram of the element structure of a power semiconductor device according to a first embodiment of the present invention;

[0008] Figure 3 A schematic diagram of the component structure of a power semiconductor device according to a second embodiment of the present invention;

[0009] Figure 4 A partial schematic diagram of the element structure of a power semiconductor device according to a second embodiment of the present invention;

[0010] Figure 5 Schematic diagram of a dielectric layer according to some embodiments of the present invention;

[0011] Figure 6 A schematic diagram of the component structure of a power semiconductor device according to a third embodiment of the present invention;

[0012] Figure 7 A flowchart of a manufacturing process of a power semiconductor device according to some embodiments of the present invention;

[0013] Figures 8 to 12 It is a schematic structural diagram of a power semiconductor device to be manufactured at different stages of the manufacturing process method according to the first embodiment of the present invention;

[0014] Figures 13 to 17 It is a schematic structural diagram of a power semiconductor device to be manufactured at different stages of a manufacturing process method according to a second embodiment of the present invention;

[0015] Figures 18 to 22 It is a schematic structural diagram of a power semiconductor device to be manufactured at different stages of a manufacturing process method according to a third embodiment of the present invention;

[0016] Fig.23 Schematic diagram of characteristic parameters of a power semiconductor device without a dummy trench according to a comparative example of the present invention and characteristic parameters of power semiconductor devices according to some embodiments of the present invention under different values ​​of the distance between the top and the bottom of the dummy trench;

[0017] Fig.24is the gate voltage (V g ) and drain current (I d ) and a schematic diagram of a characteristic curve between a gate voltage and a drain current of a power semiconductor device according to some embodiments of the present invention at different values ​​of the distance between the top and the bottom of a virtual trench;

[0018] Fig.25 is the drain voltage (V d ) and a characteristic curve between the drain voltage and the drain current and a schematic diagram of a characteristic curve between the drain voltage and the drain current of a power semiconductor device under different values ​​of the distance between the top and the bottom of a virtual trench in some embodiments of the present invention;

[0019] Fig.26 is a schematic diagram of electric field distribution of a power semiconductor device without a dummy trench according to a comparative example of the present invention;

[0020] Fig. 27 A schematic diagram of electric field distribution of a power semiconductor device according to some embodiments of the present invention when the distance between the top and bottom of a virtual trench is 1 micrometer;

[0021] Fig.28 A schematic diagram of electric field distribution of a power semiconductor device according to some embodiments of the present invention when the distance between the top and bottom of a virtual trench is 1.5 micrometers;

[0022] Fig.29 Schematic diagram of electric field distribution of a power semiconductor device according to some embodiments of the present invention when the distance between the top and bottom of a virtual trench is 2 micrometers;

[0023] Fig.30 A schematic diagram of electric field distribution of a power semiconductor device according to some embodiments of the present invention when the distance between the top and bottom of a virtual trench is 2.5 micrometers;

[0024] Fig.31 A schematic diagram of electric field distribution of a power semiconductor device according to some embodiments of the present invention when the distance between the top and bottom of a virtual trench is 3 micrometers;

[0025] Fig.32 A schematic diagram of electric field distribution of a power semiconductor device according to some embodiments of the present invention when the distance between the top and bottom of a virtual trench is 3.5 micrometers;

[0026] Fig.33 A schematic diagram of electric field distribution of a power semiconductor device according to some embodiments of the present invention when the distance between the top and bottom of a virtual trench is 4 micrometers;

[0027] Fig.34 Schematic diagrams of parasitic capacitance of a power semiconductor device without a dummy trench according to a comparative example of the present invention and parasitic capacitance of a power semiconductor device according to some embodiments of the present invention under different distances between the top and bottom of the dummy trench;

[0028] Fig.35 is the gate-drain parasitic capacitance (C gd ) and the drain voltage and a schematic diagram of a characteristic curve of gate-drain parasitic capacitance and drain voltage at different values ​​of the distance between the top and bottom of a virtual trench of a power semiconductor device according to some embodiments of the present invention;

[0029] Fig.36 Schematic diagrams of the rise time and fall time of a power semiconductor device without a dummy trench according to a comparative example of the present invention and the rise time and fall time of a power semiconductor device according to some embodiments of the present invention at different values ​​of the distance between the top and the bottom of the dummy trench;

[0030] Fig.37 Schematic diagrams of characteristic curves between drain voltage and transition time when a power semiconductor device without a dummy trench is turned on according to a comparative example of the present invention and characteristic curves between drain voltage and transition time when a power semiconductor device of some embodiments of the present invention is turned on at different distances between the top and bottom of the dummy trench;

[0031] Fig.38 This is a schematic diagram of a characteristic curve between the drain voltage and the transfer time when a power semiconductor device without a virtual trench is turned off (i.e., not conducting) in a comparative example of the present invention, and a schematic diagram of a characteristic curve between the drain voltage and the transfer time when the power semiconductor device of some embodiments of the present invention is turned off at different values ​​of the distance between the top and the bottom of the virtual trench.

[0032] Explanation of symbols

[0033] 10: Power semiconductor devices

[0034] 30:Semiconductor substrate

[0035] 40: Drift layer

[0036] 41: Top

[0037] 42: Bottom

[0038] 50: Well region

[0039] 51: Trap area

[0040] 511: Bottom

[0041] 512: Top

[0042] 513: Adjacent side

[0043] c3: third corner

[0044] 60: Doping area

[0045] 61: Top surface

[0046] 62: doped sub-region

[0047] 621: Top surface

[0048] 70: Virtual Groove

[0049] 71: Virtual Gate

[0050] 72: Bottom

[0051] 73:Inner wall surface

[0052] 74:Outer wall surface

[0053] 75: Top

[0054] c1: first corner

[0055] 80: Gate structure

[0056] 81: Real Gate

[0057] 82: Gate trench

[0058] 821: Bottom

[0059] 822:Inner wall surface

[0060] 823:Outer wall surface

[0061] c2: second corner

[0062] 83: Bottom

[0063] 90: Dielectric layer

[0064] 100: Intermetallic dielectric layer

[0065] CM: Conductive material

[0066] CT1: First contact pad

[0067] CT2: Second contact pad

[0068] CT3: Third contact pad

[0069] CT4: Fourth contact pad

[0070] r1: distance

[0071] r2: distance

[0072] r3: distance

[0073] r4: distance

[0074] r5: distance

[0075] r6: distance

[0076] RL1: first arc length

[0077] RL2: Second arc length

[0078] θ1: first center angle

[0079] θ2: Second center angle

[0080] CA: Channel Area

[0081] JA: Junction Area

[0082] S700~S714: Steps DETAILED DESCRIPTION

[0083] Reference Figure 1, is a schematic diagram of the element structure of the power semiconductor device 10 of the first embodiment of the present invention. The power semiconductor device 10 includes a semiconductor substrate 30, a drift layer 40, a well region 50, a doping region 60, two dummy trenches 70, a gate structure 80 and a dielectric layer 90. The semiconductor substrate 30 is doped with an element in the first element group (hereinafter referred to as the first element) and has a first conductive channel. The drift layer 40 is located on the semiconductor substrate 30. The drift layer 40 is doped with an element in the first element group (hereinafter referred to as the second element) and has a first conductive channel. The well region 50 is located on the drift layer 40. The well region 50 is doped with an element in the second element group (hereinafter referred to as the third element) and has a second conductive channel. The polarity of the second conductive channel is opposite to the polarity of the first conductive channel. Specifically, the polarity of the charge carriers (i.e., majority carriers) provided for the flow of the second conductive channel is opposite to the polarity of the charge carriers provided for the flow of the first conductive channel. For example, when the power semiconductor device 10 is an N-type MOSFET, the charge carriers provided by the first conductive channel are free electrons, and the charge carriers provided by the second conductive channel are holes; when the power semiconductor device 10 is a P-type MOSFET, the charge carriers provided by the first conductive channel are holes, and the charge carriers provided by the second conductive channel are free electrons. The doped region 60 is located on the well region 50. The doped region 60 is doped with an element (hereinafter referred to as the fourth element) in the first element group and has a first conductive channel. Two virtual trenches 70 penetrate the doped region 60 and the well region 50. Each virtual trench 70 has a virtual gate 71. The gate structure 80 is located between the two virtual trenches 70. The gate structure 80 has a real gate 81. The dielectric layer 90 isolates each virtual gate 71 from the doped region 60, the well region 50 and the drift layer 40, and isolates the real gate 81 from the doped region 60, the well region 50 and the drift layer 40.

[0084] When the power semiconductor device 10 is in the on state (for example, when the power semiconductor device 10 is an N-type MOSFET, a positive voltage is applied to the real gate 81 to form an inversion channel for the flow of charge carriers between the gate structure 80, the doped region 60 and the well region 50), the charge carriers flow from the doped region 60 through the well region 50 and the drift layer 40 to the semiconductor substrate 30 to establish a current path between the doped region 60 and the semiconductor substrate 30. The real gate 81 refers to an electrode (i.e., the gate of the power semiconductor device 10) that controls the electron mobility of the charge carriers by applying a voltage, thereby controlling the formation of the inversion channel, and the formation of the inversion channel is independent of the virtual trench 70 and its virtual gate 71.

[0085] The drift layer 40 and the well region 50 are subjected to the electric field formed by the voltage applied to the drain and source of the power semiconductor device 10.ds )) exceeds the rated reverse bias value that the diode formed by the PN junction between the drift layer 40 and the well region 50 can withstand, the power semiconductor device 10 is in a breakdown state. That is to say, the rated reverse bias value that the diode formed by the PN junction between the drift layer 40 and the well region 50 can withstand is the breakdown voltage of the power semiconductor device 10. The present invention can balance the charge distribution through the virtual groove 70 and its virtual gate 71, thereby uniformly dispersing the electric field distribution in the drift layer 40 and the well region 50. Specifically, through the virtual groove 70 and its virtual gate 71, the electric field can be distributed at the bottom 72 of the virtual groove 70 and the bottom of the gate structure 80 or at the bottom 72 of the virtual groove 70 and the bottom of the well region 50, without concentrating the electric field at the bottom of the gate structure 80 or the bottom of the well region 50. The reason is that the virtual trench 70 and its virtual gate 71 form a capacitive effect to attract the electric field to the bottom 72 of the virtual trench 70, and the electric field will not be concentrated only at the bottom of the gate structure 80 or the bottom of the well region 50. In this way, the voltage resistance of the power semiconductor device 10 can be improved (i.e., the breakdown voltage is improved), and it is more difficult for the power semiconductor device 10 to enter the breakdown state. If there is no virtual trench 70 and its virtual gate 71, the electric field may be concentrated at the bottom of the gate structure 80 or the bottom of the well region 50, resulting in a lower voltage resistance (i.e., a lower breakdown voltage) and a lower probability of entering the breakdown state for the power semiconductor device without the virtual trench 70 and its virtual gate 71.

[0086] In some embodiments, the first element, the second element, the third element and the fourth element doped in the semiconductor substrate 30, the drift layer 40, the well region 50 and the doping region 60 can be realized by electrical dopants. In some embodiments, the first element group and the second element group are different element groups. For example, when the power semiconductor device 10 is an N-type MOSFET, the first element group is a pentavalent element group, and the second element group is a trivalent element group. At this time, the semiconductor substrate 30, the drift layer 40 and the doping region 60 form an N-type semiconductor due to being doped with elements in the pentavalent element group, and the well region 50 forms a P-type semiconductor due to being doped with elements in the trivalent element group; when the power semiconductor device 10 is a P-type MOSFET, the first element group is a trivalent element group, and the second element group is a pentavalent element group. At this time, the semiconductor substrate 30, the drift layer 40 and the doping region 60 form a P-type semiconductor due to being doped with elements in the trivalent element group, and the well region 50 forms an N-type semiconductor due to being doped with elements in the pentavalent element group. Elements in the trivalent element group are, for example, trivalent atoms such as boron (B), aluminum (Al), gallium (Ga), and indium (In). Elements in the pentavalent element group are, for example, pentavalent atoms such as arsenic (As), tellurium (Te), phosphorus (P), and bismuth (Bi). In some embodiments, the first element, the second element, and the fourth element may be the same element or different elements in the first element group. In some embodiments, the concentration of the first element doped in the semiconductor substrate 30 is greater than the concentration of the second element doped in the drift layer 40, the concentration of the third element doped in the well region 50 is greater than the concentration of the second element doped in the drift layer 40, and the concentration of the fourth element doped in the doping region 60 is greater than the concentration of the third element doped in the well region 50.

[0087] In some embodiments, the semiconductor substrate 30 is formed of silicon carbide, silicon, gallium nitride (GaN) or sapphire. In some embodiments, the real gate 81 and the virtual gate 71 can be formed of the same conductive material or different conductive materials, such as polysilicon (Poly-Si), titanium (Ti), aluminum, tungsten (W) or gold (Au).

[0088] like Figure 1 As shown, in some embodiments, the gate structure 80 includes a gate trench 82 that penetrates the doped region 60 and the well region 50. The real gate 81 is accommodated in the gate trench 82. In this way, when the power semiconductor device 10 is subjected to an electric field, the electric field is distributed at the bottom end 72 of the virtual trench 70 and the bottom end 821 of the gate trench 82. In some embodiments, the bottom end 821 of the gate trench 82 extends into the top 41 of the drift layer 40. In some embodiments, the bottom end 72 of the virtual trench 70 extends into the top 41 of the drift layer 40. In some embodiments, the cross-sections of the gate trench 82 and the virtual trench 70 can be the same shape or different shapes, such as a trapezoid or a long strip.

[0089] like Figure 1 As shown, in some embodiments, the dielectric layer 90 is distributed on the inner wall surface 73 of the virtual trench 70, the inner wall surface 822 of the gate trench 82, and the top surface 61 of the doped region 60. The virtual gate 71 is accommodated in the virtual trench 70 and contacts the dielectric layer 90 on the inner wall surface 73 of the virtual trench 70. In this way, the dielectric layer 90 isolates the virtual gate 71 from the doped region 60, the well region 50, and the drift layer 40 contacted by the outer wall surface 74 of the virtual trench 70. The real gate 81 is accommodated in the gate trench 82 and contacts the dielectric layer 90 on the inner wall surface 822 of the gate trench 82. In this way, the dielectric layer 90 isolates the real gate 81 from the doped region 60, the well region 50, and the drift layer 40 contacted by the outer wall surface 823 of the gate trench 82.

[0090] Reference Figure 2 , is a partial schematic diagram of the element structure of the power semiconductor device 10 of the first embodiment of the present invention. In some embodiments, the distance r1 between the bottom end 72 of each virtual trench 70 and the bottom 42 of the drift layer 40 is greater than or equal to the distance r2 between the bottom end 821 of the gate trench 82 and the bottom 42 of the drift layer 40. In other words, the depth of each virtual trench 70 (here, the distance that the bottom end 72 of the virtual trench 70 extends downward from the top surface 61 of the doped region 60) is less than or equal to the depth of the gate trench 82 (here, the distance that the bottom end 821 of the gate trench 82 extends downward from the top surface 61 of the doped region 60). In other words, the bottom of the gate structure 80 (for example, the bottom end 821 of the gate trench 82) is lower than or equal to the bottom end 72 of each virtual trench 70. For clarity of explanation, in Figure 2 Only the distance r1 between the bottom end 72 of each dummy trench 70 and the bottom 42 of the drift layer 40 is shown to be greater than the distance r2 between the bottom end 821 of the gate trench 82 and the bottom 42 of the drift layer 40. In some embodiments, the difference between the distance r1 between the bottom end 72 of each dummy trench 70 and the bottom 42 of the drift layer 40 and the distance r2 between the bottom end 821 of the gate trench 82 and the bottom 42 of the drift layer 40 is less than 1 micron. In this way, the electric field can be effectively and evenly dispersed.

[0091] like Figure 2As shown, in some embodiments, the distance r1 between the bottom end 72 of each virtual trench 70 and the bottom 42 of the drift layer 40 is the distance r2 between the bottom end 821 of the gate trench 82 and the bottom 42 of the drift layer 40 divided by the cosine value of the first center angle θ1 (as shown in Formula 1). The first center angle θ1 corresponds to the first arc length RL1, and the two ends of the first arc length RL1 are respectively the first corner c1 of the bottom end 72 of the virtual trench 70 and the second corner c2 of the virtual trench 70 adjacent to the bottom end 821 of the gate trench 82. The center of the circle where the first arc length RL1 is located is the point where the first corner c1 is vertically projected to the surface of the semiconductor substrate 30 (or the bottom 42 of the drift layer 40), and the radius is the distance r1.

[0092]

[0093] like Figure 2 As shown, in some embodiments, the distance r3 between the two sides of the gate trench 82 and the two virtual trenches 70 (specifically, the distance r3 is the distance between one side of the gate trench 82 and the adjacent virtual trench 70) is approximately the distance r1 between the bottom end 72 of each virtual trench 70 and the bottom 42 of the drift layer 40 multiplied by the sine value of the first central angle θ1 (as shown in Formula 2).

[0094] r3=r1×sinθ1……………………………………(Formula 2)

[0095] In some embodiments, the distance r3 between the two sides of the gate trench 82 and the two dummy trenches 70 is less than 8 microns. In a preferred embodiment, the distance r3 between the two sides of the gate trench 82 and the two dummy trenches 70 is less than 2 microns. In this way, an effective charge balancing effect can be achieved.

[0096] Reference Figure 3, is a schematic diagram of the element structure of the power semiconductor device 10 of the second embodiment of the present invention. The difference from the first embodiment is that in the second embodiment, the gate structure 80 is located on the dielectric layer 90, and the bottom 83 of the gate structure contacts the dielectric layer 90 and is higher than the bottom 72 of the virtual trench 70. For example, the distance between the bottom 83 of the gate structure and the bottom 42 of the drift layer 40 is greater than the distance between the bottom 72 of the virtual trench 70 and the bottom 42 of the drift layer 40. The doped region 60 includes two doped sub-regions 62, which are located under the dielectric layer 90, and the top surface 621 of the doped sub-region 62 contacts the dielectric layer 90. The two ends of the gate structure 80 are respectively facing the two doped sub-regions 62, and the vertical projection thereof is located at the inner side of one end of the corresponding doped sub-region 62. The well region 50 includes two well sub-regions 51, which are respectively located under the two doped sub-regions 62. The two virtual trenches 70 respectively penetrate the two doped sub-regions 62 and the two well sub-regions 51 under the two doped sub-regions 62. Specifically, one of the two virtual trenches 70 (the virtual trench 70 on the left side of the figure) penetrates one of the two doped sub-regions 62 (the doped sub-region 62 on the left side of the figure) and the well sub-region 51 thereunder (the well sub-region 51 on the left side of the figure), and the other of the two virtual trenches 70 (the virtual trench 70 on the right side of the figure) penetrates the other of the two doped sub-regions 62 (the doped sub-region 62 on the right side of the figure) and the well sub-region 51 thereunder (the well sub-region 51 on the right side of the figure). In this way, when the power semiconductor device 10 is subjected to an electric field, due to the capacitive effect of the virtual trench 70 and its virtual gate 71, the electric field is distributed at the bottom 72 of the virtual trench 70 and the bottom 511 of the well sub-region 51.

[0097] like Figure 3 As shown, in some embodiments, the two doped sub-regions 62 are horizontally separated from each other, and the two well sub-regions 51 are horizontally separated from each other. In some embodiments, the lateral width of the doped sub-region 62 is shorter than the lateral width of the well sub-region 51, and covers a portion of the top 512 of the well sub-region 51, and the remaining area of ​​the top 512 of the well sub-region 51 (i.e., the area of ​​the top 512 of the well sub-region 51 not covered by the doped sub-region 62) is hereinafter referred to as the inversion channel region CA. In some embodiments, the well sub-region 51 covers a portion of the top 41 of the drift layer 40, and the remaining area of ​​the top 41 of the drift layer 40 (i.e., the area of ​​the top 41 of the drift layer 40 not covered by the well sub-region 51) is hereinafter referred to as the junction region JA.

[0098] like Figure 3As shown, in some embodiments, the dielectric layer 90 is distributed on the inner wall surface 73 of the virtual trench 70, the top surface 621 of the doped sub-region 62, the inversion channel region CA, and the junction region JA. The virtual gate 71 is accommodated in the virtual trench 70 and contacts the dielectric layer 90 on the inner wall surface 73 of the virtual trench 70. In this way, the dielectric layer 90 isolates the virtual gate 71 from the doped sub-region 62, the well sub-region 51, and the drift layer 40 contacted by the outer wall surface 74 of the virtual trench 70. The real gate 81 of the gate structure 80 contacts the dielectric layer 90. Specifically, the dielectric layer 90 contacted by the real gate 81 of the gate structure 80 is distributed on the top surface of one end of each doped sub-region 62 (the vertical projection of the inner side of which is located at one of the two ends of the gate structure 80) (i.e., a partial area of ​​the top surface 621 of the doped sub-region 62), the inversion channel region CA, and the junction region JA. In this way, the dielectric layer 90 isolates the real gate 81 from the doped sub-region 62 , the well sub-region 51 and the drift layer 40 .

[0099] Reference Figure 4 , is a partial schematic diagram of the element structure of the power semiconductor device 10 according to the second embodiment of the present invention. In some embodiments, the distance r1 between the bottom end 72 of each virtual trench 70 and the bottom 42 of the drift layer 40 is greater than or equal to the distance r4 between the bottom 511 of each well sub-region 51 and the bottom 42 of the drift layer 40. In other words, the depth of each virtual trench 70 (here, the distance that the bottom end 72 of the virtual trench 70 extends downward from the top surface 621 of the doped sub-region 62) is less than or equal to the distance between the top surface 621 of the doped sub-region 62 and the bottom 511 of the well sub-region 51. For the sake of clarity, in Figure 4 Only the distance r1 between the bottom end 72 of each dummy trench 70 and the bottom 42 of the drift layer 40 is shown to be greater than the distance r4 between the bottom 511 of each well sub-region 51 and the bottom 42 of the drift layer 40. In some embodiments, the difference between the distance r1 between the bottom end 72 of each dummy trench 70 and the bottom 42 of the drift layer 40 and the distance r4 between the bottom 511 of each well sub-region 51 and the bottom 42 of the drift layer 40 is less than 1 micron. In this way, the electric field can be effectively and evenly dispersed.

[0100] like Figure 4As shown, in some embodiments, the distance r1 between the bottom end 72 of each virtual trench 70 and the bottom 42 of the drift layer 40 is the distance r4 between the bottom 511 of each well sub-region 51 and the bottom 42 of the drift layer 40 divided by the cosine value of the second center angle θ2 (as shown in Formula 3). The second center angle θ2 corresponds to the second arc length RL2, and the two ends of the second arc length RL2 are respectively the first corner c1 of the bottom end 72 of the virtual trench 70 and the third corner c3 of the bottom 511 of the well sub-region 51 that is penetrated and on the same side as the first corner c1. The center of the circle where the second arc length RL2 is located is the point where the first corner c1 is vertically projected to the surface of the semiconductor substrate 30 (or the bottom 42 of the drift layer 40), and the radius is the distance r1.

[0101]

[0102] like Figure 4 As shown, in some embodiments, the distance r5 between the adjacent side 513 between the two well sub-regions 51 (i.e., one side between the two well sub-regions 51 adjacent to each other) and the two virtual grooves 70 (specifically, the distance r5 is the distance between the adjacent side 513 of a certain well sub-region 51 and the virtual groove 70 passing through the certain well sub-region 51) is approximately the distance r1 between the bottom end 72 of each virtual groove 70 and the bottom 42 of the drift layer 40 multiplied by the sine value of the second central angle θ2 (as shown in Formula 4).

[0103] r5=r1×sinθ2……………………………………(Formula 4)

[0104] In some embodiments, the distance r5 between the adjacent sides 513 of the two well sub-regions 51 and the two dummy trenches 70 is less than 8 microns. In a preferred embodiment, the distance r5 between the adjacent sides 513 of the two well sub-regions 51 and the two dummy trenches 70 is less than 2 microns. In this way, an effective charge balancing effect can be achieved.

[0105] like Figure 1 and Figure 3 As shown, in some embodiments, the distance r6 between the top 75 of each virtual trench 70 (i.e., the top of the virtual gate 71 accommodated in the virtual trench 70) and the bottom 72 is less than 4 microns. In a preferred embodiment, the distance r6 between the top 75 and the bottom 72 of each virtual trench 70 is 1.5 microns.

[0106] Reference Figure 5, which is a schematic diagram of a dielectric layer 90 of some embodiments of the present invention. In some embodiments, the dielectric layer 90 is formed of a dielectric material with a high dielectric constant (e.g., a dielectric constant greater than 3.9). The dielectric material with a high dielectric constant is, for example, lanthanum aluminate (LaAlO3), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), gallium oxide (Ga2O3), aluminum oxide (Al2O3), titanium dioxide (TiO2) or tantalum pentoxide (Ta2O5). However, the present invention is not limited to this, and the dielectric layer 90 can also be formed of a dielectric material with a low dielectric constant (e.g., a dielectric constant less than or equal to 3.9). The dielectric material with a low dielectric constant is, for example, silicon dioxide (SiO2), silicon oxynitride (SiON) or silicon nitride (SiN). In the case where the dielectric layer 90 is formed of a dielectric material with a high dielectric constant, since the dielectric material with a high dielectric constant is a polar material, negative charges (such as ions) may be formed at the contact between the dielectric layer 90 on the inner wall surface 73 of the virtual trench 70 and the well region 50 (i.e., the outer wall surface 74 of the virtual trench 70) and at the contact between the dielectric layer 90 on the inner wall surface 73 of the virtual trench 70 and the drift layer 40 (i.e., the outer wall surface 74 of the virtual trench 70). Figure 5 ), and forms positive charges in the virtual trench 70 through a dipole effect (such as Figure 5 In this way, the charge amount, charge distribution and electric field distribution of the outer wall surface 74 of the virtual groove 70 can be adjusted by the dielectric layer 90 formed of a dielectric material with a high dielectric constant, so that the electric field is dispersed rather than concentrated.

[0107] like Figure 1 and Figure 3 As shown, in the first embodiment and the second embodiment, the power semiconductor device 10 includes two contact pads (hereinafter referred to as the first contact pad CT1), which penetrate the dielectric layer 90 and contact the doped region 60 (or contact the two doped sub-regions 62 of the doped region 60 respectively) and do not contact each virtual gate 71. The first contact pad CT1 serves as the source external terminal (hereinafter referred to as the source terminal) of the power semiconductor device 10 to receive the voltage from the outside and transmit the voltage to the doped region 60 (or the two doped sub-regions 62 of the doped region 60). In the first embodiment and the second embodiment, since the virtual gate 71 of the virtual trench 70 is not connected to any contact pad (such as the two first contact pads CT1), the virtual gate 71 of the virtual trench 70 is floating. Specifically, the potential of the virtual gate 71 of the virtual trench 70 is floating rather than fixed. Therefore, the virtual gate 71 of the virtual trench 70 can preferably generate a capacitive effect to disperse the electric field distribution. In some embodiments, the first contact pad CT1 is a conductor composed of a metal material, which has a higher conductivity than a semiconductor, and a semiconductor has a higher conductivity than an insulator. The metal material is, for example, gold, silver, aluminum, or copper.

[0108] Reference Figure 6 , is a schematic diagram of the element structure of the power semiconductor device 10 of the third embodiment of the present invention. Like the first and second embodiments, the power semiconductor device 10 of the third embodiment also includes a semiconductor substrate 30, a drift layer 40, a well region 50, a doping region 60, two virtual trenches 70, a gate structure 80 and a dielectric layer 90. The main difference is that the power semiconductor device 10 of the third embodiment has two contact pads (hereinafter referred to as the second contact pad CT2), which respectively contact the virtual gates 71 of the two virtual trenches 70 and do not contact the doping region 60. The second contact pad CT2 serves as the source terminal of the power semiconductor device 10, and its composition is the same or similar to that of the first contact pad CT1, so it is not repeated. The second contact pad CT2 receives a voltage from the outside and transmits the voltage to the virtual gate 71 of the virtual trench 70. That is, in the third embodiment, the virtual gate 71 of the virtual trench 70 is non-floating, that is, the potential of the virtual gate 71 of the virtual trench 70 is controlled by the external voltage received by the second contact pad CT2.

[0109] like Figure 1 , Figure 3 and Figure 6 As shown, in some embodiments, the power semiconductor device 10 further includes an intermetallic dielectric layer 100 located on the dielectric layer 90, each dummy gate 71 and the real gate 81. In some embodiments, the intermetallic dielectric layer 100 can be formed of silicon glass (PSG) or borophosphosilicate glass (BPSG). Figure 1 and Figure 3 As shown, in the first embodiment and the second embodiment, the two first contact pads CT1 penetrate the intermetallic dielectric layer 100 and the dielectric layer 90 and contact the doped region 60 (or contact the two doped sub-regions 62 of the doped region 60 respectively) and do not contact each dummy gate 71. Figure 6 As shown, in the third embodiment, the two second contact pads CT2 penetrate the intermetallic dielectric layer 100 and contact the dummy gates 71 of the two dummy trenches 70 respectively and do not contact the doped region 60 .

[0110] like Figure 1 , Figure 3 and Figure 6 As shown, in some embodiments, the power semiconductor device 10 further includes another contact pad (hereinafter referred to as the third contact pad CT3), which penetrates the intermetallic dielectric layer 100 and contacts the real gate 81. The third contact pad CT3 serves as the gate external terminal (hereinafter referred to as the gate terminal) of the power semiconductor device 10, and its composition is the same or similar to that of the first contact pad CT1, so it is not repeated. The third contact pad CT3 receives a voltage from the outside and transmits the voltage to the real gate 81.

[0111] like Figure 1 , Figure 3 and Figure 6 As shown, in some embodiments, the power semiconductor device 10 further includes another contact pad (hereinafter referred to as the fourth contact pad CT4), which is located under the semiconductor substrate 30. The fourth contact pad CT4 serves as a drain external terminal (hereinafter referred to as the drain terminal) of the power semiconductor device 10, and its composition is the same or similar to that of the first contact pad CT1, so it is not repeated. The fourth contact pad CT4 receives a voltage from the outside and transmits the voltage to the semiconductor substrate 30.

[0112] In the first embodiment and the third embodiment, the power semiconductor device 10 may be a vertical trench MOSFET. In the second embodiment, the power semiconductor device 10 may be a vertical double diffused MOSFET.

[0113] Next, the manufacturing process of the above-mentioned embodiment will be described. Figure 7 FIG. 1 is a flowchart of a manufacturing process of a power semiconductor device 10 according to some embodiments of the present invention. Figures 8 to 12 Schematic diagram of the structure of the power semiconductor device 10 to be manufactured at different stages of the manufacturing process method according to the first embodiment of the present invention. Figures 13 to 17 Schematic diagram of the structure of a power semiconductor device 10 to be manufactured at different stages of a manufacturing process method according to a second embodiment of the present invention. Figures 18 to 22 Schematic diagram of the structure of a power semiconductor device 10 to be manufactured at different stages of a manufacturing process method according to a third embodiment of the present invention.

[0114] First, if Figure 8 , Fig.13 and Fig.18 As shown, a drift layer 40 is formed on the semiconductor substrate 30 ( Figure 7 Step S700). For example, a drift layer 40 is formed on a semiconductor substrate 30 by a gas phase epitaxy process. Then, a well region 50 is formed on the drift layer 40 ( Figure 7 Step S702), and forming a doped region 60 on the well region 50 ( Figure 7 Step S704). For example, Figure 8 and Fig.18 As shown, in the first embodiment and the third embodiment, a well region 50 is formed on the drift layer 40 by an ion implantation process, and a doped region 60 is formed on the well region 50; Fig.13 As shown, in the second embodiment, two well sub-regions 51 of the well region 50 are formed on the drift layer 40 through etching and ion implantation processes, and two doped sub-regions 62 of the doped region 60 are formed on the two well sub-regions 51 .

[0115] Then, if Fig. 9 , Fig.14 and Fig.19 As shown, a groove is formed ( Figure 7 Step S706). For example, Fig. 9 and Fig.19 As shown, in the first embodiment and the third embodiment, the dummy trench 70 and the gate trench 82 of the gate structure 80 are formed by etching process, both of which penetrate the doped region 60 and the well region 50, and the bottom end 72 of the dummy trench 70 and the bottom end 821 of the gate trench 82 can be extended into the drift layer 40; Fig.14 As shown, in the second embodiment, a dummy trench 70 is formed by an etching process, which penetrates the doped sub-region 62 of the doped region 60 and the well sub-region 51 of the well region 50 .

[0116] Then, if Fig.10 , Fig.15 and Fig. 20 As shown, a dielectric layer 90 ( Figure 7 Step S708). For example, Fig.10 and Fig. 20 As shown, in the first embodiment and the third embodiment, a dielectric layer 90 is formed on the inner wall surface 73 of the dummy trench 70, the inner wall surface 822 of the gate trench 82 and the top surface 61 of the doped region 60 by a deposition process; Fig.15 As shown, in the second embodiment, a dielectric layer 90 is formed on the inner wall surface 73 of the dummy trench 70, the top surface 621 of the doped sub-region 62 of the doped region 60, the channel region CA and the junction region JA through a deposition process.

[0117] Then, if Figure 11 to Figure 12 , Figure 16 to Figure 17 and Figure 21 to Figure 22 As shown, a virtual gate 71 and a real gate 81 are formed ( Figure 7 Step S710). For example, Fig.11 , Fig.16 and Fig.21 As shown, a conductive material CM is deposited on the dielectric layer 90 by a deposition process. The conductive material CM is, for example, polysilicon, titanium, aluminum, tungsten or gold. Fig.12 , Fig.17 and Fig. 22 As shown, the conductive material CM is subjected to an etching process to form a virtual gate 71 and a real gate 81 implemented by the conductive material CM. Fig.12 and Fig. 22 As shown, in the first embodiment and the third embodiment, a virtual gate 71 is formed in the virtual trench 70, and a real gate 81 is formed in the gate trench 82; Fig.17 As shown, in the second embodiment, a dummy gate 71 is formed in the dummy trench 70 , and a real gate 81 is formed on the dielectric layer 90 .

[0118] Then, if Figure 1 , Figure 3 , Figure 6 As shown, a metal interlayer dielectric layer 100 ( Figure 7 Step S712) and forming a contact pad ( Figure 7 Step S714). For example, a metal interlayer dielectric layer 100 is formed on the dielectric layer 90, each dummy gate 71 and the real gate 81 through a deposition process. Then, the metal interlayer dielectric layer 100 and the dielectric layer 90 are etched, and a metal sputtering process is performed with a metal material to form a contact pad (for example, Figure 1 , Figure 3 and Figure 6 Next, a back metal coating process is performed on the bottom of the semiconductor substrate 30 to form a fourth contact pad CT4. After other processes (such as packaging processes) are performed, the power semiconductor device 10 can be manufactured.

[0119] Reference Figure 23 to Figure 33 . Fig.23 Schematic diagram of characteristic parameters of a power semiconductor device without a dummy trench 70 according to a comparative example of the present invention and characteristic parameters of the power semiconductor device 10 according to some embodiments of the present invention at different values ​​of the distance r6 between the top 75 and the bottom 72 of the dummy trench 70 . Fig.24 is the gate voltage (V g ) and drain current (I d ) and a schematic diagram of characteristic curves between gate voltage and drain current at different values ​​of the distance r6 between the top 75 and the bottom 72 of the virtual trench 70 of the power semiconductor device 10 in some embodiments of the present invention. Fig.25 is the drain voltage (V d ) and a characteristic curve between the drain voltage and the drain current and a schematic diagram of a characteristic curve between the drain voltage and the drain current of the power semiconductor device 10 of some embodiments of the present invention at different values ​​of the distance r6 between the top 75 and the bottom 72 of the virtual trench 70. Fig.26 FIG. 1 is a schematic diagram of electric field distribution of a power semiconductor device without a dummy trench 70 according to a comparative example of the present invention. Fig. 27 FIG. 1 is a schematic diagram of electric field distribution of a power semiconductor device 10 according to some embodiments of the present invention when the distance r6 between the top end 75 and the bottom end 72 of a virtual trench 70 is 1 micrometer. Fig.28FIG. 1 is a schematic diagram of electric field distribution of the power semiconductor device 10 according to some embodiments of the present invention when the distance r6 between the top end 75 and the bottom end 72 of the dummy trench 70 is 1.5 micrometers. Fig.29 FIG. 1 is a schematic diagram of electric field distribution of the power semiconductor device 10 according to some embodiments of the present invention when the distance r6 between the top end 75 and the bottom end 72 of the virtual trench 70 is 2 micrometers. Fig.30 FIG. 1 is a schematic diagram of electric field distribution of the power semiconductor device 10 according to some embodiments of the present invention when the distance r6 between the top end 75 and the bottom end 72 of the dummy trench 70 is 2.5 micrometers. Fig.31 FIG. 1 is a schematic diagram of electric field distribution of the power semiconductor device 10 according to some embodiments of the present invention when the distance r6 between the top end 75 and the bottom end 72 of the virtual trench 70 is 3 micrometers. Fig.32 FIG. 1 is a schematic diagram of electric field distribution of the power semiconductor device 10 according to some embodiments of the present invention when the distance r6 between the top end 75 and the bottom end 72 of the dummy trench 70 is 3.5 micrometers. Fig.33 Schematic diagram of electric field distribution of the power semiconductor device 10 of some embodiments of the present invention when the distance r6 between the top 75 and the bottom 72 of the virtual trench 70 is 4 microns. The comparative example of the present invention is a power semiconductor device without the virtual trench 70, and thus does not have the distance r6 between the top 75 and the bottom 72 of the virtual trench 70, that is, the distance r6 is 0. For the convenience of explanation, the distance r6 between the top 75 and the bottom 72 of the virtual trench 70 is referred to as the depth of the virtual trench 70 hereinafter.

[0120] from Figure 23 to Figure 33It can be seen that as the depth of the virtual groove 70 gradually increases from 0, the virtual groove 70 and its virtual gate 71 form a capacitive effect, so as to gradually attract the electric field concentrated at the bottom of the gate structure 80 (for example, the bottom end 821 of the gate groove 82) or the bottom of the well region 50 to the bottom end 72 of the virtual groove 70, thereby gradually increasing the breakdown voltage while slightly sacrificing the current density of the power semiconductor device 10. After the depth of the virtual groove 70 exceeds 1.5 microns, as the depth of the virtual groove 70 increases, the attraction of the virtual groove 70 and its virtual gate 71 to the electric field will be stronger than the attraction of the gate structure 80 and its real gate 81 to the electric field, causing the electric field to be concentrated at the bottom end 72 of the virtual groove 70, and the increase in the breakdown voltage will gradually decrease. Therefore, when the depth of the virtual groove 70 is 1.5 microns, the virtual groove 70 and its virtual gate 71 have the largest increase in the breakdown voltage of the power semiconductor device 10. Specifically, compared to the comparative example, when the depth of the dummy trench 70 is 1.5 μm, the breakdown voltage of the power semiconductor device 10 of some embodiments of the present invention is increased by at least 600 volts (V) (e.g., 622 V). Compared to the comparative example, when the depth of the dummy trench 70 is other than 1.5 μm (e.g., 1 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm), the breakdown voltage of the power semiconductor device 10 of some embodiments of the present invention is still increased to a certain extent.

[0121] Reference Figure 34 to Figure 38 . Fig.34 Schematic diagram of parasitic capacitance of a power semiconductor device without a dummy trench 70 according to a comparative example of the present invention and parasitic capacitance of a power semiconductor device 10 according to some embodiments of the present invention under different values ​​of the distance r6 between the top 75 and the bottom 72 of the dummy trench 70 . Fig.35 is the gate-drain parasitic capacitance (C gd ) and the drain voltage and a schematic diagram of the characteristic curve of the gate-drain parasitic capacitance and the drain voltage of the power semiconductor device 10 of some embodiments of the present invention at different values ​​of the distance r6 between the top 75 and the bottom 72 of the virtual trench 70. Fig.36 Schematic diagram of the rise time and fall time of a power semiconductor device without a dummy trench 70 according to a comparative example of the present invention and the rise time and fall time of the power semiconductor device 10 according to some embodiments of the present invention at different values ​​of the distance r6 between the top 75 and the bottom 72 of the dummy trench 70. Fig.37Schematic diagram of a characteristic curve between the drain voltage and the transition time when a power semiconductor device without a dummy trench 70 of a comparative example of the present invention is turned on, and a schematic diagram of a characteristic curve between the drain voltage and the transition time when a power semiconductor device 10 of some embodiments of the present invention is turned on at different values ​​of the distance r6 between the top 75 and the bottom 72 of the dummy trench 70. Fig.38 Schematic diagram of a characteristic curve between drain voltage and transfer time when a power semiconductor device without a virtual trench 70 of a comparative example of the present invention is turned off (i.e., not conducting) and a characteristic curve between drain voltage and transfer time when a power semiconductor device 10 of some embodiments of the present invention is turned off at different values ​​of the distance r6 between the top 75 and the bottom 72 of the virtual trench 70. The comparative example of the present invention is a power semiconductor device without a virtual trench 70, and thus does not have the distance r6 between the top 75 and the bottom 72 of the virtual trench 70, i.e., the distance r6 is 0. For the convenience of explanation, the distance r6 between the top 75 and the bottom 72 of the virtual trench 70 is referred to as the depth of the virtual trench 70 hereinafter.

[0122] exist Fig.34 In the gate-source parasitic capacitance (C gs ) represents the parasitic capacitance between the gate and the source of the power semiconductor device without the dummy trench 70 of the comparative example of the present invention and the parasitic capacitance between the gate and the source of the power semiconductor device 10 of some embodiments of the present invention. ds ) represents the parasitic capacitance between the drain and source of the power semiconductor device without the dummy trench 70 of the comparative example of the present invention and the parasitic capacitance between the drain and source of the power semiconductor device 10 of some embodiments of the present invention. gd ) represents the parasitic capacitance between the gate and drain of the power semiconductor device without the dummy trench 70 of the comparative example of the present invention and the parasitic capacitance between the gate and drain of the power semiconductor device 10 of some embodiments of the present invention. Input power capacitance (C iss ) is the sum of the gate-source parasitic capacitance and the gate-drain parasitic capacitance. Output power capacitance (C oss ) is the sum of the drain-source parasitic capacitance and the gate-drain parasitic capacitance. Feedback capacitor (also called reverse transfer capacitor) (C rss ) is the gate-drain parasitic capacitance. The rise time is the voltage between the drain and the source (i.e., the drain-source voltage (V ds The fall time is the time for the voltage between the drain and source (or the drain voltage) to rise from 10% to 90%.

[0123] from Figure 34 to Figure 38 It can be seen that compared with the comparative example, the power semiconductor device 10 of some embodiments of the present invention has better dynamic characteristics through the virtual trench 70 and its virtual gate 71. For example, the rise time and fall time of the power semiconductor device 10 have better time values, and the parasitic capacitance has a better capacitance value to reduce the conduction loss and the turn-off loss. Figure 34 to Figure 38 In the embodiment of the present invention, when the depth of the dummy trench 70 is 1.5 micrometers, the power semiconductor device 10 has optimized dynamic characteristics.

[0124] In summary, according to some embodiments, the present invention can balance the charges and evenly disperse the electric field through the virtual trench and its virtual gate, so that the electric field will not be concentrated at the bottom of the well region or the bottom of the gate structure (such as the bottom of the gate trench). In this way, the voltage resistance of the power semiconductor device can be improved (i.e., the breakdown voltage is improved), so that the power semiconductor device will have a later avalanche breakdown.

Claims

1. A power semiconductor device, characterized in that: Include: A semiconductor substrate doped with a first element of a first element group and having a first conductive path; a drift layer, located on the semiconductor substrate, wherein the drift layer is doped with a second element in the first element group and has the first conductive channel; A well region, located on the drift layer, the well region is doped with a third element in the second group of elements to have a second conductive channel, and the polarity of the second conductive channel is opposite to that of the first conductive channel; a doped region, located on the well region, wherein the doped region is doped with a fourth element in the first element group and has the first conductive channel; Two virtual trenches, penetrating the doped region and the well region, each of the virtual trenches having a virtual gate; A gate structure, located between the two virtual trenches, the gate structure having a real gate; and A dielectric layer isolates each of the virtual gates from the doped region, the well region and the drift layer, and isolates the real gate from the doped region, the well region and the drift layer.

2. The power semiconductor device according to claim 1, characterized in that: The gate structure includes a gate trench penetrating the doped region and the well region, and the real gate is accommodated in the gate trench.

3. The power semiconductor device according to claim 2, characterized in that: The bottom of the gate structure is lower than or equal to the bottom of each of the virtual trenches.

4. The power semiconductor device according to claim 2, characterized in that: The distance between the bottom end of each of the dummy trenches and the bottom of the drift layer is greater than or equal to the distance between the bottom end of the gate trench and the bottom of the drift layer.

5. The power semiconductor device according to claim 4, characterized in that: The distance between the bottom end of each virtual trench and the bottom of the drift layer is the distance between the bottom end of the gate trench and the bottom of the drift layer divided by the cosine value of the first central angle, wherein the first central angle corresponds to the first arc length between the first corner of the bottom end of each virtual trench and the second corner of the bottom end of the gate trench, and the second corner is adjacent to the first corner.

6. The power semiconductor device according to claim 2, characterized in that: The distance between the two sides of the gate trench and the two virtual trenches is the distance between the bottom of each virtual trench and the bottom of the drift layer multiplied by the sine value of the first central angle, wherein the first central angle corresponds to the first arc length between the first corner of the bottom of each virtual trench and the second corner of the bottom of the gate trench, and the second corner is adjacent to the first corner.

7. The power semiconductor device according to claim 1, characterized in that: The gate structure is located on the dielectric layer, and the bottom of the gate structure contacts the dielectric layer and is higher than the bottom end of each dummy trench.

8. The power semiconductor device according to claim 7, characterized in that: The doped region includes two doped sub-regions located under the dielectric layer. The top surface of each doped sub-region contacts the dielectric layer. Two ends of the gate structure face the two doped sub-regions respectively.

9. The power semiconductor device according to claim 8, characterized in that: The well region includes two well sub-regions respectively located under the two doped sub-regions, and the two virtual trenches respectively penetrate the two doped sub-regions and the two well sub-regions under the two doped sub-regions.

10. The power semiconductor device according to claim 9, characterized in that: The distance between the bottom end of each of the dummy trenches and the bottom of the drift layer is greater than or equal to the distance between the bottom of each of the well sub-regions and the bottom of the drift layer.

11. The power semiconductor device according to claim 10, characterized in that: The distance between the bottom of each virtual trench and the bottom of the drift layer is the distance between the bottom of each well sub-region and the bottom of the drift layer divided by the cosine value of the second central angle, the second central angle corresponds to the second arc length between the first corner of the bottom of each virtual trench and the third corner of the bottom of the well sub-region that is penetrated, the first corner and the third corner are respectively located on the same side of the bottom of each virtual trench and the bottom of the well sub-region that is penetrated.

12. The power semiconductor device according to claim 9, characterized in that: The distance between the adjacent sides of the two well sub-regions and the two virtual trenches is the distance between the bottom of each of the virtual trenches and the bottom of the drift layer multiplied by the sine value of the second central angle, and the second central angle corresponds to the second arc length between the first corner of the bottom of each of the virtual trenches and the third corner of the bottom of the well sub-region corresponding to the penetration, and the first corner and the third corner are respectively located on the same side of the bottom of each of the virtual trenches and the bottom of the well sub-region corresponding to the penetration.

13. The power semiconductor device according to claim 1, characterized in that: It also includes two contact pads, which penetrate the dielectric layer and contact the doped region but do not contact the virtual gates.

14. The power semiconductor device according to claim 13, characterized in that: It also includes an intermetallic dielectric layer located on the dielectric layer, each of the virtual gates and the real gate. The two contact pads penetrate the intermetallic dielectric layer and the dielectric layer to contact the doped region but do not contact each of the virtual gates.

15. The power semiconductor device according to claim 14, characterized in that: The invention also comprises another contact pad which penetrates through the intermetallic dielectric layer and contacts the real gate.

16. The power semiconductor device according to claim 1, characterized in that: The invention also comprises two contact pads, which respectively contact the virtual gates and do not contact the doped regions.

17. The power semiconductor device according to claim 16, characterized in that: It also includes a metal interlayer dielectric layer located on the dielectric layer, each of the virtual gates and the real gate. The two contact pads penetrate the metal interlayer dielectric layer and contact each of the virtual gates respectively but do not contact the doped region.

18. The power semiconductor device according to claim 17, characterized in that: The invention also comprises another contact pad which penetrates through the intermetallic dielectric layer and contacts the real gate.

19. The power semiconductor device according to claim 1, characterized in that: The dielectric layer is formed of a dielectric material having a dielectric constant greater than 3.

9.

20. The power semiconductor device according to claim 1, characterized in that The dielectric layer is formed of a dielectric material having a dielectric constant less than or equal to 3.9.

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