Fast recovery diode with high withstand voltage and low conduction voltage drop and preparation method thereof

Abstract

The invention discloses a fast recovery diode with high withstand voltage and low conduction voltage drop and a preparation method, and relates to the field of semiconductor devices.The fast recovery diode comprises an N-type base region and a plurality of floating junction layers which are arranged in the N-type base region in a stacked mode, and each floating junction layer comprises at least one P-type floating region; the P-type floating region is used for improving the reverse breakdown voltage of the fast recovery diode. The fast recovery diode has relatively low forward conduction voltage drop, relatively high reverse recovery softness and reverse voltage resistance, and has good comprehensive performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a fast recovery diode with high withstand voltage and low on-state voltage drop and a preparation method thereof. Background Art

[0002] Fast recovery diode (FRD) is one of the most commonly used basic components and is widely used in electronic circuits. Shorter reverse recovery time, higher breakdown voltage, lower reverse cut-off current, softer recovery characteristics and lower forward conduction voltage drop are important requirements for fast recovery diodes. In particular, the switching speed of semiconductor power devices has increased rapidly in recent years, and higher and higher requirements have been placed on the reverse recovery speed of the diodes connected in parallel with them.

[0003] The structure of traditional FRD is as follows Figure 1 As shown in the figure, it consists of three parts: the anode P+ region, the base N- region and the cathode N+ region. When forward conduction occurs, the N- region stores a large number of carriers from the P+ region and the N+ region. The carriers injected into the N- region form excess carriers, resulting in a high conductivity modulation effect, which reduces the resistance of the N- region and thus reduces the forward conduction voltage drop of the FRD. When a reverse bias is applied, under the action of an external electric field, the carriers in the N- region are extracted to form a depletion region, and the diode is converted to a reverse blocking state.

[0004] It takes a certain amount of time for the carriers to be extracted from the N-region in the reverse direction. We call this process that affects the FRD turn-off speed reverse recovery, and the time required during this period is the reverse recovery time. Figure 2 As shown in Figure 2. The shorter the reverse recovery time, the higher the operating frequency of the FRD and the lower the energy consumption. Figure 2 As shown in the figure, the reverse recovery time trr is the sum of the storage time ta and the fall time tb, that is, trr=ta+tb. The total amount of charge that needs to be extracted or recombined from the N-region during the reverse recovery period is called the reverse recovery charge Qrr. The ratio of tb to ta is called the softness factor S. The larger the softness factor S, the better the reverse recovery softness, that is, the device can effectively avoid voltage overshoot and oscillation caused by hard recovery, and has better stability and reliability.

[0005] The thickness of the N-region is proportional to the forward voltage drop of the fast recovery diode. We hope to set a thinner N-region to reduce the forward voltage drop, but a thinner N-region will reduce the softness of reverse recovery and reverse withstand voltage, reducing the reliability of the device. Therefore, it is challenging to design a fast recovery diode that takes into account important performance parameters such as the forward voltage drop, reverse recovery softness, reverse recovery time, and reverse withstand voltage of the diode. Summary of the invention

[0006] In view of the above problems and technical requirements, the inventors have proposed a fast recovery diode with high withstand voltage and low on-state voltage drop and a preparation method thereof. The technical solution of the present invention is as follows: A fast recovery diode with high withstand voltage and low on-state voltage drop comprises an N-type base region and a plurality of floating junction layers stacked on each other and arranged in the N-type base region, wherein: The floating junction layer includes at least one P-type floating region, and the P-type floating region is used to increase the reverse breakdown voltage of the fast recovery diode.

[0007] A further technical solution is that when the floating junction layer includes two or more P-type floating regions, the P-type floating regions are arranged at intervals along a first direction, and the first direction is perpendicular to the thickness direction of the N-type base region.

[0008] A further technical solution is that when the N-type base region includes two or more floating junction layers, the P-type floating regions in adjacent floating junction layers are isolated from each other by the N-type base region.

[0009] A further technical solution is that the plurality of floating junction layers are arranged above a gradient buffer zone, and the gradient buffer zone includes a plurality of N-type buffer layers; The doping concentration of the multiple N-type buffer layers in the gradient buffer area decreases in sequence in a direction from the gradient buffer area to the floating junction layer.

[0010] A further technical solution is that a P-type anode region is provided above the N-type base region; An anode metal for forming an anode is prepared above the P-type anode region, and the P-type anode region is in ohmic contact with the anode metal.

[0011] A further technical solution is that the doping concentration of the P-type anode region is greater than the doping concentration of the P-type floating region.

[0012] A further technical solution is that an N-type cathode region is arranged below the gradient buffer zone, a cathode metal for forming a cathode is prepared below the N-type cathode region, and the N-type cathode region is in ohmic contact with the cathode metal.

[0013] A further technical solution is that the maximum doping concentration of the N-type buffer layer in the gradient buffer zone is less than the doping concentration of the N-type cathode region, and the minimum doping concentration of the N-type buffer layer in the gradient buffer zone is greater than the doping concentration of the N-type base region.

[0014] A method for preparing a fast recovery diode with high withstand voltage and low on-state voltage drop is used to prepare the above-mentioned fast recovery diode, the preparation method comprising preparing an N-type base region and a plurality of floating junction layers stacked on each other in the N-type base region, wherein: The floating junction layer includes at least one P-type floating region, and the P-type floating region is used to increase the reverse breakdown voltage of the fast recovery diode.

[0015] A further technical solution is that the preparation method comprises providing an N-type substrate, preparing a gradient buffer zone on the N-type substrate before preparing the N-type base region and the floating junction layer, and preparing the N-type base region and the floating junction layer on the gradient buffer zone; When preparing the N-type base region and the floating junction layer, it includes growing several layers of N-type epitaxial layers with the same doping concentration on the gradient buffer zone. After each layer of N-type epitaxial layer is grown, P-type doping ions are implanted into the corresponding N-type epitaxial layer to prepare the floating junction layer. The thickness of each N-type epitaxial layer ranges from 8μm to 13μm.

[0016] The beneficial technical effects of the present invention are: The present invention proposes a fast recovery diode with high withstand voltage and low conduction voltage drop. By setting a multi-layer floating junction layer in the N-type base region to form a floating junction structure, the reverse withstand voltage of the fast recovery diode is increased. On the basis of enabling the fast recovery diode to withstand a larger reverse withstand voltage, the thickness of the N-type base region can be reduced, and the forward conduction voltage drop of the diode can be effectively reduced. At the same time, the thinner N-type base region can also reduce the charge storage capacity of the fast recovery diode, thereby effectively reducing the reverse recovery time. The thinner N-type base region will reduce the softness of the reverse recovery, so the present invention also improves the reverse recovery softness of the fast recovery diode by setting a gradual buffer zone, thereby ensuring the comprehensive performance of the fast recovery diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a cross-sectional schematic diagram of a traditional fast recovery diode structure.

[0018] Figure 2 It is the reverse recovery characteristic waveform of the fast recovery diode.

[0019] Figure 3 The cross-sectional schematic diagram is a schematic diagram of an embodiment of a fast recovery diode with high withstand voltage and low on-state voltage drop provided by the present invention.

[0020] Figure 4-Figure 13 This is a cross-sectional view of the process steps of an embodiment of a method for preparing a fast recovery diode with high withstand voltage and low on-state voltage drop provided by the present invention, wherein: Figure 4 It is a cross-sectional view of an embodiment of an N-type substrate provided by the present invention.

[0021] Figure 5 It is a cross-sectional view of an embodiment of the present invention after the first N-type buffer layer is prepared.

[0022] Figure 6 It is a cross-sectional view of an embodiment of the present invention after preparing the second N-type buffer layer.

[0023] Figure 7 It is a cross-sectional view of an embodiment of the present invention after preparing the third N-type buffer layer.

[0024] Figure 8 It is a cross-sectional view of an embodiment of the present invention after a layer of N-type epitaxial layer is prepared.

[0025] Fig. 9 It is a cross-sectional view of an embodiment of the present invention after a floating junction layer is prepared.

[0026] Fig.10 It is a cross-sectional view of an embodiment of the present invention in which a P-type anode region is prepared.

[0027] Fig.11 It is a cross-sectional view of another embodiment of the present invention after platinum metal is deposited.

[0028] Fig.12 It is a cross-sectional view of another embodiment of the present invention for cleaning platinum metal.

[0029] Fig.13 It is a cross-sectional view of an embodiment of the present invention after performing a backside thinning process on an N-type substrate.

[0030] Explanation of the accompanying drawings: 1-N-type base region, 2-P-type anode region, 3-N-type cathode region, 4-N-type substrate, 5-N-type epitaxial layer, 6-first mask, 10-floating junction layer, 11-P-type floating region, 20-gradient buffer layer, 21-first N-type buffer layer, 22-second N-type buffer layer, 23-third N-type buffer layer. DETAILED DESCRIPTION

[0031] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0032] The present invention provides a fast recovery diode with high withstand voltage and low on-state voltage drop, comprising an N-type base region 1, and a plurality of floating junction layers 10 stacked on each other and arranged in the N-type base region 1, wherein: The floating junction layer 10 includes at least one P-type floating region 11 , and the P-type floating region 11 is used to increase the reverse breakdown voltage of the fast recovery diode.

[0033] Specifically, the floating junction layer 10 is stacked up and down in the N-type base region 1, and at least one P-type floating region 11 is set in each floating junction layer 10, and the P-type floating region 11 forms a PN floating junction structure with the N-type base region 1. When the device works in the reverse state, the floating junction structure can increase the reverse breakdown voltage of the device while keeping the doping concentration and thickness of the N-type base region 1 unchanged, that is, improve the reverse withstand voltage capability of the fast recovery diode. On the basis that the floating junction layer 10 enables the fast recovery diode to withstand a greater reverse withstand voltage, the thickness of the N-type base region 1 can be reduced, and setting a thinner N-type base region 1 can effectively reduce the forward conduction voltage drop of the diode. At the same time, the thinner N-type base region 1 can also reduce the charge storage capacity of the fast recovery diode, thereby effectively reducing the reverse recovery time of the fast recovery diode.

[0034] Further, when the floating junction layer 10 includes two or more P-type floating regions 11, the P-type floating regions 11 are arranged at intervals along a first direction, and the first direction is perpendicular to the thickness direction of the N-type base region 1. When the N-type base region 1 includes two or more floating junction layers 10, the P-type floating regions 11 in adjacent floating junction layers 10 are isolated from each other by the N-type base region 1.

[0035] Figure 3 A cross-sectional view of a fast recovery diode in an embodiment of the present invention is shown. In this embodiment, three floating junction layers 10 are provided in the N-type base region 1. In order to facilitate preparation and reduce process costs, the number, structure and distribution of the P-type floating regions 11 in each floating junction layer 10 in this embodiment are the same. In this embodiment, for any floating junction layer 10, three P-type floating regions 11 arranged at intervals along the first direction are provided in the floating junction layer 10. The spacing between adjacent P-type floating regions 11 in the same floating junction layer 10 is equal, and the spacing between the upper and lower adjacent P-type floating regions 11 in the floating junction layers 10 of two adjacent layers is also equal. The P-type floating region 11 can be prepared by ion implantation, and after diffusion, it is a semi-elliptical shape. The reverse breakdown voltage of the fast recovery diode can reach 1200V. In specific implementation, the number of floating junction layers 10, the number, shape and distribution of the P-type floating regions 11 in each floating junction layer 10 can be set according to actual needs to meet the design of the withstand voltage performance of the fast recovery diode.

[0036] Further, the plurality of floating junction layers 10 are disposed above the gradient buffer layer 20, and the gradient buffer layer 20 includes multiple N-type buffer layers; The doping concentrations of the multiple N-type buffer layers in the gradient buffer zone 20 decrease in sequence in a direction from the gradient buffer zone 20 to the floating junction layer 10 .

[0037] Since the thinner N-type base region 1 will reduce the softness of the reverse recovery of the fast recovery diode, resulting in voltage overshoot and oscillation, and reducing the reliability of the device, the present invention is also provided with a gradient buffer 20 for improving the softness of the reverse recovery of the fast recovery diode, thereby ensuring the comprehensive performance of the fast recovery diode. Specifically, in one embodiment of the present invention, the gradient buffer 20 includes three N-type buffer layers, which are the first N-type buffer layer 21, the second N-type buffer layer 22 and the third N-type buffer layer 23 from bottom to top, and the doping concentrations of the first N-type buffer layer 21, the second N-type buffer layer 22 and the third N-type buffer layer 23 decrease in sequence. The thickness of the N-type buffer layer in the gradient buffer 20 may be the same or different. In this embodiment, the thickness of the N-type buffer layer directly in contact with the N-type base region, i.e., the third N-type buffer layer 23, is slightly greater than the thickness of the first N-type buffer layer 21 and the thickness of the second N-type buffer layer 22, so as to achieve better electric field transition and improve the softness of the reverse recovery of the fast recovery diode. During specific implementation, the number and thickness of the N-type buffer layers in the gradient buffer zone 20 can be selected according to actual needs.

[0038] A P-type anode region 2 is arranged above the N-type base region 1, and the P-type anode region 2 is isolated from the floating junction layer 10 in the N-type base region 1 by the N-type base region 1. An anode metal (not shown in the drawings) for forming an anode is prepared above the P-type anode region 2, and the P-type anode region 2 is in ohmic contact with the anode metal to form the anode end of the fast recovery diode. The doping concentration of the P-type anode region 2 is greater than the doping concentration of the P-type floating region 11. An N-type cathode region 3 is arranged below the gradient buffer region 20, and a cathode metal (not shown in the drawings) for forming a cathode is prepared below the N-type cathode region 3, and the N-type cathode region 3 is in ohmic contact with the cathode metal to form the cathode end of the fast recovery diode.

[0039] Furthermore, in order to achieve a gradual transition of the electric field and better improve the reverse recovery softness of the fast recovery diode, the maximum doping concentration of the N-type buffer layer in the gradient buffer zone 20 is less than the doping concentration of the N-type cathode region 3, and the minimum doping concentration of the N-type buffer layer in the gradient buffer zone 20 is greater than the doping concentration of the N-type base region 1.

[0040] In one embodiment of the present invention, the first N-type buffer layer 21 is an N-type buffer layer with a maximum doping concentration in the gradient buffer region 20, and the doping concentration of the first N-type buffer layer 21 is less than the doping concentration of the N-type cathode region 3. The third N-type buffer layer 23 is an N-type buffer layer with a minimum doping concentration in the gradient buffer region 20, and the doping concentration of the third N-type buffer layer 23 is greater than the doping concentration of the N-type base region 1.

[0041] For the above-mentioned fast recovery diode with high withstand voltage and low conduction voltage drop, the present invention also provides a method for preparing the fast recovery diode with high withstand voltage and low conduction voltage drop, the preparation method comprising preparing an N-type base region 1, and a plurality of floating junction layers 10 stacked on each other and arranged in the N-type base region 1, wherein: The floating junction layer 10 includes at least one P-type floating region 11 , and the P-type floating region 11 is used to increase the reverse breakdown voltage of the fast recovery diode.

[0042] Specifically, the preparation method includes providing an N-type substrate 4, preparing a gradient buffer region 20 on the N-type substrate 4 before preparing an N-type base region 1 and a floating junction layer 10, and preparing an N-type base region 1 and a floating junction layer 10 on the gradient buffer region 20; When preparing the N-type base region 1 and the floating junction layer 10, it includes growing several layers of N-type epitaxial layers 5 with the same doping concentration on the gradient buffer region 20. After each layer of N-type epitaxial layer 5 is grown, P-type doping ions are implanted into the corresponding N-type epitaxial layer 5 to prepare the floating junction layer 10. The thickness of each N-type epitaxial layer 5 is in the range of 8μm-13μm. Implanting P-type doping ions into the corresponding N-type epitaxial layer 5 means implanting P-type doping ions into the N-type epitaxial layer 5 formed by the latest epitaxial layer growth.

[0043] Figure 4-Figure 13 An embodiment of the process steps of the present invention is shown in Figure 4-Figure 13 The preparation method of the present invention is specifically described with reference to the process steps.

[0044] like Figures 4 to 5 As shown, an N-type substrate 4 with a resistivity of 0.001 ohm·cm-0.004ohm·cm and a thickness of 525μm-625μm is provided, the N-type substrate 4 includes a front side and a back side corresponding to the front side, and a first N-type buffer layer 21 with a resistivity of 0.1ohm·cm-2 ohm·cm and a thickness of 5μm-10μm is grown on the front side of the N-type substrate 4.

[0045] like Figure 6 As shown, a second N-type buffer layer 22 with a resistivity of 20 ohm·cm-30 ohm·cm and a thickness of 5 μm-10 μm is grown on the surface of the first N-type buffer layer 21 .

[0046] like Figure 7 As shown, a third N-type buffer layer 23 with a resistivity of 30 ohm·cm-50 ohm·cm and a thickness of 10 μm-20 μm is grown on the surface of the second N-type buffer layer 22 , thereby completing the preparation of the gradient buffer region 20 .

[0047] like Figures 8 to 9As shown, an N-type epitaxial layer 5 with a resistivity of 50ohm·cm-65ohm·cm and a thickness of 8μm-13μm is grown on the front side of the N-type substrate 4 on which the third N-type buffer layer 23 is prepared. A photoresist is coated on the N-type epitaxial layer 5, and the injection area of ​​the P-type doped ions is defined by photolithography to form a first mask 6. The first mask 6 is used to inject the impurity Boron, i.e., the P-type doped ions, into the N-type epitaxial layer 5 twice, and the photoresist is removed to prepare a P-type floating region 11 in a floating junction layer 10. Among them, the ion implantation dose range of the P-type doped ions is 6.0 e9cm-2-2.3e10cm-2, and the ion implantation energy range is 80kev-200kev. In specific implementation, the process conditions of ion implantation can be selected according to actual needs. At this time, a layer of N-type epitaxial layer 5 and a layer of floating junction layer 10 are prepared. In this embodiment, a total of three stacked floating junction layers 10 are provided, so the steps are repeated. Figures 8 to 9 The process steps shown are performed three times in total, and three N-type epitaxial layers 5 and corresponding three floating junction layers 10 are prepared. The resistivity of the N-type epitaxial layers 5 formed by the three epitaxial growths is the same, and the preparation of the floating junction layer 10 is completed. After the preparation of the floating junction layer 10 is completed, a top N-type epitaxial layer of a preset thickness is grown above the topmost N-type epitaxial layer 5. The resistivity of the top N-type epitaxial layer is the same as that of the N-type epitaxial layer 5, and an N-type base region 1 is formed together, and the preparation of the N-type base region 1 is completed. The doping concentration of the N-type base region 1 is less than that of the third N-type buffer layer 23. The specific structural form of the floating junction layer 10 is consistent with the above, and will not be repeated here. Figures 8 to 9 The number of repetitions of the process steps shown is determined according to the number of floating junction layers 10 required.

[0048] like Fig.10 As shown, a photoresist is coated on the N-type base region 1 and an ion implantation region is defined by photolithography, P-type doping ions are implanted in the N-type base region 1, and laser annealing is performed to activate impurities after removing the photoresist to prepare a P-type anode region 2. When preparing the P-type anode region 2, the ion implantation dose range of the P-type doping ions is 5.0 e13cm-2-1.0e14cm-2, and the ion implantation energy range is 40kev-100kev. In specific implementation, the process conditions of ion implantation can be selected according to actual needs to meet the preparation requirements of the P-type anode region 2.

[0049] After the P-type anode region 2 is prepared, the heavy metal doping process in the lifetime control technology is used to increase the reverse recovery speed of the fast recovery diode, such as Figure 11-Figure 12As shown, the heavy metal doping process includes depositing metal platinum (Pt) with a thickness of 50Å-120Å above the P-type anode region 2, performing a furnace tube annealing process at 850℃-930℃ to diffuse the heavy metal into the N-type base region 1, and then washing the metal platinum with 50℃-100℃ aqua regia to complete the heavy metal doping. The specific process conditions of the heavy metal doping process and the principle of improving the reverse recovery speed of the fast recovery diode are consistent with the prior art and will not be repeated here. In specific implementation, other commonly used life control technologies can also be used to improve the reverse recovery speed of the fast recovery diode.

[0050] like Fig.13 As shown, the back side of the N-type substrate 4 is thinned to 10 μm-30 μm to prepare the N-type cathode region 3 .

[0051] Metal is deposited on the surface of the P-type anode region 2 to form an anode metal, and the anode metal is in ohmic contact with the P-type anode region 2 to form an anode terminal; metal is deposited below the N-type cathode region 3 to form a cathode metal, and the cathode metal is in ohmic contact with the N-type cathode region 3 to form a cathode terminal.

[0052] In summary, the fast recovery diode provided by the present invention has a lower forward conduction voltage drop, a faster reverse recovery speed, a softer reverse recovery characteristic and a better withstand voltage performance than the traditional fast recovery diode. The preparation method of the fast recovery diode with high withstand voltage and low conduction voltage drop provided by the present invention is compatible with the existing mature process, has simple process steps, is efficient and convenient to prepare, and is suitable for wide promotion and application.

[0053] It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the above description refer to directions in the drawings of the present application specification, and the words "front" and "back", "inner" and "outer" refer to directions toward or away from a specific component, respectively. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0054] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A fast recovery diode with high withstand voltage and low on-state voltage drop, characterized in that: It includes an N-type base region and a plurality of floating junction layers stacked on each other and arranged in the N-type base region, wherein: The floating junction layer includes at least one P-type floating region, and the P-type floating region is used to increase the reverse breakdown voltage of the fast recovery diode.

2. The fast recovery diode with high withstand voltage and low on-state voltage drop according to claim 1, characterized in that: When the floating junction layer includes two or more P-type floating regions, the P-type floating regions are arranged at intervals along a first direction, and the first direction is perpendicular to a thickness direction of the N-type base region.

3. The fast recovery diode with high withstand voltage and low on-state voltage drop according to claim 1, characterized in that: When the N-type base region includes two or more floating junction layers, the P-type floating regions in adjacent floating junction layers are isolated from each other by the N-type base region.

4. The fast recovery diode with high withstand voltage and low on-state voltage drop according to claim 1, characterized in that: The plurality of floating junction layers are disposed above a gradient buffer zone, wherein the gradient buffer zone includes a plurality of N-type buffer layers; The doping concentration of the multiple N-type buffer layers in the gradient buffer area decreases in sequence in a direction from the gradient buffer area to the floating junction layer.

5. The fast recovery diode with high withstand voltage and low on-state voltage drop according to claim 1, characterized in that: A P-type anode region is disposed above the N-type base region; An anode metal for forming an anode is prepared above the P-type anode region, and the P-type anode region is in ohmic contact with the anode metal.

6. The fast recovery diode with high withstand voltage and low on-state voltage drop according to claim 5, characterized in that: The doping concentration of the P-type anode region is greater than the doping concentration of the P-type floating region.

7. The fast recovery diode with high withstand voltage and low on-state voltage drop according to claim 4, characterized in that: An N-type cathode region is arranged below the gradient buffer zone, a cathode metal for forming a cathode is prepared below the N-type cathode region, and the N-type cathode region is in ohmic contact with the cathode metal.

8. The fast recovery diode with high withstand voltage and low on-state voltage drop according to claim 7, characterized in that: The maximum doping concentration of the N-type buffer layer in the gradient buffer zone is less than the doping concentration of the N-type cathode region, and the minimum doping concentration of the N-type buffer layer in the gradient buffer zone is greater than the doping concentration of the N-type base region.

9. A method for preparing a fast recovery diode with high withstand voltage and low on-state voltage drop, characterized in that: For preparing the fast recovery diode according to any one of claims 1 to 8, the preparation method comprises preparing an N-type base region and a plurality of floating junction layers stacked on each other in the N-type base region, wherein: The floating junction layer includes at least one P-type floating region, and the P-type floating region is used to increase the reverse breakdown voltage of the fast recovery diode.

10. The method for preparing a fast recovery diode with high withstand voltage and low on-state voltage drop according to claim 9, characterized in that: The preparation method comprises providing an N-type substrate, preparing a gradient buffer zone on the N-type substrate before preparing an N-type base region and a floating junction layer, and preparing an N-type base region and a floating junction layer on the gradient buffer zone; When preparing the N-type base region and the floating junction layer, it includes growing several layers of N-type epitaxial layers with the same doping concentration on the gradient buffer zone. After each layer of N-type epitaxial layer is grown, P-type doping ions are implanted into the corresponding N-type epitaxial layer to prepare the floating junction layer. The thickness of each N-type epitaxial layer ranges from 8μm to 13μm.

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