Semiconductor device

Abstract

Provided is a semiconductor device in which a snapback phenomenon is suppressed. The semiconductor device includes a first semiconductor element, a second semiconductor element, and a dummy region. The first semiconductor element includes: a second semiconductor region above the first semiconductor region; a third semiconductor region above the second semiconductor region; a first trench penetrating the second semiconductor region; a first in-trench electrode; a fourth semiconductor region below the first semiconductor region; an upper electrode connected to the third semiconductor region; and a lower electrode connected to the fourth semiconductor region, the second semiconductor element having: a fifth semiconductor region above the first semiconductor region and electrically connected to the upper electrode; and a sixth semiconductor region connected to the lower electrode, the dummy region having, between the first semiconductor element and the second semiconductor element, a seventh semiconductor region above the first semiconductor region, a third trench penetrating the seventh semiconductor region, and a third trench inner electrode electrically connected to the first trench electrode in the third trench.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] In the past, a semiconductor device, namely a reverse conducting IGBT (RC-IGBT), was proposed in which an insulated gate bipolar transistor (IGBT) and a diode for reflux are formed on a semiconductor substrate. In the RC-IGBT, there is a snapback phenomenon: when the IGBT is turned on, the electrons in the drift region move to the cathode region of the diode without a collector region, thereby suppressing the injection of holes from the collector layer of the IGBT into the drift region, making it difficult to produce conductivity modulation of the IGBT. In addition, an example of providing a region called a reduced surface electric field (RESURF) region for improving withstand voltage in the peripheral region of the semiconductor device is disclosed.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-154000

[0004] Patent Document 2: Japanese Patent Application Publication No. 2022-56498

[0005] Patent Document 3: Japanese Patent Application Publication No. 2018-46187

[0006] Patent Document 4: Japanese Patent Application Publication No. 2004-349556

[0007] Patent Document 5: Japanese Patent No. 5383009

[0008] Non-patent literature 1: URVemulapati, N.Kaminski, D.Silber, L.Storasta, andM.Rahimo, "Analytical Model for the Initial Snapback Phenomenon in RCIGBTs", ISPS, August 2012, Prague, Czech Republic,

[2012] IEEE. Reprinted from the Internacional Seminar on Power Semiconductors. Summary of the invention

[0009] An object of the embodiments is to provide a semiconductor device in which a snapback phenomenon is suppressed.

[0010] The semiconductor device of the embodiment comprises a first semiconductor element, a second semiconductor element and a dummy region, wherein the first semiconductor element comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, which is arranged above the first semiconductor region; a third semiconductor region of the first conductivity type, which is arranged above the second semiconductor region; a first trench, which is arranged to penetrate the second semiconductor region in a depth direction; a first in-trench electrode, which is arranged in the first trench via a first insulating film; a fourth semiconductor region of the second conductivity type, which is arranged below the first semiconductor region and on the opposite side to the second semiconductor region; an upper electrode, which is electrically connected to the third semiconductor region; and a lower electrode, which is electrically connected to the fourth semiconductor region. The second semiconductor element comprises: a second conductive type; The dummy region comprises: a 5th semiconductor region of the first conductivity type, which is electrically connected to the upper electrode and is arranged above the 1st semiconductor region; a 2nd groove, which is arranged to penetrate the 5th semiconductor region in the depth direction; and an electrode in the 2nd groove, which is arranged in the 2nd groove via a 2nd insulating film; and a 6th semiconductor region of the first conductivity type, which is electrically connected to the lower electrode and is arranged below the 1st semiconductor region and on the opposite side of the 5th semiconductor region. The dummy region comprises: a 7th semiconductor region of the second conductivity type, which is located between the 1st semiconductor element and the 2nd semiconductor element and is arranged above the 1st semiconductor region; a 3rd groove, which is arranged to penetrate the 7th semiconductor region in the depth direction; and an electrode in the 3rd groove, which is located in the 3rd groove via a 3rd insulating film and is electrically connected to the electrode in the 1st groove.

[0011] According to the embodiment of the present invention, it is possible to provide a semiconductor device in which a snapback phenomenon is suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view showing the overall structure of the semiconductor device according to the first embodiment.

[0013] Figure 2 Yes Figure 1 A magnified top view of a portion of the

[0014] Figure 3 It is along Figure 2 Cross-sectional view of line II.

[0015] Figure 4 It is along Figure 2 Cross-sectional view along line II-II.

[0016] Figure 5 It is along Figure 2 Cross-sectional view along line III-III.

[0017] Figure 6 It is along Figure 2 A cross-sectional view taken along line IV-IV.

[0018] Figure 7 It is along Figure 1 A cross-sectional view of line VV.

[0019] Fig. 8A The figure is a simulation result of the electromagnetic field distribution in the middle stage of the snapback operation in the dummy portion of the semiconductor device according to the first embodiment.

[0020] Figure 8B This is a simulation result of the electromagnetic field distribution in the dummy portion in the semiconductor device according to the first embodiment at the late stage of the snapback operation.

[0021] Fig. 9A It is a simulation result of the electromagnetic field distribution in the middle stage of the snapback operation in the dummy portion of the semiconductor device of the comparative example.

[0022] Fig. 9B This is a simulation result of the electromagnetic field distribution in the dummy portion of the semiconductor device of the comparative example at the late stage of the snapback operation.

[0023] Fig.10 It is a cross-sectional view of a semiconductor device according to a modification of the first embodiment.

[0024] Fig.11 It is a plan view of a part of the IGBT of the semiconductor device according to the first embodiment.

[0025] Fig.12 It is a plan view showing the overall structure of the semiconductor device according to the second embodiment.

[0026] Fig.13 Yes Fig.12 A magnified top view of a portion of the

[0027] Description of symbols

[0028] 1: lower electrode (collector electrode, cathode electrode); 2: collector region; 3: cathode region; 4: buffer region; 5: drift region; 6: storage region; 7, 7D: base region; 8: emitter region; 9A: anode contact region; 9D: dummy contact region; 9E: emitter contact region; 10: first semiconductor element (IGBT part); 11: upper electrode (emitter electrode); 12: anode region; 13: interlayer insulating layer; 14: first trench; 14a, 15a, 16a: trench electrodes; 14b, 15b, 16b: insulating film; 15: third trench (dummy trench); 15C1, 16C2: connection trench; 15EG: first end; 15FG: location; 16: second groove; 16EG: second end; 16FG: location; 17EG: third end; 20: second semiconductor element (diode part); 30: boundary region (dummy part); 33: N-type semiconductor region; 40: terminal region; 51, 52, 53, 54: pads; 70: eighth semiconductor region; 100, 102, 103, 104, 105: semiconductor device; 101: semiconductor substrate; 120: unit electrode; 130: termination electrode; 210: unit semiconductor region; 220, 230: surface electric field reduction region; 240, 250: floating confinement ring diffusion layer; 260: termination layer; 500: control pad part. DETAILED DESCRIPTION

[0029] Next, the embodiments of the present invention are described with reference to the accompanying drawings. In the following description of the accompanying drawings, the same or similar parts are marked with the same or similar reference numerals. However, it should be noted that the accompanying drawings are schematic, and the relationship between the thickness and the plane size, the ratio of the length of each part, etc. are different from the actual. Therefore, the specific dimensions should be determined by referring to the following description. In addition, of course, the drawings also contain parts with different size relationships or ratios.

[0030] In addition, the embodiments shown below illustrate devices for concretizing the technical concept of the present invention, and the technical concept of the present invention does not limit the shape, structure, configuration, etc. of the structural components to the following contents. The embodiments of the present invention can be modified in various ways in the claims. In addition, in the present invention, the terms "upper" and "lower" to determine upper and lower are used for the convenience of recording. Even if they are set on the side, as long as they are substantially the same as the structural elements of the present invention, they also belong to the scope of rights of the present invention. In addition, "upper" not only includes the case where it is formed in a manner of contacting with an object, but also includes the case where it is formed through other layers. In addition, in the present invention, "connection" is not limited to direct connection. Even if it is connected by interposing a resistor or the like, as long as the structural elements of the present invention are substantially the same, it belongs to the scope of rights of the present invention.

[0031] In the following description, the direction of the semiconductor device is defined by the XYZ axis. In the cross-sectional view, the left-right direction is set as the X-axis direction, the direction perpendicular to the paper is set as the Y-axis direction, and the direction perpendicular to the XY plane is set as the Z-axis direction. In addition, these directions are an example. Depending on the configuration of the pattern, it can be appropriately changed. In addition, in the following description, as a semiconductor device, IGBT is recorded as the center, but as long as it is a semiconductor device in which a diode for reflux is formed on a semiconductor substrate, it can also be a MOSFET instead of IGBT. In addition, it can also be an element of other insulating gate structures such as an electron injection enhanced insulated gate transistor (IEGT: Injection Enhanced Gate Transistor). In addition, it can also be a super junction MOSFET (Super Junction MOSFET) and a complementary metal oxide semiconductor field effect transistor (CMOSFET: Complementary Metal Oxide Semiconductor Field Effect Transistor).

[0032] (First embodiment)

[0033] Figure 1 It is a plan view showing the overall structure of the semiconductor device 100 according to the first embodiment.

[0034] like Figure 1 As shown, the semiconductor device 100 of the first embodiment includes: a semiconductor substrate 101; a diode portion 20, which is arranged on the semiconductor substrate 101; and an IGBT portion 10, which is arranged around the diode portion 20 on the semiconductor substrate 101. In the semiconductor device 100 of the first embodiment, the diode portion 20 is arranged in an island shape, and a dummy portion 30 is provided around the diode portion 20, and the IGBT portion 10 is arranged outside the dummy portion 30. That is, the IGBT portion 10, the dummy portion 30, the diode portion 20, the dummy portion 30, the IGBT portion 10, the dummy portion 30, the diode portion 20, ... are repeatedly arranged in the long side direction of the trench 14 of the IGBT portion 10.

[0035] The semiconductor device 100 of the first embodiment constitutes a reverse conducting IGBT (RC-IGBT) in which an IGBT unit 10 and a diode unit 20 for reflux are formed on a semiconductor substrate 101. A region for improving withstand voltage, which is called a reduced surface electric field region, is provided in a terminal region 40 at the periphery of the semiconductor device 100. The IGBT unit 10 is arranged around the diode unit 20 arranged in an island shape on the semiconductor substrate 101. A boundary region 30 is provided around the diode unit 20. The boundary region 30 is also called a dummy region. In addition, Figure 1In the example shown in FIG. 1 , a control pad portion 500 is further provided on the semiconductor substrate 101. Figure 1 Although not shown in the drawings, an emitter pad 51 is provided on the IGBT unit 10 and / or the diode unit 20 .

[0036] The control pad unit 500 includes, for example, a current sensing pad 50, a gate pad 52, and temperature sensing pads 53 and 54. The current sensing pad 50 is a control pad for detecting a current flowing in a cell region of the semiconductor device 100.

[0037] The gate pad 52 is a control pad to which a gate driving voltage is applied for on-off control of the semiconductor device 100. The temperature sensing pads 53 and 54 are control pads electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100, for example.

[0038] Figure 2 Yes Figure 1 FIG. 1 is an enlarged top view of a portion of the semiconductor device 102. Figure 2 , a diode unit 20, a boundary region (dummy unit) 30 surrounding the diode unit 20, and an IGBT unit 10 surrounding the boundary region 30 are shown. The inside of the dotted line FLR indicates a region where an eighth semiconductor region (FLR region) described later is provided (with or without a boundary line of the eighth semiconductor region). The dotted line DMY1 indicates a boundary line between the diode unit 20 and the boundary region 30. In addition, the dotted line DMY2 indicates a boundary line between the IGBT unit 10 and the boundary region 30.

[0039] In the IGBT unit 10 , a plurality of trenches 14 extend in a first direction (longitudinal direction, Y direction) and are arranged in parallel in a second direction (shortitudinal direction, X direction). Some trenches 14 are connected to trenches 15 in the boundary region 30 in the Y direction.

[0040] A connection trench 16C2 extending in a second direction perpendicular to the Y direction is provided at the end of the trench 16 of the diode portion 20 in the Y direction. The plurality of trenches 16 extend in the Y direction, are arranged in parallel in the second direction (short side direction, X direction), and terminate in a T-shaped structure in the connection trench 16C2.

[0041] In the portion of the boundary region 30 between the diode portion 20 and the IGBT portion 10 viewed from the diode portion 20 in the Y direction, the trench 15 is provided with an end portion separated from the trench 16 of the diode portion 20 and the connection trench 16C2 located on the extension line in the Y direction. A connection trench 15C1 extending in the X direction is provided at the end portion in the Y direction of the trench 15 in the boundary region 30. In the boundary region 30, the plurality of trenches 15 extend in the Y direction and terminate in a T-shaped structure in the connection trench 15C1.

[0042] The first end 15EG in the Y direction extending from the groove 15 is connected to the first end 15EG in the Y direction extending from the adjacent groove 15 via the connecting groove 15C1.

[0043] The second end 16EG in the Y direction extending from the groove 16 is connected to the second end 16EG in the Y direction extending from the adjacent groove 16 via the connecting groove 16C2.

[0044] A distance Y1 between a first end 15EG in the Y direction extending from the groove 15 and a second end 16EG in the Y direction extending from the groove 16 is equal to or smaller than a distance X1 between adjacent grooves 15 in the X direction of the boundary region 30. That is, Y1≤X1 holds.

[0045] In addition, if Figure 2 As shown, in the portion of the boundary region 30 between the diode portion 20 and the IGBT portion 10 viewed from the diode portion 20 along the X direction, the plurality of trenches 15 extend in the Y direction and are arranged in parallel in the second direction (short side direction, X direction). Furthermore, the plurality of trenches 15 in the boundary region 30 are connected to the plurality of trenches 14 of the IGBT portion 10 existing in the Y direction from the diode portion 20 at the third end 17EG, respectively, and the trenches 15 are continuous with the trenches 14.

[0046] An eighth semiconductor region 70 of the second conductivity type is provided between a point 15FG in the first direction where the third trench 15 extends and a point 16FG in the first direction where the second trench 16 extends. Figure 4 ).

[0047] Regarding the distance from the P-type 8th semiconductor region 70 with a low impurity concentration in the boundary region 30 to the emitter region 8 of the IGBT portion 10, the distance WL in the long side direction (Y direction) of the groove 15 is formed to be longer than the distance WS in the short side direction (X direction) of the groove 15. That is, WL>WS holds. When viewed from the diode portion 20, the emitter region 8 in the X direction (WS) has a plurality of grooves 15 between the diode portion 20, and the grooves 15 can hinder the diffusion of electrons from the emitter region to the diode portion 20 side, and can make the distance WS shorter than the distance WL.

[0048] In the IGBT part 10, the P base region 7 sandwiched by the trenches 14 in the X direction has a hole, and the hole extends in the Y direction. A P-type emitter contact region 9E is formed below the bottom of the hole and in the Z direction of the P base region 7. The n emitter region 8 is formed at the opening of the trench 14, and the n emitter region 8 is exposed on the side of the hole. Figure 2As shown, the n emitter regions 8 are adjacent to the trench 14 and are discretely arranged in the Y direction. The n emitter regions 8 are arranged at regular intervals in the Y direction, but they do not necessarily need to be arranged regularly in the Y direction. The n emitter regions 8 may also be arranged intermittently. In this way, the IGBT portion 10 may also include a region where the n emitter regions 8 are arranged and a region where the n emitter regions 8 are not arranged. By intermittently arranging the n emitter regions 8 in the IGBT portion 10, it is possible to suppress excessive electron injection and shorten the switching time.

[0049] Figure 3 It is along Figure 2 A cross-sectional view of line II. Figure 3 , a cross-sectional structure along the XZ plane spanning the diode unit 20, the boundary region 30, and the IGBT unit 10 is shown. Figure 3 In FIG. 1 , a dotted line DMY1 extending in the Z direction indicates a boundary line between the diode portion 20 and the boundary region 30. In addition, a dotted line DMY2 extending in the Z direction indicates a boundary line between the IGBT portion 10 and the boundary region 30. Figure 2 In FIG. 1 , a portion of the groove 14 along the II line is omitted, but in FIG. Figure 3 5 are shown.

[0050] The semiconductor device 100 according to the first embodiment includes a first semiconductor element 10 , a second semiconductor element 20 , and a dummy region 30 .

[0051] The first semiconductor element 10 comprises: a first semiconductor region 5 of a first conductivity type; a second semiconductor region 7 of a second conductivity type, which is arranged above the first semiconductor region 5; a third semiconductor region 8 of the first conductivity type, which is arranged above the second semiconductor region 7; a first trench 14, which is arranged to penetrate the second semiconductor region 7 in the depth direction; a first intra-trench electrode 14a, which is arranged in the first trench 14 via a first insulating film 14b; a fourth semiconductor region 2 of the second conductivity type, which is arranged below the first semiconductor region 5 and on the opposite side to the second semiconductor region 7; an upper electrode 11, which is electrically connected to the third semiconductor region 8; and a lower electrode 1, which is electrically connected to the fourth semiconductor region 2.

[0052] The second semiconductor element 20 comprises: a fifth semiconductor region 12 of the second conductivity type, which is electrically connected to the upper electrode 11 and is arranged above the first semiconductor region 5; and a sixth semiconductor region 3 of the first conductivity type, which is electrically connected to the lower electrode 1 and is arranged below the first semiconductor region 5 and on the opposite side to the fifth semiconductor region 12.

[0053] The dummy region 30 comprises: a seventh semiconductor region (P dummy region) 7D of the second conductivity type, which is located between the first semiconductor element 10 and the second semiconductor element 20 and is arranged above the first semiconductor region 5; a third trench 15, which is arranged to penetrate the seventh semiconductor region 7D in the depth direction; and a third trench electrode 15a, which is located in the third trench 15 via a third insulating film 15b and is electrically connected to the first trench electrode 14a.

[0054] like Figure 3 As shown, the semiconductor substrate 101 has: for example, an N-type high-resistance drift region 5; an N-type accumulation region 6, which is formed on the drift region 5 in the Z direction and has a higher impurity concentration than the drift region 5; P-type base regions 7, 7D and an anode region 12, which are formed on the accumulation region 6 in the Z direction; an N-type buffer region 4, which is formed below the drift region 5 (negative Z direction); and a P-type collector region 2 and an N-type cathode region 3, which are formed below the buffer region 4 (negative Z direction).

[0055] The diode portion 20 has: an N-type high-resistance drift region 5; an N-type storage region 6, which is configured on the drift region 5; a P-type anode region 12, which is set on the storage region 6; and a groove 16, which is set to penetrate the anode region 12 in the depth direction (Z direction).

[0056] In the diode part 20, the anode region 12 is sandwiched by the groove 16 extending in the Y direction and extends in the Y direction. In addition, a hole is formed in the Z direction of the anode region 12, and a P-type anode contact region 9A is provided at the bottom thereof. An emitter electrode (upper electrode) 11 is provided inside the hole, and the anode contact region 9A is connected to the emitter electrode (upper electrode) 11. The groove 16 has an in-groove electrode 16a and an insulating film 16b. The in-groove electrode 16a is connected to the emitter electrode (upper electrode) 11. In addition, the groove 16 penetrates the anode region 12, but does not penetrate the storage region 6.

[0057] In the boundary region 30, an N-type accumulation region 6 is arranged on the drift region 5, and the base region 7D is sandwiched by the groove 15 extending in the Y direction and extends in the Y direction. In addition, a P-type dummy contact region 9D is arranged in the Z direction of the base region 7D. The dummy contact region 9D connected to the base region 7D is connected to the emitter electrode (upper electrode) 11. The groove 15 has an in-groove electrode 15a and an insulating film 15b. The in-groove electrode 15a is electrically connected to the in-groove electrode 14a of the IGBT part 10. In the Z direction of the base region 7D of the boundary region 30, unlike the IGBT part 10, an emitter region 8 is provided that is not connected to the groove 15. The groove 15 penetrates the base region 7D, but does not penetrate the accumulation region 6. The base region 7D can be formed simultaneously with the base region 7 and the anode region 12 with the same P-type doping material and impurity density.

[0058] The IGBT portion 10 includes an N-type drift region 5, an N-type accumulation region 6 disposed on the drift region 5, a P-type base region 7 disposed on the accumulation region 6, and a trench 14 disposed so as to penetrate the base region 7 in the depth direction (Z direction). Here, the trench 14 does not penetrate the accumulation region 6.

[0059] In the IGBT portion 10, the base region 7 is sandwiched by the grooves 14 extending in the Y direction and extends in the Y direction. In addition, in the Z direction of the base region 7, the emitter region 8 is provided in contact with the groove 14. In addition, a hole is engraved in the Z direction of the base region 7, and a P-type emitter contact region 9E is arranged at the bottom. The emitter contact region 9E extends in the Y direction on the base region 7 sandwiched by the grooves 14. The emitter region 8 and the emitter contact region 9E are connected to the emitter electrode (upper electrode) 11. The groove 14 has an intra-trench electrode 14a and an insulating film 14b. The intra-trench electrode 14a and Figure 2 The gate pad 52 is electrically connected.

[0060] The base region 7 sandwiched by the trenches 14 in the X direction is formed with an N-type emitter region 8 and a P-type emitter contact region 9E. Fig.11 , which will be described later.

[0061] The lower electrode 1 provided in the negative Z direction of the semiconductor substrate 101 becomes a collector electrode connected to the P-type collector region 2 in the IGBT portion 10, and becomes a cathode electrode connected to the N-type cathode region 3 in the diode portion 20. Figure 3In the example of , the boundary line BL between the collector region 2 and the cathode region 3 is set on the boundary line between the diode portion 20 and the boundary region 30. The boundary line between the diode portion 20 and the boundary region 30 is indicated by a dotted line DMY1. In addition, as indicated by a dotted line BLC1, the boundary line BL between the collector region 2 and the cathode region 3 may also be set in the boundary region 30. In addition, as indicated by a dotted line BLC2, the boundary line BL between the collector region 2 and the cathode region 3 may also be set in the IGBT portion 10. In addition, as indicated by a dotted line BLA, the boundary line BL between the collector region 2 and the cathode region 3 may also be set in the diode portion 20. In this way, the relative area between the P-type collector region 2 and the N-type cathode region 3 changes according to the position of the boundary line BL between the collector region 2 and the cathode region 3. Therefore, the amount of carrier injection changes, and therefore, the switching characteristics of the semiconductor device 100 as an RC-IGBT can be appropriately changed according to the application.

[0062] Figure 4 is along Figure 1 The cross-sectional view of the II-II line. Figure 4 , a cross-sectional structure along the YZ plane is shown, which spans the diode portion 20, the boundary region (dummy portion) 30, and the region where the emitter electrode 11 of the IGBT portion 10 is connected to the P-type emitter contact region 9E. Figure 4 In FIG. 1 , a dotted line DMY1 extending in the Z direction indicates a boundary line between the diode unit 20 and the boundary region 30 . In addition, a dotted line DMY2 extending in the Z direction indicates a boundary line between the IGBT unit 10 and the boundary region 30 . Figure 4 In FIG. 1 , a dotted line FLR extending in the Z direction indicates the presence or absence of a boundary of the eighth semiconductor region 70 .

[0063] The eighth semiconductor region 70 has a bottom shallower than the bottom of the second trench 16 and deeper than the bottom of the seventh semiconductor region (P dummy region) 7D, and is provided between a point 15FG in the first direction where the second trench 16 extends and a point 16FG in the first direction where the second trench 16 extends.

[0064] That is, the eighth semiconductor region 70 is formed not only directly below the base region 7D of the boundary region 30 sandwiched between the connection groove 15C1 and the connection groove 16C2, but also extends a portion directly below the base region 7D of the boundary region 30 closer to the negative Y direction than the side wall of the connection groove 15C1, and also extends a portion directly below the anode region 12 of the diode portion 20 closer to the Y direction than the side wall of the connection groove 16C2. In addition, the dotted line DL schematically shows the depletion layer in a thermal equilibrium state extending within the N-type semiconductor region 6. The connection groove 15C1 of the boundary region 30 has an intra-trench electrode 15a and an insulating film 15b. The connection groove 16C2 of the diode portion 20 has an intra-trench electrode 16a and an insulating film 16b. As shown Figure 4 As shown, it can be seen that the provision of the eighth semiconductor region 70 reduces the penetration of the depletion layer in the Z direction into the region sandwiched between the connection trench 15C1 and the connection trench 16C2.

[0065] Furthermore, an anode contact region 9A is formed in the base region 7D between the connection trench 15C1 and the connection trench 16C2 , and the anode contact region 9A is electrically connected to the emitter electrode 11 .

[0066] Figure 5 It is along Figure 1 The cross-sectional view of the III-III line. Figure 5 , a cross-sectional structure spanning the diode portion 20, the dummy portion 30, and the IGBT portion 10 is shown. That is, a cross-sectional structure along the YZ plane of the trench 14 and the trench 16 is shown. Figure 5 In FIG. 1 , a dotted line DMY1 extending in the Z direction indicates a boundary line between the diode unit 20 and the boundary region 30 . In addition, a dotted line DMY2 extending in the Z direction indicates a boundary line between the IGBT unit 10 and the boundary region 30 . Figure 5 In FIG. 1 , a dotted line FLR extending in the Z direction indicates the boundary of the eighth semiconductor region 70. In addition, a dotted line DL schematically shows a depletion layer in a thermal equilibrium state extending in the N-type semiconductor region 6.

[0067] like Figure 5 As shown, an eighth semiconductor region 70 of the second conductivity type having a junction depth deeper than the junction depth of the P anode region 12 of the diode portion 20 is provided between the first end 15EG in the Y direction of the trench 15 extending in the boundary region 30 and the second end 16EG in the Y direction of the trench 16 extending in the diode portion 20. The first end 15EG in the Y direction of the trench 15 extending in the boundary region 30 is arranged at the connection trench 15C1, and the second end 16EG in the Y direction of the trench 16 extending in the diode portion 20 is arranged at the connection trench 16C2. Figure 5 As shown, it can be seen that the eighth semiconductor region 70 is provided to reduce the depletion layer from entering the region between the long sides of the trench 15 and the long sides of the trench 16 where no trench is formed in the Z direction.

[0068] Figure 6 It is along Figure 1 A cross-sectional view of the IV-IV line. Figure 6 , a cross-sectional structure spanning the diode portion 20, the boundary region 30, and the IGBT portion 10 is shown. That is, a cross-sectional structure along the YZ plane along the anode region 12, the eighth semiconductor region 70, and the P base regions 7 and 7D is shown. In addition, the dotted line DL schematically shows the depletion layer in a thermal equilibrium state where the depletion layer extends in the N-type semiconductor region 6. Figure 6As shown, it can be seen that by providing the eighth semiconductor region 70, the entry of the depletion layer in the Z direction into the region (7D, 12) sandwiched between the connection trench 15C1 and the connection trench 16C2 is reduced.

[0069] The impurity concentration NP(70) of the eighth semiconductor region 70 is lower than the impurity concentration NP(7) of the base region 7. That is, NP(70) < NP(7) holds. Further, the impurity concentration NP(70) of the eighth semiconductor region 70 is lower than the impurity concentration NP(12) of the anode region 12. That is, NP(70) < NP(12) holds.

[0070] Further, as Figure 6 shown, the junction depth Z4 of the eighth semiconductor region 70 is deeper than the junction depth Z3 of the anode region 12.

[0071] Further, the junction depth Z4 of the eighth semiconductor region 70 is shallower than the depth ZT1 of the trench 15 of the dummy region 30. Further, as Figure 5 shown, the depth of the trench 14 of the IGBT section 10 is equal to the depth ZT1 of the trench 15 of the dummy region 30. Therefore, the junction depth Z4 of the eighth semiconductor region 70 is shallower than the depth of the trench 14 of the IGBT section 10.

[0072] Further, the junction depth Z4 of the eighth semiconductor region 70 is shallower than the depth ZT2 of the trench 16 of the diode section 20.

[0073] In the semiconductor device 100 of the first embodiment, the diode section 20 is formed in an island shape, and the IGBT section 10 is formed surrounding the diode section 20. In addition, the portion of the dummy section 30 extending from the IGBT section 10 and having the trench 15 is continuous from the trench 14. Therefore, in the following description, it may sometimes be described as the trench 14 of the IGBT section (including the dummy section) 10. The emitter region 8 is not provided in the trench 15 of the dummy section 30, but the emitter region 8 is provided in the trench 14 of the IGBT section 10.

[0074] The length direction of the trench 14 of the IGBT section (including the dummy section) 10 in which the trench inner electrode 14a is buried inside sandwiching the insulating film 14b is formed in the same Y direction as the length direction of the trench 16 of the diode section 20 in which the trench inner electrode 16a having the same potential as the emitter electrode 11 is buried sandwiching the insulating film 16b, but the two trenches are separated from each other. Preferably, the trench 16 of the diode section 20 is arranged on the extension line of the long side direction of the trench 14 of the IGBT section (including the dummy section) 10. Thereby, when observing from above, the electric field concentration in the boundary region 30 can be alleviated, and the expansion of the depletion layer can be made gentle.

[0075] In addition, the distance Y1 between the first end 15EG in the long side direction of the groove 15 on the extension line of the groove 14 of the IGBT part 10 and the second end 16EG in the long side direction of the groove 16 of the diode part 20 is preferably equal to or less than the distance between adjacent grooves in the short side direction (X direction) of the groove 15 on the extension line of the groove 14 of the same IGBT part 10 (the groove spacing of the dummy part 30) X1.

[0076] A P-type semiconductor region (FLR region: eighth semiconductor region 70) having an impurity concentration lower than that of the P base region 7 of the IGBT portion 10 is formed above the N-type drift region 5 in the boundary region 30 extending from the first end 15EG in the long side direction of the trench 15 on the extension line of the trench 14 of the IGBT portion 10 to the second end 16EG in the long side direction of the trench 16 of the diode portion 20.

[0077] Thus, the following situation is reduced: in the accumulation region 6 below the base region 7D from the first end 15EG in the long-side direction of the trench 15 to the second end 16EG in the long-side direction of the trench 16, the depletion layer enters in the Z direction. In addition, the depletion layer of the semiconductor region including the eighth semiconductor region 70 in the boundary region 30 between the first end 15EG in the long-side direction of the trench 15 on the extension line of the trench 14 of the IGBT part (including the dummy part) 10 and the second end 16EG in the long-side direction of the trench 16 of the diode part 20 can be more easily extended.

[0078] In addition, the junction depth of the P-type eighth semiconductor region 70 having a low impurity concentration in the boundary region 30 is preferably deeper than the junction depth of the base region 7 of the IGBT portion 10, and deeper than the junction depth of the anode region 12 of the diode portion 20. However, the junction depth of the eighth semiconductor region 70 may be as deep as the bottom (trench depth) of the trenches of the IGBT portion 10 and the diode portion 20. This is to shift the breakdown point from the boundary region 30 to the IGBT portion 10 side.

[0079] The eighth P-type semiconductor region 70 having a low impurity concentration in the boundary region 30 is formed to a position closer to the inside of the first end 15EG of the trench 15 (closer to the IGBT portion 10 side than the first end 15EG of the trench 15, i.e., in the negative Y direction) in such a manner as to include the first end 15EG of the trench 15 of the dummy portion 30. Similarly, the eighth semiconductor region 70 is formed to a position closer to the inside of the diode portion 20 (in the Y direction) than the second end 16EG of the trench 16 of the diode portion 20.

[0080] The first end 15EG of the groove 15 is connected to the first end 15EG of the adjacent groove 15 through the connecting groove 15C1. That is, the first end 15EG of the groove 15 is in a T shape. Moreover, the adjacent groove electrodes 15a in the dummy portion 30 are connected via the groove electrodes 15a in the groove 15 and the groove electrodes 15a in the connecting groove 15C1. As a result, the gate bus line can be formed on the semiconductor substrate 101 in the boundary region 30 without being blocked by the gate bus line when the upper electrode 11 on the semiconductor substrate 101 is continuously formed from the IGBT portion 10 to the diode portion 20. In addition, the groove electrodes 15a and the groove electrodes 16a extend in the X direction, thereby making it possible to make the electric field distribution in the X direction of the region sandwiched by the connecting groove 15C1 and the connecting groove 16C2 more uniform.

[0081] like Figure 2 As shown, when observed from the dotted line FLR (the 8th semiconductor region 70), in the short side direction (X direction) of the groove 14 of the IGBT portion 10, a dummy trench 15 is arranged in parallel with the groove 14 of the IGBT portion 10 between the P-type 8th semiconductor region 70 with a lower impurity concentration in the boundary region 30 and the emitter region 8 in such a manner that the 8th semiconductor region 70 with a lower impurity concentration in the boundary region 30 is not connected to (does not reach) the emitter region 8, and the emitter region 8 is not formed in the dummy trench 15.

[0082] like Figure 6 As shown in the figure, the boundary BL between the P collector region 2 and the N cathode region 3 is formed directly below the boundary region 30 in the Z direction, but the boundary BL between the P collector region 2 and the N cathode region 3 may not be formed directly below the boundary region 30, and may be formed in a staggered manner. For example, the boundary BL between the P collector region 2 and the N cathode region 3 may be located closer to the diode portion 20 than directly below the boundary region 30. Alternatively, it may be located on the IGBT portion 10 side.

[0083] The P-type eighth semiconductor region 70 having a low impurity concentration in the boundary region 30 is connected to the upper electrode (emitter electrode) 11 .

[0084] (Reduced surface electric field structure)

[0085] Figure 7 It is along Figure 1 A cross-sectional view of line VV.

[0086] The semiconductor device 100 of the first embodiment has a first resurf region 220 and a second resurf region 230 in the terminal region 40. In order to improve the withstand voltage, the first resurf region 220 is connected to the P base region 7. The second resurf region 230 is connected to the first resurf region 220 via a depletion layer. The dotted line BLL extending in the Z direction represents the boundary line between the IGBT portion 10 and the terminal region 40. The lower electrode 1 is connected to the P-type collector region 2 of the IGBT portion 10. In addition, the lower electrode 1 is connected to the N-type semiconductor region 33 of the terminal region 40. The N-type semiconductor region 33 and the cathode region 3 of the diode portion 20 are at the same potential. In addition, the N-type semiconductor region 33 and the N-type stopper layer 260 of the terminal portion are at the same potential. The boundary between the P-type collector region 2 and the N-type semiconductor region 33 of the IGBT portion 10 is represented by BL3.

[0087] The semiconductor substrate 101 has an N-type drift region 5 constituting one surface thereof. A plurality of resurf regions 220 and 230 are formed of a P-type semiconductor region having a lower impurity concentration than the P-base region 7, and are formed in the surface region of the drift region 5 so as to surround the IGBT portion 10. The resurf regions 220 and 230 are formed simultaneously with the P-type eighth semiconductor region 70 having a lower impurity concentration in the boundary region 30, and therefore, the junction depth is formed to be shallower than the trench 14 and deeper than the P-base region 7.

[0088] Floating limiting ring diffusion layers 240 and 250 are arranged on the outer periphery of the second resurf region 230. In addition, an N-type stopper layer 260 is arranged at the terminal portion. The stopper layer 260 is connected to a stopper electrode 130.

[0089] The floating limiting ring diffusion layers 240 and 250 are provided to smooth the shape of the depletion layer and to relieve the electric field concentration. The floating limiting ring diffusion layers 240 and 250 are formed of a P-type diffusion layer that is equal to or shallower than the RESURF regions 220 and 230. In addition, the impurity concentration of the floating limiting ring diffusion layers 240 and 250 is set equal to or higher than the impurity concentration of the RESURF regions 220 and 230.

[0090] The eighth P-type semiconductor region 70 having a low impurity concentration in the boundary region 30 can be formed simultaneously with the first resurf region 220 and the second resurf region 230. Therefore, even if the eighth P-type semiconductor region 70 having a low impurity concentration in the boundary region 30 is additionally formed, the increase in man-hours caused thereby can be suppressed.

[0091] The semiconductor device 100 according to the first embodiment includes the RESURF regions 220 and 230 , and thus can easily achieve a high breakdown voltage.

[0092] like Figure 2 As shown in FIG. 1 , the IGBT portion 10 includes a portion where the emitter region 8 is formed and a portion where the emitter region 8 is not formed. The portion where the emitter region 8 is formed and the portion where the emitter region 8 is not formed are formed alternately and repeatedly. The portion where the emitter region 8 is formed and the portion where the emitter region 8 is not formed do not necessarily need to be arranged in a regular pattern. Figure 3 to Figure 6 As shown, the diode unit 20 includes a portion where the N cathode region 3 electrically connected to the lower electrode 1 is provided. The dummy region 30 is arranged between the IGBT unit 10 and the diode unit 20 and includes a portion where the emitter region 8 is not formed on the upper surface side and the P collector region 2 is formed on the lower surface side.

[0093] Grooves 14, 16, and 15 are formed in the IGBT section 10, the diode section 20, and the dummy section 30, respectively, and trench electrodes 14a, 16a, and 15a are provided in the grooves, respectively. The trench electrode 14a of the IGBT section 10 and the trench electrode 15a of the dummy section 30 are electrically connected to the gate pad to form a gate potential, and the trench electrode 15a in the trench 16 of the diode section 20 is electrically connected to the upper electrode 11. Here, in the structure of the semiconductor device 100 of the first embodiment, the gate signal of the dummy section 30 becomes a high level (IGBT is turned on). Therefore, since the trench electrode 15a in the dummy section 30 has a positive charge, the electrons existing in the N drift region 5 around the trench electrode 15a are reduced from moving to the cathode region 3. As a result, compared with the comparative example (hereinafter referred to as the comparative example) in which the trench electrode 15a of the dummy portion 30 is electrically connected to the upper electrode 11, more holes exist in the N drift region 5 of the dummy portion 30, and in the semiconductor device 100, more holes exist in the N drift region 5. As a result, the snapback phenomenon can be further reduced.

[0094] According to the semiconductor device 100 of the first embodiment, the in-trench electrode 15a of the trench 15 in the dummy region 30 is made to have the same potential as the in-trench electrode 14a of the trench 14 in the IGBT portion 10, thereby suppressing the snapback phenomenon. Similarly, since the in-trench electrode 15a connected to the in-trench electrode 14a of the IGBT portion 10 is also provided in the connection trench 15C1 in the dummy region 30, the electrons existing in the N drift region 5 around the connection trench 15C1 are reduced from moving to the cathode region 3. As a result, compared with the case of the comparative example, more holes exist in the N drift region 5 around the connection trench 15C1 of the dummy portion 30, and the snapback phenomenon can be further reduced.

[0095] (Results of equipment simulation for snap-back action)

[0096] Fig. 8A 1 is a simulation result of the electromagnetic field distribution in the dummy portion 30 in the semiconductor device 100 according to the first embodiment in the middle stage of the snapback operation. Figure 8B 1 is a simulation result of the electromagnetic field distribution in the dummy portion 30 in the semiconductor device 100 according to the first embodiment at the late stage of the snapback operation.

[0097] on the other hand, Fig. 9A This is a simulation result of the electromagnetic field distribution in the dummy portion 30 in the semiconductor device of the above-mentioned comparative example in the middle stage of the snapback operation. Fig. 9B 1 and 2 are simulation results of the electromagnetic field distribution in the dummy portion 30 in the semiconductor device of the comparative example at the late stage of the snapback operation.

[0098] exist Fig. 8A , Figure 8B , Fig. 9A and Fig. 9B In FIG. 1 , a portion indicated by G indicates a portion having the same potential as the in-trench electrode 14 a of the trench 14 in the IGBT portion 10 . Also, a portion indicated by E indicates a portion having the same potential as the emitter electrode 11 .

[0099] In the structure of the semiconductor device 100 of the first embodiment, Fig. 8A , Figure 8B As shown, it can be seen that holes diffuse and exist around the groove 15 in the dummy region 30, promoting conductivity modulation. This promotes the start of the IGBT mode and brings about the effect of suppressing the snapback phenomenon. In addition, the expansion of holes is due to the fact that the potential of the groove electrode 15a of the dummy part 30 is applied to be positive when the IGBT is turned on. Electrons are attracted by the potential of the groove electrode 15a, thereby reducing the potential under the dummy region 30 and promoting the injection of holes from the collector region. As a result, holes exist around the groove 15 in the dummy region 30.

[0100] In the structure of the comparative example, it can be seen that there are no holes around the groove 15 in the dummy region 30, and the conductivity modulation is reduced. This situation leads to a significant snapback phenomenon. In the structure of the comparative example, since the trench electrode 15a in the dummy region 30 is equal to the emitter potential, the electrons in the drift region 5 are more likely to move to the cathode region 3. Therefore, in the structure of the comparative example, the potential in the drift region 5 of the dummy region 30 is not reduced, and the injection of holes from the collector region 2 is also reduced compared to the first embodiment.

[0101] (Variation Example)

[0102] Fig.10 The semiconductor device 103 of the modification example of the first embodiment is Figure 3 Corresponding cross-sectional view. In the semiconductor device 103 of the modified example of the first embodiment, the P base region 7D of the boundary region 30 and the upper electrode (emitter electrode) 11 may be connected via a resistor R. In addition, the P base region 7 of the IGBT portion 10 close to the boundary region 30 and the upper electrode (emitter electrode) 11 may be connected via a resistor R. In addition, the P anode region 12 of the diode portion 20 close to the boundary region 30 and the upper electrode (emitter electrode) 11 may be connected via a resistor R.

[0103] The P-type eighth semiconductor region 70 with a low impurity concentration in the boundary region 30 may also be connected to the upper electrode (emitter electrode) 11 via a resistor. For example, since the P-type eighth semiconductor region 70 has a low impurity concentration and is connected to the upper electrode 11 via a relatively large contact resistance, when the diode portion 20 is turned on, the amount of holes injected from the P-type eighth semiconductor region 70 in the boundary region 30 to the N-type drift region 5 can be reduced, thereby shortening the reverse recovery time of the diode portion 20.

[0104] (Emitter contact structure)

[0105] Fig.11 It is a plan view of a part of the semiconductor device according to the first embodiment.

[0106] In the IGBT part 10, the P base region 7 is sandwiched by the trenches 14 extending in the Y direction and extends in the Y direction. In addition, the n emitter region 8 is arranged in contact with the trenches 14 in the Z direction of the P base region 7. In addition, there is a hole between the adjacent trenches 14, and a P-type emitter contact region 9E is arranged under the bottom of the hole and in the Z direction of the P base region 7. The P-type emitter contact region 9E extends in the Y direction on the P base region 7 sandwiched by the trenches 14. The n emitter region 8 exposed on the side of the hole and the emitter contact region 9E at the bottom of the hole are connected to the emitter electrode (upper electrode) 11 buried in the hole.

[0107] In the Y direction where the P-type emitter contact region 9E is formed, a structure consisting of an n emitter region 8 / base region 7 / n emitter region 8 exposed on the side of the hole is formed. This structure is arranged on the ZY plane of the hole. The n emitter region 8 does not necessarily need to be arranged regularly in the Y direction. By intermittently arranging the n emitter region 8 in the IGBT unit 10, it is possible to suppress excessive electron injection and shorten the switching time.

[0108] (Second embodiment)

[0109] Fig.12 It is a plan view showing the overall structure of the semiconductor device 104 according to the second embodiment.

[0110] like Fig.12 As shown, the semiconductor device 104 of the second embodiment includes: a semiconductor substrate 101; a diode portion 20, which is arranged in a strip shape and extends in the X direction on the semiconductor substrate 101; and an IGBT portion 10, which is arranged on the semiconductor substrate 101 adjacent to the diode portion 20 in the positive and negative Y directions. Similar to the first embodiment, the semiconductor device 104 of the second embodiment also constitutes an RC-IGBT, which forms the IGBT portion 10 and the diode portion 20 for reflux on one semiconductor substrate 101. A region for improving withstand voltage, which is called a reduced surface electric field region, is provided in the terminal region 40 of the outer peripheral portion of the semiconductor device 104. The IGBT portion 10 is adjacent to the diode portion 20, which is arranged in a strip shape and extends in the X direction, on the semiconductor substrate 101 in the positive and negative Y directions. The IGBT portion 10 extends in the X direction and is arranged in a strip shape. A boundary region (dummy region) 30 is provided between the diode portion 20 and the IGBT portion 10. In addition, in Fig.12 In the example shown in FIG. 1 , a control pad portion 500 is further provided on the semiconductor substrate 101. Fig.12 Although not shown in the figure, an emitter pad 51 is provided on the IGBT unit 10 and / or the diode unit 20. The control pad unit 500 has a current sensing pad 50, a gate pad 52, and temperature sensing pads 53, 54.

[0111] Fig.13 Yes Fig.12 FIG. 1 is an enlarged top view of a portion of the semiconductor device 105. Fig.13 , a state in which the diode portion 20 , a boundary region (dummy portion) 30 arranged adjacent to the diode portion 20 in the negative Y direction, and the IGBT portion 10 arranged adjacent to the boundary region 30 in the negative Y direction are arranged is shown.

[0112] The semiconductor device 104 of the second embodiment differs from the semiconductor device 100 of the first embodiment only in that the IGBT unit 10, the diode unit 20, and the dummy unit 30 are arranged in a strip shape. The other structures are the same as those of the first embodiment and its modified example, and therefore, repeated descriptions are omitted.

[0113] In the second embodiment, as in the first embodiment, a semiconductor device in which the snapback phenomenon is suppressed can be provided.

[0114] (Other Embodiments)

[0115] As described above, the present invention is described through the implementation mode, but the discussion and drawings constituting a part of the disclosure should not be understood as limiting the present invention. Based on the disclosure, various alternative implementation modes, embodiments, and application technologies are obvious to those skilled in the art. Thus, of course, the present invention includes various implementation modes and the like that are not described here. Therefore, the technical scope of the present invention is determined only by the specific matters of the invention involved in the appropriate claims according to the above description. For example, an example is shown in which the grooves 14, 15, and 16 do not penetrate the accumulation region 6, but at least one groove may penetrate the accumulation region 6, and the accumulation region 6 may not be provided in any one of the IGBT portion 10, the diode portion 20, and the dummy portion 30.

Claims

1. A semiconductor device, wherein: The semiconductor device comprises a first semiconductor element, a second semiconductor element and a dummy region. The first semiconductor element has: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed above the first semiconductor region; a third semiconductor region of the first conductivity type, disposed above the second semiconductor region; a first trench provided to penetrate the second semiconductor region in a depth direction; a first in-trench electrode disposed in the first trench via a first insulating film; a fourth semiconductor region of the second conductivity type, which is provided below the first semiconductor region and on the opposite side to the second semiconductor region; an upper electrode electrically connected to the third semiconductor region; and a lower electrode electrically connected to the fourth semiconductor region, The second semiconductor element has: a fifth semiconductor region of the second conductivity type, which is electrically connected to the upper electrode and is disposed above the first semiconductor region; a sixth semiconductor region of the first conductivity type, which is electrically connected to the lower electrode and is provided below the first semiconductor region and on the opposite side to the fifth semiconductor region; a second trench provided to penetrate the fifth semiconductor region in a depth direction; as well as a second in-trench electrode provided in the second trench via a second insulating film; The dummy area has: a seventh semiconductor region of the second conductivity type, located between the first semiconductor element and the second semiconductor element and disposed above the first semiconductor region; a third trench arranged to penetrate the seventh semiconductor region in a depth direction; as well as A third in-trench electrode is located in the third trench via a third insulating film and is electrically connected to the first in-trench electrode.

2. The semiconductor device according to claim 1, wherein The third semiconductor region is not provided above the seventh semiconductor region, The semiconductor device includes the fourth semiconductor region below the first semiconductor region and on the opposite side to the seventh semiconductor region.

3. The semiconductor device according to claim 1, wherein The third grooves adjacent to each other and arranged in the first direction in which the first grooves extend are connected to each other. The first in-trench electrode and the third in-trench electrode are connected.

4. The semiconductor device according to any one of claims 1 to 3, wherein: In a plan view, a direction in which the second semiconductor element is arranged from the first semiconductor element is not parallel to a direction in which the third in-trench electrode provided between the first semiconductor element and the second semiconductor element extends.

5. The semiconductor device according to claim 4, wherein: The dummy region is provided so as to surround the second semiconductor element when viewed from above. The first semiconductor element region is provided so as to surround the dummy region.

6. The semiconductor device according to claim 3, wherein: On the second semiconductor element side where the third trench extends, adjacent third trenches are connected via a connecting trench. The third in-trench electrode is formed in the connection trench via the third insulating film.

7. The semiconductor device according to claim 3, wherein: The second groove extends in the first direction, The semiconductor device has an eighth semiconductor region of the second conductivity type, the eighth semiconductor region being located between the first direction of the second trench and the first direction of the third trench and being disposed above the first semiconductor region. A distance between the eighth semiconductor region and the third semiconductor region in the first direction is longer than a distance between the eighth semiconductor region and the third semiconductor region in a second direction perpendicular to the first direction.

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