Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a substrate, a gate structure, a first metal layer, a second metal layer and a planarization layer. The gate structure is disposed on the substrate and between the source region and the drain region. The first metal layer is disposed on the gate structure and includes a first gate contact, a first source contact, and a first drain contact electrically connected to the gate structure, the source region, and the drain region, respectively, and a floating metal ring disposed between the first gate contact and the first drain contact. The second metal layer is arranged on the first metal layer and comprises a second source contact object and a second drain contact object which are electrically connected with the first source contact object and the first drain contact object respectively. The planarization layer is disposed between the second source contact and the second drain contact, and overlaps the floating metal ring in the normal direction of the substrate.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices having high breakdown voltage. Background Art

[0002] In order to integrate the power device with the control circuit into an integrated circuit, it is necessary to select a power device with a high breakdown voltage.

[0003] However, the power device may be invaded by mobile ions, causing the electric field to be redistributed, thereby reducing the breakdown voltage of the power device. Furthermore, the power device may also produce coupling due to the accumulation of charges between layers, which may also reduce the breakdown voltage of the power device.

[0004] Therefore, although existing semiconductor devices have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor devices. Summary of the invention

[0005] The present invention provides a semiconductor device with a high breakdown voltage to solve the problem of insufficient breakdown voltage. In view of the above problems, the present invention removes the conductive component located directly above the floating metal ring, so that the insulating material such as the planarization layer overlaps with the floating metal ring in the normal direction of the substrate. Alternatively, the present invention further removes the conductive component located directly above the first gate contact, so that the planarization layer overlaps with the first gate contact in the normal direction of the substrate. Therefore, the spacing between the second source contact and the second drain contact can be increased, thereby reducing the possibility of mobile ion invasion. Thereby, the electric field redistribution is reduced to increase the breakdown voltage and reliability of the semiconductor device.

[0006] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, a gate structure, a first metal layer, a second metal layer and a planarization layer. The substrate includes a source region and a drain region. The gate structure is disposed on the substrate and between the source region and the drain region. The first metal layer is disposed on the gate structure. The first metal layer includes a first gate contact, a first source contact, a first drain contact and a floating metal ring. The first gate contact is electrically connected to the gate structure. The first source contact is electrically connected to the source region. The first drain contact is electrically connected to the drain region. The floating metal ring is disposed between the first gate contact and the first drain contact. The second metal layer is disposed on the first metal layer. The second metal layer includes a second source contact and a second drain contact. The second source contact is electrically connected to the first source contact. The second drain contact is electrically connected to the first drain contact. The planarization layer is disposed between the second source contact and the second drain contact. The planarization layer overlaps with the floating metal ring in the normal direction of the substrate.

[0007] The semiconductor device of the present invention can be applied to various types of semiconductor equipment. To make the components and advantages of the present invention more clearly understood, various embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description in conjunction with the accompanying drawings will provide a better understanding of the present invention. It is worth noting that, according to standard industry practice, some features may not be drawn to scale. In fact, the sizes of different features may be increased or decreased for clarity of discussion.

[0009] Figures 1 to 7 2 are cross-sectional schematic diagrams respectively showing various stages of forming a semiconductor device according to some embodiments of the present invention.

[0010] Figure 8 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0011] Fig. 9 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0012] Fig.10 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0013] Fig.11 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0014] Fig.12 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0015] Figure Number:

[0016] 1, 2, 3, 4, 5, 6: Semiconductor devices

[0017] 10: Substrate

[0018] 12, 14, 16, 18: Trap

[0019] 20: Isolation Structure

[0020] 30: Gate structure

[0021] 32: Gate dielectric layer

[0022] 34: Gate electrode

[0023] 35: Gate field plate

[0024] 36: Spacer

[0025] 42: Base region

[0026] 44: Source region

[0027] 48: Drain region

[0028] 50: Overlay

[0029] 52, 54, 56, 57, 58, 72, 74, 78: guide hole

[0030] 62: First base contact

[0031] 64: First source contact

[0032] 66: First gate contact

[0033] 67: Floating metal ring

[0034] 67a, 67b, 67c, 67d: Partial

[0035] 68: First drain contact

[0036] 70: Interlayer dielectric layer

[0037] 82: Second base contact

[0038] 84: Second source contact

[0039] 86: Floating Field Plate

[0040] 88: Second drain contact

[0041] 90: Flattening layer

[0042] D1: First direction

[0043] D2: Second direction

[0044] d1: first distance

[0045] d2: second distance

[0046] d3: third distance

[0047] M1: First metal layer

[0048] M2: Second metal layer

[0049] s1: first spacing

[0050] s2: second spacing

[0051] s3: third spacing

[0052] s4: fourth spacing

[0053] w64, w66, w68, w84, w86, w88: Width DETAILED DESCRIPTION

[0054] The following invention provides many different embodiments or examples for implementing different components of the provided semiconductor device. Specific examples of each component and its configuration are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, if the description mentions that a first component is formed on a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that they are not in direct contact. In addition, the embodiments of the present invention may repeat device symbols and / or characters in different examples. Such repetition is for simplicity and clarity, and is not used to indicate the relationship between the different embodiments and / or aspects discussed.

[0055] Some variations of the embodiments are described below. In the various drawings and illustrated embodiments, similar device symbols are used to identify similar devices. It is understood that additional operations may be provided before, during, or after the method, and some of the described operations may be replaced or deleted for other embodiments of the aforementioned method.

[0056] Furthermore, spatially relative terms, such as "on", "below", "above", "below" and similar terms, include not only the orientations shown in the drawings, but also different orientations of the device in use or operation. When the device is turned to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein may also be interpreted according to the rotated orientation. Here, "approximately", "substantially" or similar terms generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific descriptions of "approximately", "substantially" or similar terms, the meaning of "approximately", "substantially" or similar terms may still be implied.

[0057] In this document, the directions are not limited to the three axes of the rectangular coordinate system such as the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following, the X-axis direction is the first direction (width direction) D1, and the Z-axis direction is the second direction (height / depth direction) D2. In some embodiments, the cross-sectional schematic diagrams described herein are schematic diagrams for observing the XZ plane.

[0058] In some embodiments, the terms "first metal layer" and "second metal layer" may represent different conductive layers in different layers, and the first metal layer and the second metal layer may be electrically isolated by an interlayer dielectric layer. In some embodiments, the first metal layer and / or the second metal layer may be a conductive interconnect layer in a semiconductor back end of line (BEOL). Furthermore, the semiconductor device may further include other metal layers, such as a third metal layer.

[0059] Reference Figures 1 to 7 , schematic cross-sectional views are respectively shown at various stages of forming a semiconductor device 1 according to some embodiments of the present invention.

[0060] like Figure 1 As shown, in some embodiments, a substrate 10 is provided. In some embodiments, the substrate 10 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate or a similar substrate thereof. Generally speaking, a semiconductor-on-insulator substrate includes a semiconductor film layer formed on an insulator. For example, the insulating layer may include a silicon oxide layer, a silicon nitride layer, a polysilicon layer or a combination thereof, and the insulating layer is provided on a silicon substrate or an aluminum nitride (AlN) substrate. In some embodiments, the substrate 10 may also be other types of substrates, such as a multi-layered substrate or a gradient substrate.

[0061] In some embodiments, the substrate 10 may include an elemental semiconductor, and the elemental semiconductor may include silicon, germanium, the like, or a combination thereof. The substrate 10 may also include a compound semiconductor, and the compound semiconductor may include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, the like, or a combination thereof. The substrate 10 may also include an alloy semiconductor, and the alloy semiconductor may include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, the like, or a combination thereof. In some embodiments, the substrate 10 is a silicon substrate.

[0062] In some embodiments, the substrate 10 may be a doped substrate or an undoped substrate. In some embodiments, a p-type or n-type dopant may be used to dope the substrate. For example, the p-type dopant may be boron (B), aluminum (Al), or the like. For example, the n-type dopant may be phosphorus (P), arsenic (As), or the like. In some embodiments, the substrate 10 may have a first conductivity type. For ease of explanation, the following is a detailed description of the substrate 10 having a first conductivity type of p-type, but the present invention is not limited thereto. In other embodiments, the first conductivity type may be n-type, that is, the substrate 10 may be an n-type substrate.

[0063] like Figure 1 As shown, in some embodiments, a well 12 and a well 14 are formed in the substrate 10. In some embodiments, the well 12 may have a second conductivity type different from the first conductivity type, and the well 14 may have the first conductivity type. For example, the well 12 is an n-type well, and the well 14 is a p-type well. In some embodiments, the well 12 and / or the well 14 may be formed by an ion implantation process, a diffusion process, or other suitable processes, but the present invention is not limited thereto. In some embodiments, a rapid thermal annealing (RTA) process may be further performed on the well 12 and / or the well 14 to activate the dopants implanted in the well 12 and / or 14 and control the doping depth of the dopants. In some embodiments, the well 12 may be formed first, and then the well 14 may be formed, but the present invention is not limited thereto.

[0064] In some embodiments, the well 12 may be embedded in the substrate 10, and the top surface of the well 12 may be coplanar with the top surface of the substrate 10. In some embodiments, the well 14 may be embedded in the well 12, and the top surface of the well 14 may be coplanar with the top surface of the substrate 10. In some embodiments, the bottom surface of the well 14 may be between the top surface and the bottom surface of the well 12. In some embodiments, the well 12 may surround the side surface and the bottom surface of the well 14. In some embodiments, in the first direction D1, the width of the well 12 is greater than the width of the well 14. In some embodiments, in the second direction D2, the depth of the well 12 is greater than the depth of the well 14.

[0065] In some embodiments, the well 12 may be a deep n-type well (DNW), and the well 14 may be a p-type well. By matching parameters such as the doping type, doping concentration, and / or doping depth of the wells 12 and 14, a depletion region is formed, thereby increasing the breakdown voltage of the subsequently formed semiconductor device.

[0066] like Figure 2As shown, an isolation structure 20 is formed on the substrate 10 to define an active region of a semiconductor device to be formed subsequently by the isolation structure 20. In some embodiments, the isolation structure 20 is disposed on the upper portion of the substrate 10, the well 12, and the well 14. In some embodiments, the isolation structure 20 may be an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like, or a combination thereof. In some embodiments, the isolation structure 20 may be a field oxide, a shallow trench isolation (STI) structure, the like, or a combination thereof. In some embodiments, the isolation structure 20 may be formed by a thermal oxidation process, a deposition process, a combination thereof, or any suitable process. In some embodiments, a deposition process and / or a patterning process may be performed in conjunction with setting a patterned mask to form the isolation structure 20. Then, a removal process may be performed to remove the patterned mask.

[0067] like Figure 3 As shown, in some embodiments, well 16 and well 18 are formed in substrate 10. In some embodiments, well 16 may have a first conductivity type, and well 18 may have a second conductivity type. For example, well 16 is a p-type well, and well 18 is an n-type well. In some embodiments, the formation process for forming well 16 and / or well 18 may be the same as or different from the formation process for forming well 12 and / or well 14. In some embodiments, well 16 may be adjacent to well 12, and well 16 and well 12 may be spaced apart by a distance. In some embodiments, in the second direction D2, the depth of well 16 may be less than the depth of well 12. In some embodiments, well 18 may be disposed in well 12 and adjacent to well 14. In some embodiments, well 18 is in contact with well 14. In some embodiments, in the second direction D2, the depth of well 18 may be greater than the depth of well 14.

[0068] like Figure 4As shown, in some embodiments, a gate structure 30 and a gate field plate 35 are formed on a substrate 10. In some embodiments, the gate structure 30 includes a gate dielectric layer 32 disposed on the substrate 10, a gate electrode 34 disposed on the gate dielectric layer 32, and spacers 36 disposed on both sides of the gate electrode 34. In some embodiments, the gate dielectric layer 32 and / or the spacer 36 may include silicon oxide, silicon nitride, silicon oxynitride, a dielectric material such as a high dielectric constant dielectric material, the like, or a combination thereof. The dielectric material may include metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, metal aluminate, the like, or a combination thereof. In some embodiments, the material of the gate dielectric layer 32 and the material of the spacer 36 may be the same or different. In some embodiments, the gate electrode 34 and / or the gate field plate 35 may include a conductive material, and the conductive material may include polysilicon, amorphous silicon, metal, metal nitride, conductive metal oxide, the like, or a combination thereof. For example, the metal may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), silver (Ag), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), rhodium (Rh), alloys thereof, the like, or combinations thereof. In some embodiments, the material of the gate electrode 34 and the material of the gate field plate 35 may be the same or different. In some embodiments, the gate electrode 34 and the gate field plate 35 may each include polysilicon.

[0069] For example, in some embodiments, a gate dielectric layer 32 is conformally formed on the top surface of the substrate 10. Next, a conductive material layer is formed on the gate dielectric layer 32, and the conductive material layer is patterned to form a gate electrode 34 located on the gate dielectric layer 32 and a gate field plate 35 located on the isolation structure 20. Then, a material for the spacer 36 is conformally formed, and an etching process is performed to form the spacer 36 on the gate electrode 34. In other embodiments, the gate electrode 34 and the gate field plate 35 can be formed separately. For example, the gate electrode 34 and the gate field plate 35 are formed successively in different processes. In some embodiments, the gate field plate 35 can be used to balance the charge to improve the reliability of the subsequently formed semiconductor device 1. In other embodiments, the gate field plate 35 can be omitted, and the subsequent formation of the gate field plate 35 for electrically connecting to the first drain contact (such as Figure 6 The first drain contact 68 shown in FIG. Figure 6 The guide hole 57 shown).

[0070] like Figure 5As shown, in some embodiments, a base region 42, a source region 44, and a drain region 48 are formed in the substrate 10. In other words, the substrate 10 may include the base region 42, the source region 44, and the drain region 48. In some embodiments, the base region 42 may have a first conductivity type, and the source region 44 and the drain region 48 may have a second conductivity type. For example, the base region 42 is a heavily doped p-type well, and the source region 44 and the drain region 48 are heavily doped n-type wells. In some embodiments, the formation process for forming the base region 42, the source region 44, and / or the drain region 48 may be the same or different from the formation process for forming the well 12, the well 14, the well 16, and / or the well 18. In some embodiments, the base region 42 and the source region 44 are formed in the well 16, and the base region 42 and the source region 44 are adjacent to each other and separated by a distance. In some embodiments, the drain region 48 is disposed in the well 18. In some embodiments, gate structure 30 is disposed between source region 44 and drain region 48. In some embodiments, base region 42 may have a doping concentration greater than that of well 16. In some embodiments, drain region 48 may have a doping concentration greater than that of well 18.

[0071] like Figure 6 As shown, in some embodiments, a capping layer 50 is blanket formed on the substrate 10 to provide electrical isolation. In some embodiments, the capping layer 50 is formed on the substrate 10, the isolation structure 20, the base region 42, the source region 44, the gate structure 30, the gate field plate 35, and the drain region 48. In some embodiments, the capping layer 50 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, a dielectric material, the like, or a combination thereof. In some embodiments, the capping layer 50 may be formed on the substrate 10 by a deposition process.

[0072] like Figure 6As shown, in some embodiments, a via 52, a via 54, a via 56, a via 57, and a via 58 are formed through the capping layer 50. In some embodiments, the via 52 can be electrically connected to the base region 42, the via 54 can be electrically connected to the source region 44, the via 56 can be electrically connected to the gate structure 30, the via 57 can be electrically connected to the gate field plate 35, and the via 58 can be electrically connected to the drain region 48. In some embodiments, an opening (not shown) can be first formed through the capping layer 50, and then a conductive material can be filled in the opening to form the via 52, the via 54, the via 56, the via 57, and / or the via 58. In some embodiments, the conductive material can be filled in the opening by a chemical vapor deposition (CVD) process, a sputtering process, a resistance heating evaporation method, an electron beam evaporation method, other suitable deposition processes, or a combination thereof. In addition, after the conductive material is filled, a chemical mechanical polishing (CMP) process can be further performed.

[0073] like Figure 6 As shown, in some embodiments, a first metal layer M1 is formed on the gate structure 30. Specifically, the first metal layer M1 is formed on the capping layer 50, the via 52, the via 54, the via 56, the via 57, and the via 58. In some embodiments, the first metal layer M1 may include a first base contact 62, a first source contact 64, a first gate contact 66, a first drain contact 68, and a floating metal ring 67.

[0074] In some embodiments, the material and forming method of the first metal layer M1 may be the same as or different from the material and forming method of the via 52, via 54, via 56, via 57 and / or via 58. In some embodiments, the first metal layer M1 may include a conductive material. In some embodiments, a conductive material layer may be conformably formed and patterned to form a first base contact 62, a first source contact 64, a first gate contact 66, a first drain contact 68 and a floating metal ring 67. In other embodiments, the first base contact 62, the first source contact 64, the first gate contact 66, the first drain contact 68 and / or the floating metal ring 67 may be formed separately as required, such as being formed successively in different processes. In some embodiments, the first base contact 62 is disposed on the via 52 and is electrically connected to the base region 42 through the via 52. In some embodiments, the first source contact 64 is disposed on the via 54 and is electrically connected to the source region 44 through the via 54. In some embodiments, the first gate contact 66 is disposed on the via 56 and electrically connected to the gate structure 30 through the via 56. In some embodiments, the first drain contact 68 is disposed on the vias 57 and 58 and electrically connected to the drain region 48 through the via 58.

[0075] In some embodiments, the floating metal ring 67 may be disposed between the first gate contact 66 and the first drain contact 68, and the floating metal ring 67 is electrically isolated from the first gate contact 66 and the first drain contact 68. In some embodiments, when viewed from a top view (not shown), the floating metal ring 67 may have a ring shape, a multi-ring shape, a racetrack shape, or a similar shape or a combination thereof to improve the breakdown voltage and reliability of a subsequently formed semiconductor device. In some embodiments, as shown in FIG. Figure 6 As shown, a floating metal ring 67 having a multi-ring shape of 4 rings is taken as an example, but the present invention is not limited thereto. For example, the floating metal ring 67 may have 1, 2, 3, 4, 5, or any positive integer number of rings. In some embodiments, the floating metal ring 67 may include a portion 67a, a portion 67b, a portion 67c, and a portion 67d arranged in a spaced relationship from each other in the first direction D1.

[0076] like Figure 7 As shown, in some embodiments, an interlayer dielectric layer 70 is blanket-formed on the cover layer 50 to provide electrical isolation. In some embodiments, the interlayer dielectric layer 70 is formed on the cover layer 50 and the first metal layer M1. In some embodiments, the material and formation process of the interlayer dielectric layer 70 may be the same as or different from the material and formation process of the cover layer 50.

[0077] like Figure 7As shown, in some embodiments, a guide hole 72, a guide hole 74, and a guide hole 78 are formed through the interlayer dielectric layer 70. In some embodiments, the guide hole 72 can be electrically connected to the first base contact 62, the guide hole 74 can be electrically connected to the first source contact 64, and the guide hole 78 can be electrically connected to the first drain contact 68. In some embodiments, an opening (not shown) can be first formed through the interlayer dielectric layer 70, and then a conductive material can be filled in the opening to form the guide hole 72, the guide hole 74, and the guide hole 78. In some embodiments, the materials and deposition processes used to form the guide hole 72, the guide hole 74, and / or the guide hole 78 can be the same as or different from the materials and formation methods used to form the guide hole 52, the guide hole 54, the guide hole 56, the guide hole 57, and / or the guide hole 58.

[0078] like Figure 7 As shown, in some embodiments, the second metal layer M2 is formed on the first metal layer M1. Specifically, the second metal layer M2 is formed on the interlayer dielectric layer 70, the guide hole 72, the guide hole 74 and the guide hole 78. In some embodiments, the second metal layer M2 may include a second base contact 82, a second source contact 84 and a second drain contact 88. In some embodiments, the material and the forming method of the second metal layer M2 may be the same as or different from the material and the forming method of the first metal layer M1. In some embodiments, the second metal layer M2 may include a conductive material. In some embodiments, a conductive material layer may be formed conformably and patterned to form a second base contact 82, a second source contact 84 and a second drain contact 88. In other embodiments, the second base contact 82, the second source contact 84 and the second drain contact 88 may be formed separately according to needs, such as being formed successively in different processes. In some embodiments, the second base contact 82 is disposed on the guide hole 72 and is electrically connected to the first base contact 62 through the guide hole 72. In some embodiments, the second source contact 84 is disposed on the via 74 and electrically connected to the first source contact 64 through the via 74. In some embodiments, the second drain contact 88 is disposed on the via 78 and electrically connected to the first drain contact 68 through the via 78.

[0079] like Figure 7As shown, in some embodiments, a planarization layer 90 is formed on the first metal layer M1 to obtain the semiconductor device 1. In some embodiments, the material and formation process of the planarization layer 90 may be the same as or different from the material and formation process of the cap layer 50 and / or the interlayer dielectric layer 70. For example, the planarization layer 90 may include an insulating material or a dielectric material. In some embodiments, the planarization layer 90 may be formed on the first metal layer M1 and the second metal layer M2 by a blanket deposition process, and then a planarization process is performed to expose the top surface of the second metal layer M2. In some embodiments, the planarization layer 90 is disposed between the second base contact 82 and the second source contact 84, and between the second source contact 84 and the second drain contact 88 to provide electrical isolation between the second base contact 82, the second source contact 84, and the second drain contact 88. In some embodiments, further processes such as a deposition process, an etching process, and a patterning process may be performed on the semiconductor device 1.

[0080] In some embodiments, in the first direction D1, the width of the planarization layer 90 between the second source contact 84 and the second drain contact 88 is greater than the width of the interlayer dielectric layer 70 between the first source contact 64 and the first drain contact 68. For example, the width of the planarization layer 90 between the second source contact 84 and the second drain contact 88 is greater than the sum of the width between the first source contact 64 and the first gate contact 66, the width between the first gate contact 66 and the portion 67a, the width between the portion 67a and the portion 67b, the width between the portion 67b and the portion 67c, the width between the portion 67c and the portion 67d, and the width between the portion 67d and the first drain contact 68. In some embodiments, the projected area of ​​the planarization layer 90 between the second source contact 84 and the second drain contact 88 on the substrate 10 is greater than the projected area of ​​the interlayer dielectric layer 70 between the first source contact 64 and the first drain contact 68 on the substrate 10.

[0081] In some embodiments, the planarization layer 90 overlaps with the floating metal ring 67 of the first metal layer M1 in the normal direction (second direction D2) of the substrate 10. In other words, there is no additional conductive component directly above the floating metal ring 67 of the first metal layer M1 and in the same layer as the second metal layer M2. For example, no additional floating metal ring is provided directly above the floating metal ring 67 and in the same layer as the second metal layer M2. In some embodiments, the second metal layer M2 does not overlap with the floating metal ring 67 of the first metal layer M1 in the normal direction (second direction D2) of the substrate 10.

[0082] In some embodiments, the projected area of ​​the second metal layer M2 on the substrate 10 may be smaller than the projected area of ​​the first metal layer M1 on the substrate 10. For example, the projected area of ​​the second metal layer M2 on the substrate 10 between the second source contact 84 and the second drain contact 88 may be smaller than the projected area of ​​the first metal layer M1 on the substrate 10 between the first source contact 64 and the first drain contact 68. For example, by providing a planarization layer such as an insulating material or a dielectric material between the second source contact 84 and the second drain contact 88, the projected area of ​​the second metal layer M2 on the substrate 10 is reduced.

[0083] Accordingly, by not providing an additional floating metal ring between the second source contact 84 and the second drain contact 88, the possibility of mobile ion invasion and / or the charge coupling caused by accumulated charges can be reduced. For example, since no additional conductive component is provided between the second source contact 84 and the second drain contact 88, a deposition process such as plasma enhanced chemical vapor deposition (PECVD) can be omitted, thereby avoiding the problem of uneven distribution of threshold voltage caused by charge accumulation at the gate structure 30 due to the use of plasma. Therefore, the present invention can improve the breakdown voltage and reliability of the semiconductor device 1. For example, the reliability of the (high temperature reverse bias, HTRB) test of the semiconductor device 1 can be improved.

[0084] In some embodiments, the planarization layer 90 overlaps with the first gate contact 66 of the first metal layer M1 in the normal direction (second direction D2) of the substrate 10. In other words, there are no additional conductive components directly above the first gate contact 66 of the first metal layer M1 and in the same layer as the second metal layer M2. For example, no additional gate contact is provided directly above the first gate contact 66 and in the same layer as the second metal layer M2. In some embodiments, the second metal layer M2 does not overlap with the first gate contact 66 of the first metal layer M1 in the normal direction (second direction D2) of the substrate 10. Accordingly, by not providing an additional gate contact between the second source contact 84 and the second drain contact 88, the possibility of mobile ion intrusion and / or the charge coupling caused by the accumulated charge can be reduced, thereby improving the breakdown voltage and reliability of the semiconductor device 1. It should be noted that although Figure 7 The additional gate contact is not shown, but the first gate contact 66 may still be electrically connected to the second metal layer M2 via an additional wiring (not disposed directly above the first gate contact 66 ).

[0085] The same or similar device symbols and / or descriptions are omitted below.

[0086] Reference Figure 8 , which is a cross-sectional schematic diagram showing a semiconductor device 2 according to some embodiments of the present invention. In some embodiments, Figure 8 As shown, in the first direction D1, the width w88 of the second drain contact 88 is smaller than the width w68 of the first drain contact 68. In some embodiments, in the first direction D1, the edge of the second drain contact 88 (e.g., the edge adjacent to the second source contact 84) and the edge of the first drain contact 68 (e.g., the edge adjacent to the floating metal ring 67) may have a first distance d1. For example, the first distance d1 may be greater than 0. Accordingly, by shortening the width w88 of the second drain contact 88, the possibility of mobile ion invasion and / or the charge coupling caused by the accumulated charges are reduced, thereby improving the breakdown voltage and reliability of the semiconductor device 2.

[0087] Reference Fig. 9 , which is a cross-sectional schematic diagram showing a semiconductor device 3 according to some embodiments of the present invention. In some embodiments, Fig. 9 As shown, in the first direction D1, the width w84 of the second source contact 84 may be smaller than the width w64 of the first source contact 64. In some embodiments, in the first direction D1, the edge of the second source contact 84 (e.g., the edge adjacent to the second drain contact 88) and the edge of the first source contact 64 (e.g., the edge adjacent to the first gate contact 66) have a second distance d2. For example, the second distance d2 may be greater than 0. Accordingly, by shortening the width w84 of the second source contact 84, the possibility of mobile ion invasion and / or the charge coupling caused by the accumulated charge is reduced, thereby improving the breakdown voltage and reliability of the semiconductor device 3. In other embodiments, if the width w84 of the second source contact 84 is greater than the width w64 of the first source contact 64, the second source contact 84 may be electrically coupled with the second drain contact 88, thereby reducing the breakdown voltage and reliability.

[0088] Reference Fig.10, which is a cross-sectional schematic diagram of a semiconductor device 4 according to some embodiments of the present invention. In some embodiments, in the first direction D1, the width w88 of the second drain contact 88 is less than the width w68 of the first drain contact 68, and the width w84 of the second source contact 84 is less than the width w64 of the first source contact 64. In some embodiments, in the first direction D1, the edge of the second drain contact 88 has a first distance d1 from the edge of the first drain contact 68, and the edge of the second source contact 84 has a second distance d2 from the edge of the first source contact 64. In some embodiments, both the first distance d1 and the second distance d2 may be greater than 0 or equal to 0. In some embodiments, the first distance d1 may be greater than 0 and the second distance d2 may be equal to 0, or the first distance d1 may be equal to 0 and the second distance d2 may be greater than 0. In some embodiments, the first spacing s1 between the first source contact 64 and the first drain contact 68 is less than or equal to the second spacing s2 between the second source contact 84 and the second drain contact 88. Accordingly, by shortening the width w88 of the second drain contact 88 and the width w84 of the second source contact 84 , the possibility of mobile ion invasion and / or the charge coupling caused by accumulated charges are reduced, thereby improving the breakdown voltage and reliability of the semiconductor device 4 .

[0089] Reference Fig.11 , which is a cross-sectional schematic diagram of a semiconductor device 5 according to some embodiments of the present invention. In some embodiments, the semiconductor device 5 may further include a floating field plate 86. In some embodiments, the floating field plate 86 is disposed on the first metal layer M1 and is electrically isolated from the first metal layer M1. Specifically, the floating field plate 86 is disposed directly above the first gate contact 66 and is disposed on the interlayer dielectric layer 70. In some embodiments, the floating field plate 86 is disposed between the second source contact 84 and the second drain contact 88. Fig.11 As shown, the planarization layer 90 is disposed between the floating field plate 86 and the second source contact 84, and the planarization layer 90 is disposed between the floating field plate 86 and the second drain contact 88, so that the floating field plate 86 is electrically isolated from the second source contact 84 and the second drain contact 88. Accordingly, the floating field plate 86 can adjust the charge balance, reduce the possibility of mobile ion invasion and / or reduce the charge coupling caused by the accumulated charge, thereby improving the breakdown voltage and reliability of the semiconductor device 5.

[0090] Reference Fig.12, which is a cross-sectional schematic diagram of a semiconductor device 6 according to some embodiments of the present invention. In some embodiments, in the first direction D1, the width w86 of the floating field plate 86 is less than the width w66 of the first gate contact 66. In some embodiments, in the first direction D1, the edge of the floating field plate 86 (for example, the edge adjacent to the second drain contact 88) and the edge of the first gate contact 66 have a third distance d3. In some embodiments, both the first distance d1 and the third distance d3 may be greater than 0 or equal to 0. In some embodiments, the first distance d1 may be greater than 0 and the third distance d3 may be equal to 0, or the first distance d1 may be equal to 0 and the third distance d3 may be greater than 0. Accordingly, by shortening the width w86 of the floating field plate 86, the possibility of mobile ion invasion and / or the charge coupling caused by the accumulated charge is reduced, thereby improving the breakdown voltage and reliability of the semiconductor device 6.

[0091] In summary, the present invention provides a planarization layer between the second source contact and the second drain contact, thereby omitting an additional floating metal ring (or further omitting a floating field plate), thereby reducing the possibility of mobile ion invasion and / or reducing charge coupling caused by accumulated charges, thereby improving the breakdown voltage and reliability of the semiconductor device.

[0092] The protection scope of the present invention is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any technician in the relevant technical field can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present invention. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of the present invention. Therefore, the protection scope of the present invention includes the aforementioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each patent application constitutes a separate embodiment, and the protection scope of the present invention also includes the combination of each patent application and the embodiment.

[0093] Several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate including a source region and a drain region; A gate structure is disposed on the substrate and between the source region and the drain region; A first metal layer is disposed on the gate structure and includes: a first gate contact electrically connected to the gate structure; a first source contact electrically connected to the source region; a first drain contact electrically connected to the drain region; and a floating metal ring disposed between the first gate contact and the first drain contact; A second metal layer, disposed on the first metal layer, and comprising: a second source contact electrically connected to the first source contact; and a second drain contact electrically connected to the first drain contact; and A planarization layer is disposed between the second source contact and the second drain contact and overlaps with the floating metal ring in the normal direction of the substrate.

2. The semiconductor device according to claim 1, wherein The planarization layer overlaps the first gate contact in a normal direction of the substrate.

3. The semiconductor device according to claim 1, wherein The second metal layer and the floating metal ring do not overlap in the normal direction of the substrate.

4. The semiconductor device according to claim 1, wherein: The second metal layer and the first gate contact do not overlap in a normal direction of the substrate.

5. The semiconductor device according to claim 1, wherein: The projection area of ​​the second metal layer on the substrate is smaller than the projection area of ​​the first metal layer on the substrate.

6. The semiconductor device according to claim 1, wherein: The width of the second drain contact is smaller than the width of the first drain contact.

7. The semiconductor device according to claim 1, wherein The width of the second source contact is smaller than the width of the first source contact.

8. The semiconductor device according to claim 1, wherein A spacing between the first source contact and the first drain contact is less than or equal to a spacing between the second source contact and the second drain contact.

9. The semiconductor device according to claim 1, wherein: Also includes: A floating field plate is disposed on the first metal layer and between the second source contact and the second drain contact.

10. The semiconductor device according to claim 9, wherein: A spacing between the first gate contact and the first drain contact is less than or equal to a spacing between the floating field plate and the second drain contact.

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