Semiconductor structure, manufacturing method of semiconductor structure and CMOS (complementary metal oxide semiconductor) device

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method of the semiconductor structure and a CMOS device. The semiconductor structure comprises a substrate; a metal gate formed on the substrate; wherein the surface of the metal gate is provided with a groove; the groove extends along the surface, away from the substrate, of the metal gate to the direction close to the substrate; the groove is provided with a bottom side surface; a gate contact structure formed on one side of the metal gate away from the substrate; wherein the gate contact structure is in contact with the bottom surface and the side surface of the groove. According to the embodiment of the invention, the contact area between the gate contact structure and the metal gate is increased, the contact resistance between the gate contact structure and the metal gate is reduced, and the performance of the CMOS device is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a semiconductor structure, a method for manufacturing a semiconductor structure, and a CMOS device. Background Art

[0002] CMOS transistors (Complementary Metal Oxide Semiconductor Field-Effect Transistor, CMOS FET) are the main semiconductor devices in large-scale integrated circuits. As the integration density of semiconductor devices increases, the feature size of CMOS transistors continues to decrease. For process nodes of 40nm and below, physical effects such as short channel effects and hot carrier effects may cause the threshold voltage control capability of CMOS transistors to decrease and leakage current to increase, resulting in a significant reduction in CMOS transistor performance.

[0003] In existing technology, HKMG (High-K Metal Gate) is primarily used to replace traditional polysilicon gates to improve the performance of CMOS transistors. Specifically, the HKMG gate dielectric layer is made of a dielectric material with a high dielectric constant, and the gate electrode is a conductive material containing a metal element. To improve the performance of CMOS transistors containing HKMG, HKMG is primarily fabricated using a gate-last process. After a CMOS transistor containing HKMG is fabricated using this existing gate-last process, CMOS devices can be manufactured based on this CMOS transistor.

[0004] However, when researchers tested the CMOS device manufactured based on the CMOS transistor containing HKMG, they found that the contact resistance between the HKMG and the gate contact structure in the CMOS transistor was relatively large. Summary of the Invention

[0005] In view of this, various embodiments of the present application provide a semiconductor structure, a method for manufacturing the semiconductor structure, and a CMOS device to reduce the contact resistance between the HKMG and the gate contact structure in the CMOS device.

[0006] In one aspect, an embodiment of the present application provides a semiconductor structure, comprising: a substrate; a metal gate formed on the substrate; wherein the surface of the metal gate has a groove; the groove extends along the surface of the metal gate away from the substrate toward the substrate; the groove has a bottom surface and a side surface; a gate contact structure formed on the side of the metal gate away from the substrate; wherein the gate contact structure is in contact with both the bottom surface and the side surface of the groove.

[0007] Optionally, the extension direction of the groove is the depth direction of the groove and the height direction of the metal gate; along the extension direction of the groove, the ratio of the depth of the groove to the height of the metal gate falls within the range of 1:4 to 2:5.

[0008] Optionally, the groove includes a gap portion and a contact portion in contact with the gate contact structure; the semiconductor structure also includes: an interlayer dielectric layer formed on the metal gate; wherein the interlayer dielectric layer has a dielectric layer opening corresponding to the contact portion; the gate contact structure contacts the contact portion through the dielectric layer opening; and an air gap is formed between the gap portion and the interlayer dielectric layer.

[0009] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method for manufacturing a semiconductor structure comprising: providing a substrate; wherein the substrate has a gate trench; the gate trench has a bottom surface and a side surface; the normal direction of the bottom surface of the gate trench is a first direction; the normal direction of the side surface of the gate trench is a second direction; depositing a metal gate material on the substrate to form a metal gate having a groove on the surface in the gate trench; wherein the deposition amount of the metal gate material along the first direction is greater than the deposition amount along the second direction; the groove extends along the surface of the metal gate away from the substrate toward the direction close to the substrate; the groove has a bottom surface and a side surface; forming a gate contact structure on the side of the metal gate away from the substrate; wherein the gate contact structure is in contact with both the bottom surface and the side surface of the groove.

[0010] Optionally, the groove has a groove depth along the extension direction of the groove; the step of providing a base comprises: providing a substrate; wherein the substrate comprises an NMOS region and a PMOS region; forming a dielectric layer on the substrate; wherein the distance between the surface of the dielectric layer away from the substrate and the substrate is not less than a specified value; the specified value is the sum of the gate base height value and the groove depth value; etching the dielectric layer to form an NMOS dielectric layer opening and a PMOS dielectric layer opening in the dielectric layer corresponding to the NMOS region and the PMOS region; in the NMOS dielectric layer An NMOS gate dielectric layer and an NMOS dummy gate are formed in the opening, and a PMOS gate dielectric layer and a PMOS dummy gate are formed in the PMOS dielectric layer opening; wherein the distance between the surface of the NMOS dummy gate and the PMOS dummy gate away from the substrate and the substrate is equal to the distance between the surface of the dielectric layer away from the substrate and the substrate; the NMOS dummy gate and the PMOS dummy gate are removed to obtain a transition substrate having a gate transition trench; and an etch stop layer and a metal work function layer are sequentially formed on the surface of the transition substrate to obtain the substrate having the gate trench.

[0011] Optionally, the step of depositing a metal gate material on the substrate and forming a metal gate having a groove on its surface in the gate groove includes: depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate groove; wherein the metal gate material layer includes a flat portion formed on the surface of the substrate, a groove bottom formed on the bottom surface of the gate groove, and a groove side formed on the side surface of the gate groove; a metal gate groove is formed between the flat portion, the groove bottom, and the groove side; the metal gate groove is filled; and a planarization treatment is performed to form the metal gate having a groove on its surface and a filling portion in the gate groove; wherein the filling portion is in contact with both the bottom and side surfaces of the groove.

[0012] Optionally, the step of depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench includes: performing a first deposition to obtain a first metal gate material layer formed on the surface of the substrate and the bottom and two side surfaces of the gate trench; wherein the first metal gate material layer includes a first flat portion formed on the surface of the substrate, a first trench bottom formed on the bottom surface of the gate trench, and a first trench side formed on the side surface of the gate trench; the thickness of the first flat portion and the first trench bottom along the first direction is equal to the thickness of the first trench side along the second direction; performing a second deposition to obtain a second metal gate material layer formed on the surface of the first flat portion and the surface of the first trench bottom; wherein the second metal gate material layer includes a second flat portion formed on the surface of the first flat portion and a second trench bottom formed on the bottom of the first trench; the thickness of the second flat portion along the first direction is equal to the thickness of the second trench bottom along the first direction; and the metal gate trench is formed between the second flat portion, the second trench bottom, and the first trench side.

[0013] Optionally, the step of depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and two side surfaces of the gate trench includes: performing a third deposition to obtain a third metal gate material layer formed on the surface of the substrate and the bottom and two side surfaces of the gate trench; wherein the third metal gate material layer includes a third flat portion formed on the surface of the substrate, a third trench bottom formed on the bottom surface of the gate trench, and a second trench side formed on the side surface of the gate trench; the thickness of the third flat portion along the first direction is equal to the thickness of the third trench bottom along the first direction; the thickness of the third flat portion along the first direction is greater than the thickness of the second trench side along the second direction; the metal gate trench is formed between the third flat portion, the third trench bottom, and the second trench side; during the third deposition process, the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction falls within the range of 24:1 to 26:1.

[0014] Optionally, the groove includes a contact portion that contacts the gate contact structure; before the step of forming the gate contact structure on the side of the metal gate away from the substrate, the method further includes: forming an interlayer dielectric layer on the metal gate; removing the interlayer dielectric layer and the filling portion corresponding to the contact portion, so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion; the gate contact structure contacts the contact portion through the dielectric layer opening.

[0015] Optionally, when the interlayer dielectric layer and the filling portion are made of the same material, the step of removing the interlayer dielectric layer and the filling portion corresponding to the contact portion so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion includes: etching and removing the interlayer dielectric layer and the filling portion corresponding to the contact portion based on specified etching process parameters so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion; wherein the interlayer dielectric layer and the filling portion are removed in the same process step.

[0016] Optionally, the groove further includes a gap portion; when the materials of the interlayer dielectric layer and the filling portion are different, the step of removing the interlayer dielectric layer and the filling portion corresponding to the contact portion so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion includes: etching and removing the interlayer dielectric layer corresponding to the contact portion based on specified etching process parameters; removing the filling portion so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion, and forming an air gap between the gap portion and the interlayer dielectric layer.

[0017] In another aspect, an embodiment of the present application provides a CMOS device, which includes the semiconductor structure described in the above embodiment or a semiconductor structure manufactured according to the method for manufacturing the semiconductor structure described in the above embodiment.

[0018] In multiple embodiments of the present application, a metal gate is prepared by depositing a metal gate material on a substrate having a gate trench, wherein the gate trench has a bottom surface and a side surface, the normal direction of the bottom surface of the gate trench is a first direction, and the normal direction of the side surface of the gate trench is a second direction. During the deposition of the metal gate material, the deposition amount of the metal gate material along the first direction is controlled to be greater than the deposition amount along the second direction, so that the surface of the metal gate obtained by the deposition process has a groove, and the groove also has a bottom surface and a side surface. A gate contact structure is then prepared on the side of the metal gate away from the substrate, so that the gate contact structure is in contact with both the bottom surface and the side surface of the groove. The unexpected effects achieved include: since the contact surface between the gate contact structure and the metal gate is increased from the bottom surface of the gate contact structure to the bottom surface and the side surface of the groove on the metal gate surface, the contact area between the gate contact structure and the metal gate is increased, and the contact resistance between the gate contact structure and the metal gate is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required to describe the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 Images of gate contact structures and metal gate contacts provided for related art.

[0021] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor structure provided in accordance with an embodiment of the present application.

[0022] Figure 3 A schematic diagram of a process for providing a substrate is provided for one embodiment of the present application.

[0023] Figure 4 A schematic diagram of forming a dielectric layer on a substrate is provided according to one embodiment of the present application.

[0024] Figure 5 A schematic diagram of forming an NMOS dielectric layer opening and a PMOS dielectric layer opening is provided for one embodiment of the present application.

[0025] Figure 6 A schematic diagram of forming an NMOS gate dielectric layer, an NMOS dummy gate, a PMOS gate dielectric layer, and a PMOS dummy gate is provided for one embodiment of the present application.

[0026] Figure 7 A schematic diagram of a transition substrate provided for one embodiment of the present application.

[0027] Figure 8 A schematic diagram of sequentially forming an etch stop layer and a first sub-work function material layer on a transition substrate provided in one embodiment of the present application.

[0028] Figure 9 A schematic diagram of forming a photolithography functional layer on the surface of a first sub-work function layer according to an embodiment of the present application.

[0029] Figure 10 A schematic diagram of removing the first sub-work function material layer corresponding to the NMOS region provided in one embodiment of the present application.

[0030] Figure 11 A schematic diagram of a substrate provided for one embodiment of the present application.

[0031] Figure 12 A schematic diagram of a process for forming a metal gate having a groove on its surface in a gate trench is provided for one embodiment of the present application.

[0032] Figure 13 A schematic diagram of sequentially forming a first metal gate material layer and a second metal gate material layer on a substrate is provided for one embodiment of the present application.

[0033] Figure 14 A schematic diagram of forming a third metal gate material layer on a substrate is provided according to another embodiment of the present application.

[0034] Figure 15 A schematic diagram of forming a metal gate and a filling portion after planarization treatment is provided in one embodiment of the present application.

[0035] Figure 16 A schematic diagram of forming a dielectric layer opening corresponding to a contact portion in an interlayer dielectric layer is provided for one embodiment of the present application.

[0036] Figure 17 A three-dimensional schematic diagram of a metal gate having grooves on its surface is provided for one embodiment of the present application.

[0037] Figure 18 A three-dimensional schematic diagram of a gate contact structure provided in accordance with an embodiment of the present application in contact with a metal gate via a groove.

[0038] Figure 19 A schematic diagram of forming an air gap is provided for one embodiment of the present application.

[0039] Figure 20 A schematic diagram of forming a gate contact structure provided for one embodiment of the present application.

[0040] Structural label description 100, substrate; 101, NMOS region; 102, PMOS region; 103, separation region; 110, dielectric layer; 111, dielectric material portion; 112, sidewall portion; 113, NMOS dielectric layer opening; 114, PMOS dielectric layer opening; 120, NMOS gate dielectric layer; 130, NMOS gate etch stop layer; 140, NMOS dummy gate; 150, PMOS gate dielectric layer; 160, PMOS gate etch stop layer; 170, PMOS dummy gate; 180, gate transition trench; 181, NMOS gate transition trench; 182, PMOS gate transition trench; 200 , transition substrate; 210, etch stop layer; 220, first sub-work function layer; 230, photolithography functional layer; 231, bottom anti-reflective coating; 232, photoresist layer; 240, second sub-work function layer; 300, substrate; 301, gate trench; 310, first metal gate material layer; 320, second metal gate material layer; 330, third metal gate material layer; 340, metal gate; 341, groove; 3411, contact portion; 3412, gap portion; 350, filling portion; 360, interlayer dielectric layer; 370, gate contact structure; 371, contact isolation layer; 372, contact metal; 380, air gap. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0042] The drawings provided in the embodiments of the present application are only for schematic illustration of the basic concept of the present application. The drawings only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of its components may also be more complicated.

[0043] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0044] With the advancement of semiconductor technology, the performance of traditional CMOS transistors using polysilicon as the gate material has become difficult to meet the requirements of high-performance integrated circuits due to polysilicon depletion, the boron transfer effect of P-type MOS transistors, and the Fermi pinning effect. To overcome these problems, related technologies can use HKMG instead of polysilicon gates to manufacture CMOS transistors.

[0045] To control the metal work function in the metal gate material, improve carrier mobility in the CMOS transistor channel, enhance CMOS transistor performance, and reduce power consumption, the current mainstream HKMG fabrication process is the gate-last process. After fabricating a CMOS transistor containing HKMG using the existing gate-last process, the gate contact structure can be used to establish an electrical connection between the CMOS transistor and the external circuit, thereby creating a highly integrated CMOS device.

[0046] During testing of these highly integrated CMOS devices, researchers discovered that some performance indicators of CMOS transistors had improved to a certain extent, such as enhanced threshold voltage control, reduced leakage current, and faster operating frequency. However, some performance indicators of CMOS transistors had declined, such as reduced maximum output current, increased energy loss, increased signal transmission delay, and reduced reliability.

[0047] The researchers used a variety of technical means to conduct further tests on highly integrated CMOS devices and found that the contact resistance between HKMG and the gate contact structure was large, which could lead to an increase in the on-resistance of the transistor, increased energy loss in the contact area, and the formation of hot spots under operating conditions, causing the above-mentioned performance indicators to decline.

[0048] Further investigation into the reason for the high contact resistance between the HKMG and the gate contact structure reveals that, according to the existing gate-last process, after the HKMG is formed, an interlayer dielectric (ILD) layer is formed on the HKMG. This interlayer dielectric layer is then dry-etched to form a dielectric layer opening corresponding to the HKMG. The gate contact structure contacts the HKMG through this dielectric layer opening. Specifically, the material of the interlayer dielectric layer is usually an oxide, and the etching gas commonly used for dry etching of this interlayer dielectric layer is a gas containing carbon (C) and fluorine (F), such as carbon tetrafluoride (CF4) and hexafluoroethane (C2F6). However, these gases cannot etch the HKMG, so only the bottom surface of the gate contact structure can contact the HKMG. Please refer to Figure 1 The contact area between HKMG and the gate contact structure is small, resulting in a large contact resistance.

[0049] Therefore, it is necessary to provide a semiconductor structure and a manufacturing method thereof, by forming a groove having a bottom surface and a side surface on the surface of the metal gate included in the semiconductor structure, and the gate contact structure is in contact with both the bottom surface and the side surface of the groove to increase the contact area between the gate contact structure and the metal gate, thereby reducing the contact resistance between the gate contact structure and the metal gate and improving the performance of the CMOS device including the semiconductor structure.

[0050] See also Figure 2 One embodiment of the present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure may include steps S110, S120, and S130.

[0051] S110: providing a substrate.

[0052] See also Figure 3 In this embodiment, providing the substrate may include steps S111, S112, S113, S114, S115, and S116.

[0053] S111: providing a substrate.

[0054] See also Figure 4 . In this embodiment, the substrate 100 can serve as the basis for the formation of CMOS transistors. Specifically, the substrate 100 may include a base wafer. The substrate may be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, the substrate may be made of silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), and the like. The substrate may be a single-layer structure or a multi-layer structure. In this embodiment, a silicon wafer is used as the substrate, taking into account factors such as dielectric loss requirements, manufacturing process, and manufacturing cost.

[0055] In this embodiment, the substrate 100 may include an NMOS region 101 and a PMOS region 102. Specifically, an N-well (NW) and a P-well (PW) may be first defined in the substrate. After the N-well and P-well are formed, the location of the active area (AA) may be defined, and an isolation region 103 may be formed in the substrate. For example, the isolation region 103 may be a shallow trench isolation (STI) structure used to reduce leakage. Subsequently, different types of dopant ions may be implanted into various regions of the substrate to form lightly doped source and drain regions (LDD), pocket doped regions (Pocket), and source and drain regions (S / D) in the substrate, resulting in the substrate 100 including the NMOS region 101 and the PMOS region 102. The NMOS region 101 corresponds to the N-well, and the PMOS region 102 corresponds to the P-well.

[0056] S112: forming a dielectric layer on the substrate.

[0057] In this embodiment, the dielectric layer 110 may include a dielectric material portion 111 and a spacer portion 112. Specifically, a layer of insulating oxide may be deposited on the substrate 100 to form a dielectric material layer. The dielectric material layer is then etched to form two dielectric material layer openings corresponding to the NMOS region 101 and the PMOS region 102, respectively. The dielectric material layer remaining after etching constitutes the dielectric material portion 111. Subsequently, a gate oxide (GOX) layer and a gate spacer may be formed in the two dielectric material layer openings, respectively, to form the spacer portion 112.

[0058] Since there are multiple planarization processes in the subsequent process flow, each planarization process may produce a depression (Dish) on the surface of the structure. In order to reduce the negative impact of residual impurities in the depression on the performance of the CMOS transistor, each planarization process requires a certain degree of over-processing. However, over-processing may cause the height of the metal gate to be reduced. In addition, since it is necessary to prepare a metal gate with a groove on the surface, the height of the metal gate below the groove is also lower than that of the metal gate at other positions. The height of the metal gate has an important influence on the control ability of the metal gate over the channel current. The reduction in the height of the metal gate will lead to a weakening of the control ability of the metal gate over the channel current, which in turn leads to a decrease in the performance of the CMOS transistor. Therefore, in order to solve the above problem, the height of the metal gate after the planarization process is increased, and redundancy for over-processing and forming grooves on the surface of the metal gate can be reserved during the preparation of the dielectric layer 110.

[0059] In this embodiment, the distance between the surface of the dielectric layer 110 away from the substrate 100 and the substrate 100 is not less than a specified value. Specifically, the specified value may be the sum of the gate base height value and the groove depth value. The gate base height and the groove depth may be determined by device design parameters. For example, if the gate base height value is 500Å and the groove depth value is 200Å, the specified value may be 700Å.

[0060] S113: etching the dielectric layer to form an NMOS dielectric layer opening and a PMOS dielectric layer opening in the dielectric layer corresponding to the NMOS region and the PMOS region.

[0061] See also Figure 5 . In order to achieve the subsequent preparation of a high-k gate dielectric layer and a polysilicon dummy gate, in this embodiment, a portion of the gate oxide in the sidewall portion 112 of the dielectric layer 110 can be etched to form an NMOS dielectric layer opening 113 corresponding to the NMOS region 101 and a PMOS dielectric layer opening 114 corresponding to the PMOS region 102 in the dielectric layer 110. Specifically, for process nodes of 40nm and below, the opening width D1 of the NMOS dielectric layer opening 113 and the opening width D2 of the PMOS dielectric layer opening 114 can both fall within the range of 38nm~42nm. D1 and D2 can be equal, for example, D1 and D2 can both be 38nm, 39nm, 40nm, 41nm, and 42nm.

[0062] S114: forming an NMOS gate dielectric layer and an NMOS dummy gate in the NMOS dielectric layer opening, and forming a PMOS gate dielectric layer and a PMOS dummy gate in the PMOS dielectric layer opening.

[0063] See also Figure 6 In this embodiment, an NMOS gate dielectric layer 120, an NMOS gate etch stop layer 130, and an NMOS dummy gate 140 may be sequentially deposited in the NMOS dielectric layer opening 113, and a PMOS gate dielectric layer 150, a PMOS gate etch stop layer 160, and a PMOS dummy gate 170 may be sequentially deposited in the PMOS dielectric layer opening 114. Specifically, the materials of the NMOS gate dielectric layer 120 and the PMOS gate dielectric layer 150 may both be high dielectric constant materials, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), aluminum oxide (Al2O3), etc. The materials of the NMOS gate etch stop layer 130 and the PMOS gate etch stop layer 160 may be titanium nitride (TiN). The materials of the NMOS dummy gate 140 and the PMOS dummy gate 170 may be polysilicon.

[0064] To further improve the performance of CMOS transistors, in this embodiment, after the NMOS dummy gate 140 and the PMOS dummy gate 170 are formed, processes such as stress memorization technique (SMT), self-aligned bilayer (SAB), metal epitaxy, metal silicide formation, and sigma trench formation may be further performed.

[0065] In this embodiment, after the above steps are completed, a chemical mechanical polishing (CMP) process may be used to perform a planarization process so that the distance between the surface of the NMOS dummy gate 140 and the PMOS dummy gate 170 away from the substrate 100 and the substrate 100 can be equal to the distance between the surface of the dielectric layer 110 away from the substrate 100 and the substrate 100.

[0066] S115: removing the NMOS dummy gate and the PMOS dummy gate to obtain a transition substrate having a gate transition trench.

[0067] See also Figure 7 To achieve the formation of the metal gate, in this embodiment, dry etching superimposed on wet etching can be used to remove the NMOS dummy gate and the PMOS dummy gate, so that the NMOS gate etch stop layer 130 is exposed in the NMOS gate transition trench 181, and the PMOS gate etch stop layer 160 is exposed in the PMOS gate transition trench 182. Specifically, the dry etching gas can be chlorine (Cl2), which has an etching selectivity ratio of 1:0 for polysilicon and silicon nitride and silicon oxide. That is, during the dry etching process using chlorine gas, only polysilicon is removed without removing silicon nitride and silicon oxide.

[0068] S116: forming an etch stop layer and a metal work function layer in sequence on the surface of the transition substrate to obtain a substrate having a gate trench.

[0069] See also Figures 8 to 11 . In order to optimize the threshold voltage of the CMOS transistor, the materials and structures of the metal work function layer of the NMOS transistor and the metal work function layer of the PMOS transistor can be different. Specifically, the metal work function layer of the NMOS transistor is usually a single-layer structure formed by titanium aluminum nitride (TiAlN), while the metal work function layer of the PMOS transistor is usually a double-layer structure formed by titanium nitride and titanium aluminum nitride. Therefore, in this embodiment, the etching stop layer 210 and the first sub-work function layer 220 can be deposited in sequence on the surface of the transition substrate 200, and then the first sub-work function layer 220 of the NMOS region 101 is removed, and then the second sub-work function layer 240 is deposited to obtain a substrate 300 with a gate trench 301.

[0070] See also Figure 8 In this embodiment, a PVD (Physical Vapor Deposition) process can be used to deposit an etch stop layer 210 on the surface of the transition substrate. The material of the etch stop layer 210 can be tantalum nitride (TaN). The etch stop layer 210 can be used as an etch stop layer for the first sub-work function layer 220 and reduce metal penetration. Subsequently, the first sub-work function layer 220 can be deposited on the surface of the etch stop layer 210 using a PVD process. The material of the first sub-work function layer 220 can be titanium nitride.

[0071] See also Figure 9 and Figure 10 . In order to remove the first sub-work function layer 220 of the NMOS region 101, in the present embodiment, a photolithography functional layer 230 may be deposited on the surface of the first sub-work function layer 220. The photolithography functional layer 230 includes a bottom anti-reflective coating layer 231 formed on the surface of the first sub-work function layer 220 and a photoresist layer 232 formed on the surface of the bottom anti-reflective coating layer 231. Subsequently, the photoresist layer 232 and the bottom anti-reflective coating layer 231 of the NMOS region 101 may be removed by exposure and development, and the first sub-work function layer 220 of the NMOS region 101 may be removed by etching, so that the etch stop layer 210 of the NMOS region 101 is exposed. Next, the photolithography functional layer 230 of the PMOS region 102 may be removed by a similar process, so that the first sub-work function layer 220 of the PMOS region 102 is exposed.

[0072] See also Figure 11 . In order to form the metal work function layer of the PMOS transistor, in this embodiment, the second sub-work function layer 240 can be deposited by a PVD process to obtain a substrate 300 having a gate trench 301. Specifically, the material of the second sub-work function layer 240 can be titanium aluminum nitride. It is worth noting that the thickness direction of the second sub-work function layer 240 can be the growth direction of the second sub-work function layer 240. Since the second sub-work function layer 240 corresponding to the NMOS region 101 and the second sub-work function layer 240 corresponding to the PMOS region 102 are formed in the same process, in the actual production process, the thickness of the second sub-work function layer 240 corresponding to the NMOS region 101 along the thickness direction is greater than the thickness of the second sub-work function layer 240 corresponding to the PMOS region 102 along the thickness direction.

[0073] In this embodiment, the gate trench 301 has a bottom surface and a side surface. The normal direction of the bottom surface of the gate trench 301 is a first direction, and the normal direction of the side surface of the gate trench 301 is a second direction.

[0074] S120: depositing a metal gate material on the substrate to form a metal gate having a groove on the surface in the gate trench.

[0075] In the related art, it is also possible to change the etching gas or the etching process to prepare grooves on the surface of the metal gate. For example, when the material of the metal gate is aluminum (Al), a gas containing a Group VII element, such as chlorine, can be used as an etching gas to dry-etch the metal gate to prepare grooves. However, this type of etching gas may introduce impurity elements, resulting in a decrease in the performance of the CMOS transistor. A special dry etching process can also be used to dry-etch the metal gate to prepare grooves. However, the special process needs to be completed in a specific etching chamber, and the process cost is relatively high. Therefore, in order to avoid increasing the process cost or introducing impurities, a deposition process can be used to control the deposition amount of the metal gate material in different directions to form a metal gate with a groove on the surface in the gate trench 301 of the substrate 300.

[0076] See also Figure 11 and Figure 12 In this embodiment, forming a metal gate having a groove on its surface in a gate trench may include steps S121, S122, and S123.

[0077] S121: depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench.

[0078] In this embodiment, the metal gate material may be aluminum. In some embodiments, the metal gate material may also be platinum (Pt), ruthenium (Ru), molybdenum (Mo), etc. This specification does not impose any specific restrictions on the metal gate material.

[0079] In this embodiment, the shape of the metal gate material layer can match the shape of the surface of the substrate 300 and the shape of the gate trench 301. Specifically, the metal gate material layer can include a flat portion formed on the surface of the substrate 300, a trench bottom formed on the bottom surface of the gate trench 301, and a trench side portion formed on the side of the gate trench 301. The metal gate trench is formed between the flat portion, the trench bottom, and the trench side portion.

[0080] In this embodiment, the deposition amount of the metal gate material along the first direction is greater than the deposition amount along the second direction.

[0081] See also Figure 13. In order to improve the ability to control the shape of the metal gate material layer, in this embodiment, the metal gate material layer can be formed by two depositions. Specifically, the step of depositing the metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench can include: performing a first deposition to obtain a first metal gate material layer 310 formed on the surface of the substrate and the bottom and side surfaces of the gate trench; performing a second deposition to obtain a second metal gate material layer 320 formed on the surface of the first flat portion and the surface of the bottom of the first trench.

[0082] In this embodiment, during the first deposition process, the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction can be 1:1, that is, during the first deposition process, the deposition rate of the metal gate material along the first direction is equal to the deposition rate of the metal gate material along the second direction.

[0083] Accordingly, in this embodiment, the shape of the first metal gate material layer 310 can match the shape of the substrate surface and the shape of the gate trench. Specifically, the first metal gate material layer 310 may include a first flat portion formed on the substrate surface, a first trench bottom formed on the bottom surface of the gate trench, and a first trench side portion formed on the side of the gate trench. In the first metal gate material layer 310, the thickness of the first flat portion and the first trench bottom along the first direction is equal to the thickness of the first trench side portion along the second direction. The thickness of the first flat portion and the first trench bottom along the first direction and the thickness of the first trench side portion along the second direction can both fall within the range of 10Å to 20Å. For example, the thickness of the first flat portion and the first trench bottom along the first direction and the thickness of the first trench side portion along the second direction can be 10Å, 12Å, 15Å, 18Å, or 20Å.

[0084] In this embodiment, during the second deposition process, the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction may fall within a range of 495:0 to 505:0. For example, the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction may be 495:0, 497:0, 500:0, 502:0, or 505:0. That is, during the second deposition process, the metal gate material is deposited only along the first direction, and no metal gate material is deposited along the second direction.

[0085] Accordingly, in this embodiment, the second metal gate material layer 320 may include a second flat portion formed on the surface of the first flat portion and a second trench bottom formed at the bottom of the first trench. In the second metal gate material layer 320, the thickness of the second flat portion along the first direction is equal to the thickness of the second trench bottom along the first direction. Specifically, the thickness of the second flat portion along the first direction and the thickness of the second trench bottom along the first direction may fall within the range of 495Å to 505Å. For example, the thickness of the second flat portion along the first direction and the thickness of the second trench bottom along the first direction may be 495Å, 497Å, 500Å, 502Å, or 505Å.

[0086] In the case where the metal gate material layer is formed by two depositions, the metal gate trench may be formed between the second flat portion, the second trench bottom, and the first trench side.

[0087] See also Figure 14 To simplify process parameters, reduce process difficulty, and lower process costs, in some embodiments, the metal gate material layer can be formed by a single deposition. Specifically, the step of depositing the metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench can include: performing a third deposition to obtain a third metal gate material layer 330 formed on the surface of the substrate and the bottom and side surfaces of the gate trench.

[0088] In this embodiment, during the third deposition process, the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction may fall within a range of 24:1 to 26:1. For example, the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction may be 24:1, 25:1, or 26:1. That is, during the third deposition process, the deposition rate of the metal gate material along the first direction is greater than the deposition rate of the metal gate material along the second direction.

[0089] In this embodiment, the shape of the third metal gate material layer 330 can match the shape of the substrate surface and the shape of the gate trench. Specifically, the third metal gate material layer 330 may include a third flat portion formed on the substrate surface, a third trench bottom formed on the bottom surface of the gate trench, and a second trench side portion formed on the side of the gate trench. The thickness of the third flat portion and the third trench bottom along the first direction may fall within the range of 495Å to 505Å. The thickness of the second trench side portion along the second direction may fall within the range of 18Å to 22Å. For example, the thickness of the third flat portion and the third trench bottom along the first direction may be 495Å, 497Å, 500Å, 502Å, or 505Å. The thickness of the second trench side portion along the second direction may be 18Å, 19Å, 20Å, 21Å, or 22Å.

[0090] In the case where the metal gate material layer is formed by one deposition, the metal gate trench may be formed between the third flat portion, the third trench bottom, and the second trench side.

[0091] In the embodiment of the present application, the first deposition, the second deposition, and the third deposition can all be implemented using a PVD process, and the deposition rate of the metal gate material along the first direction and the deposition rate along the second direction can be controlled separately.

[0092] S122: Filling the metal gate trench.

[0093] In order to protect the trench bottom and trench sides formed in the gate trench from damage in a subsequent planarization process, the metal gate trench may be filled with a designated material.

[0094] In this embodiment, a filler material can be deposited in the metal gate trench using a chemical vapor deposition (CVD) process or a hot wire assisted rapid plasma (HARP) process. Specifically, the filler material can include a first filler material and a second filler material. The first filler material can be an oxide. The second filler material can be a material that decomposes or shrinks when heated, or can be removed by etching with hydrogen chloride (HCl) gas.

[0095] S123: performing a planarization process to form a metal gate having a groove on the surface and a filling portion in the gate trench.

[0096] See also Figures 15 to 19 In this embodiment, a chemical mechanical polishing process can be used to remove the substrate surface etch stop layer 210 and the portion above it, and endpoint detection (EPD) is used to stop the polishing head on the surface of the dielectric layer 110, retaining the structure formed inside the gate trench.

[0097] In this embodiment, the groove 341 on the surface of the metal gate 340 extends from the surface of the metal gate 340 away from the substrate toward the substrate. The groove 341 has a bottom surface and side surfaces.

[0098] In this embodiment, the filling portion 350 contacts both the bottom surface and the side surface of the groove 341 .

[0099] In this embodiment, the groove 341 may include a contact portion 3411 in contact with the gate contact structure and a gap portion 3412 .

[0100] In order to achieve electrical isolation between the metal gate 340 and other metal connection lines, reduce parasitic effects, and improve the reliability and performance of CMOS devices, in this embodiment, before the step of forming a gate contact structure on the side of the metal gate 340 away from the substrate, the manufacturing method of the semiconductor structure may also include: forming an interlayer dielectric layer 360 on the metal gate 340; removing the interlayer dielectric layer 360 and the filling portion 350 corresponding to the contact portion 3411, so that the interlayer dielectric layer 360 forms a dielectric layer opening corresponding to the contact portion 3411.

[0101] In this embodiment, an interlayer dielectric layer 360, an amorphous carbon layer, a silicon oxynitride layer, an oxide layer, and a photolithography functional layer can be deposited in sequence on the metal gate 340, and the photolithography functional layer can be removed by exposure and development. The oxide layer, silicon oxynitride layer, amorphous carbon layer, interlayer dielectric layer 360 and filling portion 350 corresponding to the contact portion 3411 can be removed in sequence by multi-step etching, and a dielectric layer opening corresponding to the contact portion 3411 can be formed in the interlayer dielectric layer 360.

[0102] In this embodiment, the material of the interlayer dielectric layer 360 may be an insulating oxide. Specifically, the material of the interlayer dielectric layer 360 may be the same as or different from the material of the dielectric material portion 111 in the dielectric layer 110. When the material of the interlayer dielectric layer 360 is different from the material of the dielectric material portion 111, the material of the interlayer dielectric layer 360 may be a porous insulating oxide to reduce parasitic capacitance between metal structures such as the metal gate 340 and metal connecting lines isolated by the interlayer dielectric layer 360.

[0103] In this embodiment, after the dielectric layer opening corresponding to the contact portion 3411 is formed, the gate contact structure can contact the contact portion 3411 through the dielectric layer opening.

[0104] In this embodiment, for the filling portion 350 made of different materials, the processes for removing the interlayer dielectric layer 360 and the filling portion 350 corresponding to the contact portion 3411 are different.

[0105] To shorten the overall processing time of CMOS devices, reduce the number of process steps, and lower process costs, in this embodiment, when the interlayer dielectric layer 360 and the filling portion 350 are made of the same material, removing the interlayer dielectric layer 360 and the filling portion 350 corresponding to the contact portion 3411 to form a dielectric layer opening corresponding to the contact portion 3411 in the interlayer dielectric layer 360 may include: etching away the interlayer dielectric layer 360 and the filling portion 350 corresponding to the contact portion based on specified etching process parameters to form a dielectric layer opening corresponding to the contact portion 3411 in the interlayer dielectric layer 360. Specifically, the interlayer dielectric layer 360 and the filling portion 350 corresponding to the contact portion 3411 may be removed in the same process step. It is worth noting that in this case, the interlayer dielectric layer 360 and the filling portion 350 corresponding to the gap portion 3412 are not removed. The specified etching process parameters may be etching parameters used in related art for removing the interlayer dielectric layer 360 and are not further described here.

[0106] When the interlayer dielectric layer 360 and the filling portion 350 are made of different materials, the step of removing portions of the interlayer dielectric layer 360 and the filling portion 350 to form a dielectric layer opening in the interlayer dielectric layer 360 corresponding to the contact portion 3411 may include: etching and removing portions of the interlayer dielectric layer 360 based on specified etching process parameters; removing the filling portion 350 to form a dielectric layer opening in the interlayer dielectric layer 360 corresponding to the contact portion 3411, and forming an air gap 380 between the gap portion 3412 and the interlayer dielectric layer 360. It is noteworthy that in this case, the interlayer dielectric layer 360 corresponding to the gap portion 3412 is not removed, while the filling portion 350 corresponding to the gap portion 3412 is removed.

[0107] In this embodiment, a specific etching gas may be used to perform dry etching to remove the filling portion 350. Specifically, the specific etching gas may be hydrogen chloride.

[0108] In some embodiments, the filling portion 350 may be removed by heating. Specifically, the temperature required for heating may be determined according to the decomposition temperature or shrinkage temperature of the material of the filling portion 350 .

[0109] In this embodiment, the air gap 380 formed between the gap portion 3412 and the interlayer dielectric layer 360 can reduce the parasitic capacitance of the CMOS device, thereby reducing the signal delay caused by the signal network composed of resistors (R) and capacitors (C) in the CMOS device, and improving the performance of the CMOS device.

[0110] S130: forming a gate contact structure on a side of the metal gate away from the substrate.

[0111] See also Figure 20After forming the metal gate 340 with a groove on its surface, a gate contact structure 370 may be formed in the groove on the side of the metal gate 340 away from the substrate, thereby increasing the contact area between the gate contact structure 370 and the metal gate 340 and reducing the contact resistance therebetween.

[0112] In this embodiment, the gate contact structure 370 contacts both the bottom surface and the side surface of the groove 341 .

[0113] In this embodiment, the step of forming a gate contact structure 370 on a side of the metal gate 340 away from the substrate may include: forming a contact isolation layer 371 in the contact portion; and forming a contact metal 372 in the contact metal trench.

[0114] In this embodiment, the material of the contact metal 372 may be tungsten (W).

[0115] In related art, tungsten fluoride (WF6) is typically used to deposit tungsten to form contact metal 372. However, tungsten fluoride is highly oxidizing and may damage metal gate 340 if it comes into direct contact with the metal gate 340. To prevent damage to the metal gate 340 during the formation of contact metal 372, in this embodiment, a contact isolation layer 371 is first formed within the contact portion of the groove to isolate the contact metal 372 from the metal gate 340.

[0116] In this embodiment, the shape of the contact isolation layer 371 matches the shape of the groove. Specifically, the contact isolation layer 371 may include a bottom contact isolation layer and a sidewall contact isolation layer. The bottom contact isolation layer contacts the bottom surface of the contact portion. The sidewall contact isolation layer contacts the side surface of the contact portion. The bottom contact isolation layer and the sidewall contact isolation layer may form a contact metal trench.

[0117] In the related art, materials containing titanium (Ti) elements, such as titanium metal or titanium nitride, are typically used to prepare the contact isolation layer 371. However, titanium metal readily reacts with tungsten fluoride. Direct contact between titanium metal and tungsten fluoride may result in defects in the contact metal 372 or cause the gate contact structure 370 to peel off from the metal gate 340, thereby reducing the production yield of the CMOS device. Titanium nitride has significant stress, and direct contact between titanium nitride and the metal gate 340 may also cause the gate contact structure 370 to peel off from the metal gate 340. Therefore, titanium nitride can be used to isolate the titanium metal from the tungsten fluoride to prevent contact and diffusion between the titanium metal and the tungsten fluoride. Furthermore, titanium metal can be used as a buffer layer between the titanium nitride and the metal gate 340 to enhance the bonding strength between the gate contact structure 370 and the metal gate 340.

[0118] In this embodiment, the contact isolation layer 371 may include a first sub-isolating layer and a second sub-isolating layer. Specifically, the first sub-isolating layer contacts the bottom and side surfaces of the contact portion. The first sub-isolating layer may be made of titanium. The second sub-isolating layer is formed on the surface of the first sub-isolating layer. The second sub-isolating layer may be made of titanium nitride.

[0119] In this embodiment, the contact isolation layer 371 can be formed by using a PVD process.

[0120] In this embodiment, after the contact metal trench is formed, a contact metal 372 may be deposited in the contact metal trench, so that the contact isolation layer 371 may cover the contact metal 372 .

[0121] See also Figures 17 to 20 One embodiment of the present application provides a semiconductor structure, which may include a substrate, a metal gate 340 formed on the substrate, and a gate contact structure 370 formed on a side of the metal gate 340 away from the substrate.

[0122] To increase the contact area between the metal gate 340 and the gate contact structure 370, in this embodiment, the surface of the metal gate 340 may have a groove 341. Specifically, the groove 341 may extend from the surface of the metal gate 340 away from the substrate toward the substrate.

[0123] In order to reduce the contact resistance between the metal gate 340 and the gate contact structure 370 while not affecting the performance of the metal gate 340, in this embodiment, the extension direction of the groove 341 can be used as the depth direction of the groove 341 and the height direction of the metal gate 340. Along the extension direction of the groove 341, the ratio of the depth of the groove 341 to the height of the metal gate 340 can fall within the range of 1:4 to 2:5. Specifically, the depth of the groove 341 can fall within the range of 190Å to 210Å, and the height of the metal gate 340 can fall within the range of 500Å to 800Å. For example, the depth of the groove 341 can be 190Å, 200Å, or 210Å, and the height of the metal gate 340 can be 500Å, 600Å, 700Å, or 800Å.

[0124] In this embodiment, the groove 341 may have a bottom surface and side surfaces.

[0125] In this embodiment, the recess 341 may include a contact portion 3411 that contacts the gate contact structure 370. Accordingly, the semiconductor structure may further include an interlayer dielectric layer 360 formed on the metal gate 340. Specifically, the interlayer dielectric layer 360 has a dielectric layer opening corresponding to the contact portion 3411. The gate contact structure 370 may contact the contact portion 3411 through the dielectric layer opening.

[0126] To reduce signal delay caused by a signal network composed of resistors (R) and capacitors (C) in a CMOS device and improve the performance of the CMOS device, in some embodiments, the groove 341 may further include a gap portion 3412. An air gap 380 may be formed between the gap portion 3412 and the interlayer dielectric layer 360.

[0127] In this embodiment, the gate contact structure 370 may contact both the bottom and side surfaces of the groove 341. Specifically, the gate contact structure 370 may include a contact isolation layer 371 and a contact metal 372. The contact isolation layer 371 contacts both the bottom and side surfaces of the groove 341. The contact isolation layer 371 may include a first sub-isolating layer and a second sub-isolating layer. The first sub-isolating layer contacts both the bottom and side surfaces of the groove 341. The material of the first sub-isolating layer may be titanium. The second sub-isolating layer may be formed on the first sub-isolating layer. The material of the second sub-isolating layer may be titanium nitride.

[0128] In this embodiment, the contact isolation layer 371 may cover the contact metal 372 .

[0129] In an embodiment of the present application, a metal gate is prepared by depositing a metal gate material on a substrate having a gate trench, wherein the gate trench has a bottom surface and a side surface, the normal direction of the bottom surface of the gate trench is a first direction, and the normal direction of the side surface of the gate trench is a second direction. During the deposition of the metal gate material, the deposition amount of the metal gate material along the first direction is controlled to be greater than the deposition amount along the second direction, so that the surface of the metal gate obtained by the deposition process has a groove, and the groove also has a bottom surface and a side surface. Then, a gate contact structure is prepared on the side of the metal gate away from the substrate, so that the gate contact structure is in contact with both the bottom surface and the side surface of the groove. The unexpected effects achieved include: since the contact surface between the gate contact structure and the metal gate is increased from the bottom surface of the gate contact structure to the bottom surface and the side surface of the groove on the surface of the metal gate, the contact area between the gate contact structure and the metal gate is increased, the contact resistance between the gate contact structure and the metal gate is reduced, the performance of the CMOS transistor including the metal gate is improved, and the overall performance of the CMOS device manufactured based on the CMOS transistor is improved.

[0130] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of this application.

[0131] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0132] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0133] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art in the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms of "a", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0134] In the several embodiments provided in this application, it should be understood that the disclosed semiconductor structure and CMOS device can be implemented in other ways. For example, the embodiments of the semiconductor structure and CMOS device described above are merely illustrative.

[0135] The above descriptions are merely specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A metal gate is formed on the substrate; wherein the surface of the metal gate has a groove; the groove extends from the surface of the metal gate away from the substrate to the direction close to the substrate; the groove has a bottom surface and a side surface; A gate contact structure is formed on a side of the metal gate away from the substrate; wherein the gate contact structure is in contact with both the bottom surface and the side surface of the groove.

2. The semiconductor structure according to claim 1, characterized in that: The extending direction of the groove is the direction of the depth of the groove and the height of the metal gate; along the extending direction of the groove, the ratio of the depth of the groove to the height of the metal gate falls within the range of 1:4 to 2:

5.

3. The semiconductor structure according to claim 1, characterized in that: The groove includes a gap portion and a contact portion in contact with the gate contact structure; the semiconductor structure further includes: An interlayer dielectric layer is formed on the metal gate; wherein the interlayer dielectric layer has a dielectric layer opening corresponding to the contact portion; the gate contact structure contacts the contact portion through the dielectric layer opening; and an air gap is formed between the gap portion and the interlayer dielectric layer.

4. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: A substrate is provided; wherein the substrate has a gate trench; the gate trench has a bottom surface and a side surface; the normal direction of the bottom surface of the gate trench is a first direction; the normal direction of the side surface of the gate trench is a second direction; Depositing a metal gate material on the substrate to form a metal gate having a groove on the surface in the gate trench; wherein the deposition amount of the metal gate material along the first direction is greater than the deposition amount along the second direction; the groove extends along the surface of the metal gate away from the substrate toward the direction close to the substrate; the groove has a bottom surface and a side surface; A gate contact structure is formed on a side of the metal gate away from the substrate; wherein the gate contact structure is in contact with both the bottom surface and the side surface of the groove.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The groove has a groove depth along the extending direction of the groove; the step of providing a substrate comprises: Providing a substrate; wherein the substrate includes an NMOS region and a PMOS region; Forming a dielectric layer on the substrate; wherein the distance between the surface of the dielectric layer away from the substrate and the substrate is not less than a specified value; the specified value is the sum of the gate base height value and the groove depth value; Etching the dielectric layer to form an NMOS dielectric layer opening and a PMOS dielectric layer opening in the dielectric layer corresponding to the NMOS region and the PMOS region; An NMOS gate dielectric layer and an NMOS dummy gate are formed in the NMOS dielectric layer opening, and a PMOS gate dielectric layer and a PMOS dummy gate are formed in the PMOS dielectric layer opening; wherein the distance between the surface of the NMOS dummy gate and the PMOS dummy gate away from the substrate and the substrate is equal to the distance between the surface of the dielectric layer away from the substrate and the substrate; Removing the NMOS pseudo gate and the PMOS pseudo gate to obtain a transition substrate having a gate transition groove; An etching stop layer and a metal work function layer are sequentially formed on the surface of the transition substrate to obtain the substrate having the gate trench.

6. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The step of depositing a metal gate material on the substrate to form a metal gate having a groove on the surface in the gate trench comprises: Depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench; wherein the metal gate material layer includes a flat portion formed on the surface of the substrate, a trench bottom formed on the bottom surface of the gate trench, and a trench side portion formed on the side surface of the gate trench; a metal gate trench is formed between the flat portion, the trench bottom, and the trench side portion; filling the metal gate trench; A planarization process is performed to form a metal gate having a groove on the surface and a filling portion in the gate trench; wherein the filling portion is in contact with both the bottom surface and the side surface of the groove.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The step of depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench comprises: Performing a first deposition to obtain a first metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench; wherein the first metal gate material layer includes a first flat portion formed on the surface of the substrate, a first trench bottom formed on the bottom surface of the gate trench, and a first trench side portion formed on the side surface of the gate trench; the thickness of the first flat portion and the first trench bottom along the first direction is equal to the thickness of the first trench side portion along the second direction; A second deposition is performed to obtain a second metal gate material layer formed on the surface of the first flat portion and on the surface of the bottom of the first groove; wherein the second metal gate material layer includes a second flat portion formed on the surface of the first flat portion and a second groove bottom formed at the bottom of the first groove; the thickness of the second flat portion along the first direction is equal to the thickness of the second groove bottom along the first direction; the metal gate groove is formed between the second flat portion, the second groove bottom and the side of the first groove.

8. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The step of depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench comprises: A third deposition is performed to obtain a third metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate groove; wherein the third metal gate material layer includes a third flat portion formed on the surface of the substrate, a third groove bottom formed on the bottom surface of the gate groove, and a second groove side portion formed on the side surface of the gate groove; the thickness of the third flat portion along the first direction is equal to the thickness of the third groove bottom along the first direction; the thickness of the third flat portion along the first direction is greater than the thickness of the second groove side portion along the second direction; the metal gate groove is formed between the third flat portion, the third groove bottom and the second groove side portion; during the third deposition process, the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction falls within the range of 24:1 to 26:

1.

9. The method for manufacturing a semiconductor structure according to any one of claims 6 to 8, characterized in that: The groove includes a contact portion in contact with the gate contact structure; Before the step of forming a gate contact structure on a side of the metal gate away from the substrate, the method for manufacturing the semiconductor structure further comprises: forming an interlayer dielectric layer on the metal gate; The interlayer dielectric layer and the filling portion corresponding to the contact portion are removed, so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion; and the gate contact structure contacts the contact portion through the dielectric layer opening.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: In a case where the interlayer dielectric layer and the filling portion are made of the same material, the step of removing the interlayer dielectric layer and the filling portion corresponding to the contact portion so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion comprises: The interlayer dielectric layer and the filling portion corresponding to the contact portion are etched away based on specified etching process parameters, so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion; wherein the interlayer dielectric layer and the filling portion corresponding to the contact portion are removed in the same process step.

11. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The groove further includes a gap portion; when the interlayer dielectric layer and the filling portion are made of different materials, the step of removing the interlayer dielectric layer and the filling portion corresponding to the contact portion so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion comprises: Etching and removing the interlayer dielectric layer corresponding to the contact portion based on specified etching process parameters; The filling portion is removed, so that a dielectric layer opening corresponding to the contact portion is formed in the interlayer dielectric layer, and an air gap is formed between the gap portion and the interlayer dielectric layer.

12. A CMOS device, characterized in that: The CMOS device comprises the semiconductor structure according to any one of claims 1 to 3 or a semiconductor structure manufactured according to the method for manufacturing the semiconductor structure according to any one of claims 4 to 11.

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