Formation of isolation regions with low parasitic capacitance

Abstract

The invention relates to forming isolation regions with low parasitic capacitance. A method includes forming a gate stack, and etching the gate stack to form a trench penetrating the gate stack. A dielectric isolation region under the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench. The method includes performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first and second portions of the gate stack, and performing a second deposition process to form a second dielectric layer on the first dielectric layer. A second dielectric layer fills the trench. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant greater than the first dielectric constant.

Description

Technical Field

[0001] The present disclosure relates to forming isolation regions with low parasitic capacitance. Background Art

[0002] Technological advances in integrated circuit (IC) materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generations. In the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometry size has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This shrinkage has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. For example, gate all-around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods of manufacturing GAA transistors are being developed.

[0004] The formation of a GAA transistor generally includes forming a long strip (comprising alternating semiconductor materials) and a long gate stack, and then forming an isolation region to cut the long strip and the long gate stack into shorter sections. The shorter sections can be used to form the channel layer and gate stack of the GAA transistor. Summary of the invention

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a gate stack; etching the gate stack to form a trench penetrating the gate stack, wherein a dielectric isolation region below the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench; performing a first deposition process to form a first dielectric layer, the first dielectric layer extending into the trench and lining the sidewalls of the first portion and the second portion of the gate stack, wherein the first dielectric layer has a first dielectric constant; and performing a second deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer fills the trench, and the second dielectric layer has a second dielectric constant greater than the first dielectric constant.

[0006] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a dielectric isolation region over a body portion of a semiconductor substrate, wherein a semiconductor region is adjacent to the dielectric isolation region, and wherein the semiconductor region includes a portion higher than the dielectric isolation region; forming a replacement gate stack over the dielectric isolation region; etching the replacement gate stack to form a first gate stack and a second gate stack; and forming a gate isolation region, wherein the gate isolation region is between the first gate stack and the second gate stack and is in physical contact with the first gate stack and the second gate stack, wherein the gate isolation region extends from a top surface level of the first gate stack to a level lower than a bottom surface level of the first gate stack, and wherein forming the gate isolation region comprises: depositing a first dielectric layer, wherein the first dielectric layer comprises a low-k dielectric material; and depositing a second dielectric layer, wherein the second dielectric layer comprises a high-k dielectric material, wherein the first dielectric layer includes a portion between the second dielectric layer and the first gate stack and in contact with the second dielectric layer and the first gate stack.

[0007] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a first gate all-around (GAA) transistor, comprising a first gate stack; a second GAA transistor, comprising a second gate stack; and a gate isolation region, between the first gate stack and the second gate stack and in contact with the first gate stack and the second gate stack, wherein the gate isolation region comprises: a first dielectric layer, comprising SiOCN, wherein the first dielectric layer is in physical contact with the first gate stack and the second gate stack, and wherein the first dielectric layer has a first dielectric constant; and a second dielectric layer, on the first dielectric layer, wherein the second dielectric layer has a second dielectric constant higher than the first dielectric constant. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood from the following specific implementations. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the sizes of various features may be arbitrarily increased or reduced.

[0009] Figures 1 to 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B as well as Figures 15 to 20 A view of an intermediate stage in forming a gate all around (GAA) transistor is shown in accordance with some embodiments.

[0010] Fig.21 The distribution profile of carbon (and / or nitrogen) according to some embodiments is schematically shown.

[0011] Fig. 22 A process flow for forming a GAA transistor is shown in accordance with some embodiments.

[0012] Fig.23 A process flow for forming a gate isolation region according to some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "beneath," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0015] A gate all around (GAA) transistor, a cut metal gate (CMG) isolation region and a method for forming the same are provided. According to some embodiments of the present disclosure, the CMG isolation region includes a first layer formed of a lower k dielectric layer and a higher k dielectric layer on the lower k dielectric layer. The lower k dielectric layer can be formed of a low k dielectric material having a dielectric constant (k value) lower than that of silicon oxide. The formation of the CMG isolation can be performed by selecting appropriate precursors and adjusting RF parameters.

[0016] In the illustrated embodiment, the formation of a GAA transistor is used as an example to explain the concepts of the present disclosure. Other types of transistors (e.g., fin field effect transistors (FinFETs), forksheet transistors, complementary field effect transistors (CFETs), etc.) may also employ the concepts of the present disclosure. The purpose of the embodiments discussed herein is to provide examples to enable the subject matter of the present disclosure to be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0017] Figures 1 to 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B as well as Figures 15 to 20 FIG. 1 shows a view of an intermediate stage when forming a GAA transistor according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in FIG. Fig. 22 The process flow is shown.

[0018] refer to Figure 1, showing a perspective view of a wafer 10. The wafer 10 includes a multilayer structure including a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., while other substrates and / or structures may be used, such as semiconductor on insulator (SOI), strained SOI, silicon germanium on insulator, etc. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0019] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding processes are Fig. 22 The process flow 200 shown in FIG. 2 is shown as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0020] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes the following: SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed at about Peace However, any suitable thickness may be used while remaining within the scope of the embodiments.

[0021] Once the first layer 22A has been deposited on the substrate 20, the second layer 22B is deposited on the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GasB, InAlAs, InGaAs, GasB, GaAsSB, a combination of the foregoing, etc., and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments, where the first layer 22A is silicon germanium, the second layer 22B may be formed of silicon, and vice versa. It should be understood that any suitable combination of materials may be used for the first layer 22A and the second layer 22B.

[0022] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, for example, the second layer 22A has a thickness in a range between about 4 nm and 7 nm, while the second layer 22B has a thickness in a range between about 8 nm and 12 nm.

[0023] Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired topmost layer of the multilayer stack 22 has been formed. According to some embodiments, the first layer 22A has the same or similar thickness as each other, and the second layer 22B has the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

[0024] According to some embodiments, there may be some pad oxide layer(s) and hard mask layer(s) (not shown) formed on top of the multilayer stack 22 . These layers are patterned and used for subsequent patterning of the multilayer stack 22 .

[0025] refer to Figure 2 , the multilayer stack 22 and a portion of the underlying substrate 20 are patterned in (one or more) etching processes so that the trench 23 is formed. The corresponding process is Fig. 22 20 is shown as process 204 in the process flow 200 shown in FIG. 20. The trench 23 extends into the substrate 20. The remaining portion of the multilayer stack is referred to as the multilayer stack 22' below. Some portions of the substrate 20 are left below the multilayer stack 22' and are referred to as substrate strips 20' below. The multilayer stack 22' includes a semiconductor layer 22A and a semiconductor layer 22B. The semiconductor layer 22A is alternatively referred to as a sacrificial layer, and the semiconductor layer 22B is alternatively referred to as a nanostructure below. The multilayer stack 22' and the portions of the substrate strip 20' below are collectively referred to as semiconductor strips 24.

[0026] In the above embodiments, the GAA transistor structures can be patterned by any suitable method. For example, these structures can be patterned using one or more photolithography processes (including double patterning processes or multi-patterning processes). Typically, the double patterning process or the multi-patterning process combines the photolithography process with the self-alignment process, thereby allowing the created pattern to have a spacing that is, for example, smaller than the spacing that can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0027] Figure 3 The formation of the isolation region 26 is shown, which is also referred to as the shallow trench isolation (STI) region throughout the specification. Fig. 22 200 is shown as process 206. The STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI region 26 may also include a dielectric material on top of the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPVCD, etc. A planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) may then be performed to level the top surface of the dielectric material, and the remaining portion of the dielectric material is the STI region 26.

[0028] The STI region 26 is then recessed so that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top of the multilayer stack 22' and the substrate strip 20'. The recessing of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. During the etching process, plasma can be generated. Argon gas can also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 26 is performed by a wet etching process. For example, the etching chemical can include HF.

[0029] refer to Figure 4 , dummy gate stack 30 and gate spacer 38 are formed on the top surface and sidewalls of (protruding) fin 28. The corresponding process is Fig. 22200 is shown as process 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, the dummy gate electrode 34 may be formed using polysilicon or amorphous silicon, and other materials such as amorphous carbon may also be used.

[0030] Each dummy gate stack 30 may further include one (or more) hard mask layers 36 on the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride or a multilayer thereof. The dummy gate stack 30 may span over a single or multiple protruding fins 28 and the STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a length direction perpendicular to the length direction of the protruding fins 28. The formation of the dummy gate stack 30 includes: forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layer by (one or more) patterning processes.

[0031] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material (e.g., silicon nitride (SiN), silicon monoxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc.), and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include: depositing one or more dielectric layers, and then performing (one or more) anisotropic etching processes on (one or more) dielectric layers. The remaining portion of (one or more) dielectric layers is the gate spacer 38.

[0032] According to an alternative embodiment, one or more layers of gate spacers 38 may be formed using Fig.19 The process shown in FIG. 1 is used to form the gate spacer 38, and the resulting gate spacer 38 layer includes the gate spacer 38 shown in FIG. Figures 19 to 21 Materials discussed. For example, the gate spacer 38 may be formed of or include SiOCNH. Details of the formation process are discussed in subsequent paragraphs.

[0033] Figure 5A and Figure 5B Shows Figure 4 A cross-sectional view of the structure shown. Figure 5A Shows Figure 4The reference cross section A1-A1 in FIG. 1 cuts through the portion of the protruding fin 28 that is not covered by the gate stack 30 and the gate spacer 38 and is perpendicular to the gate length direction. The fin spacer 38 on the sidewall of the protruding fin 28 is also shown. Figure 5B Shows Figure 4 , which is parallel to the longitudinal direction of the protruding fin 28 .

[0034] refer to Fig. 6A and Figure 6B , the portion of the protruding fin 28 that is not directly below the dummy gate stack 30 and the gate spacer 38 is recessed by an etching process to form a recess 42. The corresponding process is Fig. 22 2 is shown as process 210 in the process flow 200 shown in FIG. For example, the dry etching process can be performed using C2F6, CF4, SO2, a mixture of HBr, Cl2 and O2, a mixture of HBr, Cl2, O2 and CH2F2, etc. to etch the multilayer semiconductor stack 22' and the substrate strip 20' below. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or can be lower than the bottom of the multilayer semiconductor stack 22' (e.g., Figure 6B The etching may be anisotropic so that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in FIG. Figure 6B shown.

[0035] refer to Fig. 7A and Figure 7B , the sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which is recessed from the edges of the respective upper and lower nanostructures 22B. Fig. 22 200 is shown as process 212. The lateral recessing of the sacrificial semiconductor layer 22A can be achieved by a wet etching process using an etchant that is selective to the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) rather than the material of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, the wet etching process can be performed using an etchant such as hydrochloric acid (HCl). The wet etching process can be performed using an immersion process, a spray process, etc.

[0036] According to alternative embodiments, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process, or a combination of a dry etching process and a wet etching process.

[0037] refer to Fig. 8A and Figure 8B , forming the internal spacer 44. The corresponding process is Fig. 22The process flow 200 shown in FIG. 2 is shown as process 214. According to some embodiments, the formation of the inner spacer 44 includes depositing a conformal dielectric layer that extends into the lateral recess 41 ( Figure 7B Next, an etching process (also referred to as a spacer trimming process) is performed to trim the portion of the spacer layer outside the lateral recess 41, thereby leaving a portion of the spacer layer in the lateral recess 41. The remaining portion of the spacer layer is referred to as an inner spacer 44.

[0038] Fig.9A and Fig. 9B 4 shows a cross-sectional view and a perspective view of forming a source / drain region 48 in the recess 42 by epitaxy. Fig. 22 2 is shown as process 216 in the process flow 200 shown in FIG. (One or more) source / drain regions can be referred to as source or drain individually, or collectively as source and drain, depending on the context. According to some embodiments, source / drain regions 48 can stress nanostructures 22B used as channels for corresponding GAA transistors, thereby improving performance.

[0039] According to some embodiments, the corresponding transistor is n-type, so the epitaxial source / drain region 48 is formed to be n-type by doping with n-type dopants. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown to form the epitaxial source / drain region 48. According to alternative embodiments, the corresponding transistor is p-type, so the epitaxial source / drain region 48 is formed to be p-type by doping with p-type dopants. For example, silicon boron (SiB), silicon germanium boron (SiGeB), etc. can be grown to form the epitaxial source / drain region 48. After filling the recess 42 with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally, and a small facet can be formed. Further growth of the epitaxial region 48 can also cause adjacent epitaxial regions 48 to merge with each other, thereby forming a gap.

[0040] After the epitaxial process, the epitaxial region 48 may be further implanted with p-type impurities or n-type impurities to form source and drain regions, which are also indicated using reference numeral 48. According to an alternative embodiment of the present disclosure, when the epitaxial region 48 is in-situ doped with n-type impurities or p-type impurities during epitaxy and the epitaxial region 48 is also a source / drain region, the implantation process is skipped.

[0041] Fig. 10A and 10B FIG. 4 shows a cross-sectional view of the structure after forming a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. The corresponding process is shown in FIG. Fig. 222 is shown as process 218 in the process flow 200 shown in FIG. CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. ILD 52 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0042] The CESL 50 and the ILD 52 are planarized by a planarization process such as a CMP process or a mechanical polishing process. Fig. 22 The process flow 200 shown in FIG. 2 is shown as process 220. According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, such as Fig. 10A According to alternative embodiments, the planarization process may expose the hard mask 36 and be stopped on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the ILD 52 are flush within process variations.

[0043] Next, the dummy gate electrode 34 and the dummy gate dielectric 32 (and the hard mask 36, if remaining) are removed in one or more etching processes, thereby forming the recess 58, as shown in FIG. Fig.11A and Fig. 11B The corresponding process is Fig. 22 2 is shown as process 222 in the process flow 200 shown in FIG. 2. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by an anisotropic dry etching process. For example, the etching process may be performed using a reactive gas(es) that selectively etches the dummy gate electrode 34 and the dummy gate dielectric 32 at a faster rate than the ILD 52. Each recess 58 exposes and / or overlies a portion of the multilayer stack 22', which includes a future channel region in a subsequently completed transistor.

[0044] The sacrificial layer 22A is then removed to allow the recess 58 to extend between the nanostructures 22B. Fig. 22200 is shown as process 224. Sacrificial layer 22A can be removed by performing an isotropic etching process, for example, a wet etching process using an etchant that is selective to the material of sacrificial layer 22A, while nanostructures 22B, substrate 20, and STI regions 26 remain relatively unetched compared to sacrificial layer 22A. According to some embodiments where sacrificial layer 22A includes, for example, SiGe and nanostructures 22B includes, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to remove sacrificial layer 22A.

[0045] refer to Fig. 12A and Fig. 12B , forming a gate dielectric 62 and a gate electrode 68, thereby forming a replacement gate stack 70. The corresponding process is Fig. 22 200 is shown as process 226. According to some embodiments, each gate dielectric 62 includes an interfacial layer and a high-k dielectric layer on the interfacial layer. The interfacial layer can be formed of or include silicon oxide, which can be deposited by a conformal deposition process such as ALD or CVD, or deposited by an oxidation process. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, (one or more) high-k dielectric layers may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations of the foregoing.

[0046] A gate electrode 68 is also formed. When formed, a conductive layer is first formed on the high-k dielectric layer and fills the remaining portion of the recess 58. The gate electrode 68 may include a metal-containing material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, a combination of the foregoing, and / or multiple layers of the foregoing. For example, the gate electrode 68 may include any number of layers, any number of work function layers, and possible filling materials. The gate dielectric 62 and the gate electrode 68 also fill the space between adjacent nanostructures 22B, and fill the space between the bottom nanostructure 22B and the substrate strip 20' below. After filling the recess 58, a planarization process (e.g., a CMP process or a mechanical grinding process) may be performed to remove the excess portion of the gate dielectric and the gate electrode 68 above the top surface of the ILD 52. The gate electrode 68 and the gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting transistor.

[0047] exist Fig.13A and Fig. 13B In the process shown, a gate isolation region 94 (also referred to as a cut metal gate (CMG) region) is formed to separate (cut) the gate stack 70. Therefore, the gate stack 70 is separated into two parts 70A and 70B that are electrically isolated from each other and are collectively referred to as the gate stack 70. Figures 15 to 20 The details of forming the gate isolation region 94 are discussed in detail. The corresponding process is described in Fig. 22 The process flow 200 shown in FIG. 2 is shown as process 228. The corresponding process is shown in FIG. Fig. 22 The process flow 200 shown in FIG. 2 is shown as process 228 .

[0048] Further references Fig.13A and Fig. 13B , the gate stack 70 is recessed so that recesses (occupied by the gate isolation regions 94) are formed above the gate stack 70 and between opposing portions of the gate spacers 38. A gate mask 74 including one or more layers of a dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each recess, followed by a planarization process to remove excess portions of the dielectric material extending over the ILD 52.

[0049] like Fig.13A and Fig. 13B As further shown, ILD 76 is deposited over ILD 52 and gate mask 74. The corresponding process is Fig. 22 2 is shown as process 230 in the process flow 200 shown in FIG. An etch stop layer (not shown) may or may not be deposited before forming ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, etc. ILD 76 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0050] exist Fig.14A and Fig. 14B In the embodiment, ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form recesses (occupied by contact plugs 80A and 80B) that expose the surface of source / drain regions 48 and / or gate stack 70. The recesses may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). Fig. 14B The contact plug 80A and the contact plug 80B are shown in the same cross-section, but in various embodiments, the contact plug 80A and the contact plug 80B may be formed in different cross-sections to reduce the risk of shorting each other.

[0051] After forming the recess, a silicide region 78 is formed on the epitaxial source / drain region 48. The corresponding process is Fig. 22 The process flow 200 shown in FIG. 2 is shown as process 232. A contact plug 80B is then formed over the silicide region 78. In addition, a contact 80A (also referred to as a gate contact plug) is formed in the recess, over the gate electrode 68 and in contact with the gate electrode 68. The corresponding process is shown in FIG. Fig. 22The process flow 200 shown in FIG. 2 is shown as process 234. Transistor 82 is thereby formed.

[0052] Figures 15 to 20 2 shows the formation of gate isolation region 94 according to some embodiments. Fig.23 The process flow 300 is shown. Fig.15 It shows that Fig. 12A , a cross-sectional view of an intermediate structure is shown in FIG. 5 , in which a gate stack 70 is formed and includes a gate dielectric 62 and a gate electrode 68 .

[0053] According to some embodiments, a hard mask layer 88 is deposited and may include a multi-layer structure including a plurality of layers. Fig.23 The process flow 300 is shown as process 302. According to some embodiments, hard mask layer 88 includes silicon nitride layer 88A, silicon layer 88B, and silicon nitride layer 88C. According to alternative embodiments, a single layer hard mask 88 is used, which may be formed of or include silicon nitride.

[0054] Then, an etching mask 90 is formed, such as Fig.16 The corresponding process is Fig.23 The process flow 300 is shown as process 304. The etching mask 90 may also have a single-layer structure (which may include photoresist) or a double-layer structure including a bottom anti-reflective coating (BARC) and a photoresist. Alternatively, the etching mask 90 may have three layers, which may include a bottom layer, an intermediate layer above the bottom layer, and a top layer, which may be a patterned photoresist. A groove 92 is formed in the etching mask 90.

[0055] Next, the etch mask 90 is used to etch the mask layer 88 so that the trench 92 extends into the hard mask layer 88. The corresponding process is Fig.23 The process flow 300 is shown as process 306. The resulting structure is Fig.17 . According to some embodiments, the etching process includes a main etching process and a subsequent over-etching process. Depending on the material of the mask layer 88, the main etching process can be performed using a process gas selected from CH2F2, CF4, O2, Ar, and a combination of the foregoing items. The over-etching process can be performed using a process gas selected from CH3F, O2, Ar, and a combination of the foregoing items. The etching can be anisotropic. According to some embodiments, the groove 92 extends to the top surface of the hard mask 88A. The etching mask 90 can be removed after the groove 92 is formed in the hard mask layer 88.

[0056] Next, if Fig.17 As shown, the replacement gate stack 70 is etched. The corresponding process is Fig.23The process flow 300 is shown as process 308. The etching of the replacement gate stack 70 is anisotropic. According to some embodiments, the etching is performed until the STI region 26 is exposed. The trench 92 may extend into the STI region 26. After the etching process, the hard mask layer 88 may (or may not) be removed. The trench 92 may have a width in a range between about 10 nm and about 30 nm, and a depth in a range between about 120 nm and about 200 nm. Thus, the gate stack 70 is separated into gate stacks 70A and 70B.

[0057] In the subsequent process, a dielectric layer 94 (including dielectric layer 94A and dielectric layer 94B) is deposited. Fig.18 and Fig.19 The dielectric layer 94 includes some portions extending into the trench 92 to form the isolation region, and some horizontal portions above the gate stack 70 .

[0058] refer to Fig.18 , depositing dielectric layer 94A. The corresponding process is Fig.23 The process flow 300 is shown as process 310. According to some embodiments, dielectric layer 94A includes a silicon-containing dielectric material, which may be denoted as SiC. x O y N z The value x may be less than about 1, the value y may be less than about 2, and the value z may be less than 3, but these values ​​may be outside the above ranges. According to some embodiments, dielectric layer 94A includes SiCON, SiCN, SiON, SiCO, or the like.

[0059] Dielectric layer 94A may have a first dielectric constant (k value) that is relatively low compared to the dielectric constant of subsequently deposited dielectric layer 94B. According to some embodiments, dielectric layer 94A has a k value that is lower than about 4.0, and may be in a range between about 3.0 and about 4.0. Thus, dielectric layer 94A may be a low-k dielectric layer according to some embodiments, having a corresponding k value lower than 3.8 (k value of silicon oxide). Dielectric layer 94A may be porous so that its k value is low.

[0060] According to some embodiments, the precursor for forming dielectric layer 94A may include aminosilane, etc. The deposition method may include ALD, plasma enhanced ALD (PEALD), CVD, plasma enhanced CVD (PECVD), etc. Aminosilane may have a chemical formula of C9H 23 NO3Si. Unlike other used precursors (eg, silane, disilane, dichlorosilane (DCS, SiH2Cl2), etc.), aminosilane includes carbon (and nitrogen), which can aid in the reduction of the resulting dielectric layer 94A.

[0061] Using aminosilane as a precursor can advantageously reduce the k value of the resulting dielectric layer 94A. However, aminosilane may disadvantageously cause the dielectric layer 94A to extend shallowly in the trench 92 and fail to cover the sidewalls of the gate stack 70. According to some embodiments, the deposition of the dielectric layer 94A can be performed while generating plasma. Experimental results show that when N2, NH3, and Ar are used to generate plasma in the embodiments of the present disclosure, the resulting dielectric layer 94A can extend deeper into the trench 92.

[0062] According to some embodiments, the reduction of dielectric layer 94A can also be achieved by adjusting process conditions. For example, the RF power used to generate the plasma can be performed using an on-off cycle, and the on-off cycle can have an on-duration in the range between about 0.1 seconds and about 15 seconds. The flow rate of N2 can be less than about 6 slm. The flow rate of NH3 can be less than about 6 slm. The flow rate of Ar can be less than about 1.5 slm. The wafer temperature can be in the range between about 200°C and about 400°C.

[0063] By using aminosilane, N2, NH3, and Ar as precursors and adjusting the process conditions, the resulting dielectric layer 94A can have a silicon atomic percentage in a range between about 20% and about 50%, an oxygen percentage in a range between about 5% and about 35%, a carbon percentage below about 25%, and a nitrogen atomic percentage below about 50%. The porosity of the dielectric layer 94A can be greater than about 15%, and can be in a range between about 15% and about 45%. The k value of the dielectric layer 94A is thus reduced.

[0064] According to some embodiments, by adjusting the process conditions, dielectric layer 94A has a bottommost end that is higher than the bottom end of trench 92. Therefore, the upper portion of trench 92 has dielectric layer 94A lining the sidewalls of gate stack 70 (and possible STI region 26), while the bottom of trench 92 does not have dielectric layer 94A lining it. Therefore, some surfaces of STI region 26 facing trench 92 may be exposed.

[0065] When dielectric layer 94A partially extends into trench 92, dielectric layer 94A completely covers all exposed sidewalls of gate stacks 70A and 70B, so that dielectric layer 94A with a low k value can be used to reduce parasitic capacitance in the resulting structure, such as parasitic capacitance between adjacent gate stacks 70A and 70B. According to some embodiments, the bottom end of dielectric layer 94A is substantially flush with the interface between STI region 26 and the gate stack 70 above, or slightly below the interface, and thus some portions of the sidewalls of STI region 26 are exposed to trench 92. By adjusting the process conditions, dielectric layer 94A is deposited better on gate stacks 70A and 70B than on STI region 26, and thus the bottom end of dielectric layer 94A can be pointed, such as Fig.18 and Fig.19 shown.

[0066] According to an alternative embodiment, dielectric layer 94A may have a lower portion having a gradually decreasing thickness as it extends deeper into trench 92 due to its lower ability to extend deeper into trench 92. Line 94A-S1 represents a possible sidewall of dielectric layer 94A having a bottom end between the top surface of STI region 26 and the bottom end of trench 92. The lower portion of dielectric layer 94A having sidewall 94A-S1 also has a gradually decreasing thickness as it extends deeper into trench 92. Line 94A-S2 represents an alternative profile of dielectric layer 94A that completely covers all sidewalls of STI region 26 and gate stack 70 that are exposed to trench 92. However, the bottom portion of dielectric layer 94A has a smaller thickness than the corresponding upper portion.

[0067] refer to Fig.19 The dielectric layer 94B is deposited, for example, using ALD, PEALD, CVD, PECVD, etc. The corresponding process is Fig.23 The process flow 300 is shown as process 312. According to some embodiments, dielectric layer 94B has a higher k value and a greater density than dielectric layer 94A. For example, dielectric layer 94B can be a high-k dielectric layer having a k value greater than about 6, and can be greater than about 7. The k value difference (k94B-k94A) can be greater than about 2 or greater than about 4, and can be in a range between about 2 and about 5, with k values ​​k94A and k94B being the k values ​​of dielectric layers 94A and 94B, respectively.

[0068] The dielectric layer 94B may also be formed of or include a silicon-containing dielectric material. According to some embodiments, the dielectric layer 94B may be formed using a silicon-containing precursor (which may not contain carbon and nitrogen). For example, the silicon-containing precursor may include silane, disilane, dichlorosilane, etc., or a combination of the foregoing. By using these precursors, it is easier to fill the resulting dielectric layer 94B to the bottom of the trench 92. According to some embodiments, the dielectric layer 94B may include silicon oxide (SiO2), SiN, etc. The formation may also (or may not) include other precursors containing carbon and / or nitrogen, such as CO2, NO, NO2, N2, NH3, H2, etc., so that the resulting dielectric layer 94B may also include carbon and / or nitrogen. Therefore, the dielectric layer 94B may also include SiN, SiO, SiCON, SiCN, SiON, SiCO, etc., or a combination of the foregoing.

[0069] According to some embodiments, dielectric layers 94A and 94B include different elements, wherein at least one element (e.g., C and / or N) in one of dielectric layers 94A and 94B is not in the other when deposited. According to alternative embodiments, dielectric layers 94A and 94B include the same elements and may or may not have the same composition. Throughout the specification, when two layers are referred to as having the same composition, it means that the two layers have the same elements and the percentages of the corresponding elements in the two layers are the same as each other. Conversely, when two layers are referred to as having different compositions, it means that at least one of the two layers has at least one element that is not in the other layer, or the two layers have the same elements, but the percentages of the elements in the two layers are different from each other.

[0070] According to some embodiments, dielectric layers 94A and 94B have the same elements, but different compositions. For example, dielectric layers 94A and 94B may both include SiOCN, with dielectric layer 94A having a carbon atomic percentage greater than (e.g., two or more times greater than) the carbon atomic percentage in dielectric layer 94B. According to alternative embodiments, dielectric layer 94A includes carbon when deposited, while dielectric layer 94B does not contain carbon when deposited.

[0071] According to some embodiments, dielectric layers 94A and 94B have the same composition, with the same elements and the same (or close, e.g., with a variation of less than 20%) composition. For example, both dielectric layers 94A and 94B may include SiCON. However, the k value k94A of dielectric layer 94A is lower than the k value k94B of dielectric layer 94B. The lower k value k94A may be achieved by using different precursors, different deposition methods, and / or different process conditions, such that the porosity of dielectric layer 94A is greater than the porosity of dielectric layer 94B, even if the compositions of dielectric layers 94A and 94B are the same or close to each other. For example, the porosity P94A of dielectric layer 94A may be in a range between about 20% and about 40%, and the porosity P94B of dielectric layer 94B may be less than about 10% or 5%. The porosity difference (P94A-P94B) may be greater than about 10% or greater than about 20%, and may be in a range between 10% and about 40%.

[0072] According to some embodiments, dielectric layer 94B completely fills the remaining trench 92 not filled by dielectric layer 94A. Therefore, no void is formed in dielectric layer 94B. According to an alternative embodiment, since the thickness of dielectric layer 94A in the upper portion of trench 92 is greater than the thickness of dielectric layer 94A in the deeper portion of trench 92, void 96 is formed. Void 96 is shown with a dotted line, indicating that it may be formed or not. Since dielectric layer 94A may completely cover the sidewalls of gate stack 70 without covering the lower portion, void 96 may be formed deep in trench 92. For example, the top of void 96 may be lower than or flush with the interface between STI region 26 and the gate stacks 70A and 70B above.

[0073] After the dielectric layers 94A and 94B are deposited, a planarization process such as a CMP process or a mechanical grinding process is performed. Fig.23 The process flow 300 is shown as process 314. The planarization process may be stopped on the top surface of the gate stack 70. The remaining portions of the dielectric layers 94A and 94B are collectively referred to as the gate isolation region 94 below. Fig. 20 As shown. Fig. 20 After the process shown, perform Fig.13A , Fig. 13B , Fig.14A and Fig. 14B The remaining processes shown complete the formation of the GAA transistor 82 .

[0074] According to some embodiments, dielectric layer 94A includes carbon, while dielectric layer 94B does not contain carbon, or has a lower atomic percentage of carbon than dielectric layer 94 A. Thus, the peak atomic percentage of carbon (and / or nitrogen if dielectric layer 98B also does not contain carbon and / or nitrogen when deposited) can be in dielectric layer 94A. Fig.21 The profile of carbon (and / or nitrogen) according to some embodiments is schematically shown. The X-axis represents Fig. 20 94A. The Y-axis represents the atomic percentage of carbon (and / or nitrogen). The peak percentage of carbon is shown in two portions of dielectric layer 94A and decreases in gate stacks 70A and 70B and dielectric layer 94B. The dashed line represents an alternative embodiment in which dielectric layer 94B does not have carbon (and / or nitrogen) and carbon (and / or nitrogen) cannot diffuse into the center of dielectric layer 94B.

[0075] Embodiments of the present disclosure have some advantageous features. When forming a gate isolation region (CMG region), by forming a first dielectric layer that fills the trench and has a lower k value, the first dielectric layer has a greater impact on the reduction of parasitic capacitance. The second dielectric layer has a higher k value and is denser and has a better ability to reduce leakage current. For example, the difference in the composition of the two dielectric layers of the gate isolation region can be observed using a transmission electron microscope (TEM).

[0076] According to some embodiments of the present disclosure, a method includes: forming a gate stack; etching the gate stack to form a trench penetrating the gate stack, wherein a dielectric isolation region below the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench; performing a first deposition process to form a first dielectric layer, the first dielectric layer extending into the trench and lining the sidewalls of the first portion and the second portion of the gate stack, wherein the first dielectric layer has a first dielectric constant; and performing a second deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer fills the trench, and the second dielectric layer has a second dielectric constant greater than the first dielectric constant.

[0077] In an embodiment, the first dielectric layer is deposited using aminosilane as a first precursor. In an embodiment, the second dielectric layer is deposited using a second precursor, the second precursor is selected from the group consisting of silane, disilane, dichlorosilane, and a combination of the foregoing, and wherein the first dielectric layer and the second dielectric layer include the same element. In an embodiment, the first dielectric layer and the second dielectric layer have the same composition. In an embodiment, the first dielectric layer has a higher porosity than the second dielectric layer. In an embodiment, the first dielectric layer is deposited using N2, NH3 and Ar as additional process gases.

[0078] In one embodiment, the method further includes: forming a protruding fin, wherein the gate stack is formed on the protruding fin; etching the protruding fin to form a source / drain recess; and forming a source and drain region in the source / drain recess. In an embodiment, the method further includes: performing a planarization process to remove portions of the first dielectric layer and the second dielectric layer above the top surface of the gate stack to form a gate isolation region. In an embodiment, the first dielectric layer has a bottom surface that is higher than the bottom end of the trench. In one embodiment, the second dielectric layer is in physical contact with the dielectric isolation region.

[0079] According to some embodiments of the present disclosure, a structure includes: a semiconductor substrate including a body portion; a dielectric isolation region above the body portion of the semiconductor substrate; a semiconductor region next to the dielectric isolation region, wherein the semiconductor region includes a portion higher than the dielectric isolation region; a first gate stack and a second gate stack above the dielectric isolation region; and a gate isolation region between the first gate stack and the second gate stack and in physical contact with the first gate stack and the second gate stack, wherein the gate isolation region extends from a top surface level of the first gate stack to a level below a bottom surface level of the first gate stack, and wherein the gate isolation region includes a first dielectric layer, the first dielectric layer includes a low-k dielectric material; and a second dielectric layer including a high-k dielectric material, wherein the first dielectric layer includes a portion between the second dielectric layer and the first gate stack and in contact with the second dielectric layer and the first gate stack.

[0080] In an embodiment, the first dielectric layer comprises silicon and carbon. In an embodiment, the first dielectric layer comprises SiOCN. In an embodiment, the first dielectric layer and the second dielectric layer comprise the same element, and the first dielectric layer has a higher porosity than the second dielectric layer. In an embodiment, the first dielectric layer and the second dielectric layer have the same composition. In an embodiment, a portion of the second dielectric layer is in physical contact with the dielectric isolation region.

[0081] According to some embodiments of the present disclosure, a structure includes: a first GAA transistor including a first gate stack; a second GAA transistor including a second gate stack; and a gate isolation region between the first gate stack and the second gate stack and in contact with the first gate stack and the second gate stack, wherein the gate isolation region includes a first dielectric layer, the first dielectric layer includes SiOCN, wherein the first dielectric layer is in physical contact with the first gate stack and the second gate stack, and wherein the first dielectric layer has a first dielectric constant; and a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has a second dielectric constant higher than the first dielectric constant.

[0082] In an embodiment, the first dielectric layer has a lower portion that is thinner than an upper portion, and the bottom end of the first dielectric layer is flush with or lower than the bottom surface of the first gate stack and the second gate stack. In an embodiment, the second dielectric layer also includes SiOCN, and the first dielectric layer has a higher porosity than the second dielectric layer. In an embodiment, the structure also includes a dielectric isolation region below the first gate stack and the second gate stack and in contact with the first gate stack and the second gate stack, wherein the bottom of the gate isolation region is in the dielectric isolation region, and wherein the bottom of the second dielectric layer is in physical contact with the dielectric isolation region.

[0083] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0084] Example 1 is a method for forming a semiconductor structure, comprising: forming a gate stack; etching the gate stack to form a trench penetrating the gate stack, wherein a dielectric isolation region below the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench; performing a first deposition process to form a first dielectric layer, the first dielectric layer extending into the trench and lining the sidewalls of the first portion and the second portion of the gate stack, wherein the first dielectric layer has a first dielectric constant; and performing a second deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer fills the trench and has a second dielectric constant greater than the first dielectric constant.

[0085] Example 2 is the method of Example 1, wherein the first dielectric layer is deposited using aminosilane as a first precursor.

[0086] Example 3 is the method described in Example 2, wherein the second dielectric layer is deposited using a second precursor, the second precursor is selected from the group consisting of silane, disilane, dichlorosilane, and combinations of the foregoing items, and wherein the first dielectric layer and the second dielectric layer include the same elements.

[0087] Example 4 is the method of Example 3, wherein the first dielectric layer and the second dielectric layer have the same composition.

[0088] Example 5 is the method of Example 4, wherein the first dielectric layer has a higher porosity than the second dielectric layer.

[0089] Example 6 is the method of Example 2, wherein the first dielectric layer is deposited using N2, NH3, and Ar as additional process gases.

[0090] Example 7 is the method of Example 1, further comprising: forming a protruding fin, wherein the gate stack is formed on the protruding fin; etching the protruding fin to form a source / drain recess; and forming source and drain regions in the source / drain recess.

[0091] Example 8 is the method of Example 1, further comprising: performing a planarization process to remove portions of the first dielectric layer and the second dielectric layer that are higher than a top surface of the gate stack to form a gate isolation region.

[0092] Example 9 is the method of Example 1, wherein the first dielectric layer has a bottom surface that is higher than a bottom end of the trench.

[0093] Example 10 is the method of Example 1, wherein the second dielectric layer is in physical contact with the dielectric isolation region.

[0094] Example 11 is a method for forming a semiconductor structure, comprising: forming a dielectric isolation region above a body portion of a semiconductor substrate, wherein a semiconductor region is adjacent to the dielectric isolation region, and wherein the semiconductor region includes a portion that is higher than the dielectric isolation region; forming a replacement gate stack above the dielectric isolation region; etching the replacement gate stack to form a first gate stack and a second gate stack; and forming a gate isolation region, wherein the gate isolation region is between the first gate stack and the second gate stack and is in physical contact with the first gate stack and the second gate stack, wherein the gate isolation region extends from a top surface level of the first gate stack to a level below a bottom surface level of the first gate stack, and wherein forming the gate isolation region comprises: depositing a first dielectric layer, the first dielectric layer comprising a low-k dielectric material; and depositing a second dielectric layer, the second dielectric layer comprising a high-k dielectric material, wherein the first dielectric layer includes a portion between the second dielectric layer and the first gate stack and in contact with the second dielectric layer and the first gate stack.

[0095] Example 12 is the method of Example 11, wherein depositing the first dielectric layer includes depositing a dielectric layer containing silicon and carbon.

[0096] Example 13 is the method of Example 12, wherein depositing the first dielectric layer includes depositing SiOCN.

[0097] Example 14 is the method of Example 11, wherein the first dielectric layer and the second dielectric layer are deposited to include the same element, and the first dielectric layer has a higher porosity than the second dielectric layer.

[0098] Example 15 is the method of Example 14, wherein the first dielectric layer and the second dielectric layer are deposited to have the same composition.

[0099] Example 16 is the method of Example 11, wherein a portion of the second dielectric layer is in physical contact with the dielectric isolation region.

[0100] Example 17 is a semiconductor structure comprising: a first gate all around (GAA) transistor comprising a first gate stack; a second GAA transistor comprising a second gate stack; and a gate isolation region between the first gate stack and the second gate stack and in contact with the first gate stack and the second gate stack, wherein the gate isolation region comprises: a first dielectric layer comprising SiOCN, wherein the first dielectric layer is in physical contact with the first gate stack and the second gate stack, and wherein the first dielectric layer has a first dielectric constant; and a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has a second dielectric constant higher than the first dielectric constant.

[0101] Example 18 is the structure of Example 17, wherein the first dielectric layer has a lower portion thinner than an upper portion, and a bottom end of the first dielectric layer is flush with or lower than bottom surfaces of the first gate stack and the second gate stack.

[0102] Example 19 is the structure of Example 17, wherein the second dielectric layer also includes SiOCN, and the first dielectric layer has a higher porosity than the second dielectric layer.

[0103] Example 20 is the structure described in Example 17, further including: a dielectric isolation region, below the first gate stack and the second gate stack and in contact with the first gate stack and the second gate stack, wherein the bottom of the gate isolation region is in the dielectric isolation region, and wherein the bottom of the second dielectric layer is in physical contact with the dielectric isolation region.

Claims

1. A method for forming a semiconductor structure, comprising: forming a gate stack; etching the gate stack to form a trench penetrating the gate stack, wherein a dielectric isolation region below the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench; performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first and second portions of the gate stack, wherein the first dielectric layer has a first dielectric constant; and A second deposition process is performed to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer fills the trench and has a second dielectric constant greater than the first dielectric constant.

2. The method according to claim 1, wherein: The first dielectric layer is deposited using aminosilane as a first precursor.

3. The method of claim 2, wherein the second dielectric layer is deposited using a second precursor selected from the group consisting of silane, disilane, dichlorosilane, and combinations of the foregoing, and wherein, The first dielectric layer and the second dielectric layer include the same element.

4. The method according to claim 3, wherein: The first dielectric layer and the second dielectric layer have the same composition.

5. The method according to claim 4, wherein: The first dielectric layer has a higher porosity than the second dielectric layer.

6. The method according to claim 2, wherein: The first dielectric layer is deposited using N2, NH3 and Ar as additional process gases.

7. The method according to claim 1, further comprising: forming a protruding fin, wherein the gate stack is formed on the protruding fin; etching the protruding fins to form source / drain recesses; and Source and drain regions are formed in the source / drain recesses.

8. The method according to claim 1, further comprising: A planarization process is performed to remove portions of the first dielectric layer and the second dielectric layer above a top surface of the gate stack to form a gate isolation region.

9. A method of forming a semiconductor structure, comprising: forming a dielectric isolation region over a bulk portion of a semiconductor substrate, wherein a semiconductor region is adjacent to the dielectric isolation region, and wherein the semiconductor region includes a portion that is higher than the dielectric isolation region; forming a replacement gate stack over the dielectric isolation region; etching the replacement gate stack to form a first gate stack and a second gate stack; and forming a gate isolation region between the first gate stack and the second gate stack and in physical contact with the first gate stack and the second gate stack, wherein the gate isolation region extends from a top surface level of the first gate stack to a level below a bottom surface level of the first gate stack, and wherein forming the gate isolation region comprises: depositing a first dielectric layer, the first dielectric layer comprising a low-k dielectric material; and A second dielectric layer is deposited, the second dielectric layer comprising a high-k dielectric material, wherein the first dielectric layer includes a portion between and in contact with the second dielectric layer and the first gate stack.

10. A semiconductor structure comprising: a first gate all around (GAA) transistor including a first gate stack; a second GAA transistor comprising a second gate stack; as well as a gate isolation region between the first gate stack and the second gate stack and in contact with the first gate stack and the second gate stack, wherein the gate isolation region comprises: a first dielectric layer comprising SiOCN, wherein the first dielectric layer is in physical contact with the first gate stack and the second gate stack, and wherein the first dielectric layer has a first dielectric constant; and A second dielectric layer is on the first dielectric layer, wherein the second dielectric layer has a second dielectric constant higher than the first dielectric constant.

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