Three-dimensional stacked semiconductor device and manufacturing method thereof

Abstract

A three-dimensional (3D) stacked semiconductor device and a method of manufacturing the same are provided. The 3D stacked semiconductor device includes: a first source / drain region connected to a first channel structure; and a second source / drain region over the first source / drain region connected to a second channel structure over the first channel structure, where the second channel structure has a smaller length than the first channel structure in a channel length direction, the second source / drain region is connected to the third source / drain region through the second channel structure in the channel length direction.

Description

Technical Field

[0001] Apparatus and methods related to the present invention relate to three-dimensional stacked (3D stacked) or multi-stacked semiconductor devices in which source / drain regions are formed using channel spacers. Background Art

[0002] In response to the increasing demand for integrated circuits with high device integration density and performance, a 3D stacked semiconductor device including a lower transistor and an upper transistor stacked thereon has been introduced. Each of the lower transistor and the upper transistor can be a fin field effect transistor (FinFET), a nanosheet transistor, or any other type of transistor. The FinFET has one or more horizontally arranged vertical fin structures as a channel structure, at least three surfaces of which are surrounded by a gate structure, and the nanosheet transistor is characterized by one or more nanosheet channel layers vertically stacked on a substrate as a channel structure and a gate structure surrounding all four surfaces of each nanosheet channel layer. The nanosheet transistor is called a gate all around (GAA) transistor or a multi-bridge channel field effect transistor (MBCFET).

[0003] However, there are various challenges in forming the upper source / drain region for the upper transistor and the lower source / drain region for the lower transistor of the 3D stacked semiconductor device, including the difficulty in isolating the two source / drain regions from each other. This problem arises because the lower source / drain region in the 3D stacked semiconductor device vertically overlaps the upper source / drain region. In addition, as the contact polysilicon pitch (CPP) or gate pitch is scaled down to achieve even higher density 3D stacked semiconductor devices, forming the lower source / drain region and the upper source / drain region in the nanoscale region between the gate structures becomes more challenging than before.

[0004] The information disclosed in this background technology section is known to the inventor or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information acquired in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0005] The present disclosure provides a 3D stacked semiconductor device, in which a source / drain region is formed using a channel spacer formed at the side surface of one or more upper channel layers for an upper transistor. When the lower source / drain region is formed by one or more lower channel layers, the channel spacer can block the upper channel layer, and the channel spacer can be removed to expose the upper channel layer, so that an upper source / drain region can be formed from the upper channel layer.

[0006] According to an embodiment, a 3D stacked semiconductor device is provided, which may include: a first source / drain region connected to a first channel structure; and a second source / drain region, above the first source / drain region, connected to a second channel structure above the first channel structure, wherein the second channel structure has a smaller length than the first channel structure in a channel length direction, and the second source / drain region is connected to a third source / drain region through the second channel structure in the channel length direction.

[0007] According to an embodiment, a 3D stacked semiconductor device is provided, which may include: a first source / drain region connected to a first channel structure; and a second source / drain region, above the first source / drain region, connected to a second channel structure above the first channel structure, wherein the second source / drain region has a greater length than the first source / drain region in a channel length direction, and the second source / drain region is connected to a third source / drain region through the second channel structure in the channel length direction.

[0008] According to an embodiment, a 3D stacked semiconductor device is provided, which may include: a first source / drain region connected to a first channel structure; a second source / drain region, above the first source / drain region, connected to a second channel structure above the first channel structure; a gate structure surrounding the first channel structure and the second channel structure; a first inner spacer, between a first portion of the gate structure and the first source / drain region; and a second inner spacer, between a second portion of the gate structure and the second source / drain region, wherein the second inner spacer has a smaller length than the first inner spacer in a channel length direction, and the second source / drain region is connected to another second source / drain region through the second channel structure in the channel length direction.

[0009] According to an embodiment, a method for manufacturing a 3D stacked semiconductor device is provided. The method may include: providing a semiconductor stack including a first channel layer and a second channel layer above the first channel layer; partially recessing the second channel layer from at least one side surface of the second channel layer so that a side groove is formed at the at least one side surface, while passivating the first channel layer by a passivation structure; forming a channel spacer in the side groove; removing the passivation structure and forming a first source / drain region based on the first lower channel layer; and removing the channel spacer and forming a second source / drain region based on the second channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A top plan view of an intermediate semiconductor device prepared for manufacturing a 3D stacked semiconductor device according to an embodiment is shown, wherein source / drain regions are formed based on channel spacers;

[0012] Figures 2A-2D to Figures 12A-12D According to an embodiment, the Figure 1 The intermediate semiconductor device is obtained after the corresponding steps of forming the intermediate semiconductor device into a 3D stacked semiconductor device;

[0013] Fig.13 A flow chart describing a method of forming a 3D stacked semiconductor device according to an embodiment is shown, wherein source / drain regions are formed based on channel spacers; and

[0014] Fig.14 is a schematic block diagram showing an electronic device including a 3D stacked semiconductor device according to an embodiment, wherein Figures 2A-2D to Figures 12A-12D and Fig.13 The source / drain regions are formed using channel spacers as shown in FIG. DETAILED DESCRIPTION

[0015] The embodiments of the present disclosure described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each embodiment or example provided in the following description does not exclude association with one or more features of another embodiment or another example that is also provided herein or is not provided herein but is consistent with the present disclosure. For example, even if the content described in a specific embodiment or example is not described in an embodiment or example different therefrom, these contents may also be understood to be related to or combined with different embodiments or examples, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure. For example, the source / drain region, gate structure, channel layer, spacer, sacrificial layer and isolation layer described herein may be of different types or forms, as long as the present disclosure can be applied thereto.

[0016] It should be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on", "over", "up", "under", "below", "under", "connected to", or "coupled to" another element of the semiconductor device, it may be directly on, over, over, under, under, under, connected to, or coupled to the other element, or there may be intervening elements. Conversely, when an element of a semiconductor device is referred to as being "directly on" another element of the semiconductor device, "directly over", "directly on", "directly below", "directly below", "directly below", "directly connected to", or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Throughout this disclosure, the same reference numerals refer to the same elements.

[0017] For ease of description, spatially relative terms such as "above", "above", "up", "upper", "below", "below", "below", "lower", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc. may be used herein to describe the relationship of one element to another element as shown in the figure. It should be understood that spatially relative terms are intended to cover different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figure. For example, if the semiconductor device in the figure is flipped, the element described as being "below" or "below" another element will be oriented as being "above" another element. Therefore, the term "below" can cover both the above and below orientations. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article are interpreted accordingly. As another example, the elements referred to as "left" elements and "right" elements can be "right" elements and "left" elements when the device or structure including these elements is oriented differently. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, and the necessary description is performed to distinguish the two elements.

[0018] It should be understood that although the terms "1st", "2nd", "3rd", "4th", "5th", "6th", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, a first element discussed in the description of the embodiments may be referred to as a second element in the claims.

[0019] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. In this document, when the term "same" or "equal" is used to compare the size of two or more elements, the term can encompass "substantially the same" or "substantially equal" sizes.

[0020] It should also be understood that even if a certain step or operation of manufacturing a device or structure is described earlier than other steps or operations, the step or operation may be performed later than the other steps or operations unless the other steps or operations are described as being performed after the step or operation.

[0021] Many embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments (and intermediate structures). Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions shown herein, but rather include shape deviations, for example, caused by manufacturing. The various regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0022] For the sake of brevity, conventional elements, structures or layers of semiconductor devices including nanosheet transistors and the materials forming them may or may not be described in detail herein. For example, when this layer or structure is irrelevant to the novel features of the implementation, a certain isolation layer or structure of the semiconductor device and the material forming the isolation layer or structure may be omitted herein. In addition, when the material of the known structural elements forming the semiconductor device is irrelevant to the novel features of the implementation, the description of the material may be omitted herein. For example, the present disclosure omits the description of the materials of the substrate (e.g., silicon, germanium, etc.), the source / drain region (e.g., silicon doped with p-type or n-type impurities), and the gate structure (e.g., copper (Cu), aluminum (Al), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta) or a combination thereof).

[0023] Figure 1A top plan view of an intermediate semiconductor device prepared for fabricating a 3D stacked semiconductor device according to an embodiment is shown, wherein source / drain regions are formed based on channel spacers. Figures 2A-2D to Figures 12A-12D According to an embodiment, the Figure 1 The intermediate semiconductor device is obtained after the corresponding steps of forming the 3D stacked semiconductor device.

[0024] Figure 2A-12A yes Figure 1 A cross-sectional view of the intermediate semiconductor device in the direction D1 along the line II' shown therein. Figure 2B-12B yes Figure 1 A cross-sectional view of the intermediate semiconductor device in the direction D1 along the line II-II' shown therein. Figure 2C and Figures 10C-12C yes Figure 1 A cross-sectional view of the intermediate semiconductor device along line III-III' in the direction D2, and Figure 2D and Figures 10D-12D They are Figure 1 A cross-sectional view of the intermediate semiconductor device in the direction D2 along the line IV-IV' shown therein.

[0025] It should be understood that providing Figure 1 Only the positional relationship between the substrate and the dummy gate structure formed on the channel structure is shown to help understand Figures 2A-2D to Figures 12A-12D Therefore, Figure 1 All structural elements shown in these cross-sectional views are not shown. Here, the D1 direction is the channel length direction along which the source / drain regions are connected to each other through the channel structure, and the D2 direction is the channel width direction intersecting the D1 direction. The D3 direction is a vertical direction intersecting the D1 and D2 directions, which are both horizontal directions.

[0026] refer to Figure 1 and Figures 2A-2D , the intermediate semiconductor device 10 may include a plurality of semiconductor stacks 10 - 1 , 10 - 2 , and 10 - 3 on a substrate 105 .

[0027] The three semiconductor stacks 10-1, 10-2 and 10-3 can be obtained by dividing a single initial semiconductor stack formed on the substrate 105 through operations such as photolithography, masking and top-down etching to provide two grooves R1 and R2 that expose the top surface of the substrate 105. In a later step of manufacturing a 3D stacked semiconductor device, a lower source / drain region and an upper source / drain region will be formed in the two grooves R1 and R2. The lower source / drain region can form a lower transistor together with the lower gate structure, and the lower gate structure will also be formed in a later step. The upper source / drain region can form an upper transistor in a 3D stacked semiconductor device together with the upper gate structure in a later step. Hereinafter, when the upper gate structure and the lower gate structure are configured to receive a common gate input signal when the 3D stacked semiconductor device is completed from the intermediate semiconductor device 10, the upper gate structure and the lower gate structure can be collectively referred to as gate structures. However, according to another embodiment, the upper gate structure and the lower gate structure can be formed to be isolated from each other.

[0028] Before the initial semiconductor stack is divided into three semiconductor stacks 10-1, 10-2 and 10-3, the initial semiconductor stack can be formed by epitaxially growing multiple lower sacrificial layers 111, lower channel layers 112, channel isolation layers 117, upper sacrificial layers 121 and upper channel layers 122 from the substrate 105 in an alternating manner. The sacrificial layers 111 and 121 are so called because these layers will be replaced by gate structures in a later step. The lower channel layer 112 and the upper channel layer 122 will form the lower current channel of the lower transistor and the upper current channel of the upper transistor of the 3D stacked semiconductor device in a later step, respectively. In this article, the lower sacrificial layer 111 and the lower channel layer 112 are collectively referred to as the lower channel structure 110, and the upper sacrificial layer 121 and the upper channel layer 122 are collectively referred to as the upper channel structure 120.

[0029] Figure 2C and Figure 2DIt is shown that the upper channel structure 120 including the upper sacrificial layer 121 and the upper channel layer 122 may have a smaller channel width in the D2 direction than the lower channel structure 110 including the lower sacrificial layer 111 and the lower channel layer 112. Such a configuration of the channel structure for a 3D stacked semiconductor device may be intended to facilitate the formation of a lower contact structure on the top surface of the lower source / drain region to be epitaxially grown from the lower channel layer 112 in a later step. For example, when the upper channel layer 122 and the lower channel structure 110 have the same channel width, the upper source / drain region and the lower source / drain region epitaxially grown therefrom may also have the same width, and therefore, the lower source / drain region may completely overlap with the upper source / drain region in the D3 direction, and therefore, the lower contact structure may not be formed on the top surface of the lower source / drain region to connect the lower source / drain region to the back-end of line (BEOL) structure in the upper portion of the 3D stacked semiconductor device. In this case, the lower contact structure may be formed on the side surface of the lower source / drain region, which may increase the occupied area of ​​the 3D stacked semiconductor device.

[0030] Therefore, if Figure 2C and Figure 2D As shown, the upper channel structure 120 may be formed to have a smaller width than the lower channel structure 110, so that the lower source / drain region epitaxially grown from the lower channel layer 112 may also have a smaller width than the lower source / drain region epitaxially grown from the upper channel layer 122, thereby forming a non-overlap region NR above the lower source / drain region. Through the non-overlap region NR, the lower contact structure may extend downward from the BEOL structure and be connected to the top surface of the lower source / drain region.

[0031] After the lower channel structure 110 and the upper channel structure 120 are stacked with the trench isolation layer 117 therebetween to form an initial semiconductor stack, the initial semiconductor stack may be patterned to form a shallow trench isolation (STI) structure 106 that isolates the intermediate semiconductor device 10 from an adjacent device (such as another intermediate semiconductor device). The STI liner 108 may be formed before the STI structure 106 is formed on the substrate 105.

[0032] Each of the semiconductor stacks 10-1, 10-2, and 10-3 may include a dummy gate structure 150 having a hard mask pattern 161 thereon. When the initial semiconductor stack is patterned and divided into the semiconductor stacks 10-1, 10-2, and 103, the initial dummy gate structure included therein may also be patterned so that the dummy gate structure 150 is formed on the channel structures 110 and 120. The dummy gate structure 150 will be replaced by a gate structure that will also replace the sacrificial layers 111 and 121 in a later step. The hard mask pattern 161 may have been used to pattern the initial semiconductor stack into the semiconductor stacks 10-1, 10-2, and 103 by photolithography, masking, and top-down etching operations, and may have remained on the dummy gate structure 150. The dummy gate structure 150 in each of the semiconductor stacks 10-1, 10-2, and 10-3 may be used as a mask structure when forming the lower source / drain region and the upper source / drain region.

[0033] The oxide layer 118 may be formed on the channel structures 110 and 120 of each of the semiconductor stacks 10-1, 10-2, and 10-3 to protect the channel structures when the dummy gate structure 150 is replaced with a gate structure in each of the semiconductor stacks in a later step. The oxide layer 118 may also be formed to partially disable the channel structures 110 and 120 formed in the semiconductor stacks 10-1 and 10-3 when the 3D stacked semiconductor device is completed in a later step. However, the semiconductor stacks 10-1 and 10-3 may be used to form lower source / drain regions and upper source / drain regions for the 3D stacked semiconductor device in a later step.

[0034] Gate spacers 151 may be formed on side surfaces of the hard mask pattern 161 and each dummy gate structure 150. The gate spacers 151 will isolate or protect a gate structure that will replace each of the dummy gate structures 150 in a later step from other circuit elements.

[0035] Then, the pattern can be Figure 2A The semiconductor stacks 10-1, 10-2, and 10-3 shown in FIG. 1 have recesses R1 and R2 therebetween, each of which exposes a top surface of the substrate 105 and side surfaces of the lower and upper channel structures 110 and 120 of the semiconductor stacks 10-1, 10-2, and 10-3.

[0036] In addition, the side surface of the lower sacrificial layer 111 can be etched to form a lower inner spacer 116, which will isolate the lower source / drain region to be formed in the grooves R1 and R2 from the gate structure that will replace the lower sacrificial layer 111 in a later step. Similarly, the side surface of the upper sacrificial layer 121 can be etched to form an upper inner spacer 126, which will isolate the upper source / drain region to be formed in the grooves R1 and R2 from the gate structure that will replace the upper sacrificial layer 121 and the dummy gate structure 150 in a later step.

[0037] Thus, each of the grooves R1 and R2 may expose side surfaces of the lower channel layer 112 , the lower inner spacer 116 , the channel isolation layer 117 , the upper channel layer 122 , and the upper inner spacer 126 , which may be vertically aligned or coplanar with each other.

[0038] In each of the semiconductor stacks 10-1, 10-2, and 10-3, the channel layers 112 and 122 may have the same length in the D1 direction. For example, in the semiconductor stack 10-2, the lower channel layer 112 and the upper channel layer 122 may both have a length CL1. In addition, in each of the semiconductor stacks 10-1, 10-2, and 10-3, the inner spacers 116 and 126 may also have the same length in the D1 direction. For example, in the semiconductor stack 10-2, the inner spacers 116 and 125 may both have a length SL1.

[0039] The substrate 105 may be a silicon (Si) substrate, but it may include other materials such as silicon germanium (SiGe), silicon carbide (SiC), but not limited thereto. Each of the sacrificial layers 111 may include silicon germanium (SiGe), and each of the channel layers 112 may include silicon (Si). The channel isolation layer 117 may also include SiGe or silicon nitride (e.g., SiBCN), but not limited thereto. The STI structure 106 may include silicon oxide (e.g., SiO, SiO 2 etc.), but not limited thereto, and the STI liner 108 may include silicon nitride (eg, SiN, Si 3 N 4 The oxide layer 118 may be a silicon oxide layer (eg, SiO, SiO 2 The dummy gate structure 150 may include polysilicon or amorphous silicon. The gate spacer 151 and the inner spacers 116 and 126 may each include silicon nitride (eg, SiN, Si 3 N 4 The hard mask pattern 161 may include silicon nitride or titanium nitride (eg, SiN, Si 3 N 4 , TiN, etc.), but not limited to these.

[0040] refer to Figure 3A and Figure 3B A passivation structure 171 including a spin-on glass (SOG) material may be formed in the lower portion of each of the grooves R1 and R2 to protect the lower channel structure 110 from subsequent operations. The SOG material may include, for example, silicon oxide (e.g., SiO, SiO 2 wait).

[0041] In order to form a passivation structure 171 in the lower portion of each of the grooves R1 and R2, the SOG material can be deposited in the grooves R1 and R2 by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or a combination thereof, and partially etched down by, for example, dry etching or wet etching to expose the side surface of the upper channel structure 120 and the side surface of the channel isolation layer 117.

[0042] It should be understood that corresponding to Figure 2C and Figure 2D Some cross-sectional views of the intermediate semiconductor device 10 may be omitted when describing subsequent operations when they are not relevant to the novel features of the present disclosure.

[0043] refer to Figure 4A and Figure 4B , each of the upper channel layers 122 may be partially etched from its side surface exposed in the upper portion of the grooves R1 and R2 located above the passivation structure 171 to form a side groove R3 .

[0044] A side groove R3 may be formed in this step to provide a space in which a channel spacer will be formed in the next step. The side groove R3 may be formed between two vertically adjacent upper inner spacers 126 so that each side surface of the upper channel layer 122 between the two upper inner spacers 126 is etched by a side depth DT that is less than the length SL1 of each of the inner spacers 116 and 126.

[0045] Since the side recess R3 is formed in the above-described manner, the length of each upper channel layer 122 can be reduced. For example, in the semiconductor stack 10-2, the upper channel layers 122 can each have a length CL2 that is twice the length CL1 reduced by the side depth DT, while the lower channel layer 112 passivated by the passivation structure 171 maintains the length CL1. Due to the side recess R3, the side surface of the upper channel layer 122 may no longer be vertically aligned or coplanar with the side surfaces of the upper inner spacer 126 and the side surfaces of the channel isolation layer 117 in the recesses R1 and R2.

[0046] The side recess R3 can be formed by, for example, dry etching or using an etchant such as chlorine / fluorine plasma or hydrofluoric acid (HF) and nitric acid (HNO 3 ) is performed by wet etching of a mixture of, but not limited to, a silicon nitride film to selectively etch the upper channel layer 122 formed of silicon relative to the upper inner spacer 126 formed of silicon nitride.

[0047] refer to Figure 5A and Figure 5B , a channel spacer 136 is formed in each of the side recesses R3 formed in the previous step.

[0048] The channel spacers 136 may be formed in the corresponding side recesses R3 to protect the upper channel layer 122 from subsequent operations including removing the passivation structure 171 in the next step and forming lower source / drain regions thereafter.

[0049] The trench spacers 136 may be formed by, for example, atomic layer deposition (ALD), PVD, CVD, PECVD, or a combination thereof of the same material as that forming the inner spacers 116 and 126, so that the side surfaces of the trench spacers 136 may be vertically aligned or coplanar with the side surfaces of the upper inner spacers 126 and the side surfaces of the trench isolation layer 117. Therefore, the length SL2 of each trench spacer 136 may be equal to the side depth DT of the side recess R3.

[0050] refer to Fig. 6A and Figure 6B , the passivation structure 171 may be removed from a lower portion of each of the grooves R1 and R2.

[0051] The passivation structure 171 can be removed by, for example, dry etching, wet etching, stripping or ashing to expose the top surface of the substrate 105 and the side surfaces of the lower sacrificial layer 111 and the lower channel layer 112 again, and the side surfaces of the lower sacrificial layer 111 and the lower channel layer 112 can be vertically aligned or coplanar with each other on the top surface of the substrate 105.

[0052] refer to Fig. 7A and Figure 7B , the lower source / drain region 135 may be formed by, for example, epitaxial growth of silicon included in the substrate 105 exposed in the lower portions of the grooves R1 and R2 and the lower channel layer 112 of the semiconductor stacks 10 - 1 , 10 - 2 , and 10 - 3 .

[0053] The lower source / drain regions 135 may include the same material as that forming the substrate 105 and the lower channel layer 112, such as silicon. In addition, when the lower source / drain regions 135 are to be n-type source / drain regions, the lower source / drain regions 135 may be doped with impurities such as phosphorus (P), arsenic (As), antimony (Sb), etc. However, when the lower source / drain regions 135 are to be p-type source / drain regions, they may be doped with boron (B), gallium (Ga), indium (In), etc.

[0054] When the 3D stacked semiconductor device is completed, current will flow between the lower source / drain regions 135 through the lower channel layer 112 of the semiconductor stack 10 - 2 to function as a lower transistor of the 3D stacked semiconductor device.

[0055] In this step, epitaxy to form the lower source / drain region 135 may be selectively performed based on only the lower channel layer 112 and the substrate 105 because the upper channel layer 122 is covered by the channel spacer 136 .

[0056] refer to Fig. 8A and Figure 8B , a first interlayer dielectric (ILD) layer 141 may be formed on the lower source / drain regions 135 in lower portions of the recesses R1 and R2 to isolate the lower source / drain regions 135 from each other and from other circuit elements.

[0057] The formation of the first ILD layer 141 may be performed by, for example, PVD, CVD, PECVD, or a combination thereof followed by planarization such as CMP, so that a top surface of the first ILD layer 141 may be at the level of a top surface of the trench isolation layer 117 .

[0058] refer to Fig. 9A and Fig. 9B , the channel spacer 136 and the corresponding portions of the upper inner spacer 126 may be removed to expose the upper channel layer 122 in the upper portion of each of the grooves R1 and R2 and the remaining portion of the upper inner spacer 126 , so that formation of the upper source / drain region may be performed from the upper channel layer 122 in the next step.

[0059] The removal of the channel spacer 136 may be performed by, for example, dry etching and / or wet etching. When the channel spacer 136 having the length SL2 is removed, the portions of the upper inner spacer 126 located vertically above and below the channel spacer 136 may also be removed by the same amount or length SL2, because the upper inner spacer 126 and the channel spacer 136 may be formed of the same silicon nitride. However, the remaining portion of the upper inner spacer 126 having the length SL3 still prevents the upper sacrificial layer from being exposed to the recesses R1 and R2, so that in the next step, the silicon germanium included in the upper sacrificial layer 121 does not destroy the epitaxial growth of the silicon included in the upper channel layer 122 to form the upper source / drain regions in the recesses R1 and R2.

[0060] Due to the removal of the channel spacers 136 and corresponding portions of the upper inner spacers 126 , side surfaces of the upper channel layer 121 having the reduced length CL2 and side surfaces of the remaining portions of the upper inner spacers 126 exposed in the grooves R1 and R2 may become vertically aligned or coplanar with each other.

[0061] refer to Figures 10A-10D , the upper source / drain region 145 may be formed by, for example, epitaxial growth of silicon included in the upper channel layer 122 of the semiconductor stacks 10 - 1 , 10 - 2 , and 10 - 3 exposed in the upper portions of the grooves R1 and R2 .

[0062] Since the upper source / drain regions 145 can be epitaxially grown from the upper channel layer 122, the length CL2 of each upper channel layer 122 in the D1 direction is less than the length CL1 of each lower channel layer 112 by twice the length SL2 of the channel spacer 136 removed in the previous step, and therefore each upper source / drain region 145 can have a length EL2, which can be greater than the length EL1 of the lower source / drain region 135 thereunder by twice the length SL2 of the channel spacer 136.

[0063] On the contrary, Fig. 10D As shown in , in the D2 direction, the upper source / drain region 145 may have a width EW2, which may be smaller than the width EW1 of the lower source / drain region 135, so that the lower source / drain region 135 does not completely overlap with the upper source / drain region 145 in the D3 direction. This is because the upper channel layer 122 from which the upper source / drain region 145 is epitaxially grown has a smaller width in the D2 direction than the lower channel layer 112 from which the lower source / drain region 135 is epitaxially grown. Therefore, as described above with reference to Figures 2A-2D As described above, a lower source / drain contact structure may be formed through the non-overlapping region to contact the top surface of the lower source / drain region 135 in a later step.

[0064] The upper source / drain regions 145 may include the same material as that forming the upper channel layer 112, such as silicon. In addition, when the upper source / drain regions 145 are to be n-type source / drain regions, the upper source / drain regions 145 may be doped with impurities such as phosphorus (P), arsenic (As), antimony (Sb), etc. However, when the upper source / drain regions 145 are to be p-type source / drain regions, they may be doped with boron (B), gallium (Ga), indium (In), etc.

[0065] When the 3D stacked semiconductor device is completed, current will flow between the upper source / drain regions 145 through the upper channel layer 122 of the semiconductor stack 10 - 2 to function as an upper transistor of the 3D stacked semiconductor device.

[0066] refer to Figures 11A-11D , portions of the hard mask pattern 161 and the gate spacer 151 at the sides of the hard mask pattern 161 may be removed, and the second ILD layer 142 may be formed to surround the semiconductor stacks 10 - 1 , 10 - 2 , and 10 - 3 including the grooves R1 and R2 remaining after the previous step.

[0067] The removal of the hard mask pattern 161 and the portion of the gate spacer 151 may be performed by, for example, ashing, stripping, and / or dry etching, but is not limited thereto, thereby exposing the upper surface of the dummy gate structure 150. The formation of the second ILD layer 142 may be performed by, for example, PVD, CVD, PECVD, or a combination thereof of the same material as that of the first ILD layer 141 and then planarization (such as CMP), so that the top surface of the dummy gate structure 150 is surrounded by the second ILD layer 142. The second ILD layer 142 may isolate the upper source / drain regions 145 from each other and from other circuit elements.

[0068] refer to Figures 12A-12D , the dummy gate structure 150 and the sacrificial layers 111 and 121 may be removed and replaced by the gate structure 155. In addition, the upper contact structure 129 and the lower contact structure 119 may be formed to contact the upper source / drain region 145 and the lower source / drain region 135 through the second ILD layer 142, respectively.

[0069] The removal of the dummy gate structure 150 and the sacrificial layers 111 and 121 may be performed by, for example, dry etching, wet etching, reactive ion etching (RIE), and / or chemical oxide removal (COR) processes. The formation of the gate structure 155 may be performed by, for example, at least one of ALD, CVD, PVD, PECVD, etc. The gate structure 155 may surround the channel layers 112 and 122 as gate structures of lower and upper transistors of a 3D stacked semiconductor device.

[0070] Contact structures 129 and 119 may be formed on the top surfaces of the source / drain regions 145 and 135, respectively, by, for example, photolithography, masking, and etching on the second ILD layer 142, followed by deposition of a metal or metal compound such as copper (Cu), aluminum (Al), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof. Fig.12D As shown in , due to the width difference between the lower source / drain region 135 and the upper source / drain region 145 thereover, the lower contact structure 119 may be formed on the top surface of the lower source / drain region 135 .

[0071] Fig.13 A flow chart describing a method of forming a 3D stacked semiconductor device according to an embodiment is shown, wherein source / drain regions are formed based on channel spacers. Figures 2A-2D to Figures 12A-12D The method is described and therefore the same reference numerals may be used.

[0072] In step S10, an intermediate semiconductor device 10 including a semiconductor stack 10-2 is provided, wherein the lower channel structure 110 may include alternately stacked lower sacrificial layers 111 and lower channel layers 112, and the upper channel structure 120 may include alternately stacked upper sacrificial layers 121 and upper channel layers 122. Figures 2A-2D .

[0073] In the lower channel structure 110, two lower inner spacers 116 may be formed on two opposite side surfaces of each of the lower sacrificial layers 111 so that the lower source / drain region 135 may be epitaxially grown from only the lower channel layer 112 among the lower channel layer 112 and the lower sacrificial layer 111 in a later step. Similarly, in the upper channel structure 120, two upper inner spacers 126 may be formed in two opposite side surfaces of each of the upper sacrificial layers 121 so that the upper source / drain region 145 may be epitaxially grown from only the upper channel layer 122 among the upper channel layer 122 and the upper sacrificial layer 121 in a later step.

[0074] The lower channel layer 112 and the upper channel layer 122 may each have a length CL1 , and the lower inner spacer 116 and the upper inner spacer 126 may each have a length SL1 .

[0075] In step S20, each of the upper channel layers 122 may be partially recessed from both side surfaces thereof so that side grooves R3 may be formed above and below two vertically adjacent upper inner spacers 126 formed at each of both side surfaces of the upper sacrificial layer 121, while the lower channel structure 110 is passivated by the passivation structure 171. Figure 3A-3B and Figures 4A-4B .

[0076] Each of the upper channel layers 122 may be partially recessed at each of its two side surfaces by a side depth DT that is less than a length SL1 of each of the inner spacers 116 and 126 , and thus each of the partially recessed upper channel layers 122 may be reduced from a length CL1 to a length CL2 by twice the side depth DT.

[0077] In step S30, the channel spacer 136 may be filled in the side groove R3 to protect the upper channel layer 122 from subsequent operations including removing the passivation structure 171 and forming a lower source / drain region from the lower channel layer 112 exposed by removing the passivation structure 171. Figure 5A and Figure 5B .

[0078] The channel spacer 136 may be formed in each of the side grooves R3 such that the length of the channel spacer 136 may have a length SL2 equal to the side depth DT of the side groove R3 .

[0079] In step S40, the passivation structure 171 may be removed to expose the lower channel structure 110 including the lower channel layer 112, and the lower source / drain region 135 may be formed from the lower channel layer 112. Figure 6A-6B to Figure 7A-7B .

[0080] The lower source / drain region 135 may be formed from the epitaxial growth of only the lower channel layer 112 among the lower sacrificial layer 111, the lower channel layer 112, the upper sacrificial layer 121, and the upper channel layer 122. This is because the layers other than the lower channel layer 112 are blocked by the lower inner spacer 116, the upper inner spacer 126, and the channel spacer 136, respectively.

[0081] In step S50, the channel spacer 136 may be removed to expose the upper channel layer 122 while the upper sacrificial layer 121 is still blocked by the upper inner spacer 126, and the upper source / drain region 145 may be formed from the upper channel layer 122. Figures 8A-8B To 10A-10D.

[0082] Since the upper source / drain regions 145 may be formed from the upper channel layers 122, each upper channel layer 122 has a length CL2 in the D1 direction that is less than the length CL1 of each lower channel layer 112 by twice the length SL2 of the channel spacer 136 removed in the previous step, each upper source / drain region 145 may have a length EL2 that may be greater than the length EL1 of the lower source / drain region 135 thereunder by twice the length SL2 of the channel spacer 136.

[0083] Furthermore, when the channel spacer 136 is removed, the corresponding portion of the upper inner spacer 126 may also be removed by the same length SL2 , and thus the remaining portion of the upper inner spacer 126 may have a length SL3 that is smaller than the length SL1 of the lower inner spacer 116 by the length SL2 of the channel spacer 136 .

[0084] In step S60, the dummy gate structure and the sacrificial layers 111 and 121 included in the semiconductor stack 10-2 may be removed and replaced by the gate structure, and contact structures 119 and 129 may be formed on the lower source / drain region 135 and the upper source / drain region 145, respectively, to form a 3D stacked semiconductor device in which the source / drain region is formed using a channel spacer. Figures 11A-11D and Figures 12A-12D .

[0085] In the above-described embodiment, the channel spacer 136 is formed and used to form a 3D stacked semiconductor device in which the upper channel structure 120 for the upper transistor has a smaller width than the lower channel structure 110 for the lower transistor to facilitate the formation of the lower contact structure 119 on the top surface of the lower source / drain region 135. However, the present disclosure is not limited thereto, and according to an embodiment, the channel spacer 136 may also be formed and used to manufacture a 3D stacked semiconductor device in which the upper channel structure and the lower channel structure have the same width.

[0086] In addition, in the above-described embodiment, the channel spacer 136 is formed and used to form a 3D stacked semiconductor device in which each of the lower transistor and the upper transistor is a nanosheet field effect transistor. However, the present disclosure is not limited thereto, and according to an embodiment, at least one of the lower transistor and the upper transistor may be a FinFET.

[0087] Fig.14 is a schematic block diagram showing an electronic device including a 3D stacked semiconductor device according to an embodiment, wherein Figures 2A-2D to Figures 12A-12D and Fig.13 The source / drain regions are formed using channel spacers as shown in FIG.

[0088] refer to Fig.14 , the electronic device 1000 may include at least one processor 1100, a communication module 1200, an input / output module 1300, a storage device 1400, and a buffer random access memory (RAM) module 1500. According to an embodiment, the electronic device 1000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

[0089] The processor 1100 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or any other processor that controls the operation of the electronic device 1000. The communication module 1200 may be implemented to perform wireless or wired communication with an external device. The input / output module 1300 may include at least one of a touch sensor, a touch panel, a keyboard, a mouse, a proximity sensor, a microphone, etc. for receiving an input, and at least one of a display, a speaker, etc. for generating an output signal processed by the processor 1100. The memory 1400 may be implemented to store user data, output signals, etc. input through the input / output module 1300. The storage device 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash storage (UFS) device, etc.

[0090] The buffer RAM module 1500 may temporarily store data used for processing operations of the electronic device 1000. For example, the buffer RAM 1500 may include a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0091] although Fig.14 Although not shown in the figure, the electronic device 1000 may further include at least one sensor, such as an image sensor.

[0092] According to the implementation mode, the Figures 2A-2D to Figures 12A-12D and Fig.13 At least one of the 3D stacked semiconductor devices manufactured as shown in FIG. 1 is used to form at least one component in the electronic device 1000 .

[0093] The foregoing is a description of exemplary embodiments and should not be construed as limiting the present disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications in the above embodiments are possible without materially departing from the present disclosure.

[0094] This application is based on and claims priority from U.S. Provisional Application No. 63 / 527,414 filed in the U.S. Patent and Trademark Office on July 18, 2023 and U.S. Patent Application No. 18 / 380,476 filed on October 16, 2023, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional (3D) stacked semiconductor device, comprising: a first source / drain region connected to the first channel structure; as well as a second source / drain region, above the first source / drain region, connected to a second channel structure above the first channel structure, The second channel structure has a shorter length than the first channel structure in a channel length direction, and the second source / drain region is connected to the third source / drain region through the second channel structure in the channel length direction.

2. The three-dimensional stacked semiconductor device according to claim 1, further comprising: a gate structure surrounding the first channel structure and the second channel structure; a first inner spacer between the first portion of the gate structure and the first source / drain region; as well as a second inner spacer between the second portion of the gate structure and the second source / drain region, The second inner spacer has a length smaller than that of the first inner spacer in the channel length direction.

3. The three-dimensional stacked semiconductor device according to claim 2, wherein: The second source / drain region has a greater length in the channel length direction than the first source / drain region.

4. The three-dimensional stacked semiconductor device according to claim 3, wherein: Each of the first channel structure and the second channel structure includes a plurality of channel layers vertically stacked with a portion of the gate structure therebetween.

5. The three-dimensional stacked semiconductor device according to claim 1, wherein: The second source / drain region has a greater length in the channel length direction than the first source / drain region.

6. The three-dimensional stacked semiconductor device according to claim 5, wherein: The second source / drain region has a smaller width than the first source / drain region in a channel width direction intersecting the channel length direction.

7. The three-dimensional stacked semiconductor device according to claim 6, wherein: The second channel structure has a smaller width than the first channel structure in the channel width direction.

8. The three-dimensional stacked semiconductor device according to claim 7, wherein: Each of the first channel structure and the second channel structure includes a plurality of channel layers vertically stacked with a portion of a gate structure therebetween.

9. A three-dimensional (3D) stacked semiconductor device, comprising: a first source / drain region connected to the first channel structure; as well as a second source / drain region, above the first source / drain region, connected to a second channel structure above the first channel structure, The second source / drain region has a greater length than the first source / drain region in the channel length direction, and the second source / drain region is connected to the third source / drain region through the second channel structure in the channel length direction.

10. The three-dimensional stacked semiconductor device according to claim 9, further comprising: a gate structure surrounding the first channel structure and the second channel structure; a first inner spacer between the first portion of the gate structure and the first source / drain region; as well as a second inner spacer between the second portion of the gate structure and the second source / drain region, The second inner spacer has a length smaller than that of the first inner spacer in the channel length direction.

11. The three-dimensional stacked semiconductor device according to claim 10, wherein: The second channel structure has a smaller length in the channel length direction than the first channel structure.

12. The three-dimensional stacked semiconductor device according to claim 11, wherein: Each of the first channel structure and the second channel structure includes a plurality of channel layers vertically stacked with a portion of the gate structure therebetween.

13. The three-dimensional stacked semiconductor device according to claim 9, wherein: The second channel structure has a smaller length in the channel length direction than the first channel structure.

14. The three-dimensional stacked semiconductor device according to claim 9, wherein: The second source / drain region has a smaller width than the first source / drain region in a channel width direction intersecting the channel length direction.

15. The three-dimensional stacked semiconductor device according to claim 14, wherein: The second channel structure has a smaller length in the channel length direction than the first channel structure.

16. The three-dimensional stacked semiconductor device according to claim 15, wherein: The second channel structure has a smaller width than the first channel structure in the channel width direction.

17. A three-dimensional (3D) stacked semiconductor device, comprising: a first source / drain region connected to the first channel structure; a second source / drain region above the first source / drain region and connected to a second channel structure above the first channel structure; a gate structure surrounding the first channel structure and the second channel structure; a first inner spacer between the first portion of the gate structure and the first source / drain region; as well as a second inner spacer between the second portion of the gate structure and the second source / drain region, The second inner spacer has a smaller length than the first inner spacer in a channel length direction, and the second source / drain region is connected to the third source / drain region through the second channel structure in the channel length direction.

18. The three-dimensional stacked semiconductor device according to claim 17, wherein: The second channel structure has a smaller length in the channel length direction than the first channel structure.

19. The three-dimensional stacked semiconductor device according to claim 17, wherein: The second source / drain region has a greater length in the channel length direction than the first source / drain region.

20. The three-dimensional stacked semiconductor device according to claim 17, wherein: The second source / drain region has a smaller width than the first source / drain region in a channel width direction intersecting the channel length direction.

21. A method for manufacturing a three-dimensional stacked semiconductor device, comprising: providing a semiconductor stack comprising a first channel layer and a second channel layer above the first channel layer; partially recessing the second channel layer from at least one side surface of the second channel layer so that a side groove is formed at the at least one side surface, while passivating the first channel layer by a passivation structure; forming a channel spacer in the side recess; removing the passivation structure and forming a first source / drain region based on the first lower channel layer; as well as The channel spacer is removed, and a second source / drain region is formed based on the second channel layer.

22. The method according to claim 21, wherein: The side groove is formed between the side surface of the second channel layer, a first inner spacer above the side surface of the second channel layer, and a second inner spacer below the side surface of the second channel layer, When the trench spacer is removed, a portion of the first inner spacer and a portion of the second inner spacer are removed together with the trench spacer.

23. The method according to claim 21, wherein: The trench spacer includes silicon nitride.

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