Complementary field effect transistor and preparation method thereof
By using side wall materials with different dielectric constants in the complementary field effects crystal, the problem that the traditional FINFET structure is limited by nodes below 3nm, which significantly reduces parasitic capacitors and improves the working speed of the circuit.
Patent Information
- Application Number
- CN202411274827.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2025-01-24
AI Technical Summary
In the field of semiconductor technology, with the shrinking of the characteristic size of integrated circuits, traditional FinFET structures are limited at nodes below 3 nm, resulting in an increase in parasitic capacitance and limiting the circuit operating rate.
A complementary field effect transistor (GAAFET) structure is adopted, which includes a first MOS tube and a second MOS tube, which are integrated through bonding. The sidewalls of the first MOS tube and the sidewalls of the second MOS tube have different dielectric constants. .
By using the side wall materials with different dielectric constants, the parasitic capacitance of the device is significantly reduced, and the working speed of the circuit is improved.
Smart Images
Figure CN119364852A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a complementary field effect transistor and a method for preparing the same. Background Art
[0002] The feature size of integrated circuits continues to shrink, and traditional three-gate or dual-gate FinFETs are limited to nodes below 3nm. The nano-ring gate transistor (GAAFET) compatible with the mainstream post-high-k metal gate FinFET process will be the next-generation key structure to achieve size miniaturization. Its channel is mainly a stacked nanosheet structure.
[0003] However, in the related art, the increase in parasitic capacitance caused by the miniaturization of gate-all-around transistors is the main factor limiting the circuit operating speed, and the parasitic capacitance between the main gate and the source and drain continues to increase with the miniaturization of the size. Due to the unused space between the stacked nanosheets, the parasitic capacitance has a greater impact on the circuit operating speed.
[0004] The above statements are only used to provide background information related to the present application and do not necessarily constitute prior art. Summary of the invention
[0005] The purpose of the present application is to provide a complementary field effect transistor and a method for making the same. In order to have a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary is not a general review, nor is it intended to identify key / important components or to describe the scope of protection of these embodiments. Its only purpose is to present some concepts in a simple form as a preface to the detailed description that follows.
[0006] According to one aspect of an embodiment of the present application, a complementary field effect transistor is provided, comprising a first MOS transistor and a second MOS transistor; the first MOS transistor and the second MOS transistor are sequentially integrated together by bonding; a side wall of the first MOS transistor and a side wall of the second MOS transistor have different dielectric constants.
[0007] In some embodiments of the present application, the first MOS tube is a PMOS tube, and the second MOS tube is an NMOS tube; or, the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube.
[0008] According to another aspect of an embodiment of the present application, a method for preparing a complementary field effect transistor is provided, comprising:
[0009] Prepare a PMOS tube and an NMOS tube respectively, wherein the side wall of the PMOS tube and the side wall of the NMOS tube have different dielectric constants;
[0010] Bonding the PMOS transistor and the NMOS transistor together to form a complementary field effect transistor;
[0011] The method of preparing the PMOS tube or the NMOS tube comprises:
[0012] preparing a fin structure;
[0013] preparing a shallow trench isolation layer on the fin-shaped structure;
[0014] An inner sidewall and a source / drain epitaxial layer are prepared based on the shallow trench isolation layer and the stacked layer; the inner sidewall includes a plurality of parts with different dielectric constant values;
[0015] Channel release is performed and a metal gate is prepared to obtain a MOS tube.
[0016] In some embodiments of the present application, the step of preparing the fin-shaped structure includes:
[0017] Prepare a laminated epitaxial portion, the laminated epitaxial portion comprising a base layer of doped silicon material and a laminate located on the base layer, the laminate comprising a cross-laminated silicon layer and a germanium-silicon alloy layer;
[0018] depositing a layer of silicon nitride material on the stack;
[0019] The silicon nitride material layer, the stacked epitaxial portion and the base layer are etched in a direction perpendicular to the top surface of the base layer to form a fin structure, wherein the fin structure includes a first part, a second part and a third part stacked in sequence from bottom to top, wherein the first part is a part of the base layer, the second part is a remaining part after the silicon nitride material layer is etched, and the third part is a remaining part after the stacked epitaxial portion is etched.
[0020] In some embodiments of the present application, the step of preparing inner sidewalls and source / drain epitaxial layers based on the shallow trench isolation layer and the stacked layer includes:
[0021] Depositing polysilicon material to form a polysilicon dummy gate;
[0022] Deposition is performed on both sides of the polysilicon dummy gate in the second direction to form sidewalls;
[0023] Etching the stack to form a source region and a drain region;
[0024] forming inner side walls on the remaining portion of the stack;
[0025] A source-drain epitaxial layer is prepared on the first portion located on both sides of the inner sidewall, and the first portion is the portion of the base layer belonging to the fin structure.
[0026] In some embodiments of the present application, the performing of channel release includes:
[0027] The silicon layer in the stack is replaced with a high dielectric constant material layer to achieve channel release.
[0028] In some embodiments of the present application, the step of preparing a metal gate includes:
[0029] Etching and removing the polysilicon dummy gate;
[0030] A metal material is deposited in the space formed after removing the polysilicon dummy gate to form the metal gate.
[0031] In some embodiments of the present application, bonding the PMOS transistor and the NMOS transistor together to form a complementary field effect transistor includes:
[0032] Thinning the base layer of the PMOS tube to obtain a PMOS tube with a thinned base layer;
[0033] The PMOS transistor after the substrate layer is thinned is bonded and integrated with the NMOS transistor to form a complementary field effect transistor.
[0034] In some embodiments of the present application, bonding the PMOS transistor and the NMOS transistor together to form a complementary field effect transistor includes:
[0035] Thinning the base layer of the NMOS tube to obtain an NMOS tube with a thinned base layer;
[0036] The NMOS transistor after the substrate layer is thinned is bonded and integrated with the PMOS transistor to form a complementary field effect transistor.
[0037] In some embodiments of the present application, the widths of the side walls of the PMOS tube and the NMOS tube are both in the range of 0.5 nm-10 nm, and the thicknesses of the side walls of the PMOS tube and the NMOS tube are different.
[0038] The technical solution provided by one aspect of the embodiments of the present application may have the following beneficial effects:
[0039] The complementary field effect transistor provided in the embodiment of the present application includes a first MOS transistor and a second MOS transistor, wherein the first MOS transistor and the second MOS transistor are sequentially integrated together by bonding, and the sidewall of the first MOS transistor and the sidewall of the second MOS transistor have different dielectric constants. In this way, the sidewall of the complementary field effect transistor includes materials with different dielectric constants, thereby being able to significantly reduce device parasitic capacitance and improve circuit operating speed.
[0040] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0042] Figure 1 A cross-sectional view of a complementary field effect transistor according to an embodiment of the present application along a first cross-sectional plane is shown.
[0043] Figure 2 Shows Figure 1 A cross-sectional view of the corresponding complementary field effect transistor along the second cross-sectional plane.
[0044] Figure 3 A flow chart of a method for preparing a complementary field effect transistor according to an embodiment of the present application is shown.
[0045] FIG. 4( a ) shows a cross-sectional view along a first cross-sectional plane of a semiconductor structure after a stacked epitaxial portion is prepared in a process of preparing a PMOS tube in one embodiment of the present application.
[0046] FIG4( b ) shows a cross-sectional view of the semiconductor structure corresponding to FIG4( a ) along a second cross-sectional plane.
[0047] FIG4( c ) shows a cross-sectional view along a first cross-sectional plane of a semiconductor structure after a stacked epitaxial portion is prepared in a process of preparing an NMOS tube in one embodiment of the present application.
[0048] FIG4(d) shows a cross-sectional view of the semiconductor structure corresponding to FIG4(c) along the second cross-sectional plane.
[0049] FIG. 5( a ) shows a cross-sectional view along a first cross-sectional plane after a fin structure is formed on the basis of the semiconductor structure corresponding to FIG. 4( a ).
[0050] FIG5(b) shows a cross-sectional view of the semiconductor structure corresponding to FIG5(a) along a second cross-sectional plane.
[0051] FIG5(c) shows a cross-sectional view along a second cross-sectional plane after a fin structure is formed on the basis of the semiconductor structure corresponding to FIG4(c).
[0052] FIG5(d) shows a cross-sectional view of the semiconductor structure corresponding to FIG5(c) along the second cross-sectional plane.
[0053] FIG. 6( a ) shows a cross-sectional view along a first cross-sectional plane after a shallow trench isolation layer is formed on the basis of the semiconductor structure corresponding to FIG. 5( a ).
[0054] FIG6( b ) shows a cross-sectional view of the semiconductor structure corresponding to FIG6( a ) along a second cross-sectional plane.
[0055] FIG6( c ) shows a cross-sectional view along a second cross-sectional plane after a shallow trench isolation layer is formed on the basis of the semiconductor structure corresponding to FIG5( c ).
[0056] FIG6(d) shows a cross-sectional view of the semiconductor structure corresponding to FIG6(c) along the second cross-sectional plane.
[0057] FIG. 7( a ) shows a cross-sectional view along a first cross-sectional plane after a polysilicon dummy gate is formed on the basis of the semiconductor structure corresponding to FIG. 6( a ).
[0058] FIG. 7( b ) shows a cross-sectional view of the semiconductor structure corresponding to FIG. 7( a ) along a second cross-sectional plane.
[0059] FIG. 7( c ) shows a cross-sectional view along a second cross-sectional plane after a polysilicon dummy gate is formed on the basis of the semiconductor structure corresponding to FIG. 6( c ).
[0060] FIG. 7( d ) shows a cross-sectional view of the semiconductor structure corresponding to FIG. 7( c ) along the second cross-sectional plane.
[0061] FIG8( a ) shows a cross-sectional view along a first cross-sectional plane after a sidewall spacer is formed on the basis of the semiconductor structure corresponding to FIG7( a ).
[0062] FIG8( b ) shows a cross-sectional view of the semiconductor structure corresponding to FIG8( a ) along a second cross-sectional plane.
[0063] FIG8( c ) shows a cross-sectional view along a second cross-sectional plane after a sidewall spacer is formed on the basis of the semiconductor structure corresponding to FIG7( c ).
[0064] FIG8( d ) shows a cross-sectional view of the semiconductor structure corresponding to FIG8( c ) along the second cross-sectional plane.
[0065] FIG. 9( a ) shows a cross-sectional view along a second cross-sectional plane after etching the stack based on the semiconductor structure corresponding to FIG. 8( b ).
[0066] FIG9( b ) shows a cross-sectional view along a second cross-sectional plane after etching the stack based on the semiconductor structure corresponding to FIG8( d ).
[0067] FIG. 10( a ) shows a cross-sectional view along a second cross-sectional plane after an inner sidewall is formed on the basis of the semiconductor structure corresponding to FIG. 9( a ).
[0068] FIG10( b ) shows a cross-sectional view along a second cross-sectional plane after an inner sidewall is formed on the basis of the semiconductor structure corresponding to FIG9( b ).
[0069] FIG. 11( a ) shows a cross-sectional view along a second cross-sectional plane after a source-drain epitaxial layer is prepared on the basis of the semiconductor structure corresponding to FIG. 10( a ).
[0070] FIG11( b ) shows a cross-sectional view along a second cross-sectional plane after a source-drain epitaxial layer is prepared on the basis of the semiconductor structure corresponding to FIG10( b ).
[0071] FIG. 12( a ) shows a cross-sectional view along a first cross-sectional plane after releasing the channel and preparing a high dielectric constant metal gate based on the semiconductor structure corresponding to FIG. 11( a ).
[0072] FIG12( b ) shows a cross-sectional view of the semiconductor structure corresponding to FIG12( a ) along the second cross-sectional plane.
[0073] FIG12(c) shows a cross-sectional view along the second cross-sectional plane after the channel is released and a high dielectric constant metal gate is prepared based on the semiconductor structure corresponding to FIG11(b).
[0074] FIG12( d ) shows a cross-sectional view of the semiconductor structure corresponding to FIG12( c ) along the second cross-sectional plane. DETAILED DESCRIPTION
[0075] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.
[0076] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.
[0077] In view of the technical problem in the related art that the parasitic capacitance of transistor devices is large and limits the circuit operating speed, an embodiment of the present application provides a complementary field effect transistor, including a first MOS tube and a second MOS tube, the first MOS tube and the second MOS tube are sequentially integrated together by bonding, and the side wall of the first MOS tube and the side wall of the second MOS tube have different dielectric constants. In this way, the side wall of the complementary field effect transistor includes materials with different dielectric constants, thereby greatly reducing the device parasitic capacitance and improving the circuit operating speed.
[0078] A complementary field effect transistor and a method for manufacturing the same proposed in accordance with an embodiment of the present application are described below in conjunction with the accompanying drawings.
[0079] An embodiment of the present application provides a complementary field effect transistor, including a first MOS tube and a second MOS tube; the first MOS tube and the second MOS tube are sequentially integrated together by bonding; the side wall of the first MOS tube and the side wall of the second MOS tube have different dielectric constants.
[0080] Exemplarily, the first MOS tube is a PMOS tube, and the second MOS tube is an NMOS tube; or, the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube.
[0081] refer to Figure 1 and Figure 2 As shown, Figure 1 is a cross-sectional view of a complementary field effect transistor along a first cross-sectional plane of a specific example, wherein a straight line XX' in a first direction is parallel to the first cross-sectional plane. Figure 2 The cross-sectional view of the complementary field effect transistor of this example along the second cross-sectional plane, the straight line Y-Y' in the second direction is parallel to the second cross-sectional plane, the second cross-sectional plane is perpendicular to the first cross-sectional plane, and Y-Y' is perpendicular to XX'. The PMOS tube 100 and the NMOS tube 200 are sequentially integrated together by bonding. The sidewalls of the PMOS tube 100 and the sidewalls of the NMOS tube 200 have different dielectric constants.
[0082] refer to Figure 3 As shown, another embodiment of the present application provides a method for preparing a complementary field effect transistor, which may include:
[0083] S10, preparing a PMOS tube and an NMOS tube respectively, wherein the side wall of the PMOS tube and the side wall of the NMOS tube have different dielectric constants.
[0084] S20, bonding the PMOS transistor and the NMOS transistor together to form a complementary field effect transistor.
[0085] Exemplarily, bonding the PMOS tube and the NMOS tube together to form a complementary field effect transistor may include: thinning the base layer of the PMOS tube to obtain a PMOS tube with a thinned base layer; and bonding the PMOS tube with a thinned base layer and the NMOS tube together to form a complementary field effect transistor.
[0086] Exemplarily, bonding the PMOS tube and the NMOS tube together to form a complementary field effect transistor may include: thinning the base layer of the NMOS tube to obtain an NMOS tube with a thinned base layer; and bonding the NMOS tube with a thinned base layer to integrate with the PMOS tube to form a complementary field effect transistor.
[0087] In some implementations, preparing the PMOS transistor or the NMOS transistor may include:
[0088] S101. Prepare a fin structure.
[0089] Exemplarily, the preparation of the fin-shaped structure may include: preparing a stacked epitaxial portion, the stacked epitaxial portion including a base layer of doped silicon material and a stack located on the base layer, the stack including a silicon layer and a germanium-silicon alloy layer arranged in a cross-stacked manner; depositing a silicon nitride material layer on the stack; etching the silicon nitride material layer, the stacked epitaxial portion and the base layer in a direction perpendicular to the top surface of the base layer to form a fin-shaped structure, the fin structure including a first part, a second part and a third part stacked in sequence from bottom to top, the first part being a part of the base layer, the second part being a remaining part of the silicon nitride material layer after being etched, and the third part being a remaining part of the stacked epitaxial portion after being etched.
[0090] S102, preparing a shallow trench isolation layer on the fin-shaped structure.
[0091] S103, preparing an inner sidewall and a source / drain epitaxial layer based on the shallow trench isolation layer and the stack; the inner sidewall includes a plurality of parts with different dielectric constant values.
[0092] Exemplarily, the preparation of the inner sidewall and the source-drain epitaxial layer based on the shallow trench isolation layer and the stack may include: depositing polysilicon material to form a polysilicon dummy gate; depositing on both sides of the polysilicon dummy gate in the second direction to form sidewalls; etching the stack to form a source region and a drain region; forming an inner sidewall on the remaining part of the stack; and preparing the source-drain epitaxial layer on the first part located on both sides of the inner sidewall, the first part being the part of the base layer belonging to the fin-like structure.
[0093] S104, performing channel release and preparing a metal gate to obtain a MOS tube.
[0094] Exemplarily, performing channel release may include: replacing a silicon layer in the stack with a high dielectric constant material layer to achieve channel release.
[0095] Exemplarily, the preparing of the metal gate may include: etching to remove the polysilicon dummy gate; and depositing a metal material in a space formed after removing the polysilicon dummy gate to form the metal gate.
[0096] Exemplarily, the widths of the side walls of the PMOS tube and the NMOS tube are both in the range of 0.5 nm-10 nm, and the thicknesses of the side walls of the PMOS tube and the NMOS tube may be different.
[0097] The complementary field effect transistor prepared by the preparation method of the embodiment of the present application includes a first MOS tube and a second MOS tube, the first MOS tube and the second MOS tube are sequentially integrated together by bonding, and the side wall of the first MOS tube and the side wall of the second MOS tube have different dielectric constants. In this way, the side wall of the complementary field effect transistor includes materials with different dielectric constants, thereby being able to greatly reduce the parasitic capacitance of the device and improve the circuit operating speed.
[0098] Another embodiment of the present application provides a method for preparing a complementary field effect transistor, which may include the following steps:
[0099] Step 01: Prepare a laminated epitaxial portion, wherein the laminated epitaxial portion includes a base layer of doped silicon material and a laminate located on the base layer, wherein the laminate includes a cross-stacked silicon layer and a germanium-silicon alloy layer.
[0100] refer to Figure 4(a)-Figure 4(d) As shown, FIG4(a) is a cross-sectional view of a semiconductor structure after a laminated epitaxial portion is prepared in the process of preparing a PMOS tube along a first cross-sectional plane, and a straight line X-X' in the first direction is parallel to the first cross-sectional plane. FIG4(b) is a cross-sectional view of a semiconductor structure corresponding to FIG4(a) along a second cross-sectional plane, and a straight line Y-Y' in the second direction is parallel to the second cross-sectional plane, the second cross-sectional plane is perpendicular to the first cross-sectional plane, and Y-Y' is perpendicular to X-X'. FIG4(c) is a cross-sectional view of a semiconductor structure after a laminated epitaxial portion is prepared in the process of preparing an NMOS tube along a first cross-sectional plane, and a straight line X-X' in the first direction is parallel to the first cross-sectional plane. FIG4(d) is a cross-sectional view of a semiconductor structure corresponding to FIG4(c) along a second cross-sectional plane, and a straight line Y-Y' in the second direction is parallel to the second cross-sectional plane, the second cross-sectional plane is perpendicular to the first cross-sectional plane, and Y-Y' is perpendicular to X-X'. In a PMOS tube, the first substrate layer 1 is an N-type silicon material. In the NMOS tube, the second base layer 15 is a P-type silicon material. The stacked layers of the PMOS tube and the NMOS tube both include a silicon layer 2 and a germanium-silicon alloy layer 3 which are cross-stacked.
[0101] Step 02: Etch the stacked epitaxial portion to form a fin-shaped structure.
[0102] refer to Figure 5(a)-Figure 5(d) As shown, a silicon nitride layer 4 is formed on the stacked layer substrate with silicon nitride material, and then an etching operation is performed. During the etching operation, the middle part of the stacked epitaxial part in the XX' direction is retained, and the parts on both sides of the middle part are etched until a part of the base layer is etched away, and a recessed part 5 is formed on both sides of the middle part to obtain a fin structure.
[0103] Step 03: deposit an oxide material on the fin structure to form a shallow trench isolation layer.
[0104] Shallow trench isolation, also known as shallow trench isolation, is referred to as STI.
[0105] Specifically, refer to Figure 6(a)-Figure 6(d) As shown, a filling oxide material 6 is deposited in the recess 5 , and the upper edge of the filling oxide material 6 is flush with the uppermost edge of the remaining base layer, thereby forming a shallow trench isolation layer.
[0106] Step 04: deposit polysilicon material to form a polysilicon dummy gate.
[0107] refer to Figure 7(a)-Figure 7(d) As shown, a polysilicon material 7 is deposited to cover the remaining portion of the stack and the upper surface of the shallow trench isolation layer STI to form a polysilicon dummy gate.
[0108] Step 05: Deposit sidewalls on both sides of the polysilicon dummy gate in the second direction.
[0109] refer to Figure 8(a)-Figure 8(d) As shown, in the PMOS tube, a first high dielectric constant material is deposited on both sides of the shallow trench isolation layer STI along the Y-Y' direction to form a sidewall 8. In the NMOS tube, a second high dielectric constant material is deposited on both sides of the shallow trench isolation layer STI along the Y-Y' direction to form a sidewall 4.
[0110] Step 06: Etch the stack to form source and drain regions.
[0111] refer to Figure 9(a)-Figure 9(b) As shown, after etching away the two side portions of the stacked layer, a spare portion 9 is formed on the two sides of the remaining stacked layer.
[0112] The stack is etched along a direction perpendicular to the upper surface of the substrate layer to form a source region and a drain region. The two side surfaces of the remaining portion of the stack in the YY' direction are respectively located on the same plane as the outer surface of a sidewall 8.
[0113] Step 07: Form inner side walls on the remaining part of the stack.
[0114] refer to Figure 10(a)-Figure 10(b) As shown, a portion of the silicon layer 2 in the remaining part of the stack in the PMOS tube is removed on both sides along the XX' direction and then filled with the first high dielectric constant material to form an inner sidewall 10; a portion of the silicon layer 2 in the remaining part of the stack in the NMOS tube is removed on both sides along the XX' direction and then filled with the second high dielectric constant material to form an inner sidewall 16. The sidewall 8 and the inner sidewall 10 are both made of the first high dielectric constant material, and the sidewall 4 and the inner sidewall 16 are both made of the second high dielectric constant material.
[0115] Step 08: Prepare source and drain epitaxial layers.
[0116] refer to Figure 11(a)-Figure 11(b) As shown, in the PMOS tube, boron-doped silicon germanium material is deposited to form the source-drain epitaxial portion 11. In the NMOS tube, boron-doped silicon material is deposited to form the source-drain epitaxial portion 17.
[0117] The cross-sectional views of the semiconductor structures corresponding to Figures 9(a), 10(a) and 11(a) along the first cross-sectional plane are the same as Figure 8(a), and therefore, the cross-sectional views of the semiconductor structures corresponding to Figures 9(a), 10(a) and 11(a) along the first cross-sectional plane are not shown.
[0118] The cross-sectional views of the semiconductor structures corresponding to Figures 9(b), 10(b) and 11(b) along the first cross-sectional plane are the same as Figure 8(c), and therefore, the cross-sectional views of the semiconductor structures corresponding to Figures 9(b), 10(b) and 11(b) along the first cross-sectional plane are not shown.
[0119] Step 08: Release the channel and prepare a high dielectric constant metal gate.
[0120] The polysilicon pseudo gate is removed by etching to realize channel release, and a high dielectric constant layer and a metal gate are deposited. The high dielectric constant layer is located outside the germanium silicon alloy layer and between the metal gate and the doped silicon.
[0121] refer to Figure 12(a)-Figure 12(d) As shown, in the PMOS tube, an oxide material 12 is deposited on the source and drain epitaxial portion 11. The remaining polysilicon material 7 is replaced with a metal gate material to form a metal gate 13. In the NMOS tube, an oxide material 12 is deposited on the source and drain epitaxial portion 17. The remaining polysilicon material 7 is replaced with a metal gate material to form a metal gate 13.
[0122] Step 09: Bond the PMOS and NMOS together to form a complementary field effect transistor with mixed dielectric constant value sidewalls.
[0123] The complementary field effect transistor of the embodiment of the present application may be a gate-all-around complementary field effect transistor, which is called Gate-All-Around Complementary Metal-Oxide-Semiconductor Field-Effect Transistor in English, or GAA CFET for short.
[0124] CFET combines PMOS and NMOS transistors together, making the switching speed and driving capability complementary, thereby improving the overall performance of the transistor.
[0125] Exemplarily, the dielectric constant value of the low dielectric constant material is selected between 1-3.9, and the dielectric material can be, for example, SiNx, SiC, SiCN, SiOCN, SiOC, SiON, BN, SiBN, SiBCN, SiCN, aC, SOG, polymer and other insulating materials; the width of the sidewall can be set between 0.5nm-10nm, and N / P devices with different sidewall widths can be obtained by sequential integration. The width and dielectric constant value are combined and optimized to obtain a balance of N / P device performance and an increase in device speed. The N / P devices in the CFET can be located at the top or bottom, respectively, and low-k materials can also be integrated into the N / P.
[0126] In this example, PMOS and NMOS are prepared separately, and then PMOS and NMOS are bonded together to form a complementary field effect transistor. The dielectric constant of the sidewall of the PMOS tube is different from the dielectric constant of the sidewall of the NMOS tube. In this way, the sidewall of the complementary field effect transistor is a mixed dielectric constant value sidewall. Because different dielectric constants will weaken the interaction of electromagnetic fields, the complementary field effect transistor can reduce the mutual coupling effect. In addition, the difference in dielectric constant of the sidewall can improve the high-frequency characteristics of the transistor. Generally, materials with higher dielectric constants will lead to lower cut-off frequencies, which is very beneficial for improving the speed and response time of CMOS circuits; the sidewall has a variety of dielectric constants, which can improve the electron flow characteristics of the transistor, reduce current leakage, and optimize the balance between power consumption and performance; sidewalls with different dielectric constants can also reduce circuit instability caused by electric field effects and charge accumulation.
[0127] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.
[0128] It should be noted that:
[0129] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.
[0130] The above embodiments only express the implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A complementary field effect transistor, characterized in that: It comprises a first MOS tube and a second MOS tube; the first MOS tube and the second MOS tube are sequentially integrated together by bonding; the side wall of the first MOS tube and the side wall of the second MOS tube have different dielectric constants.
2. The method according to claim 1, characterized in that The first MOS tube is a PMOS tube, and the second MOS tube is an NMOS tube; or, the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube.
3. A method for preparing a complementary field effect transistor, characterized in that: include: Prepare a PMOS tube and an NMOS tube respectively, wherein the side wall of the PMOS tube and the side wall of the NMOS tube have different dielectric constants; Bonding the PMOS transistor and the NMOS transistor together to form a complementary field effect transistor; The method of preparing the PMOS tube or the NMOS tube comprises: preparing a fin structure; preparing a shallow trench isolation layer on the fin-shaped structure; An inner sidewall and a source / drain epitaxial layer are prepared based on the shallow trench isolation layer and the stacked layer; the inner sidewall includes a plurality of parts with different dielectric constant values; Channel release is performed and a metal gate is prepared to obtain a MOS tube.
4. The method according to claim 3, characterized in that The method of preparing the fin-shaped structure comprises: Prepare a laminated epitaxial portion, the laminated epitaxial portion comprising a base layer of doped silicon material and a laminate located on the base layer, the laminate comprising a cross-laminated silicon layer and a germanium-silicon alloy layer; depositing a layer of silicon nitride material on the stack; The silicon nitride material layer, the stacked epitaxial portion and the base layer are etched in a direction perpendicular to the top surface of the base layer to form a fin structure, wherein the fin structure includes a first part, a second part and a third part stacked in sequence from bottom to top, wherein the first part is a part of the base layer, the second part is a remaining part after the silicon nitride material layer is etched, and the third part is a remaining part after the stacked epitaxial portion is etched.
5. The method according to claim 3, characterized in that: The method of preparing the inner sidewall and the source / drain epitaxial layer based on the shallow trench isolation layer and the stacked layer comprises: Depositing polysilicon material to form a polysilicon dummy gate; Deposition is performed on both sides of the polysilicon dummy gate in the second direction to form sidewalls; Etching the stack to form a source region and a drain region; forming inner side walls on the remaining portion of the stack; A source-drain epitaxial layer is prepared on the first portion located on both sides of the inner sidewall, and the first portion is the portion of the base layer belonging to the fin structure.
6. The method according to claim 3, characterized in that The channel release comprises: The silicon layer in the stack is replaced with a high dielectric constant material layer to achieve channel release.
7. The method according to claim 3, characterized in that The method of preparing the metal gate comprises: Etching and removing the polysilicon dummy gate; A metal material is deposited in the space formed after removing the polysilicon dummy gate to form the metal gate.
8. The method according to claim 3, characterized in that The step of bonding the PMOS transistor and the NMOS transistor together to form a complementary field effect transistor comprises: Thinning the base layer of the PMOS tube to obtain a PMOS tube with a thinned base layer; The PMOS transistor after the substrate layer is thinned is bonded and integrated with the NMOS transistor to form a complementary field effect transistor.
9. The method according to claim 3, characterized in that: The step of bonding the PMOS transistor and the NMOS transistor together to form a complementary field effect transistor comprises: Thinning the base layer of the NMOS tube to obtain an NMOS tube with a thinned base layer; The NMOS transistor after the substrate layer is thinned is bonded and integrated with the PMOS transistor to form a complementary field effect transistor.
10. The method according to claim 3, characterized in that: The width of the side walls of the PMOS tube and the NMOS tube are both in the range of 0.5 nm to 10 nm, and the thickness of the side walls of the PMOS tube and the NMOS tube are different.