Preparation method of semiconductor structure, semiconductor structure, device and equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment, the semiconductor structure comprises a first semiconductor structure and a second semiconductor structure which are stacked in a first direction, the first semiconductor structure is a complementary metal oxide semiconductor (CMOS), and the second semiconductor structure is a CMOS image sensor; the method comprises the following steps: forming an active structure on a substrate; the active structure comprises a first active structure and a second active structure; forming a first semiconductor structure based on the first active structure; the first semiconductor structure comprises a first transistor with a first polarity and a second transistor with a second polarity; reversing and thinning the substrate until the second active structure is exposed; forming a second semiconductor structure based on the second active structure; the second semiconductor structure comprises a third transistor of the first polarity and an image sensor unit; the third transistor and the image sensor unit are arranged side by side in the second direction.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] CMOS image sensor is an optical sensor that converts light signals into electrical signals and converts them into digital signals through readout circuits. It is widely used in the field of vision and is the core component of camera modules. CMOS image sensors are often used in electronic devices such as high-end mobile phone cameras, digital cameras, and digital SLR cameras.

[0003] Currently, the integration of CMOS image sensors and logic circuits suffers from poor process compatibility. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus to solve the process compatibility problem of a complementary metal oxide semiconductor (CMOS) logic unit and a CMOS image sensor.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, wherein the semiconductor structure includes a first semiconductor structure and a second semiconductor structure stacked in a first direction, the first semiconductor structure is a CMOS, and the second semiconductor structure is a CMOS image sensor; the method includes: forming an active structure on a substrate; the active structure includes a first active structure and a second active structure; based on the first active structure, forming a first semiconductor structure; the first semiconductor structure includes a first transistor of a first polarity and a second transistor of a second polarity; the first transistor and the second transistor are arranged side by side in the second direction; the second direction is perpendicular to the first direction; flipping and thinning the substrate until the second active structure is exposed; based on the second active structure, forming a second semiconductor structure; the second semiconductor structure includes a third transistor of a first polarity and an image sensor unit; the third transistor and the image sensor unit are arranged side by side in the second direction.

[0006] In some possible embodiments, the second active structure is divided into a first part and a second part in the second direction; based on the second active structure, a second semiconductor structure is formed, including: based on the first part of the second active structure, a third source-drain structure and a third gate structure in a third transistor are formed; based on the second part of the second active structure, a photodiode in an image sensor unit is formed; a second metal interconnection layer in the second semiconductor structure is formed on the third gate structure and the photodiode; an optical element is set in the second metal interconnection layer; and the optical element is connected to the photodiode.

[0007] In some possible embodiments, a photodiode in an image sensor unit is formed based on a second portion of a second active structure, including: forming a first mask on the second portion of the second active structure; and performing ion implantation on the second portion of the second active structure under the masking action of the first mask to form a photodiode.

[0008] In some possible embodiments, the optical element includes a filter and a microlens; the optical element is set in the second metal interconnection layer, including: forming a second mask on the second metal interconnection layer; under the masking action of the second mask, etching the second metal interconnection layer until the photodiode is exposed to form a first groove; and stacking the filter and the microlens in the first groove in sequence.

[0009] In some possible embodiments, the first active structure is divided into a third part and a fourth part in the second direction; based on the first active structure, a first semiconductor structure is formed, including: based on the third part of the first active structure, a first transistor of a first polarity is formed; based on the fourth part of the first active structure, a second transistor of a second polarity is formed.

[0010] In some possible embodiments, based on the third part of the first active structure, a first transistor of a first polarity is formed, including: performing source-drain epitaxial growth in the source-drain region of the first transistor to form a first source-drain structure in the first transistor; depositing metal material in the gate region of the first transistor to form a first gate structure in the first transistor; and performing post-processing on the first gate structure to obtain a metal interconnection layer in the first transistor.

[0011] In some possible embodiments, a second transistor of a second polarity is formed based on the fourth portion of the first active structure, including: performing source-drain epitaxial growth in the source-drain region of the second transistor to form a second source-drain structure in the second transistor; depositing metal material in the gate region of the second transistor to form a second gate structure in the second transistor; and performing post-processing on the second gate structure to obtain a metal interconnection layer in the second transistor.

[0012] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by the method described in the first aspect, and the semiconductor structure includes: a first semiconductor structure; a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked in a first direction; wherein the first semiconductor structure includes a first transistor of a first polarity and a second transistor of a second polarity, and the second semiconductor structure includes a third transistor of the first polarity and an image sensor unit; the first transistor and the second transistor are arranged side by side in the second direction; the second direction is perpendicular to the first direction; the third transistor and the image sensor unit are arranged side by side in the second direction.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, the first semiconductor structure and the second semiconductor structure are stacked, and the first semiconductor structure is a CMOS logic unit, and the second semiconductor structure is a CMOS image sensor. Through the flipping process, the first semiconductor structure and the second semiconductor structure are stacked "back to back" to achieve the process compatibility of the CMOS logic unit and the CMOS image sensor.

[0016] Furthermore, while achieving homogeneous integration of CMOS logic units and CMOS image sensors, no additional area is occupied, thereby improving the integration density of the semiconductor structure; due to the interconnection between the first semiconductor structure and the second semiconductor structure, the bandwidth of the semiconductor structure is higher, the interconnection delay is low, and it is more friendly to the performance of the overall system (i.e., the semiconductor structure).

[0017] Furthermore, the preparation of the first semiconductor structure and the preparation of the second semiconductor structure are independent of each other, and there is no need to consider the complex and cumbersome process compatibility issues of CMOS logic circuits and CMOS image sensors, which has great advantages in improving the yield and performance of the overall system.

[0018] Furthermore, because the distance between the preparation of the first semiconductor structure and the second semiconductor structure is very close, the system performance degradation caused by interconnection delay can be greatly reduced, which is very friendly to future artificial intelligence (AI), sensing, storage and computing integration and other environments.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0021] Figure 1 This is the first example of the integration of a CMOS image sensor and a logic circuit;

[0022] Figure 2 A second example of the integration method of a CMOS image sensor and a logic circuit;

[0023] Figure 3 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0024] Figure 4 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application;

[0025] FIG. 5A to FIG. 5D A schematic diagram of a process for preparing a semiconductor structure in an embodiment of the present application;

[0026] Figure 6 This is a schematic diagram of a second structure of a semiconductor structure in an embodiment of the present application;

[0027] The above pictures:

[0028] 10. semiconductor structure; 11. first semiconductor structure; 111. first transistor; 1111. first interlayer dielectric layer; 1112. first gate dielectric layer; 1113. first gate structure; 1114. first source-drain structure; 112. second transistor; 1121. second interlayer dielectric layer; 1122. second gate dielectric layer; 1123. second gate structure; 1124. second source-drain structure; 113. first metal interconnect layer; 12. second semiconductor structure; 121. third transistor; 1211. third interlayer dielectric layer; 1 212, third gate dielectric layer; 1213, third gate structure; 1214, third source-drain structure; 122, image sensor unit; 1221, fourth interlayer dielectric layer; 1222, photodiode; 1224, filter; 1225, microlens; 123, second metal interconnect layer; 13, insulating layer; 14, carrier wafer; 21, substrate; 22, fin structure; 221, first fin structure; 222, second fin structure; 23, shallow trench isolation structure; 31, first nanosheet structure; 32, second nanosheet structure. DETAILED DESCRIPTION

[0029] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0030] CMOS image sensor is an optical sensor that converts light signals into electrical signals and converts them into digital signals through readout circuits. It is widely used in the field of vision and is the core component of camera modules. CMOS image sensors are often used in electronic devices such as high-end mobile phone cameras, digital cameras, and digital SLR cameras.

[0031] At present, there are several ways to integrate CMOS image sensors and logic circuits: 1. Integrate the CMOS image sensor chip and the logic computing chip (i.e., logic circuit) in the same packaging substrate through traditional packaging methods; 2. Figure 1 This is the first example of the integration of CMOS image sensors and logic circuits, see Figure 1 As shown, through silicon via (TSV) technology is used to interconnect the pixel array and logic circuit in the peripheral area of ​​the chip; 3. Figure 2 For a second example of the integration of a CMOS image sensor and a logic circuit, see Figure 2 As shown, the CMOS image sensor chip and the logic computing chip are integrated together through copper-copper hybrid bonding to form a three-dimensional stack.

[0032] However, the above-mentioned method 1 is implemented by traditional packaging means, and the distance between the logic unit and the image sensor unit is relatively far, so the performance is poor; method 2 uses TSV technology to interconnect the pixel array and the logic circuit in the peripheral area of ​​the chip, and the bandwidth is relatively low; the logic circuit and the CMOS image sensor of method 3 are homogeneously integrated and are relatively close to each other, and the circuit design is relatively flexible, but its process is complex and the wafer bonding process has high alignment requirements.

[0033] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure to solve the process compatibility problem of a CMOS logic unit and a CMOS image sensor.

[0034] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0035] In some embodiments, the semiconductor structure includes: a first semiconductor structure; a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked in a first direction; wherein the first semiconductor structure includes a first transistor of a first polarity and a second transistor of a second polarity, and the second semiconductor structure includes a third transistor of the first polarity and an image sensor unit; the first transistor and the second transistor are arranged side by side in the second direction; the second direction is perpendicular to the first direction; the third transistor and the image sensor unit are arranged side by side in the second direction.

[0036] In the embodiment of the present application, the first transistor, the second transistor and the third transistor in the semiconductor structure may be transistors of the same type, such as any of the following: a fin-type field effect transistor; a full-surround gate transistor; a planar transistor.

[0037] Figure 4 The semiconductor structure composed of fin field effect transistors is combined below Figure 4The schematic diagram of the semiconductor structure shown illustrates the method for preparing the semiconductor structure provided in the embodiment of the present application.

[0038] Figure 3 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application. In some embodiments, the semiconductor structure includes a first semiconductor structure and a second semiconductor structure stacked in a first direction. Figure 3 As shown, the method for preparing the semiconductor structure may include:

[0039] S301, forming an active structure on a substrate, wherein the active structure includes a first active structure and a second active structure.

[0040] It can be understood that an active structure can be formed by etching the substrate. The active structure includes a first active structure and a second active structure that are stacked; the semiconductor structure includes a first semiconductor structure and a second semiconductor structure that are stacked; the first semiconductor structure is formed based on the first active structure, and the second semiconductor structure is formed based on the second active structure.

[0041] In some embodiments, when the first transistor, the second transistor, and the third transistor are fin-type field effect transistors, the active structure is a fin structure.

[0042] In some embodiments, when the first transistor, the second transistor and the third transistor are all-around gate transistors, the active structure is a columnar structure; and the columnar structure is a stack formed by sequentially stacking a first semiconductor material and a second semiconductor material; for example, the first semiconductor material may be silicon (Si), and the second semiconductor material may be silicon germanium (SiGe), and the second semiconductor material serves as a sacrificial material. In the subsequent preparation process of the transistor, the second semiconductor material can be removed to form a nanosheet or nanolayer structure in the all-around gate transistor.

[0043] In some embodiments, when the first transistor, the second transistor, and the third transistor are planar transistors, the active structure is a bulk structure.

[0044] In some embodiments, since the first active structure and the second active structure are formed through the same process, the first semiconductor structure formed based on the first active structure and the second semiconductor structure formed based on the second active structure share the same active region.

[0045] In the embodiment of the present application, the active region is a collective name for the source region, the drain region and the channel region.

[0046] S302, based on the first active structure, forming a first semiconductor structure, wherein the first semiconductor structure comprises a first transistor of a first polarity and a second transistor of a second polarity; the first transistor and the second transistor are arranged side by side in a second direction; and the second direction is perpendicular to the first direction.

[0047] It can be understood that the polarities of the first transistor and the second transistor are different, and the first transistor and the second transistor are complementary transistors, that is, the first polarity and the second polarity are complementary. Based on the complementary first transistor and the second transistor, the first semiconductor structure is a complementary metal oxide semiconductor (CMOS). The first polarity can be N-type, and the second polarity can be P-type, then the first transistor is an N-channel (metal-oxide-semiconductor field-effect transistor, MOS) tube, and the second transistor is a P-channel MOS tube.

[0048] S303, flipping over and thinning the substrate until the second active structure is exposed.

[0049] It is understandable that after forming the first semiconductor structure, the first semiconductor structure can be flipped so that the substrate is placed upward, and then the substrate is thinned until the surface of the second active structure away from the first active structure is exposed. The first semiconductor structure and the second semiconductor structure formed based on the flipping process are arranged "back to back".

[0050] In some embodiments, the substrate may be thinned by a chemical-mechanical planarization (CMP) process.

[0051] In some possible implementations, before the above S303, the method for preparing the above semiconductor structure may further include: depositing an insulating material on a surface of the first semiconductor structure away from the second active structure to form an insulating layer; and bonding the insulating layer to a carrier wafer.

[0052] In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped first semiconductor structure after inversion, thereby effectively preventing the first semiconductor structure from being broken by external force during the preparation of the second semiconductor structure.

[0053] It should be noted that the insulating material forming the insulating layer can be selected according to actual needs, and the embodiments of the present application do not specifically limit this.

[0054] S304, forming a second semiconductor structure based on the second active structure, wherein the second semiconductor structure includes a third transistor of the first polarity and an image sensor unit; the third transistor and the image sensor unit are arranged side by side in the second direction.

[0055] It is understandable that after the second active structure is exposed, a third transistor and an image sensor unit can be formed based on a standard process for manufacturing transistors and image sensors. The third transistor is a transistor of the first polarity, that is, the third transistor is an N-channel MOS transistor.

[0056] In some possible embodiments, the second active structure is divided into a first part and a second part in the second direction; the above S304 may include: forming a second semiconductor structure based on the second active structure, including: forming a third source-drain structure and a third gate structure in a third transistor based on the first part of the second active structure; forming a photodiode in an image sensor unit based on the second part of the second active structure; forming a second metal interconnection layer in the second semiconductor structure on the third gate structure and the photodiode; setting an optical element in the second metal interconnection layer; and connecting the optical element to the photodiode.

[0057] It can be understood that the third transistor and the image sensor unit in the second semiconductor structure are arranged side by side. Based on this, the second active structure can be divided into two parts arranged side by side, namely the first part and the second part; the third transistor is formed based on the first part of the second active structure, and the image sensor unit is formed based on the second part of the second active structure.

[0058] In some embodiments, after exposing the second active structure, a third source-drain structure and a third gate structure in the third transistor can be formed based on the first portion of the second active structure; then, a photodiode is formed based on the second portion of the second active structure; post-processing is performed on the third gate structure and the photodiode to form a second metal interconnection layer in the second semiconductor structure; an optical element in contact with the photodiode is set in the second metal interconnection layer; and thus, the second semiconductor structure is formed.

[0059] In some embodiments, the photodiode may be a PIN diode or a PN junction diode; other types of photodiodes may also be selected according to actual needs, and the embodiments of the present application do not specifically limit this.

[0060] In some possible embodiments, the formation of a photodiode in the image sensor unit based on the second part of the second active structure may include: forming a first mask on the second part of the second active structure; and performing ion implantation on the second part of the second active structure under the mask of the first mask to form a photodiode.

[0061] It can be understood that a mask material is first deposited on the second active structure, and a portion of the mask material is etched to obtain a first mask plate with a preset pattern; under the masking action of the first mask plate, the second portion of the second active structure is subjected to ion implantation, and P-type ions can be implanted first, and then N-type ions can be implanted to form a photodiode.

[0062] In some possible embodiments, the optical element includes a filter and a microlens; the above-mentioned setting of the optical element in the second metal interconnection layer may include: forming a second mask on the second metal interconnection layer; under the masking action of the second mask, etching the second metal interconnection layer until the photodiode is exposed to form a first groove; and stacking the filter and the microlens in the first groove in sequence.

[0063] It can be understood that after the second metal interconnection layer is formed, the second metal interconnection layer covers the photodiode, and a second mask plate can be formed by depositing a mask material on the second metal interconnection layer; then, under the action of the second mask plate, the second metal interconnection layer is etched, and the etching stops at the photodiode to form a first groove; optical elements such as stacked filters and microlenses are sequentially formed in the first groove to form an image sensor unit.

[0064] It should be noted that the formation process of the second mask is the same as the formation process of the first mask, and this embodiment of the present application will not be described in detail.

[0065] In some possible implementations, the first active structure is divided into a third part and a fourth part in the second direction; the above S302 may include: forming a first transistor of a first polarity based on the third part of the first active structure; forming a second transistor of a second polarity based on the fourth part of the first active structure.

[0066] It can be understood that the first transistor and the second transistor in the first semiconductor structure are arranged side by side. Based on this, the first active structure can be divided into two parts arranged side by side, namely the third part and the fourth part; the first transistor is formed based on the third part of the first active structure, and the second transistor is formed based on the fourth part of the first active structure.

[0067] In some possible embodiments, the above-mentioned formation of the first transistor of the first polarity based on the third part of the first active structure may include: performing source-drain epitaxial growth in the source-drain region of the first transistor to form a first source-drain structure in the first transistor; depositing metal material in the gate region of the first transistor to form a first gate structure in the first transistor; and performing post-processing on the first gate structure to obtain a metal interconnection layer in the first transistor.

[0068] It is understandable that the first transistor of the first polarity may be manufactured according to a standard process for manufacturing an N-channel MOS transistor.

[0069] In some embodiments, the process of forming the first transistor may include: opening the first gate region of the first transistor by photolithography, depositing a semiconductor material in the first gate region to form a first dummy gate structure; and forming a first spacer on both sides of the first dummy gate structure. The third portion of the first active structure is etched to provide a source-drain groove of the first transistor. Using the first spacer as a mask, a strained material such as silicon germanium or silicon carbide is formed in the source-drain groove of the first transistor by selective epitaxial growth to fill the source-drain groove of the first transistor, and then a first source-drain structure is formed on the strained material by a heavy doping process. An insulating material (such as silicon dioxide (SiO2)) is deposited on the third portion of the first active structure and the first source-drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer may cover the third portion of the first active structure and the first source-drain structure. The first dummy gate structure is removed by etching to expose the first gate region, and an insulating material is deposited on the first active structure located in the first gate region to form a first gate dielectric layer of the first transistor. A metal material is deposited in the first gate region to form a first gate structure of the first transistor. The first interlayer dielectric layer is etched to a portion of the area above the first source-drain structure until the upper surface of the first source-drain structure is exposed to form a first source-drain metal groove. A metal material is deposited in the first source-drain metal groove to form a first source-drain metal structure. Interconnection line dielectric deposition, metal line formation, lead pad formation, and other processes are performed on the first gate structure and the first source-drain metal to form a metal interconnect layer of the first transistor.

[0070] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the third source-drain structure, the source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0071] In some possible embodiments, the formation of the second transistor of the second polarity based on the fourth part of the first active structure may include: performing source-drain epitaxial growth in the source-drain region of the second transistor to form a second source-drain structure in the second transistor; depositing metal material in the gate region of the second transistor to form a second gate structure in the second transistor; and performing post-processing on the second gate structure to obtain a metal interconnection layer in the second transistor.

[0072] It is understandable that the second transistor of the second polarity can be prepared according to the standard process for preparing a P-channel MOS transistor.

[0073] In some embodiments, the process of forming the second transistor may include: opening the second gate region of the second transistor by photolithography, depositing a semiconductor material in the second gate region to form a second dummy gate structure; and forming a second spacer on both sides of the second dummy gate structure. The fourth portion of the second active structure is etched to provide a source-drain groove of the second transistor. Using the second spacer as a mask, a strained material such as silicon germanium or silicon carbide is formed in the source-drain groove of the second transistor by selective epitaxial growth to fill the source-drain groove of the second transistor, and then a second source-drain structure is formed on the strained material by a heavy doping process. An insulating material is deposited on the fourth portion of the second active structure and the second source-drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer may cover the fourth portion of the second active structure and the second source-drain structure. The second dummy gate structure is removed by etching to expose the second gate region, and an insulating material is deposited on the first active structure located in the second gate region to form a second gate dielectric layer of the second transistor. A metal material is deposited in the second gate region to form a second gate structure of the second transistor. The second interlayer dielectric layer is etched to a portion of the area above the second source-drain structure until the upper surface of the second source-drain structure is exposed to form a second source-drain metal groove. A metal material is deposited in the second source-drain metal groove to form a second source-drain metal structure. Interconnection line dielectric deposition, metal line formation, lead pad formation, etc. are performed on the second gate structure and the second source-drain metal to form a metal interconnect layer of the second transistor.

[0074] It should be noted that the metal interconnect layer in the first transistor and the metal interconnect layer in the second transistor together constitute a first metal interconnect layer in the first semiconductor structure.

[0075] In the embodiment of the present application, the metal materials of the gate structure (the first gate structure, the second gate structure and the third gate structure) may include but are not limited to: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), and the materials of the first gate structure, the second gate structure and the third gate structure may be selected according to actual conditions and are not limited to the metal materials listed above.

[0076] It should be noted that the same structures in the first transistor and the second transistor can be formed in the same process, for example, the source-drain structure (i.e., the first source-drain structure and the second source-drain structure), the spacer (i.e., the first spacer and the second spacer), the interlayer dielectric layer (i.e., the first interlayer dielectric layer and the second interlayer dielectric layer) and the metal interconnection layer (i.e., the first metal interconnection layer and the second metal interconnection layer).

[0077] In some embodiments, the first semiconductor structure serves as a complementary metal oxide semiconductor, wherein the first gate structure and the second gate structure may be formed separately, that is, the first dummy gate structure corresponding to the position of the first gate structure may be first removed by etching to expose the first gate region, and a metal material may be deposited in the first gate region to form the first gate structure; then, the second dummy gate structure corresponding to the second dummy gate structure may be removed by etching to expose the second gate region, and a metal material may be deposited in the second gate region to form the second gate structure.

[0078] In the embodiment of the present application, the semiconductor material forming the dummy gate structure (i.e., the first dummy gate structure, the second dummy gate structure, and the third dummy gate structure) may include, but is not limited to: amorphous carbon, amorphous silicon, etc., or may be other semiconductor materials, and the embodiment of the present application does not specifically limit this.

[0079] In some embodiments, the process of forming the third transistor may include: opening the third gate region of the third transistor by photolithography, depositing semiconductor material in the third gate region to form a third dummy gate structure; and forming a third spacer on both sides of the third dummy gate structure. Etching the first part of the second active structure to provide a source-drain groove of the third transistor. Using the third spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the third transistor by selective epitaxial growth to fill the source-drain groove of the third transistor, and then forming a third source-drain structure on the strained material by a heavy doping process. Depositing an insulating material on the first part of the second active structure and the third source-drain structure to form a third interlayer dielectric layer; the third interlayer dielectric layer may cover the first part of the first active structure and the third source-drain structure. Removing the third dummy gate structure by etching to expose the third gate region, depositing an insulating material on the second active structure located in the third gate region to form a third gate dielectric layer of the third transistor. Depositing a metal material in the third gate region to form a third gate structure of the third transistor. The third interlayer dielectric layer is etched to a portion of the area above the third source-drain structure until the upper surface of the third source-drain structure is exposed to form a third source-drain metal groove. A metal material is deposited in the third source-drain metal groove to form a third source-drain metal structure. Interconnection line dielectric deposition, metal line formation, lead pad formation, and other processes are performed on the third gate structure and the third source-drain metal to form a metal interconnect layer of the third transistor.

[0080] In some embodiments, the process of forming the image sensor unit may include: depositing an insulating material on the second portion of the second active structure to form a fourth interlayer dielectric layer; the fourth interlayer dielectric layer may cover the second portion of the first active structure. Performing ion implantation on the second portion of the second active structure to form a photodiode. Depositing dielectric material on the photodiode and the fourth interlayer dielectric layer may form a metal interconnect layer of the image sensor unit. Etching the metal interconnect layer in the image sensor unit to form a first groove, forming a filter in the first groove and on the photodiode, and forming a microlens on the filter.

[0081] It should be noted that the metal interconnection layer in the third transistor and the metal interconnection layer in the image sensor unit together constitute the second metal interconnection layer in the second semiconductor structure.

[0082] In some embodiments, in order to achieve isolation between the first semiconductor structure and the second semiconductor structure, a silicon on insulator (SOI) substrate may be used to prepare the semiconductor structure. The insulating layer in the SOI substrate is located between the first active structure and the second active structure, which can effectively isolate the first active structure and the second active structure, and further isolate the first semiconductor structure and the second semiconductor structure.

[0083] In some embodiments, in order to achieve isolation between the first semiconductor structure and the second semiconductor structure, ion implantation may be performed between the first active structure and the second active structure to achieve electrical isolation between the first active structure and the second active structure, thereby isolating the first semiconductor structure and the second semiconductor structure.

[0084] In some embodiments, the ions implanted between the first active structure and the second active structure may include, but are not limited to, any one of the following: P-type ions, N-type ions, and oxygen ions.

[0085] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the case where the first transistor, the second transistor and the third transistor are fin-type field effect transistors and the substrate is an SOI substrate as an example. Figure 4 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application. Figure 4 (a) is a design layout of the semiconductor structure. It should be noted that, for ease of understanding, only the fin structure, gate structure and source-drain structure are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure made along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure made along the cross-sectional direction of the fin structure corresponding to the first transistor and the third transistor (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure made along the cross-sectional direction of the fin structure corresponding to the third transistor and the image sensor unit (i.e., CC' direction).

[0086] Figure 4 The semiconductor structure 10 shown may be FIG. 5A to FIG. 5D The process shown is prepared FIG. 5A to FIG. 5D A schematic diagram of the preparation process of the semiconductor structure in an embodiment of the present application.

[0087] In one example, the preparation process of the semiconductor structure 10 may include the following steps:

[0088] Step 1: Provide a substrate 21 (see Figure 5A (a)).

[0089] Step 2: Etch the substrate by sidewall etching to form a fin structure 22 (see Figure 5B (a)). The number of the first fin structures 221 corresponding to the first semiconductor structure 11 is 4, and the number of the second fin structures 222 corresponding to the second semiconductor structure 12 is 2. The first fin structure 221 and the second fin structure 222 are isolated by an insulating layer in the SOI substrate.

[0090] Step 3: depositing insulating material on the first fin structure 221, the second fin structure 222 and the substrate 21 to form a shallow trench isolation structure 23. At this time, the height of the shallow trench isolation structure 23 is greater than the height of the fin structure 22; removing the shallow trench isolation structure 23 that wraps the first fin structure 221 through a CMP process and a selective etching process to expose the first fin structure 221 (see Figure 5A (c)).

[0091] Step 4: Based on the first fin structure 221, a first interlayer dielectric layer 1111, a second interlayer dielectric layer 1121, a first gate dielectric layer 1112, a second gate dielectric layer 1122, a first gate structure 1113, a second gate structure 1123, a first source-drain structure 1114, a second source-drain structure 1124 and a first metal interconnect layer 113 are formed (see Figure 5B At this point, the first transistor 111 and the second transistor 112 are formed.

[0092] Step 5: Deposit an insulating material on the first semiconductor structure 11 to form an insulating layer 13; bond the insulating layer 13 to the carrier wafer 14 (see Figure 5B (b)).

[0093] Step 6: Flip the first semiconductor structure 11 so that the substrate 21 faces upward (see Figure 5B (c)).

[0094] Step 7: Thinning the substrate 21 so that the surface of the second fin structure 222 away from the first fin structure 221 is exposed (see Figure 5C (a)).

[0095] Step 8: Based on the second fin structure 222, a third gate dielectric layer 1212, a third gate structure 1213 and a third source-drain structure 1214 in the third transistor 121 are formed (see Figure 5C (b)).

[0096] Step 9: Perform ion implantation on the second fin structure 222 corresponding to the second transistor 112 to form a photodiode 1222 in the image sensor unit 122 (see Figure 5C (c)).

[0097] Step 10: forming a third interlayer dielectric layer 1211 in the third transistor 121 and a fourth interlayer dielectric layer 1221 in the image sensor unit 122; forming a second metal interconnect layer 123 in the second semiconductor structure 12; and providing a filter 1224 and a microlens 1225 in the second metal interconnect layer 123 and on the photodiode 1222 (see Figure 5D ).

[0098] At this point, the semiconductor structure 10 is manufactured according to the above manufacturing method.

[0099] In one embodiment, the semiconductor structure provided in the embodiment of the present application is described by taking the case where the first transistor, the second transistor and the third transistor are all-around gate transistors and the substrate is an SOI substrate as an example. Figure 6 This is a schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application. Figure 6 (a) is the design layout of the semiconductor structure. It should be noted that, for ease of understanding, only the nanosheet structure, gate structure and source-drain structure are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the nanosheet structure corresponding to the first transistor and the third transistor (i.e., BB' direction).

[0100] In some embodiments, see Figure 6 As shown, the first nanosheet structure 31 in the first semiconductor structure 11 and the second nanosheet structure 32 in the second semiconductor structure 12 are formed by removing the sacrificial material (i.e., the second semiconductor material) in the active structure. It should be noted that, in addition to the first nanosheet structure 31 and the second nanosheet structure 32, Figure 6 The semiconductor structure 10 shown is Figure 4 The preparation method of the semiconductor structure shown is the same, and the embodiments of the present application do not specifically limit this.

[0101] In an embodiment of the present application, a first semiconductor structure and a second semiconductor structure are stacked, and the first semiconductor structure is a CMOS logic unit, and the second semiconductor structure is a CMOS image sensor. Through a flip-chip process, the first semiconductor structure and the second semiconductor structure are stacked "back to back" to solve the process compatibility problem between the CMOS logic unit and the CMOS image sensor.

[0102] Furthermore, while achieving homogeneous integration of CMOS logic units and CMOS image sensors, no additional area is occupied, thereby improving the integration density of the semiconductor structure; due to the interconnection between the first semiconductor structure and the second semiconductor structure, the bandwidth of the semiconductor structure is higher, the interconnection delay is low, and it is more friendly to the performance of the overall system (i.e., the semiconductor structure).

[0103] Furthermore, the preparation of the first semiconductor structure and the preparation of the second semiconductor structure are independent of each other, and there is no need to consider the complex and cumbersome process compatibility issues of CMOS logic circuits and CMOS image sensors, which has great advantages in improving the yield and performance of the overall system.

[0104] Furthermore, because the distance between the preparation of the first semiconductor structure and the second semiconductor structure is very close, the system performance degradation caused by interconnection delay can be greatly reduced, which is very friendly to future artificial intelligence (AI), sensing, storage and computing integration and other environments.

[0105] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application can be detected by TEM slicing, for example, the first semiconductor structure includes a first transistor and a second transistor, the second semiconductor structure includes a third transistor and an image sensor unit, and the first semiconductor structure and the second semiconductor structure share the same active area.

[0106] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 4 and Figure 6 The semiconductor structure shown will not be described in detail here.

[0107] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 4 and Figure 6 , I will not go into details here.

[0108] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0109] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The semiconductor structure comprises a first semiconductor structure and a second semiconductor structure stacked in a first direction, the first semiconductor structure is a complementary metal oxide semiconductor (CMOS), and the second semiconductor structure is a CMOS image sensor; the method comprises: An active structure is formed on a substrate; the active structure comprises a first active structure and a second active structure; Based on the first active structure, the first semiconductor structure is formed; the first semiconductor structure includes a first transistor of a first polarity and a second transistor of a second polarity; the first transistor and the second transistor are arranged side by side in a second direction; the second direction is perpendicular to the first direction; Flipping and thinning the substrate until the second active structure is exposed; Based on the second active structure, a second semiconductor structure is formed; the second semiconductor structure includes a third transistor of the first polarity and an image sensor unit; the third transistor and the image sensor unit are arranged side by side in the second direction.

2. The method according to claim 1, characterized in that: The second active structure is divided into a first portion and a second portion in the second direction; The forming of a second semiconductor structure based on the second active structure comprises: Based on the first part of the second active structure, forming a third source-drain structure and a third gate structure in the third transistor; forming a photodiode in the image sensor unit based on a second portion of the second active structure; forming a second metal interconnect layer in a second semiconductor structure on the third gate structure and the photodiode; An optical element is arranged in the second metal interconnection layer; the optical element is connected to the photodiode.

3. The method according to claim 2, characterized in that The forming of a photodiode in the image sensor unit based on the second portion of the second active structure comprises: forming a first mask on a second portion of the second active structure; Under the masking effect of the first mask plate, ion implantation is performed on the second portion of the second active structure to form the photodiode.

4. The method according to claim 2, characterized in that: The optical element includes a filter and a microlens; The optical element is arranged in the second metal interconnection layer, comprising: forming a second mask on the second metal interconnection layer; Under the masking action of the second mask plate, etching the second metal interconnection layer until the photodiode is exposed to form a first groove; The filter and the microlens are stacked in sequence in the first groove.

5. The method according to claim 1, characterized in that The first active structure is divided into a third part and a fourth part in the second direction; The forming of the first semiconductor structure based on the first active structure includes: Based on the third portion of the first active structure, forming a first transistor of a first polarity; A second transistor of a second polarity is formed based on the fourth portion of the first active structure.

6. The method according to claim 5, characterized in that The forming of a first transistor of a first polarity based on the third part of the first active structure comprises: Performing source-drain epitaxial growth in the source-drain region of the first transistor to form a first source-drain structure in the first transistor; Depositing a metal material in a gate region of the first transistor to form a first gate structure in the first transistor; A back-end process is performed on the first gate structure to obtain a metal interconnection layer in the first transistor.

7. The method according to claim 5, characterized in that The forming of a second transistor of a second polarity based on the fourth portion of the first active structure comprises: Performing source-drain epitaxial growth in the source-drain region of the second transistor to form a second source-drain structure in the second transistor; Depositing a metal material in a gate region of the second transistor to form a second gate structure in the second transistor; A back-end process is performed on the second gate structure to obtain a metal interconnection layer in the second transistor.

8. A semiconductor structure, characterized in that: Prepared by the method according to any one of claims 1 to 7, the semiconductor structure comprises: a first semiconductor structure; A second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked in a first direction; Among them, the first semiconductor structure is a complementary metal oxide semiconductor CMOS, and the second semiconductor structure is a CMOS image sensor; the first semiconductor structure includes a first transistor of a first polarity and a second transistor of a second polarity, and the second semiconductor structure includes a third transistor of the first polarity and an image sensor unit; the first transistor and the second transistor are arranged side by side in a second direction; the second direction is perpendicular to the first direction; the third transistor and the image sensor unit are arranged side by side in the second direction.

9. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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