Photodiodes, diode components and optical filters

Abstract

The present application provides a photodiode, a diode assembly and an optical filter, which relate to the technical field of optical communication. The photodiode includes: a substrate, a first deep well, a second well and a doped region; wherein the first deep well is arranged on the substrate, the second well is arranged on the first deep well, and the doped region is arranged on the second well; the doped region includes a first type of wide doped region and a second type of narrow doped region, the first type of wide doped region and the second type of narrow doped region are alternately distributed on the second well, and the first type of wide doped region or the second type of narrow doped region forms an electrode structure with the second well. The diode assembly includes a photodiode; a plurality of photodiodes form a fully differential array. The optical filter includes a time reading circuit, a clock circuit, and a diode assembly; the diode assembly is used to perform photoelectric conversion on the received optical signal to obtain a current signal; the time reading circuit is used to perform analog-to-digital conversion based on the current signal to obtain a transmission signal; the clock circuit is used to calibrate the clock phase.

Description

Technical Field

[0001] The present application relates to the field of optical communication technology, and in particular to a photodiode, a diode assembly and an optical filter. Background Art

[0002] A quantum computer is a computer that uses the principles of quantum mechanics to process information. Unlike traditional classical computers, quantum computers use quantum bits (qubits) as the basic unit of information, which can improve the efficiency of processing large amounts of data and complex calculations. At room temperature, optical communication is becoming the preferred I / O solution in high-performance systems. The communication interface using optical fiber as the communication medium will not increase the refrigeration burden of the cryogenic cavity. In addition, optical communication has high bandwidth, low signal attenuation, and is resistant to electromagnetic interference. It can realize wavelength division multiplexing, thereby reducing the number of communication interfaces and improving the integration of cryogenic measurement and control systems.

[0003] Since low temperature will affect the movement efficiency of carriers, in order to improve the communication speed of the communication interface under low temperature conditions, integrated serializers and passive backscattering communication schemes are usually used. However, these methods will cause the existing communication interfaces to have high energy consumption, severe crosstalk, poor stability, poor photoelectric detection responsiveness, etc., resulting in poor optical communication effects and unable to meet current optical communication needs. Summary of the invention

[0004] In view of this, an object of the embodiments of the present application is to provide a photodiode, a diode assembly and an optical filter to improve the problem of poor optical communication effect existing in the prior art.

[0005] In order to solve the above problems, in a first aspect, an embodiment of the present application provides a photodiode, the photodiode comprising: a substrate, a first deep well, a second well and a doped region;

[0006] Wherein, the first deep well is arranged on the substrate, the second well is arranged on the first deep well, and the doped region is arranged on the second well;

[0007] The doped region includes a first type wide doped region and a second type narrow doped region, the first type wide doped region and the second type narrow doped region are alternately distributed on the second well, and the first type wide doped region or the second type narrow doped region and the second well form an electrode structure;

[0008] Wherein, the electrode structure includes a PN structure, a PP structure or a NN structure.

[0009] In the above implementation process, since the efficiency of the incident light incident on the photodiode is positively correlated with the magnitude of the output current of the photodiode, a corresponding first deep well can be firstly set on the substrate, and then a corresponding second well can be set on the first deep well, and then a corresponding doping region can be set on the second well, wherein the doping region includes alternately distributed first-type wide doping regions and second-type narrow doping regions, and the first-type wide doping regions and the second-type narrow doping regions form PN, PP, NN and other electrode structures with the second well at the bottom, and the first-type wide doping regions or the second-type narrow doping regions in the substrate and the first deep well, the second well and the first deep well, the second well and the surface doping regions can form PN junctions, which can make full use of the PN junctions at various depths, increase the area of ​​the overall depletion region in the photodiode, realize the collection of more photogenerated carriers, and thus improve the photoelectric signal conversion efficiency.

[0010] Optionally, an isolation region is provided between adjacent first-type wide doping regions and second-type narrow doping regions.

[0011] In the above implementation process, in order to reduce the premature breakdown of the PN junction formed between the two adjacent first-type wide doped regions, the second-type narrow doped regions and the well or the substrate, a corresponding isolation region can be set between the adjacent first-type wide doped regions and the second-type narrow doped regions to reduce the adverse effects of premature breakdown on the avalanche voltage of the photodiode, thereby further improving the stability of the photodiode during operation.

[0012] Optionally, on the optical communication surface where the first type wide doping region and the second type narrow doping region are distributed, the edge of the doping region is the second type narrow doping region;

[0013] The second type narrow doped region is used for receiving diffused carriers.

[0014] In the above implementation process, in order to realize the reception and conversion of optical signals, on the optical communication surface of the photodiode, the edge of the doped area can be set as a second-type narrow doped area, and the first-type wide doped area is set at the central area of ​​the optical communication surface, so that the second-type narrow doped area can receive the diffused carriers, and the first-type wide doped area can receive the optical signal, which effectively improves the reception efficiency of the optical signal and the migration efficiency of the carriers, thereby improving the photoelectric signal conversion efficiency.

[0015] Optionally, on the optical communication surface, the isolation region is provided between the second type narrow doped region at the edge and the deep well doped region of the first deep well;

[0016] The isolation region is arranged between the deep well doping region and the substrate doping region of the substrate.

[0017] In the above implementation process, in order to power the substrate and the deep well, on the optical communication surface, the first deep well is also provided with a corresponding deep well doping region, thereby forming a corresponding deep well electrode structure, and the deep well electrode structure is used to power the first deep well, and the substrate is also provided with a corresponding substrate doping region, thereby forming a corresponding substrate electrode structure, and the substrate is powered by the substrate electrode structure. Accordingly, in order to reduce the adverse situation of premature breakdown of the PN junction between the second type of narrow doping region at the edge of the doping region and the deep well doping region of the first deep well, and reduce the adverse situation of premature breakdown of the N junction between the deep well doping region and the substrate doping region, an isolation region can be set between the second type of narrow doping region and the deep well doping region, and an isolation region can be set between the deep well doping region and the substrate doping region, so as to achieve power supply while further reducing the adverse effect of premature breakdown of the PN junction on the avalanche voltage of the photodiode.

[0018] Optionally, if there are a plurality of the first-type wide doping regions, the bias voltages of the electrode structure on two adjacent first-type wide doping regions of each second-type narrow doping region are different.

[0019] In the above implementation process, since the diffusion time of the photodiode under some processes is greater than the drift time of the depletion region and the time constant of the device RC, the light detection bandwidth will be limited by the diffusion process of the charge neutral region. Therefore, in the case of multiple first-type wide doping regions, the bias voltages applied to the electrode structures on the two adjacent first-type wide doping regions of each second-type narrow doping region are different, so as to generate corresponding electric fields through different bias voltages, accelerate the migration speed of the carriers generated by light, reduce the transmission time of the carriers, and thus improve the efficiency of the tube detection bandwidth.

[0020] Optionally, the different bias voltages of the electrode structure on the first type wide doping region include V1 and V2, V1 is the bias voltage of the electrode structure on the first type wide doping region in the central area of ​​the doping region, V2 is another bias voltage of the electrode structure on the first type wide doping region that is different from V1, and the bias voltage of the electrode structure on the second type narrow doping region is V3, V2>V1>V3.

[0021] In the above implementation process, the different bias voltages set on multiple first-type wide doping regions may include V1 and V2, V1 is the bias voltage of the electrode structure on the first-type wide doping region in the central area of ​​the doping region, V2 is another bias voltage different from V1, and the bias voltage of the electrode structure on the second-type narrow doping region is V3. In order to further improve the migration rate of photogenerated carriers and accelerate the collection speed of charges, the three different bias voltage sizes can be set to V2>V1>V3, so that the photogenerated carriers generated by the electrode structure on both sides of the first-type wide doping region on both sides of the second-type narrow doping region are mainly accelerated by the electric field and swept into the electrode structure on the middle second-type narrow doping region, thereby further improving the photoelectric signal conversion efficiency of the photodiode.

[0022] Optionally, the number and size parameters of the first type wide doping regions and the second type narrow doping regions are determined based on area parameters of an optical communication surface of the photodiode;

[0023] The first type of wide doped region includes a shielding area and a non-shielding area formed by the electrode structure, and the non-shielding area is an effective light-receiving area.

[0024] In the above implementation process, the size of the doped region is determined based on the area parameter of the optical communication surface of the photodiode. Therefore, the number and size parameters of the first type of wide doped region and the second type of narrow doped region in the doped region are also determined based on the area parameter of the optical communication surface. The first type of wide doped region includes a shielding area formed by the electrode structure and a non-shielding area not formed by the electrode structure. The non-shielding area is used as the effective light receiving area of ​​the first type of wide doped region, so that the light signal is received according to the area difference between the electrode structure and the first type of wide doped region. The number and size of the doped region can be set according to the actual size of the photodiode to adapt to a variety of different bandwidth requirements.

[0025] In a second aspect, an embodiment of the present application provides a diode assembly, wherein the diode assembly includes the photodiode described in any one of the above items;

[0026] Wherein, the plurality of photodiodes form a fully differential array.

[0027] In the above implementation process, in order to reduce the interference caused by the on-chip common-mode signal and reduce the requirements for optical alignment, multiple photodiodes can be set to a fully differential array to reduce the interference of the offset voltage caused by the light spot not being in the center of the optical detector, effectively reduce the common-mode noise, and improve the accuracy and stability of the diode component in processing the optical signal.

[0028] Optionally, the diode assembly comprises a first surface and a second surface;

[0029] A plurality of first groups of differential photodiodes are disposed on the first surface;

[0030] A plurality of second groups of differential photodiodes are disposed on the second surface;

[0031] The first group of photodiodes and the second group of photodiodes are in a central symmetric structure;

[0032] The first group of photodiodes and the second group of photodiodes are provided with a first bias voltage and a second bias voltage respectively.

[0033] In the above implementation process, in order to reduce the loss of light energy caused by the pseudo-differential structure, two groups of differential photodiodes can be set on the first and second surfaces of the diode component, and two different bias voltages can be applied to realize a true differential photoelectric receiver structure, which effectively improves the conversion efficiency of the photoelectric signal and reduces the noise and area waste caused by the virtual part in the pseudo-differential structure. In addition, in order to avoid on-chip common-mode signal interference and reduce the requirements for light alignment, the two groups of photodiodes can also be set to a central symmetrical structure to reduce the interference of the offset voltage caused by the light spot not being in the center of the light detector, effectively reduce common-mode noise, and further improve the accuracy and stability of the diode component when processing the optical signal.

[0034] In a third aspect, an embodiment of the present application provides an optical filter, the optical filter comprising a time reading circuit, a clock circuit, and a diode assembly as described in any one of the above items;

[0035] The time reading circuit is connected to the diode component and the clock circuit;

[0036] The diode assembly is used to perform photoelectric conversion on the received optical signal to obtain a current signal;

[0037] The time reading circuit is used to perform analog-to-digital conversion based on the current signal to obtain a transmission signal;

[0038] The clock circuit is used to calibrate the clock phase.

[0039] In the above implementation process, the diode component set in the optical filter performs photoelectric conversion on the optical signal to obtain a corresponding current signal, and the current signal is converted into an analog-to-digital signal by time reading the current to obtain a transmission signal for transmission. In addition, considering the impact of burst communication and other situations on the transmission process, a clock circuit can also be set to calibrate the clock phase during transmission. While reducing the power consumption of the optical filter, it can improve the accuracy and stability of the optical signal processing, thereby optimizing the optical communication effect of the optical communication interface and meeting a variety of different optical communication needs.

[0040] In summary, the embodiments of the present application provide a photodiode, a diode assembly, and an optical filter. By setting multiple deep PN junctions in the photodiode to increase the migration efficiency of photogenerated carriers, the accuracy and stability of the optical signal can be further improved through the diode assembly of the fully differential array, so as to improve the accuracy, stability, and efficiency of the optical filter in processing the optical signal, thereby optimizing the optical communication effect of the optical communication interface and meeting a variety of different optical communication needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A schematic diagram of the structure of a photodiode provided in an embodiment of the present application;

[0043] Figure 2 A detailed structural diagram of a photodiode provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the structure of a diode assembly provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of the structure of an optical filter provided in an embodiment of the present application.

[0046] Icons: 110-substrate; 120-first deep well; 130-second well; 141-first type wide doped region; 142-second type narrow doped region; 143-electrode structure; 150-isolation region; 121-deep well doped region; 111-substrate doped region; PD1-first group of photodiodes; PD2-second group of photodiodes; A-distribution direction; 200-diode assembly; 300-time reading circuit; 400-clock circuit. DETAILED DESCRIPTION

[0047] The technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the embodiments of the present application.

[0048] With the development of the scale expansion of superconducting quantum computing, the room temperature measurement and control system cannot achieve the kilobit level due to the large heat leakage of the cable across the temperature range (300K to 4K) and the low integration. Low temperature quantum measurement and control is a technology for precise operation and measurement of quantum systems in extremely low temperature environments. In a low temperature environment, the noise of the quantum system will be greatly reduced, and the lifetime of the quantum state will be significantly increased, which is very beneficial for achieving precise quantum operations and measurements. At the same time, the low temperature environment is also conducive to the initialization and readout of the quantum system. Because the cooling power of the cryogenic cavity is limited, the digital controller needs to perform algorithm execution and quantum error correction at room temperature. The entire process including quantum bit readout, data transmission, quantum error correction and algorithm execution needs to be completed within the quantum bit decoherence time. Therefore, a low-power, high-speed communication link is required between the cryogenic processor and the room temperature classical processor.

[0049] Photons are ideal low-noise carriers for quantum information. Photons are weakly coupled to their environment, are not subject to the anti-coherence problems of material-based systems, and can operate at millikelvin temperatures or high vacuum. The thermal conductivity of optical fiber is 2-3 orders of magnitude lower than that of copper coaxial cable, and has ultra-high bandwidth and the characteristics of wavelength division and frequency division multiplexing. Silicon photonic integrated circuits are also developing rapidly due to their compatibility with CMOS, and optical interfaces are gradually being used more in low-temperature communications. In order to receive optical signals, there must be an efficient, high-speed, miniaturized, and low-power on-chip optical receiver. Photomultiplier tubes have been used on a large scale, but they are large in size, easily affected by magnetic fields, and have a large heat load in low-temperature environments. Although the gain of photodiodes is not as large as that of photomultiplier tubes, and the noise term is also larger, it is compatible with commercial CMOS processes, has a compact structure, and is not affected by magnetic fields, making it a better choice. Ordinary photodiodes are mostly designed for use at room temperature, and carrier freezing will occur at low temperatures, resulting in a decrease in quantum efficiency. Since low temperature will affect the movement efficiency of carriers, in order to improve the communication speed of the communication interface under low temperature conditions, integrated serializers and passive backscattering communication schemes are usually used. However, these methods will cause the existing communication interfaces to have high energy consumption, severe crosstalk, poor stability, poor photoelectric detection responsiveness, etc., resulting in poor optical communication effects and unable to meet current optical communication needs.

[0050] In order to solve the above problems, the embodiment of the present application provides a photodiode, which is arranged in a diode assembly, and the diode assembly is arranged in an optical filter. The optical filter can be integrated in a variety of CMOS (Complementary Metal-Oxide Semiconductor) electro-optical devices, such as various types of semiconductor chips, sensors, etc., which can transmit the control signal of the classical control processor on the room temperature side to the electro-optical device of low-temperature quantum measurement and control. The input optical fiber transmits the uplink green light to be modulated in the low-temperature modulator and the red light carrying the downlink control signal from the room temperature side to the electro-optical device in the low-temperature cavity. The red light is converted into an electrical signal by the diode assembly with an upper differential structure integrated with the optical filter and the front-end amplifier circuit. After parallel sampling and judgment, it directly drives the low-temperature high-speed DAC (Digital-to-Analog Converte) to realize quantum bit manipulation. It can reduce the power consumption of the digital signal processing circuit on the quantum measurement and control chip, significantly reduce the heat load of the dilution refrigerator, reduce system complexity, improve the measurement and control fidelity, and effectively reduce the energy consumption, high-speed communication crosstalk and loss of the digital processing circuit of the cross-temperature communication interface, thereby optimizing the optical communication effect of the optical communication interface.

[0051] See also Figure 1 , Figure 1 A structural schematic diagram of a photodiode provided in an embodiment of the present application, the photodiode may include: a substrate 110, a first deep well 120, a second well 130 and a doped region; wherein the first deep well 120 is arranged on the substrate 110, the second well 130 is arranged on the first deep well 120, and the doped region is arranged on the second well 130.

[0052] It should be noted that the substrate 110, the first deep well 120, the second deep well, etc. can be set to various types of hole-type semiconductor materials or electron-type semiconductor materials, i.e., P-type semiconductors or N-type semiconductors, according to actual conditions and needs. Taking a P-type substrate as an example, the first deep well 120 set on the substrate 110 is N-type, and the first deep well 120 is recorded as the corresponding deep N-well (i.e., DNW, Deep N-Well), and the second well 130 set on the first deep well 120 is the corresponding P-well (i.e., PW, P-Well).

[0053] It should be noted that the doping region can be a heavily doped region, and the doping region can include a first type wide doping region 141 and a second type narrow doping region 142. The first type wide doping region 141 and the second type narrow doping region 142 can also be selected according to the material conditions of the substrate 110, the first deep well 120, and the second deep well. For example, based on the above example, the first type wide doping region 141 can be set to a narrower heavily doped P+ region, and the second type narrow doping region 142 can be set to a wider heavily doped N+ region.

[0054] Among them, the first type wide doping region 141 and the second type narrow doping region 142 are alternately distributed on the second well 130, and the first type wide doping region 141 or the second type narrow doping region 142 and the second well 130 form an electrode structure 143, wherein the electrode structure 143 may include a PN structure (ie, a PN junction), a PP structure or a NN structure.

[0055] For example, based on the above example, a corresponding PP structure can be formed between the narrower heavily doped P+ region in the first type wide doped region 141 and the second well 130 of PW, and a corresponding PN structure can be formed between the wider heavily doped N+ region in the second type narrow doped region 142 and the second well 130 of PW.

[0056] exist Figure 1 In the illustrated embodiment, the substrate 110 and the first deep well 120, the second well 130 and the first deep well 120, the second well 130 and the first type of wide doped region 141 or the second type of narrow doped region 142 in the surface doped region can form a PN junction, which can fully utilize the PN junctions at various depths, increase the area of ​​the overall depletion region in the photodiode, and achieve the collection of more photogenerated carriers, thereby improving the photoelectric signal conversion efficiency.

[0057] Optionally, see Figure 2 , Figure 2 A detailed structural schematic diagram of a photodiode provided in an embodiment of the present application, wherein, in order to reduce the premature breakdown of the PN junction formed between two adjacent first-type wide doping regions 141, the second-type narrow doping region 142 and the well or substrate 110, an isolation region 150 is arranged between the adjacent first-type wide doping regions 141 and the second-type narrow doping regions 142. By arranging the corresponding isolation region 150 between the adjacent first-type wide doping regions 141 and the second-type narrow doping regions 142, the adverse effects of premature breakdown on the avalanche voltage of the photodiode are reduced, thereby further improving the stability of the photodiode during operation.

[0058] Optionally, the isolation region 150 can be set to a corresponding shallow trench isolation region 150, namely STI (Shallow Trench Isolation), and a shallow trench can be etched on the second well 130 and filled with insulating material (such as silicon dioxide) to isolate the adjacent first type wide doping region 141 and second type narrow doping region 142, which can effectively reduce the capacitive coupling and leakage current between devices and improve the performance and reliability of the integrated circuit.

[0059] For example, the manufacturing method of the isolation region 150 may include: cleaning and pre-treating the second well 130, forming a group of isolation grooves on the second well 130 using photolithography technology, and then transferring the pattern to the substrate 110 through an etching process to form a shallow groove. Filling the shallow groove with insulating material (such as silicon dioxide) to form the isolation region 150, the compactness and uniformity of the insulating material need to be ensured during the filling process. Performing CMP (Chemical Mechanical Polishing) on ​​the filled substrate 110 to remove excess insulating material and restore the flatness of the substrate 110. The isolation region 150 is also subjected to subsequent treatments such as annealing, cleaning, etc. according to specific needs.

[0060] Optionally, in order to realize the reception and conversion of optical signals, on the optical communication surface where the first type wide doping region 141 and the second type narrow doping region 142 are distributed, the edge of the doping region is the second type narrow doping region 142, and the first type wide doping region 141 is set in the central area of ​​the optical communication surface, and the second type narrow doping region 142 is used to receive diffused carriers. The diffused carriers are received by the second type narrow doping region 142, and the optical signal is received by the first type wide doping region 141, which effectively improves the reception efficiency of the optical signal and the migration efficiency of the carriers, thereby improving the photoelectric signal conversion efficiency.

[0061] It should be noted that in order to power the substrate 110 and the deep well, on the optical communication surface, the first deep well 120 is also provided with a corresponding deep well doping region 121, thereby forming a corresponding deep well electrode structure, and the deep well electrode structure is used to power the first deep well 120, and the substrate 110 is also provided with a corresponding substrate doping region 111, thereby forming a corresponding substrate electrode structure, and the substrate 110 is powered by the substrate electrode structure.

[0062] For example, the doping materials of the deep well doping region 121 and the substrate doping region 111 can also be selected according to the materials of the substrate 110, the first deep well 120, and the second deep well. For example, based on the above example, the deep well doping region 121 can be set to a heavily doped N+ region, and the substrate doping region 111 can be set to a heavily doped P+ region, so as to perform corresponding power supply processing for the substrate 110 and the first deep well 120 respectively.

[0063] Optionally, in order to reduce the adverse situation of premature breakdown of the PN junction between the second type narrow doping region 142 at the edge of the doping region and the deep well doping region 121 of the first deep well 120, on the optical communication surface, an isolation region 150 is arranged between the second type narrow doping region 142 at the edge and the deep well doping region 121 of the first deep well 120, and an isolation region 150 is arranged between the deep well doping region 121 and the substrate doping region 111 of the substrate 110, which can further reduce the adverse effect of premature breakdown of the PN junction on the avalanche voltage of the photodiode while achieving power supply.

[0064] Optionally, since the diffusion time of the photodiode under some processes is greater than the drift time of the depletion region and the time constant of the device RC, the light detection bandwidth will be limited by the diffusion process of the charge neutral region. Therefore, if there are multiple first-type wide doping regions 141, the bias voltages of the electrode structure 143 on two adjacent first-type wide doping regions 141 of each second-type narrow doping region 142 are different, the corresponding electric field is generated through different bias voltages, which accelerates the migration speed of the carriers generated by light and reduces the transmission time of the carriers, thereby improving the efficiency of the tube detection bandwidth.

[0065] Optionally, the bias voltages of the electrode structures 143 on two adjacent first type wide doping regions 141 may be set to V1 and V2 respectively, and V1≠V2.

[0066] Furthermore, different bias voltages of the electrode structure 143 on the first type wide doping region 141 include V1 and V2, V1 is the bias voltage of the electrode structure 143 on the first type wide doping region 141 in the central area of ​​the doping region, V2 is another bias voltage different from V1, and the bias voltage of the electrode structure 143 on the second type narrow doping region 142 is V3. In order to further improve the migration rate of photogenerated carriers and accelerate the collection speed of charges, the three different bias voltage sizes can be set to V2>V1>V3, so that the photogenerated carriers generated by the electrode structure 143 on both sides of the first type wide doping region 141 on both sides of the second type narrow doping region 142 are mainly accelerated by the electric field and swept into the electrode structure 143 on the middle second type narrow doping region 142, thereby further improving the photoelectric signal conversion efficiency of the photodiode.

[0067] For example, taking the applied bias voltage as a positive charge as an example, it can be set as: V1=0.5V, V2=1V, V3=0V.

[0068] For example, V1 and V2 may also be set to two voltages of the same magnitude but opposite to each other, such as V1=-0.5V, V2=0.5V, V3=0V, etc.

[0069] It should be noted that the size of the doped region is determined based on the area parameters of the optical communication surface of the photodiode. Therefore, the number and size parameters of the first type wide doped region 141 and the second type narrow doped region 142 are determined based on the area parameters of the optical communication surface of the photodiode. Among them, the first type wide doped region 141 includes a shielding area and a non-shielding area formed by the electrode structure 143, and the non-shielding area is an effective light-receiving area. The first type wide doped region 141 includes a shielding area formed by the electrode structure 143, and a non-shielding area not formed by the electrode structure 143. The non-shielding area is used as the effective light-receiving area of ​​the first type wide doped region 141, so as to realize the reception of the optical signal according to the area difference between the electrode structure 143 and the first type wide doped region 141. The number and size of the doped region can be set according to the actual size of the photodiode to adapt to a variety of different bandwidth requirements.

[0070] Optionally, the larger the optical communication surface, the larger the light receiving area of ​​the photodiode, the larger the photocurrent that can be generated, but at the same time the parasitic capacitance becomes larger and the bandwidth decreases. Therefore, the number of electrode structures 143 formed on the doped region can be set according to the actual current demand and bandwidth demand, that is, the number of the first type wide doped region 141 and the second type narrow doped region 142 can be set. Figure 2 Only one feasible embodiment with three first-type wide doping regions 141 and four second-type narrow doping regions 142 is shown, and other numbers are not described in detail. In the distribution direction A of the doping regions on the optical communication surface, the length, depth and other parameters of the first-type wide doping region 141 and the second-type narrow doping region 142 can be set according to actual needs and standard manufacturing processes, for example, the length of the first-type wide doping region 141 is set to 4μm, and the length of the second-type narrow doping region 142 is set to 0.25μm, etc.

[0071] For example, the length of the electrode structure 143 in the distribution direction A can be set to 0.22 μm. Therefore, the length of the effective light receiving area on each first type wide doping region 141 in the distribution direction A is 4-0.22=3.78 μm.

[0072] Optionally, the present application also provides a diode assembly, which may include Figure 1-Figure 2 In order to reduce the interference caused by on-chip common-mode signals and reduce the requirements for optical alignment, the photodiodes described in any one of the above-mentioned embodiments are composed of multiple photodiodes to form a fully differential array to reduce the interference of the offset voltage caused by the light spot not being in the center of the optical detector, effectively reduce the common-mode noise, and improve the accuracy and stability of the diode component when processing the optical signal.

[0073] Optionally, a fully differential array is composed of multiple photodiodes arranged in a specific manner, and each photodiode forms a differential pair with its adjacent photodiode. When light is irradiated on the array, each photodiode generates a corresponding photocurrent, and the difference in photocurrent between the differential pairs reflects the spatial distribution of light intensity. Each photodiode unit is a semiconductor device that can convert light signals into electrical signals. It contains multiple PN junctions with photosensitive characteristics of different depths. When light is irradiated on the PN junction, electron-hole pairs are generated, thereby forming a photocurrent under reverse voltage. In a fully differential array, adjacent photodiodes are organized into differential pairs. The two photodiodes in each differential pair share a common electrode (such as an anode or cathode), while the other electrode is connected to different circuit nodes. When the light signal is irradiated on the differential pair, the difference in photocurrent generated by the two photodiodes can be measured and recorded. Multiple differential pairs are arranged in an array form according to a specific layout. The actual shape of the array can be designed according to application requirements, such as a linear array, a two-dimensional array, etc.

[0074] Among them, the quantum efficiency of the photodiode designed for room temperature tends to 0 when the temperature is below 50K, and the photoelectric response provided by the present application can be performed normally at low temperatures. As the temperature decreases, the breakdown voltage and ionization coefficient of the photodiode will decrease significantly, and the photoresponse current and multiplication layer thickness in the avalanche region will increase significantly. The photodiode can be regarded as a current source with a large impedance, and the current size increases with the increase of the incident light power. The mechanism is that in a reverse-biased diode, the incident photon irradiates the depletion region, causing the covalent bond to ionize and produce electron-hole pairs, which are called photogenerated carriers. Some of the carriers recombine during the movement, and the remaining ones drift to the electrode under the action of the built-in electric field, and the current generated is called photocurrent. The responsivity of the photodiode The photodiode can be regarded as a current source with a large impedance, and the current size increases with the increase of the incident light power. The mechanism is that in a reverse-biased diode, the incident photon irradiates the depletion region, causing the covalent bond to ionize and produce electron-hole pairs, which are called photogenerated carriers. Some of the carriers recombine during the movement, and the rest drift to the electrode under the action of the built-in electric field. The current generated is called photocurrent. , that is, the current generated by unit light power; quantum efficiency It is the number of photogenerated carriers generated by one photon incident, that is, the current generated by unit light power; the quantum efficiency η is the number of photogenerated carriers generated by one photon incident.

[0075] Optionally, see Figure 3 , Figure 3A schematic diagram of a diode assembly provided in an embodiment of the present application, wherein the diode assembly may include a first surface and a second surface. A plurality of differential first photodiodes PD1 are arranged on the first surface, and a plurality of differential second photodiodes PD2 are arranged on the second surface.

[0076] It should be noted that the first group of photodiodes PD1 and the second group of photodiodes PD2 are in a centrally symmetrical structure, and the first group of photodiodes PD1 and the second group of photodiodes PD2 are provided with a first bias voltage and a second bias voltage, respectively.

[0077] In high-speed communication, the bit error rate is usually guaranteed by transmitting differential signals. However, the commonly used optical communication receiver is a pseudo-differential structure, which uses a light-shielded photodiode as a dummy device. This structure will lose half of the input light energy, so the responsiveness is low, and its noise performance is reduced, because the virtual part mainly generates noise. In addition, the corresponding design area will be wasted. It should be noted that the differential structure of the present application is a true differential structure, which has more advantages in terms of photoelectric conversion efficiency (responsiveness) and noise, and does not waste the design area. In order to avoid on-chip common-mode signal interference and reduce the requirements for light alignment, a centrally symmetrical fully differential diode array is designed, which can reduce the interference of the offset voltage caused by the light spot not being in the center of the light detector, effectively reduce common-mode noise, and improve the accuracy and stability of the signal.

[0078] For example, the number of differential photodiodes in the first group of photodiodes PD1 and the second group of photodiodes PD2 can be designed according to actual needs. In order to achieve a centrally symmetrical structure, multiple pairs of photodiodes can be provided. Figure 3 Only one structure in which each group of photodiodes includes two pairs of differential photodiodes is shown, and other numbers are not described in detail. The first bias voltage applied to the first group of photodiodes PD1 can be recorded as V B1 , the second bias voltage applied to the second group of photodiodes PD2 can be recorded as V B2 .

[0079] Optionally, see Figure 4 , Figure 4 This is a schematic diagram of the structure of an optical filter provided in an embodiment of the present application. The optical filter may include a time reading circuit 300, a clock circuit 400, and the above-mentioned diode assembly 200.

[0080] Among them, the time reading circuit 300 connects the diode component 200 and the clock circuit 400, the diode component 200 is used to perform photoelectric conversion on the received optical signal to obtain a current signal, the time reading circuit 300 is used to perform analog-to-digital conversion based on the current signal to obtain a transmission signal, and the clock circuit 400 is used to calibrate the clock phase. The diode component 200 set in the optical filter performs photoelectric conversion on the optical signal to obtain a corresponding current signal, and the time reading current performs analog-to-digital conversion on the current signal to obtain a transmission signal for transmission. In addition, considering the impact of burst communication and other situations on the transmission process, the clock circuit 400 can also be set to calibrate the clock phase during transmission, while reducing the power consumption of the optical filter, it can improve the accuracy and stability of processing the optical signal, thereby optimizing the optical communication effect of the optical communication interface and meeting a variety of different optical communication needs.

[0081] For example, in a high-speed communication interface across temperature zones for quantum bit manipulation, serial signal transmission needs to be compiled into parallel signals to drive ADC (Analog-to-Digital Converter). Common serial-to-parallel conversion is implemented using a shift register, and a judgment needs to be made before the shift register. Here, both the judgment circuit and the parallel-to-serial conversion circuit need to work at the full speed of the communication rate. High-speed operation requires a high speed of the circuit, which makes the circuit design complicated. Therefore, in the time reading circuit 300 of the present application, the analog signal amplified by the front end can be converted into a digital signal to drive the ADC by using a time interleaving method. The process is to first amplify the voltage output by the front end to the rail-to-rail range, and then perform multi-channel processing sampling by a time interleaving method, sample and hold by DFF according to the sampled value, and then drive the two-way selector to restore the corresponding to the corresponding level. This is mainly because there may be noise in the output of the front end, and the noise of the output serial signal is reduced by this method. The control signals of different paths are generated by global clock division to control different paths.

[0082] Through the method of time interleaving, signals sampled from different paths can be processed in parallel and can be directly output to the ADC without the need for additional serial-to-parallel conversion circuits. At the same time, the speed requirements of each path after time interleaving are reduced, thereby reducing the required operating speed, and enabling lower power consumption to convert the front-end output voltage into the required parallel output signal.

[0083] For example, in the process of quantum operation, the communication required is not continuous, but high-speed communication in bursts for a period of time, and calculation and error correction are performed at other times. Communication is not required during these times, which means that the interface circuit needs to be turned off when not communicating to save power consumption, and quickly turned on for communication when needed, that is, burst mode communication needs to be implemented. In order to implement burst communication, the present application sets a clock circuit 400 for clock recovery in burst mode. First, burst mode optical communication requires fast clock recovery. Traditional clock recovery requires more time to adjust the VCO to try the CDR, which often requires hundreds of cycles. The application of burst mode must avoid the CDR circuit working in a transient state. On the other hand, the clock of traditional clock recovery is generated by a voltage-controlled oscillator VCO. This method essentially generates an independent new clock through an oscillator. The energy of this clock needs to be provided additionally, so it consumes a large amount of power. Due to the existence of an off-chip clock, in order to maximize the use of the local clock, the clock circuit 400 of the present application generates a suitable sampling clock by continuously feedforward adjusting the phase of the local clock.

[0084] In the clock circuit 400 of the present application, a phase interpolator can be used to adjust the local clock. The phase interpolator requires multiple input clocks of different phases, usually four-phase input or eight-phase input, and then it will select two adjacent input phases and perform weighted interpolation on them. By adjusting the weights of the two phases, the phase interpolator can output a clock of any phase. First, the amplified signal is compared with the local clock input phase detector. The output voltage of the phase detector is linearly related to the phase difference between the two. The output voltage of the phase detector is fed back to the phase interpolator. The phase interpolator adjusts the weight ratio between different phases through the output voltage of the phase detector, changes the adjusted phase, thereby reducing the phase difference between the clock and the signal, and finally recovers the optimal sampling clock through continuous feedforward to reduce the timing error. Compared with the structure of the CDR using VCO in the prior art, since the phase interpolator completely uses the external input clock excitation and does not require an oscillator, it is better than the VCO in noise performance and can achieve the same random jitter performance with lower power consumption. Moreover, the phase interpolator directly performs phase feedback instead of frequency feedback, and its locking will be more accurate and stable compared to the VCO.

[0085] In addition, the various parts in the various embodiments of the present application can be integrated together to form an independent part, or the various parts can exist separately, or two or more parts can be integrated to form an independent part.

[0086] The above description is only an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0087] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

[0088] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, article or device including the elements.

Claims

1. A photodiode, characterized in that: The photodiode comprises: a substrate, a first deep well, a second well and a doped region; Wherein, the first deep well is arranged on the substrate, the second well is arranged on the first deep well, and the doped region is arranged on the second well; The doped region includes a first type wide doped region and a second type narrow doped region, the first type wide doped region and the second type narrow doped region are alternately distributed on the second well, and the first type wide doped region or the second type narrow doped region and the second well form an electrode structure; Wherein, the electrode structure includes a PN structure, a PP structure or a NN structure; If there are multiple first-type wide doping regions, the bias voltages of the electrode structure on two adjacent first-type wide doping regions of each second-type narrow doping region are different; wherein the different bias voltages of the electrode structure on the first-type wide doping regions include V1 and V2, V1 is the bias voltage of the electrode structure on the first-type wide doping region in the central area of ​​the doping region, V2 is another bias voltage of the electrode structure on the first-type wide doping region that is different from V1, and the bias voltage of the electrode structure on the second-type narrow doping region is V3, V2>V1>V3.

2. The photodiode according to claim 1, characterized in that in, An isolation region is provided between adjacent first-type wide doping regions and second-type narrow doping regions.

3. The photodiode according to claim 2, characterized in that in, On the optical communication surface where the first type wide doping region and the second type narrow doping region are distributed, the edge of the doping region is the second type narrow doping region; The second type narrow doped region is used for receiving diffused carriers.

4. The photodiode according to claim 3, characterized in that: in, On the optical communication surface, the isolation region is provided between the second type narrow doped region at the edge and the deep well doped region of the first deep well; The isolation region is arranged between the deep well doping region and the substrate doping region of the substrate.

5. The photodiode according to any one of claims 1 to 4, characterized in that: in, The number and size parameters of the first type wide doping regions and the second type narrow doping regions are determined based on the area parameters of the optical communication surface of the photodiode; The first type of wide doped region includes a shielding area and a non-shielding area formed by the electrode structure, and the non-shielding area is an effective light-receiving area.

6. A diode assembly, characterized in that: The diode assembly comprises a photodiode as claimed in any one of claims 1 to 5; Wherein, the plurality of photodiodes form a fully differential array.

7. The diode assembly according to claim 6, characterized in that in, The diode assembly includes a first side and a second side; A plurality of first groups of differential photodiodes are disposed on the first surface; A plurality of second groups of differential photodiodes are disposed on the second surface; The first group of photodiodes and the second group of photodiodes are in a central symmetric structure; The first group of photodiodes and the second group of photodiodes are provided with a first bias voltage and a second bias voltage respectively.

8. An optical filter, characterized in that: The optical filter comprises a time reading circuit, a clock circuit, and a diode assembly as claimed in any one of claims 6 to 7; The time reading circuit is connected to the diode component and the clock circuit; The diode assembly is used to perform photoelectric conversion on the received optical signal to obtain a current signal; The time reading circuit is used to perform analog-to-digital conversion based on the current signal to obtain a transmission signal; The clock circuit is used to calibrate the clock phase.

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