Display device, epitaxial structure and electronic equipment

Abstract

The invention relates to a display device, an epitaxial structure and electronic equipment, the display device comprises an epitaxial function layer, a first distributed Bragg reflection layer, a first conductive bonding layer and a CMOS driving backboard which are stacked in sequence, the epitaxial function layer is used for emitting light, the first conductive bonding layer is formed on the first distributed Bragg reflection layer, and the CMOS driving backboard is used for driving the first distributed Bragg reflection layer to emit light. The CMOS driving backboard is bonded on the first conductive bonding layer, and the first distributed Bragg reflection layer is used for improving the light emitting efficiency of the display device and electrically connecting the epitaxial function layer and the first conductive bonding layer. According to the display device, the pixel resolution and the display brightness of the electronic equipment can be improved. The selection space of the metal of the bonding layer is widened, and the process difficulty of the bonding part is greatly reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor optoelectronic devices, and in particular to a display device, an epitaxial structure and an electronic device. Background Art

[0002] With the continuous improvement of 5G communication technology and the popularization of concepts such as the metaverse, the pixel resolution and display brightness of conventional electronic devices such as mobile phones, tablets, and computers can no longer meet the demand. However, when the pixel resolution and display brightness of electronic devices in related technologies are improved, other performance of the electronic devices will be reduced, or the manufacturing process of the electronic devices will be more difficult. Summary of the invention

[0003] The embodiments of the present application provide a display device, an epitaxial structure and an electronic device to improve the pixel resolution and display brightness of the electronic device and reduce the difficulty of the manufacturing process.

[0004] In a first aspect, an embodiment of the present application provides a display device, comprising an epitaxial functional layer, a first distributed Bragg reflection layer, a first conductive bonding layer and a CMOS driving backplane stacked in sequence, wherein the epitaxial functional layer is used to emit light, the first conductive bonding layer is formed on the first distributed Bragg reflection layer, and the CMOS driving backplane is bonded to the first conductive bonding layer, wherein the first distributed Bragg reflection layer is used to improve the light extraction efficiency of the display device and electrically connect the epitaxial functional layer and the first conductive bonding layer.

[0005] In this embodiment, by forming a first distributed Bragg reflective layer between the first conductive bonding layer and the epitaxial functional layer, not only can the reflectivity be improved by the first distributed Bragg reflective layer, but the reflectivity of the first distributed Bragg reflective layer can be close to 100%, thereby effectively improving the light extraction efficiency of the epitaxial structure. By forming a first distributed Bragg reflective layer between the first conductive bonding layer and the epitaxial functional layer, the difficulty of integrating the process of the high-reflectivity metal electrode at the bottom of the flip-chip device can be avoided, the selection space of the bonding layer metal is broadened, and the process difficulty of the bonding part is greatly reduced. In addition, the first distributed Bragg reflective layer in this embodiment can improve the light extraction efficiency of the display device without affecting the carrier transmission in the epitaxial functional layer.

[0006] In some possible embodiments, the first distributed Bragg reflector layer is a layer structure formed by doping doping atoms in a Bragg reflector.

[0007] In this embodiment, since the material of the first distributed Bragg reflector layer is doped with doping atoms, the first distributed Bragg reflector layer has electrical conductivity, thereby solving the ohmic contact problem between the epitaxial functional layer and the first conductive bonding layer.

[0008] In some possible embodiments, the material of the Bragg reflector includes one or more of GaN, AlN, InN, AlGaN, InGaN, InAlN, InAlGaN, etc., and the material of the doping atom includes Si. By doping Si in the Bragg reflector composed of one or more of GaN, AlN, InN, AlGaN, InGaN, InAlN, InAlGaN, InAlN, InAlN, and InAlN / GaN, etc., the first distributed Bragg reflector layer has electrical conductivity characteristics, thereby solving the problem of electrical connection between the epitaxial functional layer and the first conductive bonding layer.

[0009] In some possible embodiments, the material of the Bragg reflector includes one or more of GaP, AlP, InP, AlGaP, InGaP, InAlP and InAlGaP, and the material of the doping atom includes Mg. By doping Mg in the Bragg reflector composed of one or more of GaP, AlP, InP, AlGaP, InGaP, InAlP and InAlGaP, the hole carrier concentration in the first distributed Bragg reflective layer can be increased, thereby solving the electrical connection problem between the epitaxial functional layer and the first conductive bonding layer.

[0010] In some possible embodiments, the material of the first conductive bonding layer includes one or more of Au, In, Sn, Cu, Al, Cr, Ti, TiW, Ta, Ni, Pt, W, TiN, and TaN.

[0011] In this embodiment, since the material of the first conductive bonding layer can be one or more of Au, In, Sn, Cu, Al, Cr, Ti, TiW, Ta, Ni, Pt, W, TiN, and TaN, the range of choices is wide, so that metals that are not easily diffused in semiconductors can be selected, thereby reducing the pollution of the Metal process to the production line and reducing the difficulty of the process.

[0012] In some possible embodiments, the display device further includes a tunneling junction layer having the same doping type as the first distributed Bragg reflective layer, the tunneling junction layer being formed on the epitaxial functional layer, the first distributed Bragg reflective layer being formed on the tunneling junction layer, and the tunneling junction layer being capable of improving the transmission capability of electrons or holes from the epitaxial functional layer to the first distributed Bragg reflective layer.

[0013] In this embodiment, the tunneling junction layer can improve the charge transfer capability of the epitaxial functional layer, so that the epitaxial functional layer and the first conductive bonding layer can be electrically connected, thereby solving the ohmic contact problem between the epitaxial functional layer and the first conductive bonding layer.

[0014] In some possible embodiments, the material of the tunnel junction layer includes one or more of n-type doped GaN, n-type doped AlN, and n-type doped InN.

[0015] In some possible embodiments, the material of the tunnel junction layer includes one or more of n-type doped AlGaN, n-type doped InGaN, n-type doped InAlN and n-type doped InAlGaN.

[0016] In this embodiment, since the material of the tunneling junction layer includes n-type doped GaN, n-type doped AlN and n-type doped InN; or the material of the tunneling junction layer includes one or more of n-type doped AlGaN, n-type doped InGaN, n-type doped InAlN and n-type doped InAlGaN, the transmission capability of electrons in the tunneling junction layer and the first distributed Bragg reflector layer can be effectively improved, and the presence of the tunneling junction layer avoids the p-type ohmic contact problem between the p-GaN transmission layer in the epitaxial functional layer and the first conductive bonding layer, and broadens the material selection range of the first conductive bonding layer.

[0017] In some possible embodiments, the material of the tunnel junction layer includes one or more of GaN, AlN, InN and doping atoms, and the doping atoms are Si.

[0018] In some possible embodiments, the material of the tunnel junction layer includes one or more of AlGaN, InGaN, InAlN and InAlGaN and doping atoms, and the doping atoms are Si.

[0019] In some possible embodiments, the material of the tunnel junction layer includes one or more of p-type doped AlAs, p-type doped GaAs, p-type doped GaP, p-type doped AlP, p-type doped InP, p-type doped AlGaP, p-type doped InGaP, p-type doped AlGaAs, p-type doped InAlP and p-type doped InAlGaP.

[0020] In this embodiment, since the material of the tunnel junction layer can be selected from one or more of p-type doped AlAs, p-type doped GaAs, p-type doped GaP, p-type doped AlP, p-type doped InP, p-type doped AlGaP, p-type doped InGaP, p-type doped AlGaAs, p-type doped InAlP and p-type doped InAlGaP, the hole transmission capacity between the tunnel junction layer and the first distributed Bragg reflection layer can be effectively improved, and the ohmic contact problem between the epitaxial functional layer and the first conductive bonding layer can be solved.

[0021] In some possible embodiments, the material of the tunnel junction layer includes one or more of AlAs, GaAs, GaP, AlP, InP, AlGaP, InGaP, AlGaAs, InAlP and InAlGaP and doping atoms, and the doping atoms are Mg.

[0022] In some possible embodiments, the display device further includes a second distributed Bragg reflection layer, the epitaxial functional layer is located between the second distributed Bragg reflection layer and the tunnel junction layer / first distributed Bragg reflection layer, and a resonant cavity is formed between the second distributed Bragg reflection layer and the first distributed Bragg reflection layer.

[0023] In the present embodiment, since the second distributed Bragg emission layer and the first distributed Bragg reflection layer are respectively formed on the opposite sides of the epitaxial functional layer, the second distributed Bragg reflection layer and the first distributed Bragg reflection layer form a resonant cavity without affecting the carrier transmission in the epitaxial functional layer. The formed resonant cavity can effectively reduce the light output angle of the display device and increase the vertical light output efficiency of the display device.

[0024] In some possible embodiments, the first direction is the direction in which the second distributed Bragg reflection layer and the first distributed Bragg reflection layer are stacked, the second distributed Bragg reflection layer and the first distributed Bragg reflection layer constitute a q-mode resonator, the distance between the second distributed Bragg reflection layer and the first distributed Bragg reflection layer in the first direction is d, the wavelength of the light emitted by the epitaxial functional layer is λ, and the comprehensive equivalent refractive index of the epitaxial functional layer is n, wherein,

[0025] In this embodiment, for display devices that emit long wavelengths, such as the AlInGaP epitaxial system that emits red light, the front light extraction efficiency is low due to the high refractive index of the material corresponding to the AlInGaP system. By constructing an RC (resonant cavity)-LED epitaxial device structure, the front light extraction efficiency of the display device of this embodiment can be effectively improved, and the light output angle of the corresponding red light device can be shortened at the same time.

[0026] In some possible embodiments, the first conductive bonding layer and the first distributed Bragg reflection layer form a full-angle reflector.

[0027] In this embodiment, the first distributed Bragg reflector and the first conductive bonding layer constitute an omni-directional reflector (ODR) structure, which can reflect light at all angles. Therefore, without destroying the carrier transmission effect of the epitaxial functional layer in the above-mentioned resonant cavity, it can effectively improve the overall light output efficiency of the display device.

[0028] In some possible embodiments, the display device further includes a second conductive bonding layer, the second conductive bonding layer is aligned and bonded to the first conductive bonding layer, and the second conductive bonding layer is integrated on the CMOS driving backplane.

[0029] In this embodiment, since the display device includes a first conductive bonding layer and a second conductive bonding layer, in terms of the manufacturing process, a pixelation process can be performed first, and then the CMOS driving backplane can be aligned and bonded. Therefore, the CMOS driving backplane will not be damaged during the LED pixelation process, and the yield of the display device (such as a microdisplay) can be effectively improved.

[0030] In some possible embodiments, the first conductive bonding layer includes a first metal part and a first dielectric part adjacent to the first metal part, the second conductive bonding layer includes a second metal part and a second dielectric part adjacent to the second metal part, the first metal part and the second metal part are bonded one-to-one, and the first dielectric part and the second dielectric part correspond one-to-one.

[0031] In this embodiment, when aligning the second conductive bonding layer with the first conductive bonding layer, it is only necessary to align the first metal part with the second metal part, and the first dielectric part with the second dielectric part, so that the second conductive bonding layer can be connected to the first conductive bonding layer, ensuring the driving path and achieving electrical connection.

[0032] In a second aspect, the present application provides an epitaxial structure, comprising a substrate, an epitaxial functional layer, a tunnel junction layer, a first distributed Bragg reflection layer and a first conductive bonding layer stacked in sequence, wherein the first distributed Bragg reflection layer is formed on the tunnel junction layer and the epitaxial functional layer, the first conductive bonding layer is formed on the first distributed Bragg reflection layer, and the first distributed Bragg reflection layer is used to improve the light extraction efficiency of the epitaxial structure and electrically connect the epitaxial functional layer and the first conductive bonding layer.

[0033] In this embodiment, by forming a first distributed Bragg reflector layer between the first conductive bonding layer and the epitaxial functional layer, not only can the reflectivity be improved by the first distributed Bragg reflector layer, but also the light extraction efficiency of the epitaxial structure can be improved. Since the tunneling junction layer can also solve the ohmic contact problem between the epitaxial functional layer and the first conductive bonding layer, the problem of integrating the bottom layer high reflectivity metal electrode of the CMOS+LED flip-chip device can be avoided by forming a first distributed Bragg reflector layer between the first conductive bonding layer and the epitaxial functional layer, which broadens the selection space of the bonding layer metal and greatly reduces the process difficulty of the bonding part. In addition, the first distributed Bragg reflector layer in this embodiment can improve the light extraction efficiency of the epitaxial structure without affecting the carrier transmission in the epitaxial functional layer.

[0034] In some possible embodiments, the substrate includes a silicon base, the epitaxial structure further includes an AlON crystal layer, the AlON crystal layer is formed on the silicon base, and the epitaxial functional layer is formed on the AlON crystal layer.

[0035] In this embodiment, the size and distribution of the compressive stress of the epitaxial structure are directly determined by controlling the oxygen concentration ratio in the AlON crystal layer. By growing AlON crystal layers at low temperatures in batches on a silicon substrate, the crystal quality of the epitaxial functional layer grown later can be effectively improved. By introducing O atoms into the AlON crystal layer, the Al-O bond length is <Al-N bond length , thereby increasing the tensile stress of the AlON layer, effectively reducing the lattice mismatch between the silicon wafer and the epitaxial functional layer, releasing stress, and alleviating epitaxial warping.

[0036] In some possible embodiments, in the AlON crystal layer, the proportion of O element is 10ppm-50%.

[0037] In this embodiment, since the proportion of O element in the AlON crystal layer is 10ppm-50%, within this range, the lattice mismatch between the silicon wafer and the epitaxial functional layer can be effectively reduced, stress can be released, and epitaxial warping can be alleviated.

[0038] In some possible embodiments, the epitaxial functional layer is pixelated to form a plurality of pixel installation steps, and projections of the plurality of pixel installation steps on the substrate are spaced apart from each other in a first direction, where the first direction is a stacking direction of the substrate and the epitaxial functional layer.

[0039] In the present embodiment, since the epitaxial functional layer is pixelated and forms a number of spaced pixel installation steps, in the subsequent process of forming the display device, the epitaxial structure no longer needs to perform pixelation process steps for the epitaxial functional layer, but can be directly connected to the CMOS driver backplane, thereby avoiding damage to the CMOS driver backplane during the pixelation process of the display device.

[0040] In a third aspect, an embodiment of the present application provides an electronic device, comprising a housing and a display device as described in any one of the first aspect or an epitaxial structure as described in any one of the second aspect, wherein the display device is disposed on the housing. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0042] Figure 1 A schematic diagram of the structure of a possible electronic device provided in an embodiment of the present application;

[0043] Figure 2 for Figure 1 An exploded schematic diagram of the electronic equipment in the;

[0044] Figure 3 A schematic diagram of a possible layer structure of an epitaxial structure provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of the layer structure of another possible epitaxial structure provided in an embodiment of the present application;

[0046] Figure 5 for Figure 3 A schematic diagram of one layer structure of an epitaxial structure in the embodiment;

[0047] Figure 6 A schematic diagram of a layer structure of a specific epitaxial structure provided in an embodiment of the present application;

[0048] Fig. 6A for Figure 6 The manufacturing process steps of the epitaxial structure in;

[0049] Figure 7 for Figure 3 A schematic diagram of one layer structure of an epitaxial structure in the embodiment;

[0050] Figure 8 A schematic diagram of the layer structure of another specific epitaxial structure provided in an embodiment of the present application;

[0051] Fig. 9 A schematic diagram of the layer structure of another possible epitaxial structure provided in an embodiment of the present application;

[0052] Fig.10 Based on Fig. 9 A schematic diagram of a layer structure of a specific epitaxial structure in the embodiment;

[0053] Fig.11 Based on Fig. 9 A schematic diagram of a layer structure of a specific epitaxial structure in the embodiment;

[0054] Fig.12 A schematic diagram of a layer structure of another possible epitaxial structure provided in an embodiment of the present application;

[0055] Fig.13 A schematic diagram of a possible layer structure of a display device provided in an embodiment of the present application;

[0056] Fig.14 Based on Figure 6 A schematic diagram of the layer structure of a display device formed by epitaxial structure processing in an embodiment;

[0057] Fig.14A for Fig.14 The manufacturing process steps of the display device in

[0058] Fig.15 Based on Figure 6 A schematic diagram of the layer structure of another display device formed by processing the epitaxial structure in the embodiment;

[0059] Fig.15A for Fig.15 The manufacturing process steps of the display device in

[0060] Fig. 15B for Fig.15A One of the top views of the array structure after step e;

[0061] Fig. 15C for Fig.15A Another top view of the array structure after step e;

[0062] Fig.16 Based on Figure 8 A schematic diagram of the layer structure of a display device formed by epitaxial structure processing in an embodiment;

[0063] Fig.17 Based on Fig.11 Schematic diagram of the layer structure of the display device formed by epitaxial structure processing in the embodiment.

[0064] Description of reference numerals:

[0065] 100. Electronic device; 101. Housing; 102. Display device; 103. Main controller; 104. Battery; 105. Epitaxial structure; 106. Lens; 10. Substrate; 11. Silicon substrate; 12. Gallium arsenide substrate; 20. Buffer layer; 21. AlGaN buffer layer; 22. u-GaN stress buffer layer; 30. Epitaxial functional layer; 301. Pixel mounting step; 302. Metal retaining wall; 303. Dielectric layer; 31. n-GaN electron injection layer; 32. InGaN short-period superlattice layer; 33. Multi-period InGaN light-emitting quantum well layer; 34. p-AlGaN electron blocking layer; 35. p-GaN hole injection Layer; 31a, p-AlInGaP layer; 32a, p-AlInP layer; 33a, multi-period InGaP / AlGaInP light-emitting quantum well layer; 34a, n-AlInP layer; 35a, n-AlGaInP layer; 36a, GaP layer; 40, first distributed Bragg reflection layer; 51, first conductive bonding layer; 511, first metal part; 512, first dielectric part; 52, transparent electrode layer; 53, second conductive bonding layer; 531, second metal part; 532, second dielectric part; 60, tunneling junction layer; 70, crystal layer; 80, second distributed Bragg reflection layer; 90, CMOS driving backplane. DETAILED DESCRIPTION

[0066] The following first explains some terms involved in the embodiments of the present application.

[0067] The terms "first", "second", "third", "fourth", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0068] In this specification, the terms "perpendicular" and "parallel" are explained.

[0069] Vertical: The verticality defined in this application is not limited to an absolute vertical intersection relationship (angle of 90 degrees). It allows for non-absolute vertical intersection relationships caused by factors such as assembly tolerance, design tolerance, and influence of structural flatness. It also allows for errors in a small angle range. For example, the assembly error range of 80 to 100 degrees can be understood as a vertical relationship.

[0070] Parallelism: The parallelism defined in this application is not limited to absolute parallelism. This definition of parallelism can be understood as basic parallelism, which allows for situations where the absolute parallelism is not caused by factors such as assembly tolerance, design tolerance, and influence of structural flatness. These situations will lead to the sliding fitting part and the first door panel not being absolutely parallel, but this application also defines this situation as parallelism.

[0071] Figure 1 A schematic diagram of a possible electronic device 100 provided in an embodiment of the present application; Figure 2 for Figure 1 Schematic diagram of an exploded view of the electronic device 100.

[0072] See also Figure 1 , the electronic device 100 displays moving images or still images, so various products with a display function can be the electronic device 100 in this embodiment, and the electronic device 100 can be such as a portable electronic device 100 (such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device and an ultra-mobile PC (UMPC) as well as a television, a notebook computer, a monitor, an advertising panel and an Internet of Things (IoT) device. The electronic device 100 can also be a wearable device such as a smart watch, a watch phone, a glasses-type display and a head-mounted display (HMD). The electronic device 100 can also be a dashboard of a vehicle, a central information display (CID) of a center fascia or dashboard of a vehicle, an interior mirror display instead of a side mirror of a vehicle, and a display arranged or set on the rear side of a front seat to be used as an entertainment device for rear seat passengers of the vehicle.

[0073] For ease of explanation, Figure 1 and Figure 2 A smartphone is shown as the electronic device 100 of this embodiment. The electronic device 100 of this embodiment may include a housing 101 , a display device 102 , a main controller 103 , and a battery 104 .

[0074] The housing 101 serves as a structural bearing component of the display device 102 and is used to install the display device 102 , as well as to accommodate or install other components such as a main controller 103 and a battery 104 .

[0075] The shape of the housing 101 is roughly rectangular, but this does not mean that the housing 101 has only one rectangular embodiment. In other embodiments, the housing 101 can also be circular, square or some irregular shapes.

[0076] The main controller 103 may be disposed on the display device 102, and in other embodiments, may also be disposed in the housing 101. The embodiment of the present application does not limit the specific location of the main controller 103. The main controller 103 includes but is not limited to a system on chip (System On Chip, SOC), and the main controller 103 is used to output video data, clock signals and / or main commands to the display device 102. In other embodiments, the main controller 103 may also include various types of processors such as an application processor (Application Processor, AP) or a general processor.

[0077] The display device 102 is not only applicable to the above display device, but also to any device that has a demand for displaying text, images, videos, etc., and the embodiments of the present application do not strictly limit this. The display device 102 can be used to display text, images, videos, etc. The display device 102 can be a folding screen, and the display device 102 can also be implemented using a flexible screen or a hard display device 102. The specific type can be an organic light-emitting diode (OLED) display device 102, and can also be a (Light Emitting Diode, LED) display device 102 or a micro light-emitting diode (mirco Light Emitting Diode, mirco LED) display device 102, etc. For the convenience of description below, the display device 102 is an example of LED.

[0078] An embodiment of the present application provides a possible epitaxial structure, and the display device 102 in the above embodiment is manufactured based on the epitaxial structure.

[0079] Figure 3 A schematic diagram of a possible layer structure of an epitaxial structure 105 provided in an embodiment of the present application.

[0080] See also Figure 3The epitaxial structure 105 includes a substrate 10, a buffer layer 20, an epitaxial functional layer 30, a first distributed Bragg reflector 40 and a first conductive bonding layer 51, wherein the substrate 10, the buffer layer 20, the epitaxial functional layer 30, the first distributed Bragg reflector 40 and the first conductive bonding layer 51 are stacked in sequence. For the convenience of description, the stacking direction of the substrate 10, the buffer layer 20, the epitaxial functional layer 30, the first distributed Bragg reflector 40 and the first conductive bonding layer 51 is set to be a first direction.

[0081] The buffer layer 20 , the epitaxial functional layer 30 , the first distributed Bragg reflector layer 40 , the first conductive bonding layer 51 and the like in this embodiment are all formed by epitaxial growth.

[0082] The substrate 10 may be a silicon substrate 11, a sapphire substrate, a gallium nitride substrate, a gallium arsenide substrate 12, an indium phosphide substrate, an aluminum nitride substrate or a silicon carbide substrate, and may also be any known substrate that can be used to prepare a III-V group nitride thin film. In some embodiments, when the substrate 10 is a silicon substrate 11, the crystal orientation of the silicon substrate 11 is not limited, but is generally a silicon substrate 11 with a (111) crystal plane index.

[0083] The main function of the buffer layer 20 is to reduce crystal defects caused by lattice mismatch and improve the quality and performance of the epitaxial functional layer 30. The main function of the epitaxial functional layer 30 is to realize the specific functions of the display device 102 (such as LED display).

[0084] The materials of the buffer layer 20 and the epitaxial functional layer 30 in this embodiment can be determined according to the material type of the substrate 10. For example, in some embodiments, when the substrate 10 is a silicon substrate 11, the material of the buffer layer 20 can be AlN, u-GaN or a combination thereof, AlGaN. When the substrate 10 is a silicon substrate 11, the epitaxial functional layer 30 is an LED epitaxial functional layer formed of III-V group nitride formed on the buffer layer 20, and the material of the epitaxial functional layer 30 can include one or more of GaN, AlN, InN, AlGaN, InGaN, InAlN and InAlGaN (for example, the epitaxial functional layer 30 includes an InGaNLED epitaxial structure such as an n-GaN electron injection layer, an InGaN short-period superlattice layer, a multi-period InGaN light-emitting quantum well layer, a p-AlGaN electron blocking layer, and a p-GaN hole injection layer stacked in sequence). In this embodiment, a method for growing the buffer layer 20 and the epitaxial functional layer 30 with good uniformity and high crystal quality is provided, which can be applied to semiconductor devices to improve device performance. The Si substrate epitaxial structure 105 in this embodiment can have a large size of 6 inches, 8 inches or more to meet the needs of large-scale mass production. For example, in some embodiments, the substrate 10 is a gallium arsenide substrate 12, and the material of the buffer layer 20 can be a p-type AlInGaP film. The p-type AlInGaP buffer layer can improve the lattice mismatch between the epitaxial functional layer 30 and the gallium arsenide substrate 12. It can be understood that other buffer structures for adjusting the lattice mismatch between the epitaxial functional layer 30 and the gallium arsenide substrate 12 known to those skilled in the art can be used as the buffer layer 20 in this embodiment. The substrate 10 is a gallium arsenide substrate 12, and the epitaxial functional layer 30 is at least one layer of III-V group phosphide formed above the buffer layer 20. The material of the epitaxial functional layer 30 includes one or more of GaP, AlP, InP, AlGaP, InGaP, InAlP and InAlGaP. A typical structure is to epitaxially grow a p-AlInGaP buffer layer, a p-AlInP transmission layer, a multi-period InGaP / AlGaInP light-emitting quantum well layer, an n-AlInP transmission layer, an n-AlGaInP transmission layer, and a GaP layer in sequence on a GaAs substrate.

[0085] It can be understood that in the embodiments of the present application, different epitaxial functional layers 30 can be suitable for different semiconductor devices. In order to meet the performance requirements, other elements can also be added to the epitaxial functional layer 30. For example, in order to improve insulation, carbon can be added to form high resistance and improve voltage resistance.

[0086] The first distributed Bragg reflector 40 is formed on the epitaxial functional layer 30, and the first conductive bonding layer 51 is formed on the first distributed Bragg reflector 40. The first distributed Bragg reflector 40 in this embodiment includes at least two properties. The first is high reflectivity. The reflectivity of the first distributed Bragg reflector 40 to the LED light can be close to 100%. The first distributed Bragg reflector 40 in this embodiment can effectively improve the light extraction efficiency of the epitaxial structure 105 in this embodiment. The second is conductivity. Specifically, the first distributed Bragg reflector 40 is a layer structure formed by doping doping atoms in the Bragg reflector. It should be noted that in a material (matrix), a small amount of other elements or compounds are doped to make the material (matrix) produce specific electrical, magnetic and optical properties, so that it has practical application value or specific use. The process is called doping. The "doping atom" in this embodiment refers to other elements or compounds added to the substrate. For example, doping phosphorus or gallium in semiconductor silicon can obtain n-type or p-type semiconductor materials, and phosphorus or gallium is a doping atom.

[0087] In this embodiment, the doping atoms may be Si or a material of the same family as Si, or a metal material such as Mg. Since the material of the first distributed Bragg reflector 40 is doped with doping atoms, the first distributed Bragg reflector 40 may have electrical conductivity, and the tunneling junction layer 60 is combined with the conductive first distributed Bragg reflector 40, thereby solving the electrical connection problem between the epitaxial functional layer 30 and the first conductive bonding layer 51.

[0088] The material of the first distributed Bragg reflector 40 in this embodiment can be determined according to the type of specific material epitaxial system. For example, in some embodiments, when the epitaxial functional layer 30 is a III-V nitride epitaxial system, the material of the first distributed Bragg reflector 40 can be a periodic stack formed by III-V nitrides, such as two or more periodic stack structures of GaN, AlN, InN, AlGaN, InGaN, InAlN, InAlGaN and InAlN / GaN, etc. Typically, it can be a distributed Bragg reflector composed of n-InAlN / GaN high refractive index / low refractive index material. For another example, when the epitaxial functional layer 30 is a III-V phosphide epitaxial system, the material of the first distributed Bragg reflection layer 40 can be a periodic stack formed by III-V phosphides. The material of the first distributed Bragg reflection layer 40 includes two or more periodic stack structures of GaP, AlP, InP, AlGaP, InGaP, InAlP and InAlGaP. Typically, it can be a distributed Bragg reflection layer composed of p-AlGaInP / AlInP high-refractive index / low-refractive index material.

[0089] It is understandable that the first distributed Bragg reflector layer 40 in this embodiment can be n-type doped, such as doped Si or a material of the same family as Si, with a typical doping concentration range of 1e 19 -5e 20 cm -3 The first distributed Bragg reflector layer 40 may also be p-type doped, such as doped with metal materials such as Mg, with a typical doping concentration range of 1e 19 -5e 20 cm -3 The specific value may be determined according to the doping type of the epitaxial functional layer 30 connected thereto.

[0090] For example, in some embodiments, the first distributed Bragg reflector 40 is composed of two or more high-refractive index / low-refractive index materials doped with Si, such as GaN, AlN, InN, AlGaN, InGaN, InAlN, InAlGaN, and InAlN / GaN. At this time, the first distributed Bragg reflector 40 is connected to the p-type doped functional layer in the epitaxial functional layer 30, such as the p-GaN hole injection layer 35. The first distributed Bragg reflector 40 is doped with Si, which is n-type doping, and the p-GaN hole injection layer 35 is p-type doping. A tunnel junction (such as the tunnel junction layer 60 described below) can be constructed between the p-GaN hole injection layer 35 and the first distributed Bragg reflector 40 to achieve electrical connection between the p-GaN and the n-type InAlN / GaNDBR.

[0091] Or in some other embodiments, the first distributed Bragg reflector 40 is composed of two or more high-refractive index / low-refractive index materials doped with Mg among GaP, AlP, InP, AlGaP, InGaP, InAlP and InAlGaP. In this case, the n-type doped functional layer in the epitaxial functional layer 30, such as the n-GaP layer 36a, is connected to the first distributed Bragg reflector 40. The first distributed Bragg reflector 40 is doped with Mg and is p-type doped, and n-GaP is n-type doped. A tunnel junction (such as the tunnel junction layer 60 described below) can be constructed between the n-GaP electron injection layer 36a and the first distributed Bragg reflector 40 to achieve electrical connection between n-GaP and the first distributed Bragg reflector 40.

[0092] It is understandable that the first distributed Bragg reflector 40 in this embodiment is formed by periodic stacking to achieve high reflectivity. The doping atoms doped in the first distributed Bragg reflector 40 in this embodiment may be Si, Mg, or other II and IV group doping elements to achieve conductive properties.

[0093] The first conductive bonding layer 51 can provide good electrical connection for the epitaxial structure 105 in this embodiment to ensure normal operation. At the same time, the first conductive bonding layer 51 can also play a role of mechanical support to ensure the stability of the epitaxial structure 105. The first conductive bonding layer 51 can be made of but not limited to Au, In, Sn, Cu, Al, Cr, Ti, TiW, Ta, Ni, Pt, W, TiN, TaN and other metal materials with a thickness between 1nm-50μm. The material of the first conductive bonding layer 51 can be selected in a wide range, so that metals that are not easy to diffuse in semiconductors can be selected, reducing the risk of short circuits and the pollution of metal processes to the production line, and can reduce the difficulty of the process. In some other embodiments, the first conductive bonding layer 51 can also be made of some non-metallic conductive materials.

[0094] In the present embodiment, by forming a first distributed Bragg reflection layer 40 between the first conductive bonding layer 51 and the epitaxial functional layer 30, not only can the reflectivity be improved by the first distributed Bragg reflection layer 40, thereby improving the light extraction efficiency of the epitaxial structure 105, but also the difficulty of integrating the high-reflectivity metal bonding layer at the bottom of the flip-chip device can be avoided, the selection space of the bonding layer metal is broadened, and the process difficulty of the bonding part is greatly reduced. For example, in the related art, there is no epitaxial structure 105 with a Bragg reflection layer. In order to improve the light extraction efficiency of the epitaxial structure 105, the first conductive bonding layer 51 is selected to use an Ag bonding layer with high reflectivity. However, Ag is very easy to diffuse in semiconductors, which can easily cause Ag diffusion short circuit and serious yield reduction during the processing of LED devices. It is incompatible with the CMOS (Complementary Metal-Oxide-Semiconductor) process, which will cause a short circuit in the CMOS drive backplane, and it is difficult to use ICP (Inductively-Coupled-Plasma etching) to etch the bonding layer pixels, so that high PPI micro display screen pixel level driving cannot be achieved. In this embodiment, by forming a first distributed Bragg reflection layer 40 between the first conductive bonding layer 51 and the epitaxial functional layer 30, the requirement of high reflectivity of the bonding layer is avoided, and the selection space of the bonding layer metal is broadened, so that some metals that are not easy to diffuse in semiconductors can be selected as the first conductive bonding layer 51. Moreover, the first distributed Bragg reflection layer 40 is well compatible with the CMOS process, decoupling the first conductive bonding layer 51 and the high reflectivity bottom surface, thereby effectively reducing the process difficulty of the bonding part.

[0095] It is understandable that in some embodiments of the present application, when the performance requirements are not high or the performance of the substrate 10 is relatively high, the epitaxial functional layer 30 may be formed directly on the substrate 10 rather than first forming the buffer layer 20 and then growing the epitaxial functional layer 30 .

[0096] Figure 4 A schematic diagram of the layer structure of another possible epitaxial structure 105 provided in an embodiment of the present application.

[0097] See also Figure 4 The epitaxial structure 105 includes a substrate 10, an epitaxial functional layer 30, a tunnel junction layer 60 (Tunnel Junction, TJ), a first distributed Bragg reflector layer 40 and a first conductive bonding layer 51, wherein the substrate 10, the epitaxial functional layer 30, the first distributed Bragg reflector layer 40 and the first conductive bonding layer 51 can refer to the above text and are not described here. Specifically, the tunnel junction layer 60 is located between the epitaxial functional layer 30 and the first distributed Bragg reflector layer 40, that is, the tunnel junction layer 60 is grown and formed on the epitaxial functional layer 30, the first distributed Bragg reflector layer 40 is grown and formed on the tunnel junction layer 60, and the first conductive bonding layer 51 is grown and formed on the first distributed Bragg reflector layer 40.

[0098] The tunneling junction layer 60 provides a low resistance path, which can improve the electron mobility of the epitaxial functional layer 30, so that the epitaxial functional layer 30 and the first conductive bonding layer 51 can be electrically connected, solving the ohmic contact problem between the epitaxial functional layer 30 and the first conductive bonding layer 51.

[0099] The material of the tunneling junction layer 60 can be determined according to the type of specific material epitaxial system. For example, in some embodiments, when the epitaxial functional layer 30 is a III-V nitride epitaxial system, the material of the tunneling junction layer 60 can be at least one layer formed by the III-V nitride, such as the tunneling junction layer 60 can include one or more of GaN, AlN, InN and doping atoms. Or the tunneling junction layer 60 can include one or more of AlGaN, InGaN, InAlN and InAlGaN and doping atoms. When the epitaxial functional layer 30 is a III-V phosphide epitaxial system, the material of the tunneling junction layer 60 can be at least one layer formed by the III-V phosphide, and the material of the tunneling junction layer 60 can include one or more of AlAs, GaAs, GaP, AlP, InP, AlGaP, InGaP, AlGaAs, InAlP and InAlGaP and doping atoms.

[0100] It can be understood that the tunneling junction layer 60 can be n-type doped, for example, the doping atom is Si or a material of the same family as Si, and the material of the tunneling junction layer 60 includes one or more of n-type doped GaN, n-type doped AlN, and n-type doped InN. Or the material of the tunneling junction layer includes one or more of n-type doped AlGaN, n-type doped InGaN, n-type doped InAlN, and n-type doped InAlGaN. The tunneling junction layer 60 can also be p-type doped, for example, the doping atom is Mg and a metal material of the same family as Mg, and the material of the tunneling junction layer 60 includes one or more of p-type doped AlAs, p-type doped GaAs, p-type doped GaP, p-type doped AlP, p-type doped InP, p-type doped AlGaP, p-type doped InGaP, p-type doped AlGaAs, p-type doped InAlP, and p-type doped InAlGaP. The doping type of the tunneling junction layer 60 is opposite to the doping type of the epitaxial functional layer 30 connected thereto, and the doping type of the tunneling junction layer 60 is the same as the doping type of the first distributed Bragg reflector 40, and the doping distribution can be uniform doping or gradient doping. For example, in some embodiments, the material doping concentration at the interface between the epitaxial functional layer 30 and the tunneling junction layer 60 is the highest, and the typical doping concentration range is 1e 19 -5e 20 cm -3 .

[0101] It can be understood that the tunnel junction layer 60 can be a single layer, multiple layers, or a multi-layer periodic structure.

[0102] Figure 5 for Figure 3 FIG. 1 is a schematic diagram of a layer structure of an epitaxial structure 105 in the embodiment.

[0103] based on Figure 3 For an example, see Figure 5 In some embodiments, the substrate 10 is a silicon substrate 11. Since the substrate 10 is a silicon substrate 11, the cost of the silicon substrate 11 is low and it is easy to bond with a silicon-based CMOS. The silicon-based epitaxial structure 105 of a large size of 8 inches or more can effectively reduce edge and arrangement losses and effectively reduce costs. This is particularly advantageous for microLED or RF chips.

[0104] In some implementations, the epitaxial structure 105 further includes a crystalline layer 70 grown on the silicon substrate 11. In this embodiment, the crystalline layer 70 can reduce the lattice mismatch between the silicon substrate 11 and the buffer layer 20 or the epitaxial functional layer 30, thereby releasing stress.

[0105] In some embodiments, the crystalline layer 70 is an AlON crystalline layer 70. By controlling the proportion of oxygen concentration in the AlON crystalline layer 70, the magnitude and distribution of the compressive stress of the epitaxial structure 105 are directly determined. By batch-growing the AlON crystalline layer 70 on the silicon substrate 11 at a low temperature, the crystal quality of the subsequent epitaxially grown epitaxial functional layer 30 can be effectively improved. By introducing oxygen atoms into the AlON crystalline layer 70, because the Al-O bond length < is shorter than the Al-N bond length , the tensile stress of the AlON layer can be increased, which can further reduce the lattice mismatch between the silicon wafer and the epitaxial functional layer 30, release stress, and relieve epitaxial warping.

[0106] In some embodiments, in the AlON crystalline layer 70, the mass proportion of the O element is 10 ppm - 50%. Since the proportion of the O element in the AlON crystalline layer 70 is 10 ppm - 50%, within this range, the lattice mismatch between the silicon wafer and the epitaxial functional layer 30 can be effectively reduced, stress can be released, and epitaxial warping can be relieved.

[0107] In some embodiments, in the AlON crystalline layer 70, the mass proportion of the O element is 1% - 50%, such as 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc.

[0108] In some embodiments, the crystalline layer 70 can also be an AlN crystalline layer 70, which reduces the lattice mismatch between the silicon substrate 11 and the buffer layer 20 or the epitaxial functional layer 30 and releases stress.

[0109] In order to further reduce the lattice mismatch between the silicon substrate 11 and the buffer layer 20 or the epitaxial functional layer 30, in some embodiments, an AlN crystalline layer 70 or an AlON crystalline layer 70 is grown on the silicon substrate 11 by a low-temperature deposition method. The low temperature in this embodiment refers to a temperature below 500°C. Since the AlN crystalline layer 70 or the AlON crystalline layer 70 is grown on the silicon substrate 11 by a low-temperature deposition method, low-temperature growth can avoid the reaction between Si in the silicon substrate 11 and the AlN crystalline layer 70 or the AlON crystalline layer 70, thereby reducing the dislocation density between the silicon substrate 11 and the AlN crystalline layer 70 or the AlON crystalline layer 70, and further reducing the dislocation density of the subsequent buffer layer 20 and / or the epitaxial functional layer 30, etc., so as to improve the epitaxial quality of the epitaxial structure 105.

[0110] In some embodiments, the AlN crystalline layer 70 or the AlON crystalline layer 70 can be grown by low temperature deposition methods such as ALD, magnetron sputtering, molecular beam epitaxy, PECVD, and ICP-CVD. The AlN crystalline layer 70 or the AlON crystalline layer 70 formed by the low temperature process is not only conducive to improving the epitaxial quality of the epitaxial structure 105, but the piezoelectric properties of the high-quality epitaxial structure 105 are conducive to the formation of a two-dimensional electron gas, thereby improving the display performance of the display device 102, or the electrical characteristics of the RF power device.

[0111] In addition, since the structure of the silicon substrate 11 combined with the AlN crystal layer 70 or the AlON crystal layer 70 in this embodiment has high epitaxial quality, the structure of the silicon substrate 11 combined with the AlN crystal layer 70 or the AlON crystal layer 70 can be mass-produced as a new type of epitaxial substrate 10, thereby shortening the epitaxial growth time and improving production efficiency. The application fields of the structure of the silicon substrate 11 combined with the AlN crystal layer 70 or the AlON crystal layer 70 in this embodiment include but are not limited to LED epitaxy, RF power device epitaxy or other chip epitaxy, etc.

[0112] Figure 6 A schematic diagram of the layer structure of a specific epitaxial structure 105 provided in an embodiment of the present application. Fig. 6A for Figure 6 1 and 2. The manufacturing process steps of the epitaxial structure 105 in FIG.

[0113] based on Figure 3-Figure 5 For an example, see Figure 6 In some embodiments, the epitaxial structure 105 includes a silicon substrate 11 , a crystalline layer 70 , a buffer layer 20 , an epitaxial functional layer 30 , a tunneling junction layer 60 , a first distributed Bragg reflector layer 40 and a first conductive bonding layer 51 .

[0114] Among them, the crystal layer 70 is an AlN crystal layer 70 or an AlON crystal layer 70, and the AlN crystal layer 70 or the AlON crystal layer 70 is grown and formed on the silicon substrate 11 by low temperature deposition. The buffer layer 20 includes an AlGaN buffer layer 21 and a u-GaN stress buffer layer 22, the AlGaN buffer layer 21 is grown and formed on the crystal layer 70, and the u-GaN stress buffer layer 22 is grown and formed on the AlGaN buffer layer 21. The problem of poor stress caused by lattice mismatch can be effectively solved by the AlGaN buffer layer 21. The u-GaN stress buffer layer 22 can reduce the stress of the GaN material on the substrate 10 with poor lattice matching, thereby improving the quality and performance of the GaN epitaxial film. In addition, since the AlN crystal layer 70 or the AlON crystal layer 70 is grown and formed on the silicon substrate 11 by low-temperature deposition, the dislocation density between the AlN crystal layer 70 or the AlON crystal layer 70 and the silicon substrate 11 is low. On this basis, the AlGaN buffer layer 21 and the u-GaN stress buffer layer 22 are grown and formed, which can effectively reduce the dislocation density between the AlN crystal layer 70 or the AlON crystal layer 70 and the AlGaN buffer layer 21, and the AlGaN buffer layer 21 and the u-GaN stress buffer layer 22, thereby improving the epitaxial quality.

[0115] The epitaxial functional layer 30 includes an n-GaN electron injection layer 31, an InGaN short-period superlattice layer 32, a multi-period InGaN light-emitting quantum well layer 33 (Multi-Quantum Well, MQW), a p-AlGaN electron blocking layer 34 and a p-GaN hole injection layer 35, wherein the n-GaN electron injection layer 31 is grown on the u-GaN stress buffer layer 22, the InGaN short-period superlattice layer 32 is formed on the n-GaN electron injection layer 31, the multi-period InGaN light-emitting quantum well layer 33 is grown on the InGaN short-period superlattice layer 32, the p-AlGaN electron blocking layer 34 is grown on the multi-period InGaN light-emitting quantum well layer 33, and the p-GaN hole injection layer 35 is grown on the p-AlGaN electron blocking layer 34.

[0116] Specifically, the n-GaN electron injection layer 31 is used to improve the electron injection efficiency and uniformity. The n-GaN electron injection layer 31 can provide an electron supply area so that electrons can be more easily injected into the light-emitting quantum well. The InGaN short-period superlattice layer 32 is used to adjust the stress adaptation of the n-GaN electron injection layer 31 and the multi-period InGaN light-emitting quantum well layer 33, and improve the crystal quality of the short-period superlattice layer. The multi-period InGaN light-emitting quantum well layer 33 is the light-emitting part of the LED. The multi-period InGaN light-emitting quantum well layer 33 can control the light-emitting wavelength and intensity by adjusting the thickness and composition, thereby achieving light emission of different colors. The p-AlGaN electron blocking layer 34 is used to prevent electrons from diffusing to the p-GaN layer, thereby improving the recombination efficiency of electrons and holes in the multi-period InGaN light-emitting quantum well layer 33. The p-GaN hole injection layer 35 is used to provide a hole injection region, so as to achieve good injection and recombination of electrons and holes in the InGaN light-emitting quantum well 33 to generate light. The p-GaN hole injection layer 35 can provide a hole supply region so that holes can be more easily injected into the light-emitting quantum well. In the epitaxial functional layer 30 of this embodiment, holes and electrons are first injected into the p-GaN hole injection layer 35 and the n-GaN electron injection layer 31, and then recombine and emit light in the multi-period InGaN light-emitting quantum well layer 33. The InGaN short-period superlattice layer 32 can improve the efficiency and stability of the light-emitting quantum well, and the p-AlGaN electron blocking layer 34 can prevent electrons from entering the p-GaN hole injection layer 35, thereby reducing non-radiative recombination.

[0117] The tunneling junction layer 60 is grown on the p-GaN hole injection layer 35. The tunneling junction layer 60 in this embodiment is an n-type tunneling junction. For example, the tunneling junction layer 60 can be one or more of n-type doped AlN, n-type doped GaN, n-type doped InN, n-type doped InGaN, n-type doped InAlN and n-type doped AlGaN. The doping type of the tunneling junction layer 60 is opposite to the doping type of the underlying p-GaN hole injection layer 35. The material doping concentration at the interface between the p-GaN hole injection layer 35 and the tunneling junction layer 60 is the highest, and the typical doping concentration range is 1e 19 -5e 20 cm -3 .

[0118] In some embodiments, the first distributed Bragg reflector layer 40 is grown and formed on the tunneling junction layer 60. The material of the first distributed Bragg reflector layer 40 includes two or more periodic stacked structures and doping atoms of GaN, AlN, InN or a combination thereof of AlGaN, InGaN, InAlN and InAlGaN, the doping atom is Si, and the tunneling junction layer 60 is one or more of n-type doped AlN, n-type doped GaN, n-type doped InN, n-type doped InGaN, n-type doped InAlN and n-type doped AlGaN, so that the mobility of electrons between the tunneling junction layer 60 and the first distributed Bragg reflector layer 40 can be effectively improved. The introduction of the tunneling junction layer 60 can simultaneously avoid the p-type ohmic contact problem between the p-GaN hole injection layer 35 in the epitaxial functional layer 30 and the first conductive bonding layer 51.

[0119] Reference Fig. 6A The manufacturing method of the epitaxial structure 105 in the embodiment of the present application includes five steps a, b, c, d, and e, which are specifically described as follows:

[0120] a. Removal of oxide layer of substrate 10: Put silicon substrates 11 in batches into a reaction furnace, and introduce HF gas to remove the oxide layer on the surface of substrate 10.

[0121] AlN crystal layer 70 and / or AlON crystal layer 70 are grown in batches: H2O and plasma treatment form H+terminated surface, and then multiple pieces of crystal seed layer are grown in batches. The crystal seed layer can be grown into a single crystal crystal layer 70 by low temperature deposition methods such as ALD, magnetron sputtering, PECVD, ICP-CVD, molecular beam epitaxy, etc. It can be understood that the crystal layer 70 in this embodiment includes but is not limited to AlN crystal layer 70 and AlON crystal layer 70, the seed layer thickness ranges from 5 to 500 nm, and the oxygen content in the AlON crystal layer 70 can be controlled by adjusting the film forming process (such as temperature, reaction atmosphere, source concentration...).

[0122] b. On the basis of the high-quality AlN and / or AlON crystal layer 70 on the silicon substrate 11, an InGaN LED epitaxial structure 105 including an AlGaN buffer layer 21, a u-GaN stress buffer layer 22, an n-GaN electron injection layer 31, an InGaN short-period superlattice layer, a multi-period InGaN light-emitting quantum well layer, a p-AlGaN electron blocking layer 34, and a p-GaN hole injection layer 35 are grown.

[0123] c. Further epitaxially growing a tunnel junction layer 60 based on step 3), the tunnel junction layer 60 is an n-type doped alloy, the tunnel junction layer 60 is a single layer, a multi-layer or a multi-layer periodic structure, the material is a Group III nitride material, including one or more of AlN, GaN, InN, InGaN, InAlN, AlGaN, the doping type is opposite to the doping type of the lower p-GaN hole injection layer 35, the doping distribution includes uniform doping and gradient doping, the material doping concentration at the interface between the p-GaN hole injection layer 35 and the tunnel junction layer 60 is the highest, and the typical doping concentration range is 1e 19 -5e 20 cm -3 .

[0124] d. On the basis of the tunneling junction layer 60, an n-type InAlN / GaN multi-period superlattice structure is further epitaxially grown to construct a high-refractive / low-refractive high-reflectivity first distributed Bragg reflection layer 40 to reflect the photons emitted by the multi-period InGaN light-emitting quantum well layer 33 below. The first distributed Bragg reflection layer 40 is made of n-InAlN / GaN material, and the doping type of the first distributed Bragg reflection layer 40 is the same as that of the tunneling junction layer 60, with a doping concentration range of 1e17-5e20 cm-3. In practical applications, the tunneling junction layer 60 can also be omitted, and the first distributed Bragg reflection layer 40 in this embodiment can be directly used as a tunneling junction to solve the ohmic contact problem of the p-GaN material.

[0125] e. Based on the above step d, a first conductive bonding layer 51 is deposited on the first distributed Bragg reflection layer 40. The first conductive bonding layer 51 includes but is not limited to metal materials such as Au, In, Sn, Ag, Cu, Al, Cr, Ti, TiW, Ta, Ni, Pt, W, TiN, TaN, etc., with a thickness ranging from 1 nm to several μm.

[0126] Figure 7 for Figure 3 A schematic diagram of one layer structure of the epitaxial structure 105 in the embodiment; Figure 8 A schematic diagram of the layer structure of another specific epitaxial structure 105 provided in an embodiment of the present application, wherein the substrate 10 in this embodiment is a gallium arsenide substrate 12 .

[0127] based on Figure 3-Figure 5 For examples, see Figure 7 and Figure 8 In some embodiments, the substrate 10 is a gallium arsenide substrate 12. For the preparation of the red light microdisplay device 102, when the substrate 10 is a gallium arsenide substrate 12, how to improve the performance of the red light display device 102 is particularly important for the development of microLED devices.

[0128] In a specific embodiment, the epitaxial structure 105 includes a gallium arsenide substrate 12 , an epitaxial functional layer 30 , a tunnel junction layer 60 , a first distributed Bragg reflector layer 40 and a first conductive bonding layer 51 .

[0129] The epitaxial functional layer 30 includes a p-AlInGaP layer 31a, a p-AlInP layer 32a, a multi-period InGaP / AlGaInP light-emitting quantum well layer 33a, an n-AlInP layer 34a, an n-AlGaInP layer 35a, and a GaP layer 36a. The p-AlInGaP layer 31a is grown on the gallium arsenide substrate 12, the p-AlInP layer 32a is grown on the p-AlInGaP layer 31a, the multi-period InGaP / AlGaInP light-emitting quantum well layer 33a is grown on the p-AlInP layer 32a, the n-AlInP layer 34a is grown on the multi-period InGaP / AlGaInP light-emitting quantum well layer 33a, the n-AlGaInP layer 35a is grown on the n-AlInP layer 34a, and the GaP layer 36a is grown on the n-AlGaInP layer 35a.

[0130] The p-AlInGaP layer 31a is a p-type doped AlInGaP material layer, which can provide a hole supply region so that holes can be more easily injected into the light-emitting quantum well to achieve injection and recombination of electrons and holes to generate light emission.

[0131] The p-AlInP layer 32a is a p-type doped AlInP material layer, and the p-AlInP layer 32a can also provide a hole supply area, so that holes can be more easily injected into the light-emitting quantum well. The p-AlInP layer 32a cooperates with the p-AlInGaP layer 31a to provide more hole supply areas and improve the hole injection efficiency.

[0132] The multi-period InGaP / AlGaInP light-emitting quantum well layer 33a is the light-emitting core of the display device 102. The multi-period InGaP / AlGaInP light-emitting quantum well layer 33a is composed of multiple periods of InGaP and AlGaInP and is used to generate light. The band gap size of materials with different thicknesses, periods, and components is different, and the light emission wavelength and intensity can be controlled to achieve light emission of different colors.

[0133] The n-AlInP layer 34a is an n-type doped AlInP material layer, which is used to provide an electron injection region so that electrons can be more easily injected into the light-emitting quantum well, thereby achieving the injection and recombination of electrons and holes to generate light emission.

[0134] The n-AlGaInP layer 35a is an n-type doped AlGaInP material layer, which is used to provide an electron injection region, so that electrons can be more easily injected into the light-emitting quantum well, thereby achieving the injection and recombination of electrons and holes to generate light. The cooperation of the n-AlInP layer 34a and the n-AlGaInP layer 35a can provide more electrons and improve the electron injection rate.

[0135] The GaP layer 36 a is an undoped material used for buffering and enhancing the structure, and can improve the efficiency and stability of the epitaxial structure 105 in this embodiment.

[0136] The above layers interact with each other to form a complete functional structure. Holes and electrons are first injected into the p-AlInGaP layer 31a and the n-AlInP layer 34a. The p-AlInP layer 32a and the n-AlGaInP layer 35a also provide additional injection areas to enhance the injection efficiency. Then the light is recombined in the multi-period InGaP / AlGaInP light-emitting quantum well layer 33a. The GaP layer 36a is used for buffering and enhancing the structure to improve the efficiency and stability of the LED.

[0137] The tunneling junction layer 60 is grown on the GaP layer 36a, wherein the tunneling junction layer 60 may be one or more of AlAs, GaAs, GaP, InP, and AlGaInP ternary and quaternary alloy materials thereof, such as AlGaAs, AlInP, AlGaInP, etc., and the doping type is opposite to the doping type of the lower n-AlGaInP layer 35a, and the doping distribution includes uniform doping and gradient doping, which is characterized in that the material doping concentration at the interface between the n-AlGaInP layer 35a and the tunneling junction layer 60 is the highest, and the typical doping concentration range is 1e 19 -5e 20 cm -3 .

[0138] The first distributed Bragg reflector 40 is made of p-AlGaInP / AlInP material, and is grown on the tunneling junction layer 60. The doping type of the first distributed Bragg reflector 40 is the same as that of the tunneling junction layer 60, and the doping concentration range is 1e17-5e20 cm-3. In practical applications, the tunneling junction layer 60 can also be omitted, and the first distributed Bragg reflector 40 in this embodiment can be directly used to solve the ohmic contact problem of the p-GaN material.

[0139] In some embodiments, the material of the tunnel junction layer 60 includes one or more of AlAs, GaAs, GaP, AlP, InP, AlGaP, InGaP, AlGaAs, InAlP and InAlGaP and doping atoms, wherein the doping atom is Mg, that is, Mg is doped into AlAs, GaAs, GaP, AlP, InP, AlGaP, InGaP, AlGaAs, InAlP and InAlGaP, and the material of the first distributed Bragg reflector 40 includes AlAs, GaAs, GaP, AlP, InP, AlGa Two or more periodic high-fold / low-fold layer structures and doping atoms among P, InGaP, AlGaAs, InAlP and InAlGaP, wherein the doping atom is Mg, that is, Mg is doped into AlAs, GaAs, GaP, AlP, InP, AlGaP, InGaP, AlGaAs, InAlP and InAlGaP, thereby effectively improving the mobility of holes between the tunneling junction layer 60 and the first distributed Bragg reflection layer 40, and solving the n-type ohmic contact problem between the GaP layer 36a in the epitaxial functional layer 30 and the first conductive bonding layer 51.

[0140] In addition, the refractive index of the material of the gallium arsenide substrate 12 system is large, and it is difficult for the display device 102 to extract light; the introduction of the first distributed Bragg reflection layer 40 of p-AlGaInP / AlInP material can effectively improve the light extraction efficiency of the display device 102.

[0141] In some embodiments, a buffer layer 20 is grown on the gallium arsenide film, and the buffer layer 20 may be at least one layer formed of group III phosphides. The buffer layer 20 can further eliminate the influence of dislocations and increase tensile stress.

[0142] Fig. 9 A schematic diagram of the layer structure of another possible epitaxial structure 105 provided in an embodiment of the present application. Fig.10 Based on Fig. 9 A schematic diagram of a specific layer structure of an epitaxial structure 105 in the embodiment; Fig.11 Based on Fig. 9 A schematic diagram of a specific layer structure of the epitaxial structure 105 in the embodiment.

[0143] based on Figure 3-Figure 5 For an example, see Fig. 9The epitaxial structure 105 includes a substrate 10, a second distributed Bragg reflector layer 80, an epitaxial functional layer 30, a first distributed Bragg reflector layer 40 and a first conductive bonding layer 51, wherein the substrate 10, the epitaxial functional layer 30, the first distributed Bragg reflector layer 40 and the first conductive bonding layer 51 can be referred to the above text and will not be described in detail here. The distributed Bragg emitting layer and the first distributed Bragg reflector layer 40 are respectively formed on opposite sides of the epitaxial functional layer 30, that is, the second distributed Bragg reflector layer 80 is formed on the side of the epitaxial functional layer 30 facing the substrate 10, and the first distributed Bragg reflector layer 40 is formed on the side of the epitaxial functional layer 30 away from the substrate 10. In this embodiment, the second distributed Bragg reflector layer 80 and the first distributed Bragg reflector layer 40 form a resonant cavity without affecting the carrier transmission in the epitaxial functional layer 30, and the formed resonant cavity can effectively reduce the light output angle of the epitaxial structure 105 and increase the vertical light output efficiency of the epitaxial structure 105.

[0144] In some embodiments, the distance d between the resonant cavities in the first direction should satisfy the formula:

[0145] The physical meanings of the parameters in the formula are as follows: q is the resonance mode number; λ is the wavelength of the light emitted by the display device 102 ; and n is the comprehensive average refractive index of the epitaxial functional layer 30 , that is, the equivalent refractive index of the epitaxial functional layer 30 .

[0146] The distance d between the resonant cavities in the first direction in this embodiment is the distance between the second distributed Bragg reflector layer 80 and the first distributed Bragg reflector layer 40 in the first direction. For the red light display device 102 of the GaAs system, such as the red light AlInGaP display device 102, due to the high refractive index (3.0-3.5) of the AlInGaP-based material, the side total reflection accounts for a large proportion and the front light extraction efficiency is low. By adjusting the distance d between the first and second distributed Bragg reflectors in the RC (resonant cavity)-LED in the first direction, the front light extraction efficiency of the display device 102 of this embodiment can be effectively improved, and the front light extraction angle of the display device 102 can be shortened.

[0147] In some embodiments, the first conductive bonding layer 51 is a high reflectivity metal film, such as high reflectivity metals including but not limited to Al, Au, Pt, Cu, etc. In this embodiment, the first distributed Bragg reflector layer 40 and the high reflectivity first conductive bonding layer 51 can form an omni-directional reflector (ODR) structure, which can reflect light at all angles. Therefore, without destroying the carrier transmission effect of the epitaxial functional layer 30 in the resonant cavity as described above, the overall light extraction efficiency of the epitaxial structure 105 can be further improved, and the light extraction efficiency of the subsequent display device 102 can be increased. In particular, when the epitaxial structure 105 in this embodiment is applied to microLED, this is crucial for the application of microLED in AR, VR and other projection systems. The small-angle front light emission of the device can enable the emitted light to be efficiently coupled into the waveguide module, solving the light efficiency and brightness problems in NED (near-eye display system). The omni-directional reflector system composed of high-reflectivity metal and DBR can further improve the overall light extraction efficiency of the device and increase the device efficiency of the subsequent microLED.

[0148] It is understandable that the second distributed Bragg reflector 80 in this embodiment may be conductive or non-conductive. The material of the second distributed Bragg reflector 80 depends on the material of the substrate 10 of the epitaxial structure 105 or the type of specific material epitaxial system. In addition to the in-situ epitaxial growth of the second distributed Bragg reflector 80, further, on the flip-chip epitaxial wafer after removing the substrate, a typical distributed Bragg reflector structure such as SiO2 / TiO2 can be grown by typical PECVD (Plasma-Enhanced Chemical Vapor Deposition) coating and the like.

[0149] based on Figure 6 and Fig. 9 For an example, see Fig.10 In some embodiments, the substrate 10 is a silicon substrate 11, and the second distributed Bragg reflection layer 80 is located between the AlGaN buffer layer 21 and the u-GaN stress buffer layer 22. In this embodiment, the second distributed Bragg reflection layer 80 is located between the AlGaN buffer layer 21 and the u-GaN stress buffer layer 22, which will not affect the carrier transmission effect of the epitaxial functional layer 30, and the second distributed Bragg reflection layer 80 and the first distributed Bragg reflection layer 40 can form a resonant cavity to improve the overall light extraction efficiency of the epitaxial structure 105.

[0150] Of course, in some other embodiments, the second distributed Bragg reflector layer 80 may also be located between the n-GaN electron injection layer 31 and the u-GaN stress buffer layer 22 .

[0151] In some embodiments, the second distributed Bragg reflection layer 80 may be at least two high-fold / low-fold layers formed of group III nitrides, such as two or more periodic stacked structures of GaN, AlN, InN, AlGaN, InGaN, InAlN, and InAlGaN.

[0152] based on Figure 7-Figure 9 For an example, see Fig.11 In some embodiments, the substrate 10 is a gallium arsenide substrate 12, and the second distributed Bragg reflection layer 80 is located between the gallium arsenide substrate 12 and the p-AlInGaP layer 31a, so as not to affect the carrier transmission effect of the epitaxial functional layer 30, and the second distributed Bragg reflection layer 80 and the first distributed Bragg reflection layer 40 can form a resonant cavity to improve the overall light extraction efficiency of the epitaxial structure 105.

[0153] In some embodiments, the second distributed Bragg reflection layer 80 may be at least two high-folding / low-folding layers formed of Group III phosphides, and the material of the second distributed Bragg reflection layer 80 includes two or more periodic stacked structures of GaP, AlP, InP, AlGaP, InGaP, InAlP and InAlGaP.

[0154] In some embodiments, the first conductive bonding layer 51 is formed on the first distributed Bragg reflector layer 40, and the first conductive bonding layer 51 is a high reflectivity metal film, such as a metal material with a reflectivity of more than 70% for the light emitted by the LED device. High reflectivity metals include but are not limited to Al, Au, Pt, Cu, etc.

[0155] Fig.12 A schematic diagram of the layer structure of another possible epitaxial structure 105 provided in an embodiment of the present application.

[0156] based on Figure 3-Figure 11 For an example, see Fig.12 , the epitaxial functional layer 30 is pixelated and forms a plurality of spaced pixel mounting steps 301. In the epitaxial structure 105 in this embodiment, since the epitaxial functional layer 30 is pixelated and forms a plurality of spaced pixel mounting steps 301, in the subsequent process of forming the display device 102, the epitaxial structure 105 does not need to be pixelated in the epitaxial functional layer 30, but can be directly connected to the CMOS driving backplane 90 (as shown in the embodiment below), thereby avoiding damage to the CMOS driving backplane 90 during the pixelation process of the display device 102.

[0157] In some implementations, the epitaxial functional layer 30 is pixelated to form a plurality of pixel installation steps 301 , and in the first direction, projections of the plurality of pixel installation steps 301 on the substrate 10 are spaced apart from each other.

[0158] In some embodiments, a metal retaining wall 302 and a dielectric layer 303 are provided between the plurality of spaced pixel installation steps 301. In this embodiment, the plurality of pixel installation steps 301 are spaced apart by the metal retaining wall 302 and the dielectric layer 303 and no longer affect each other.

[0159] It is understood that the pixelation of the epitaxial functional layer 30 in this embodiment can be combined with Figure 3-Figure 12 In any of the embodiments.

[0160] It can be understood that the epitaxial structure 105 in this embodiment can be sold as an independent sales unit, and can also be sold as a part of the display device 102 in conjunction with the display device 102. As long as it can be determined that the CMOS driver backplane 90 is docked on the basis of the epitaxial structure 105 in this embodiment, it is within the protection scope of the epitaxial structure 105 in this embodiment.

[0161] It can be understood that the epitaxial structure 105 in the above embodiments can be applied not only to the display device 102 , but also to various chip structures or other devices that require the epitaxial structure 105 .

[0162] The embodiment of the present application also provides a display device 102. The display device 102 in the present embodiment is further processed on the basis of the epitaxial structure 105 in the above embodiment. In order to avoid redundant and repeated content, some components included in the epitaxial structure 105 in the above embodiment will be directly quoted in the display device 102 in the embodiment of the present application without giving too much explanation on their principles, materials, positional relationships, connection relationships, etc.

[0163] Fig.13 A schematic diagram of a possible layer structure of a display device 102 provided in an embodiment of the present application.

[0164] See also Fig.13 The display device 102 includes a lens 106, an epitaxial functional layer 30, a first distributed Bragg reflection layer 40, a first conductive bonding layer 51 and a CMOS driving backplane 90, wherein the epitaxial functional layer 30, the first distributed Bragg reflection layer 40, the first conductive bonding layer 51 and the CMOS driving backplane 90 are stacked in sequence.

[0165] The epitaxial functional layer 30 is used for emitting light, and the lens 106 is used for focusing the light emitted by the epitaxial functional layer 30 .

[0166] The epitaxial functional layer 30 , the first distributed Bragg reflector layer 40 and the first conductive bonding layer 51 may refer to the epitaxial functional layer 30 , the first distributed Bragg reflector layer 40 and the first conductive bonding layer 51 in the epitaxial structure 105 in the previous embodiment, and no further details are given here.

[0167] The CMOS driving backplane 90 is bonded to the first conductive bonding layer 51, and the lens 106 is arranged on the side of the epitaxial functional layer 30 away from the CMOS driving backplane 90. The display device 102 in this embodiment is conducive to improving the internal quantum efficiency (Internal Quantum Efficiency, IQE) of the display device 102 in this embodiment due to the high-quality epitaxial growth of the epitaxial structure 105, and the structural integration of the lens 106 is conducive to improving the light extraction efficiency (Light Extraction Efficiency, LEE) of the display device 102, thereby improving the device efficiency and light shape of the display device 102. In addition, the light extraction efficiency of the display device 102 can be significantly improved by the first distributed Bragg reflection layer 40. In addition, since the first conductive bonding layer 51 is located on the side of the first distributed Bragg reflector 40 away from the lens 106, the CMOS driving backplane 90 is bonded to the first conductive bonding layer 51, so that the light absorption problem of the first conductive bonding layer 51 and the CMOS driving backplane 90 on the light emitted by the LED device can be avoided through the reflection of the first distributed Bragg reflector 40, so as to improve the light extraction efficiency of the display device 102. In addition, the in-situ epitaxial first distributed Bragg reflector 40 is well compatible with the CMOS process, decoupling the two problems of the first conductive bonding layer 51 and the high reflectivity bottom surface, effectively reducing the process difficulty of the bonding part.

[0168] In some embodiments, the display device 102 further includes a transparent electrode layer 52, which is disposed on a side of the epitaxial functional layer 30 away from the CMOS driving backplane, and the lens 106 is disposed on the transparent electrode layer 52. Part of the light emitted by the epitaxial functional layer 30 is directly emitted in a direction away from the CMOS driving backplane 90, and part of the light is emitted toward the conductive Bragg emission layer in the direction of the CMOS driving backplane 90, and then the part of the light is reflected by the conductive Bragg emission layer and emitted again in a direction away from the CMOS driving backplane 90, thereby improving the light extraction efficiency of the display device 102 in this embodiment.

[0169] In some embodiments, the material constituting the transparent electrode layer 52 includes but is not limited to indium tin oxide (ITO), indium zinc oxide (Indium Zinc Oxide, IZO), indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), zinc magnesium oxide (ZnMgO), zinc oxide (IZO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), and zirconium oxide (ZrO2).

[0170] In some embodiments, the thickness of the deposited film of the transparent electrode layer 52 is 10 nm-500 nm.

[0171] In some embodiments, the epitaxial functional layer 30 is pixelated to form a plurality of pixel mounting steps 301 . In a first direction, projections of the plurality of pixel mounting steps 301 on the substrate 10 are spaced apart from each other. The first direction is the stacking direction of the substrate 10 and the epitaxial functional layer 30 . A lens 106 is provided on each pixel mounting step 301 in a one-to-one correspondence.

[0172] In some embodiments, a metal retaining wall 302 is provided between several spaced pixel installation steps 301, and a dielectric layer 303 is provided between the metal retaining walls 302. In this embodiment, several pixel installation steps 301 are separated by the metal retaining wall 302 and the dielectric layer 303, and no longer affect each other. The dielectric layer 303 includes but is not limited to SiO2, Al2O3, SiNx, ZrO3, HfO2, TiO2, Ta2O5, AlN, SiON, SiCN; the metal retaining wall 302 includes but is not limited to high reflectivity metal materials such as Al, Ag, Pt, Au, Cu, Ti, Ni and Cr.

[0173] In some implementations, the display device 102 further includes a second conductive bonding layer 53, the second conductive bonding layer 53 is aligned and bonded with the first conductive bonding layer 51, and the second conductive bonding layer 53 is located on the CMOS driving backplane 90. In this implementation, since the CMOS driving backplane 90 is easily aligned and bonded with the first conductive bonding layer 51 through the second conductive bonding layer 53, the bonding process difficulty of the CMOS driving backplane 90 can be reduced.

[0174] In some embodiments, the first conductive bonding layer 51 includes a first metal portion 511 and a first dielectric portion 512, and the second conductive bonding layer 53 includes a second metal portion 531 and a second dielectric portion 532. When aligning the second conductive bonding layer 53 with the first conductive bonding layer 51, it is only necessary to align the first metal portion 511 with the second metal portion 531, align the first dielectric portion 512 with the second dielectric portion 532, and then bond them. In this embodiment, since it is easy to align the second conductive bonding layer 53 with the first conductive bonding layer 51, the bonding process difficulty of the CMOS driver backplane 90 can be reduced.

[0175] In some implementations, the first metal portion 511 is disposed in a one-to-one correspondence with the pixel mounting step 301 , and the first dielectric portion 512 is disposed in a one-to-one correspondence with the dielectric layer 303 .

[0176] In some implementations, the first dielectric portion 512 and the second dielectric portion 532 both include, but are not limited to, SiOx, SiNx, SiON, Al2O3, and the like.

[0177] In some implementations, a metal mesh electrode and an n-metal electrode are formed on the transparent electrode layer 52 , thereby increasing the charge transfer efficiency of the display device 102 .

[0178] Fig.14 Based on Figure 6 Schematic diagram of the layer structure of the display device 102 formed by processing the epitaxial structure 105 in the embodiment. Fig.14A for Fig.14 1 and 2. The manufacturing process steps of the display device 102 in FIG.

[0179] See also Figure 6 , Fig.13 as well as Fig.14 In some embodiments, the display device 102 includes a lens 106 , a transparent electrode layer 52 , an epitaxial functional layer 30 , a first distributed Bragg reflection layer 40 , a first conductive bonding layer 51 , and a CMOS driving backplane 90 .

[0180] The epitaxial functional layer 30 includes an n-GaN electron injection layer 31, an InGaN short-period superlattice layer 32, a multi-period InGaN light-emitting quantum well layer 33, a p-AlGaN electron blocking layer 34 and a p-GaN hole injection layer 35, wherein the n-GaN electron injection layer 31, the InGaN short-period superlattice layer 32, the multi-period InGaN light-emitting quantum well layer 33, the p-AlGaN electron blocking layer 34 and the p-GaN hole injection layer 35 can refer to the above embodiments and are not described in detail here. Each pixel installation step 301 is composed of an n-GaN electron injection layer 31, an InGaN short-period superlattice layer 32, a multi-period InGaN light-emitting quantum well layer 33, a p-AlGaN electron blocking layer 34 and a p-GaN hole injection layer 35 stacked.

[0181] In some embodiments, the transparent electrode layer 52 is formed on the n-GaN electron injection layer 31, and each layer constituting the epitaxial functional layer 30 is made of transparent materials, so that the light emitted by the multi-period InGaN light-emitting quantum well layer 33 can reach the first distributed Bragg reflection layer 40 from the epitaxial functional layer 30, so that the first distributed Bragg reflection layer 40 can play its reflective role to improve the light extraction efficiency of the display device 102.

[0182] In some implementations, the CMOS driving backplane 90 is bonded to the first conductive bonding layer 51 .

[0183] In some implementations, the first conductive bonding layer 51 includes a first metal portion 511 and a first dielectric portion 512 , the first metal portion 511 is disposed in one-to-one correspondence with the pixel mounting step 301 , and the first dielectric portion 512 is disposed in one-to-one correspondence with the dielectric layer 303 .

[0184] See also Fig. 6A as well as Fig.14A The manufacturing process steps of the display device 102 in this embodiment include Fig. 6A The five steps a, b, c, d, e and Fig.14A The four steps f, g, h, and i are described as follows:

[0185] f, will Fig. 6A Based on step e in Figure 6 The epitaxial structure 105 of the embodiment is bonded to the CMOS driving backplane 90 in a “top-down” manner.

[0186] g. Remove the silicon substrate 11, the AlN crystal layer 70 and / or the AlON crystal layer 70, the AlGaN buffer layer 21, and the u-GaN stress buffer layer 22. Specific removal methods include but are not limited to dry etching, wet etching, polishing, CMP (Chemical-Mechanical Planarization), etc.

[0187] h. Next, the wafer structure bonded with the CMOS driving backplane 90 is further processed for display device 102 manufacturing, such as ICP etching, dielectric coating, CMP planarization and other pixel manufacturing processes, the epitaxial functional layer 30 is divided into a number of pixel installation steps 301, and then the transparent electrode layer 52 is deposited.

[0188] i. Next, lenses 106 are integrated on a plurality of pixel installation steps 301 , wherein the lenses 106 correspond to the pixel installation steps 301 one by one.

[0189] Fig.15 Based on Figure 6 Schematic diagram of the layer structure of another display device 102 formed by processing the epitaxial structure 105 in the embodiment. Fig.15A for Fig.15 1 and 2. The manufacturing process steps of the display device 102 in FIG. Fig. 15B for Fig.15A One of the top views of the array structure after step e. Fig. 15C for Fig.15A Another top view of the array structure after step e.

[0190] See also Figure 13-Figure 15 The display device 102 includes a lens 106 , a transparent electrode layer 52 , an epitaxial functional layer 30 , a first distributed Bragg reflection layer 40 , a first conductive bonding layer 51 and a CMOS driving backplane 90 .

[0191] The display device 102 in this embodiment is compared with Fig.14 The display device 102 of the embodiment in the structure is different in that the display device 102 in this embodiment also includes a second conductive bonding layer 53, the second conductive bonding layer 53 is deposited on the CMOS driving backplane 90, and the second conductive bonding layer 53 is aligned and connected with the first conductive bonding layer 51.

[0192] In some embodiments, the second conductive bonding layer 53 includes a second metal portion 531 and a second dielectric portion 532. When aligning the second conductive bonding layer 53 with the first conductive bonding layer 51, it is only necessary to align the first metal portion 511 with the second metal portion 531 and the first dielectric portion 512 with the second dielectric portion 532. This can easily realize the connection between the second conductive bonding layer 53 and the first conductive bonding layer 51.

[0193] See also Fig. 6A as well as Fig.15A Based on the structure of the display device 102 in this embodiment, the manufacturing process steps of the display device 102 in this embodiment include: Fig. 6A The five steps a, b, c, and d in Fig.15A The five steps e, f, g, h, and i are described as follows:

[0194] e, will Figure 6 The epitaxial structure 105 of the embodiment is used to manufacture the display device 102, for example: Fig. 6A On the basis of step d in the above, a pixelation process is performed to separate the epitaxial functional layer 30 into a plurality of pixel installation steps 301, for example, the epitaxial functional layer 30 is separated into a plurality of pixel installation steps 301 by an etching process.

[0195] like Fig. 15B and Fig. 15C The top view of the two array structures after etching in step e is shown in FIG. Fig. 15B In some embodiments, a plurality of pixel mounting steps 301 may be arranged in a square array. Fig. 15B The dotted line portion in FIG. 3 is a square structure surrounded by four adjacent pixel installation steps 301. Fig. 15C In some other implementations, the plurality of pixel mounting steps 301 may also be arranged in a regular hexagonal array. Fig. 15CThe dotted line portion in FIG. 3 is a regular hexagonal structure surrounded by six adjacent pixel installation steps 301. It can be understood that the distribution of the plurality of pixel installation steps 301 can be various and is not limited to the above Fig. 15B and Fig. 15C In addition to the square and regular hexagonal array structures, the plurality of pixel mounting steps 301 may also be arranged in an elliptical array, a rectangular array, or arrays of other shapes.

[0196] The pixelated epitaxial structure 105 is subjected to nitrogen atmosphere annealing, that is, the p-GaN hole injection layer 35 is subjected to nitrogen atmosphere annealing to remove hydrogen after growth, so that the p-GaN hole injection layer can be activated with Mg, thereby improving p-GaN charge transport and device luminescence performance.

[0197] A dielectric layer 303 and a high-reflectivity metal sidewall barrier are filled between a plurality of pixel installation steps 301 .

[0198] f. On the basis of filling the dielectric layer 303 and the metal retaining wall 302, the first conductive bonding layer 51 is further processed to form a first metal portion 511 and a through hole corresponding to the dielectric layer 303 surrounded by the first metal portion 511, and then the dielectric is filled around the through hole to form a first dielectric portion 512 of the first conductive bonding layer 51.

[0199] The second conductive bonding layer 53 is processed to form a second metal portion 531 and a through hole surrounded by the second metal portion 531 and corresponding to the dielectric layer 303 , and then a dielectric is filled around the through hole to form a second dielectric portion 532 of the second conductive bonding layer 53 .

[0200] g. The CMOS driving backplane 90 deposited with the second conductive bonding layer 53 is bonded to the first conductive bonding layer 51 by aligning the first metal part 511 with the second metal part 531 and the first dielectric part 512 with the second dielectric part 532.

[0201] h. Remove the silicon substrate 11, the AlN crystal layer 70 and / or the AlON crystal layer 70, the AlGaN buffer layer 21, and the u-GaN stress buffer layer 22. Specific removal methods include but are not limited to dry etching, wet etching, polishing, CMP, and the like.

[0202] i. After the n-GaN electron injection layer 31 is exposed, a transparent electrode layer 52 is deposited on this basis.

[0203] The lenses 106 are integrated on a plurality of pixel installation steps 301 , wherein the lenses 106 correspond to the pixel installation steps 301 one by one.

[0204] The display device 102 in this embodiment includes the first conductive bonding layer 51 and the second conductive bonding layer 53. Therefore, in terms of the manufacturing process, a pixelation process can be performed first, and then the CMOS driving backplane 90 can be bonded. Therefore, the CMOS driving backplane 90 will not be damaged during the pixelation process, and the yield of the display device 102 can be effectively improved.

[0205] Fig.16 Based on Figure 8 Schematic diagram of the layer structure of the display device 102 formed by processing the epitaxial structure 105 in the embodiment.

[0206] See also Figure 8 , Fig.13 as well as Fig.16 In some embodiments, the display device 102 includes a lens 106 , a transparent electrode layer 52 , an epitaxial functional layer 30 , a first distributed Bragg reflection layer 40 , a first conductive bonding layer 51 , a second conductive bonding layer 53 and a CMOS driving backplane 90 .

[0207] The epitaxial functional layer 30 includes a p-AlInGaP layer 31a, a p-AlInP layer 32a, a multi-period InGaP / AlGaInP light-emitting quantum well layer 33a, an n-AlInP layer 34a, an n-AlGaInP layer 35a, and a GaP layer 36a. The p-AlInGaP layer 31a, the p-AlInP layer 32a, the multi-period InGaP / AlGaInP light-emitting quantum well layer 33a, the n-AlInP layer 34a, the n-AlGaInP layer 35a, and the GaP layer 36a can refer to the above embodiments, and no further details are given here.

[0208] The transparent electrode layer 52 is formed on the p-AlInGaP layer 31a, the first conductive bonding layer 51 is formed on the first distributed Bragg reflection layer 40 of the p-AlGaInP / AlInP material, and the CMOS driving backplane 90 is bonded to the first conductive bonding layer 51 through the second conductive bonding layer 53. The bonding method of the CMOS driving backplane 90 being bonded to the first conductive bonding layer 51 through the second conductive bonding layer 53 can be referred to in the above Fig.16 The embodiments in .

[0209] The bonding difficulty of the CMOS driving backplane 90 of the epitaxial structure 105 of the gallium arsenide substrate 12 is relatively large, and the gallium arsenide substrate 12 is very easy to break, thereby increasing the difficulty of the bonding process. However, the display device 102 in this embodiment introduces the first distributed Bragg reflection layer 40 of p-AlGaInP / AlInP material, which broadens the metal type selection space of the first conductive bonding layer 51, thereby effectively reducing the process difficulty of the bonding part.

[0210] The manufacturing process of the display device 102 in this embodiment can refer to the previous embodiment and will not be described in detail here.

[0211] Fig.17 Based on Fig.11 Schematic diagram of the layer structure of the display device 102 formed by processing the epitaxial structure 105 in the embodiment.

[0212] See also Fig.11 , Fig.13 as well as Fig.17 The display device 102 includes a lens 106 , a transparent electrode layer 52 , an epitaxial functional layer 30 , a first distributed Bragg reflection layer 40 , a first conductive bonding layer 51 , a second conductive bonding layer 53 and a CMOS driving backplane 90 .

[0213] The display device 102 in this embodiment is compared with Fig.16 The display device 102 further includes a second distributed Bragg reflection layer 80, which is located between the transparent conductive layer and the p-AlInGaP layer 31a. The distributed Bragg emission layer and the first distributed Bragg reflection layer 40 are respectively formed on opposite sides of the epitaxial functional layer 30. In this embodiment, the second distributed Bragg reflection layer 80 and the first distributed Bragg reflection layer 40 form a resonant cavity without affecting the carrier transmission in the epitaxial functional layer 30. The formed resonant cavity can effectively reduce the light output angle of the display device 102 and increase the vertical light output efficiency of the display device 102.

[0214] In some embodiments, the first conductive bonding layer 51 is a high reflectivity metal film, such as a metal film with a reflectivity of more than 70%. In this embodiment, the first distributed Bragg reflector 40 is combined with the first conductive bonding layer 51, and the two can form an omni-directional reflector (ODR) structure. The omni-directional reflector structure can reflect light at all angles, so that the overall light extraction efficiency of the display device 102 can be further improved without destroying the carrier transmission effect of the epitaxial functional layer 30.

[0215] It should be noted that the drawings in the embodiments of the present application are mostly layer structures, and the layer name referred to by each layer needs to refer to the label. Two layers with the same filling method do not mean that the layer names are the same, nor do they mean that the components are the same.

[0216] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A display device, characterized in that: The display device includes an epitaxial functional layer, a first distributed Bragg reflection layer, a first conductive bonding layer and a CMOS driving backplane which are stacked in sequence, the epitaxial functional layer is used for emitting light, the first conductive bonding layer is formed on the first distributed Bragg reflection layer, and the CMOS driving backplane is bonded to the first conductive bonding layer, wherein the first distributed Bragg reflection layer is used for improving the light extraction efficiency of the display device and electrically connecting the epitaxial functional layer and the first conductive bonding layer.

2. The display device according to claim 1, characterized in that The first distributed Bragg reflector layer is a layer structure formed by doping doping atoms in a Bragg reflector.

3. The display device according to claim 2, characterized in that The material of the Bragg reflector includes one or more of GaN, AlN, InN, AlGaN, InGaN, InAlN and InAlGaN, and the material of the doping atoms includes Si; or The material of the Bragg reflector includes one or more of GaP, AlP, InP, AlGaP, InGaP, InAlP and InAlGaP, and the material of the doping atoms includes Mg.

4. The display device according to any one of claims 1 to 3, characterized in that: The material of the first conductive bonding layer includes one or more of Au, In, Sn, Cu, Al, Cr, Ti, TiW, Ta, Ni, Pt, W, TiN, and TaN.

5. The display device according to claim 3, characterized in that: The display device also includes a tunneling junction layer of the same doping type as the first distributed Bragg reflective layer, the tunneling junction layer is formed on the epitaxial functional layer, the first distributed Bragg reflective layer is formed on the tunneling junction layer, and the tunneling junction layer can improve the transmission capability of electrons or holes from the epitaxial functional layer to the first distributed Bragg reflective layer.

6. The display device according to claim 5, characterized in that The material of the tunnel junction layer includes one or more of n-type doped GaN, n-type doped AlN and n-type doped InN; or The material of the tunnel junction layer includes one or more of n-type doped AlGaN, n-type doped InGaN, n-type doped InAlN and n-type doped InAlGaN; or The material of the tunnel junction layer includes one or more of p-type doped AlAs, p-type doped GaAs, p-type doped GaP, p-type doped AlP, p-type doped InP, p-type doped AlGaP, p-type doped InGaP, p-type doped AlGaAs, p-type doped InAlP and p-type doped InAlGaP.

7. The display device according to any one of claims 1 to 6, characterized in that: The display device further includes a second distributed Bragg reflection layer. The epitaxial functional layer is located between the second distributed Bragg reflection layer and the first distributed Bragg reflection layer. A resonant cavity is formed between the second distributed Bragg reflection layer and the first distributed Bragg reflection layer.

8. The display device according to claim 7, characterized in that: The first direction is the direction in which the second distributed Bragg reflection layer and the first distributed Bragg reflection layer are stacked, the second distributed Bragg reflection layer and the first distributed Bragg reflection layer constitute a q-mode resonator, the distance between the second distributed Bragg reflection layer and the first distributed Bragg reflection layer in the first direction is d, the wavelength of the light emitted by the epitaxial functional layer is λ, and the comprehensive refractive index of the epitaxial functional layer is n, wherein, 9. The display device according to claim 7 or 8, characterized in that: The first conductive bonding layer and the first distributed Bragg reflection layer form a full-angle reflection mirror.

10. The display device according to any one of claims 1 to 9, characterized in that: The display device further comprises a second conductive bonding layer, the second conductive bonding layer is aligned and bonded with the first conductive bonding layer, and the second conductive bonding layer is above the CMOS driving backplane.

11. The display device according to claim 10, characterized in that: The first conductive bonding layer includes a first metal part and a first dielectric part adjacent to the first metal part, the second conductive bonding layer includes a second metal part and a second dielectric part adjacent to the second metal part, the first metal part and the second metal part are bonded one-to-one, and the first dielectric part and the second dielectric part correspond one-to-one.

12. An epitaxial structure, characterized in that: The invention comprises a substrate, an epitaxial functional layer, a tunneling junction layer, a first distributed Bragg reflector layer and a first conductive bonding layer which are stacked in sequence, wherein the tunneling junction layer is formed on the epitaxial functional layer, the first distributed Bragg reflector layer is formed on the tunneling junction layer, the first conductive bonding layer is formed on the first distributed Bragg reflector layer, and the first distributed Bragg reflector layer is used to improve the light extraction efficiency of the epitaxial structure and electrically connect the epitaxial functional layer and the first conductive bonding layer.

13. The epitaxial structure according to claim 12, characterized in that: The substrate includes a silicon base, the epitaxial structure further includes an AlON crystal layer, the AlON crystal layer is formed on the silicon base, and the epitaxial functional layer is formed on the AlON crystal layer.

14. The epitaxial structure according to claim 13, characterized in that: In the AlON crystal layer, the proportion of O element is 10ppm-50%.

15. The epitaxial structure according to any one of claims 12 to 14, characterized in that: The epitaxial functional layer is pixelated to form a plurality of pixel installation steps, and projections of the plurality of pixel installation steps on the substrate are spaced apart from each other in a first direction, wherein the first direction is a stacking direction of the substrate and the epitaxial functional layer.

16. An electronic device, characterized in that: The invention comprises a housing and a display device as claimed in any one of claims 1 to 11, wherein the display device is arranged on the housing.

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