Back-end-of-line resistor structure

Abstract

The invention relates to a back-end-of-line resistor structure. The present disclosure describes a resistor structure having a dielectric layer, a trench, a metal layer, a semiconductor layer, and an insulating layer. A dielectric layer is disposed over an electrical component formed on a substrate. The trenches are disposed in the dielectric layer and are separated from each other by a dielectric region of the dielectric layer. A metal layer is disposed on a bottom surface and side surfaces of each trench and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, a side surface, and a top surface of the metal layer. An insulating layer is disposed in the trench and is in contact with a side surface of the semiconductor layer and a top surface of the semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to a back end of line resistor structure. Background Art

[0002] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the size of circuit elements, such as active devices (e.g., planar metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (finFETs), and gate all around field effect transistors (GAAFETs)) and passive devices (e.g., capacitors, inductors, and resistors). As the number of circuit elements increases, the implementation of these circuit elements becomes increasingly complex. Summary of the invention

[0003] According to one embodiment of the present disclosure, a resistor structure is provided, including: a dielectric layer, arranged above a plurality of electrical components formed on a substrate; a plurality of grooves, arranged in the dielectric layer and separated from each other by dielectric regions of the dielectric layer; a metal layer, arranged on the bottom surface and side surfaces of each of the plurality of grooves and on the top surface of the dielectric region; a semiconductor layer, arranged on the bottom surface, side surface and top surface of the metal layer; and an insulating layer, arranged in the plurality of grooves and in contact with the side surface of the semiconductor layer and the top surface of the semiconductor layer.

[0004] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate having a plurality of electrical components formed on the substrate; and a metal region disposed above the plurality of electrical components, wherein the metal region comprises: a dielectric layer; a plurality of interconnect structures disposed in the dielectric layer; and a resistor structure disposed in the dielectric layer and in contact with the plurality of interconnect structures, wherein the resistor structure comprises: a plurality of grooves separated from each other by the dielectric region of the dielectric layer; a metal layer disposed on the bottom surface and side surfaces of each of the plurality of grooves and on the top surface of the dielectric region; a semiconductor layer disposed on the bottom surface, side surface and top surface of the metal layer; and an insulating layer disposed in the plurality of grooves and in contact with the side surface of the semiconductor layer and the top surface of the semiconductor layer.

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a dielectric layer above a plurality of electrical components disposed on a substrate; forming a plurality of grooves in the dielectric layer, the plurality of grooves being separated from each other by a dielectric region of the dielectric layer; depositing a metal layer on a bottom surface and a side surface of each of the plurality of grooves and on a top surface of the dielectric region; depositing a semiconductor layer on a bottom surface, a side surface, and a top surface of the metal layer; and depositing an insulating layer in the plurality of grooves, the insulating layer being in contact with the side surface of the semiconductor layer and the top surface of the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features can be arbitrarily increased or reduced.

[0007] Figure 1 A cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0008] Figure 2 A cross-sectional view of a portion of a semiconductor device according to some embodiments of the present disclosure is shown.

[0009] Figure 3 Another cross-sectional view of a portion of a semiconductor device according to some embodiments of the present disclosure is shown.

[0010] Figure 4 A deep trench resistor formed in a back end of line region of a semiconductor device according to some embodiments of the present disclosure is shown.

[0011] Figure 5 A method of forming a resistor structure in a back-end-of-line region of a semiconductor device according to some embodiments of the present disclosure is shown.

[0012] FIG. 6A to FIG. 14A as well as FIG. 6B to FIG. 14B Top-level and cross-sectional views of a deep trench resistor in a back-end-of-line region of a semiconductor device at various stages of fabrication are shown according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are examples only and are not intended to be limiting. In addition, the present disclosure repeats the figure marks and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and unless otherwise indicated, the relationship between the various embodiments and / or configurations discussed is not indicated by itself. Spatial related terms (e.g., "below," "below," "lower," "above," "higher," etc.) can be used herein to easily describe the relationship between an element or feature shown in the figure relative to another (one or more) element or (one or more) feature. These spatial related terms are also intended to cover different orientations of the device in use or operation except for the orientation shown in the figure. The device can be oriented in other directions (rotated 90 degrees or in other directions), and the spatial related descriptors used herein can be similarly interpreted accordingly.

[0014] It should be noted that references in the specification to "one embodiment", "an embodiment", "an example embodiment", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered that it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0015] It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, so that the phraseology or terminology of the specification is interpreted by persons skilled in the relevant art(s) based on the teachings and guidance herein.

[0016] In some embodiments of the present disclosure, the terms "about" and "substantially" may mean that the value of a given amount varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value interpreted by a person skilled in the relevant art(s) in accordance with the teachings herein.

[0017] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the size of circuit elements, such as active devices (e.g., MOSFETs, finFETs, and GAAFETs) and passive devices (e.g., capacitors, inductors, and resistors). As the number of circuit elements increases, the implementation of these circuit elements becomes increasingly complex.

[0018] The present disclosure describes a semiconductor structure and a method for forming a resistor structure (e.g., an interconnect structure disposed above a substrate of a semiconductor device) in a back-end process region of a semiconductor device. The resistor structure may include a dielectric layer, a groove, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above an electrical component formed on a substrate. The grooves are disposed in the dielectric layer and are separated from each other by dielectric regions of the dielectric layer. The metal layer is disposed on the bottom surface and side surface of each groove and on the top surface of the dielectric region. The semiconductor layer is disposed on the bottom surface, side surface, and top surface of the metal layer. The insulating layer is disposed in a plurality of grooves and contacts the side surface of the semiconductor layer and the top surface of the semiconductor layer. One of the benefits of implementing a resistor structure in a back-end process region of a semiconductor device is that the back-end process region can be used to manufacture passive devices (e.g., resistor structures), thereby increasing the available area on the substrate for implementing additional active devices and / or passive devices to enhance the functionality and performance of the semiconductor device.

[0019] Figure 1 A cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure is shown. The semiconductor device 100 may be a central processing unit, a graphics processing unit, an application-specific integrated circuit, or any other suitable electronic device. In some embodiments of the present disclosure, the semiconductor device 100 may include a substrate 110, a device region 120, and a back-end process region 130.

[0020] The substrate 110 may include a semiconductor material, such as crystalline silicon (Si). In some embodiments of the present disclosure, the substrate 110 may include (i) an elemental semiconductor, such as germanium (Ge); (ii) a compound semiconductor, such as silicon carbide (SiC), silicon arsenide (SiAs), gallium arsenide (GaAs), gallium phosphide (GaP) and / or III-V semiconductor materials; (iii) an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium tin (GeSn) and / or aluminum gallium arsenide (AlGaAs); (iv) a silicon-on-insulator (SOI) structure; (v) a silicon-germanium (SiGe) on-insulator structure (SiGeOI); (vi) a germanium-on-insulator (GeOI) structure; or (vii) a combination of the foregoing. Alternatively, the substrate 110 may be made of a non-conductive material, such as glass and sapphire wafers. In addition, the substrate 110 may be doped, depending on the design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments of the present disclosure, the substrate 110 may be doped with a p-type dopant (eg, boron, indium, aluminum, or gallium) or an n-type dopant (eg, phosphorus or arsenic).

[0021] The device region 120 may be disposed on the substrate 110. In some embodiments of the present disclosure, the device region 120 may include electrical components, such as active devices, passive devices, or a combination of the foregoing. Examples of active devices may include planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nanoribbon transistors). The device region 120 may include one or more of these different types of active devices, which may be separated from each other using shallow trench isolation, deep trench isolation, local oxidation of silicon, any other suitable isolation technology, or a combination of the foregoing. Examples of passive devices may include resistors, capacitors, and inductors. The device region 120 may also include one or more of these different types of passive devices. In some embodiments of the present disclosure, the combination of active devices and passive devices in the device region 120 may form one or more electronic circuits, such as a central processing unit, a graphics processing unit, an application-specific integrated circuit, any other suitable electronic circuit, and parts thereof.

[0022] refer to Figure 1 According to some embodiments of the present disclosure, the back-end process region 130 is disposed above the device region 120 (e.g., in the y direction), and may include a first interconnect region 131, a second interconnect region 132, and a third interconnect region 136. The first interconnect region 131 may include one or more interconnect structures (e.g., a metal line structure and a metal through hole structure), which are disposed in an interlayer dielectric structure ( Figure 1 ). The metal line structure and the metal via structure may include copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or any other suitable conductive material. The interlayer dielectric structure may include a dielectric material, such as silicon oxide (SiOx), silicon hydroxide (SiOH), silicon oxynitride (SiON), silicon nitride (SiNx), silicon oxycarbide (SiOC), silicon oxynitride carbide (SiOCN), and a combination of the foregoing. The interlayer dielectric structure may include a stack of dielectric layers to achieve a multilayer interconnect structure. One or more interconnect structures in the first interconnect region 131 may be electrically connected to an electrical component (e.g., an active device, a passive device, or a combination of the foregoing) in the device region 120.

[0023] refer to Figure 1According to some embodiments of the present disclosure, the second interconnect region 132 is above the first interconnect region 131 (e.g., in the y direction) and may include a passive device region 133 and a metal via structure 134, both of which are disposed in the interlayer dielectric structure 135. The metal via structure 134 may electrically connect the interconnect structure in the first interconnect region 131 to the interconnect structure in the third interconnect region 136. Figure 1 13. Although not shown in the figure, the second interconnect region 132 may also include metal line structures and other metal via structures. The metal line structures and metal via structures (including metal via structures 134) may include Cu, Al, TiN, TaN, W or any other suitable conductive material. The interlayer dielectric structure 135 may include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN, and a combination of the foregoing. The interlayer dielectric structure 135 may include a stack of dielectric layers to achieve a multilayer interconnect structure.

[0024] In some embodiments of the present disclosure, the passive device region 133 may include one or more resistor structures. According to some embodiments of the present disclosure, each of the one or more resistor structures may be a deep trench resistor. One of the benefits of implementing a resistor structure in the passive device region 133 is that the back-end process region 130 can be used to manufacture passive devices (e.g., resistor structures), thereby increasing the available area in the device region 120 for implementing additional active devices and / or passive devices to enhance the functionality and performance of the semiconductor device 100. Although the following description is in the context of a resistor structure (e.g., a deep trench resistor), other types of passive devices (e.g., capacitor structures and inductor structures) may be implemented in the passive device region 133.

[0025] refer to Figure 1 The third interconnect region 136 is above the second interconnect region 132 (e.g., in the y direction) and may include one or more interconnect structures disposed in the interlayer dielectric structure 138. These interconnect structures may include metal line structures 137 and metal via structures ( Figure 1 The metal line structure and the metal via structure may include Cu, Al, TiN, TaN, W or any other suitable conductive material. The interconnection structure in the third interconnection region 136 may be formed by the metal via structure 134 (and Figure 1The third interconnect region 136 may include a plurality of metal wire structures 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 154, 156, 157, 158, 160, 161, 162, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 200, 201, 202, 203, 204, 205, 210, 211, 212, 213, 214, 221, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 250, 256, 267, 278, 280, 281, 282, 283, 284, 290, 291, 292, 293, 294, 295, 296, 297, 298,

[0026] Figure 2 2 shows a cross-sectional view of a portion of a semiconductor device according to some embodiments of the present disclosure. The portion 200 includes a substrate 110, a device region 120, and a first interconnect region 131. Figure 2 Not shown, but Figure 1 As shown, the second interconnect region 132 and the third interconnect region 136 are disposed above the first interconnect region 131 .

[0027] The device region 120 may include active devices 210 implemented within and / or on the substrate 110. According to some embodiments of the present disclosure, the active devices 210 may include one or more of the following: MOSFETs, finFETs, GAAFETs, and nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nanoribbon transistors). The active devices 210 may be separated from each other using shallow trench isolation, deep trench isolation, local oxidation of silicon, other suitable isolation techniques, or a combination of the foregoing. In some embodiments of the present disclosure, the active devices 210 may represent portions of a central processing unit, a graphics processing unit, an application specific integrated circuit, or any other suitable electronic device. In addition, although in Figure 2 Not shown, but device region 120 may also include passive devices (eg, resistors, capacitors, and inductors) implemented within and / or on substrate 110 .

[0028] In some embodiments of the present disclosure, the first interconnect region 131 may include an interconnect structure disposed in the interlayer dielectric structure 221, such as a metal line structure 220 and a metal via structure 134. The metal line structure 220 and the metal via structure 134 may be electrically connected to active devices and / or passive devices (e.g., active device 210) in the device region 120, so that these electrical components may be electrically connected to each other and / or electrically connected to the above interconnect structures (e.g., in Figure 2 The interconnection structure in the second interconnection region 132 and the third interconnection region 136 is not shown in FIG. Figure 2Although not shown in the figure, the first interconnection region 131 may also include other metal via structures. The metal line structure and the metal via structure (including the metal via structure 134) may include Cu, Al, TiN, TaN, W or any other suitable conductive material. The interlayer dielectric structure 221 may include a dielectric material, such as SiO x 、SiOH、SiON、SiN x , SiOC, SiOCN, and combinations of the foregoing. The interlayer dielectric structure 221 may include a stack of dielectric layers to implement a multi-layer interconnect structure.

[0029] Figure 3 Another cross-sectional view of a portion 300 of a semiconductor device 100 is shown in accordance with some embodiments of the present disclosure. Figure 3 , but according to some embodiments of the present disclosure, the second interconnection region 132 and the third interconnection region 136 are arranged above the first interconnection region 131, such as Figure 1 shown.

[0030] Portion 300 includes substrate 110, device region 120, and first interconnect region 131. According to some embodiments of the present disclosure, device region 120 may include backside interconnect region 310 and device region 320. In some embodiments of the present disclosure, backside interconnect region 310 is below device region 120 (e.g., in the y direction). Backside interconnect region 310 may include interconnect structures (e.g., as part of a redistribution layer network of interconnect wiring) disposed in interlayer dielectric structure 317 and arranged to provide power supply voltages to electronic components in device region 320. Interlayer dielectric structure 317 may include a dielectric material, such as SiO x 、SiOH、SiON、SiN x , SiOC, SiOCN, and combinations of the foregoing. The interlayer dielectric structure 317 may include a stack of dielectric layers to implement a multilayer interconnect structure. In addition, the interconnect structure may include metal line structures 311, 313, 315, and 316 and metal via structures 312 and 314, which are electrically connected to each other and to a power supply to provide a power supply voltage to the device region 320. The metal line structures 311, 313, 315, and 316 and the metal via structures 312 and 314 may include Cu, Al, TiN, TaN, W, or any other suitable conductive material.

[0031] According to some embodiments of the present disclosure, the device region 120 may include an active device 322 disposed above the substrate 110 (eg, in the y direction). Figure 3As shown, the active device 322 may be a GAAFET electrically connected to the backside interconnection region 310 and the first interconnection region 131 through the metal contact structure 321 and the metal contact structure 323, respectively. In some embodiments of the present disclosure, the active device 322 may receive a power supply voltage from the interconnection structure in the backside interconnection region 310 through the metal contact structure 321. In addition, in some embodiments of the present disclosure, the active device 322 may receive a gate control voltage from the interconnection structure in the first interconnection region 131 through the metal contact structure 323. The metal contact structures 321 and 323 may include Cu, Al, TiN, TaN, W, or any other suitable conductive material.

[0032] In some embodiments of the present disclosure, the power supply voltage provided to the device region 120 through the backside interconnect structure 310 is different from the power supply voltage provided to other parts of the semiconductor device 100. For example, the power supply voltage provided to the active devices 322 in the device region 120 may require a higher power supply voltage than the power supply voltage provided to other parts of the device region 120. Figure 1 and Figure 3 , a power supply voltage to the device region 120 can be provided by the backside interconnect region 310, and a power supply voltage to other parts of the device region 120 can be provided by a power supply electrically connected to the second interconnect region 132, which includes an interconnect structure electrically connected to the passive device region 133.

[0033] refer to Figure 3 According to some embodiments of the present disclosure, the active devices 322 may be other types of devices, such as MOSFETs, finFETs, nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nanoribbon transistors), and combinations of the foregoing. The active devices 322 are separated from each other using shallow trench isolation, deep trench isolation, local oxidation of silicon, other suitable isolation techniques, and combinations of the foregoing. In addition, although in Figure 3 Not shown, but the device region 120 may also include passive devices (eg, resistors, capacitors, and inductors).

[0034] In some embodiments of the present disclosure, the first interconnect region 131 may include an interconnect structure disposed in the interlayer dielectric structure 334, for example, metal line structures 331 and 332 and metal via structures 134 and 333. The metal line structures 331 and 332 and the metal via structures 134 and 333 may be electrically connected to active devices and / or passive devices (for example, active device 322) in the device region 120, so that these electrical components may be electrically connected to each other and / or electrically connected to an upper interconnect structure (for example, Figure 3The metal line structure and the metal via structure may include Cu, Al, TiN, TaN, W or any other suitable conductive material. The interlayer dielectric structure 334 may include a dielectric material such as SiO x 、SiOH、SiON、SiN x , SiOC, SiOCN, and combinations of the foregoing. The interlayer dielectric structure 334 may include a stack of dielectric layers to implement a multi-layer interconnect structure.

[0035] Figure 4 is formed according to some embodiments of the present disclosure ( Figure 1 ) is an illustration of a cross-sectional view of a resistor structure 400 in a passive device region 133. Figure 4 The cross-sectional view of FIG. 1 shows a second interconnection region 132 disposed on the first interconnection region 131. Although not shown in FIG. Figure 4 As shown in FIG. 1 , the device region 120 and the substrate 110 are disposed below the first interconnect region 131 (eg, in the y direction), as shown in FIG. Figure 1 shown. Figure 4 With Figures 1 to 3 The elements in the same annotations as the elements in the description above.

[0036] refer to Figure 4 The first interconnection region 131 includes an etch stop layer 432 and a metal line structure 434 disposed in an interlayer dielectric structure 436. The etch stop layer 432 may include a dielectric material, such as aluminum oxide (Al x O y ), nitrogen-doped silicon carbide (SiCN), oxygen-doped silicon carbide (SiCO), and silicon nitride (SiN). Figure 4 , but in addition to the metal line structure 434, the first interconnect region 131 may include other metal line structures and metal via structures, which may include Cu, Al, TiN, TaN, W, or any other suitable conductive material. According to some embodiments of the present disclosure, the metal line structure 434 is electrically connected to one or more interconnect structures in the second interconnect region 132, and is electrically connected to ( Figure 1 One or more active devices (e.g., planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors) and / or passive devices (e.g., resistors, capacitors, and inductors) in a device region 120.

[0037] refer to Figure 4According to some embodiments of the present disclosure, the second interconnect region 132 includes metal line structures 446, 447, and 448, a metal via structure 449, and a resistor structure 400 (in the passive device region 133) disposed in the interlayer dielectric structure 135. According to some embodiments of the present disclosure, the interlayer dielectric structure 135 is disposed in ( Figure 1 Over electrical components in device region 120, such as active devices (e.g., planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors), passive devices (e.g., resistors, capacitors, and inductors), or combinations of the foregoing.

[0038] The metal line structure 448 and the metal via structure 449 connect other interconnect structures in the second interconnect region 132 (and those not in the Figure 4 132) are electrically connected to the metal line structure 434 and other interconnect structures (not shown) in the first interconnect region 131. Figure 4 According to some embodiments of the present disclosure, metal line structures 446 and 447 are electrically connected to the resistor structure 400 and are provided in the first interconnection region 131 (in Figure 4 The interconnect structure in (not shown) electrically connects the resistor structure 400 to ( Figure 1 One or more active devices (e.g., planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors) and / or passive devices (e.g., resistors, capacitors, and inductors) in the device region 120. Figure 4 , but in addition to metal line structures 446, 447 and 448 and metal via structure 449, second interconnect region 132 may include other metal line structures and metal via structures, which may include Cu, Al, TiN, TaN, W or any other suitable conductive material.

[0039] In some embodiments of the present disclosure, the resistor structure 400 in the passive device region 133 is a deep trench resistor disposed in the interlayer dielectric structure 135. The resistor structure 400 includes a trench 410, a metal layer 441, a semiconductor layer 442, an insulating layer 443, a first contact structure 444, and a second contact structure 445. The trenches 410 are disposed in the interlayer dielectric structure 135 and separated from each other by dielectric regions 415 of the interlayer dielectric structure 135. For example, the resistor structure 400 includes three trenches 410 separated from each other by two dielectric regions 415. Although in Figure 4 Three trenches 410 are shown in FIG. 4 , but based on the description herein, more or less than three trenches 410 may be implemented, depending on the desired resistance value of the resistor structure 400 .

[0040] According to some embodiments of the present disclosure, the metal layer 441 is disposed on the bottom surface and the side surface of each trench 410 and on the top surface of the dielectric region 415. According to some embodiments of the present disclosure, the metal layer 441 may include gold, platinum, chromium, titanium, tantalum, copper, silver, cobalt, nickel, iron, lead, aluminum, ruthenium, iridium, molybdenum, tungsten, or any other suitable material. In some embodiments of the present disclosure, the metal layer 441 may include ruthenium oxide, iridium oxide, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum aluminum nitride, or any other suitable material.

[0041] According to some embodiments of the present disclosure, the semiconductor layer 442 is disposed on the bottom surface, the side surface, and the top surface of the metal layer 441. The semiconductor layer 442 may include silicon, germanium, silicon germanium, gallium nitride, indium nitride, indium gallium nitride, gallium arsenide, indium arsenide, indium gallium arsenide, indium gallium zinc oxide, copper oxide, indium zinc oxide, gallium zinc oxide, or any other suitable material. In some embodiments of the present disclosure, the semiconductor layer 442 may include silicon germanium doped with boron or phosphorus or other doping materials.

[0042] In some embodiments of the present disclosure, the metal layer 441 may be a substantially conformal layer disposed on the bottom surface and the side surface of each trench 410. The semiconductor layer 442 may be a substantially conformal layer different from the substantially conformal metal layer 441, disposed on the bottom surface, the side surface, and the top surface of the metal layer 441. According to some embodiments of the present disclosure, the ratio of the thickness of the semiconductor layer 442 to the thickness of the metal layer 441 may be between about 0.1 and about 0.5. According to some embodiments of the present disclosure, when the ratio is maintained between about 0.1 and about 0.5, the temperature coefficient of resistance of the resistor structure 400 approaches zero. The temperature coefficient of resistance is a relative change in resistance calculated for each degree of change in temperature, wherein a temperature coefficient of resistance of approximately zero indicates a small change in resistance (if any) within the temperature range. Although the resistor structure 400 has a single-layer semiconductor layer 442 disposed on a single-layer metal layer 441 to form a single metal / semiconductor double layer, the resistor structure 400 may have a plurality of metal / semiconductor double layers to adjust the temperature coefficient of resistance to a desired value (e.g., a value close to zero).

[0043] According to some embodiments of the present disclosure, the insulating layer 443 is disposed in the trench 410 and contacts the side surface of the semiconductor layer 442 and the top surface of the semiconductor layer 442. In some embodiments of the present disclosure, the insulating layer 443 may include a dielectric material, such as Al x O y , SiCN, SiCO, and SiN.

[0044] The first contact structure 444 contacts a portion of the semiconductor layer 442, which is disposed on a first portion of the interlayer dielectric layer structure 135 opposite to the dielectric region 415 separating adjacent trenches. Similarly, the second contact structure 445 contacts another portion of the semiconductor layer 442, which is disposed on a second portion of the interlayer dielectric structure 135, which is different from another dielectric region 415 separating adjacent trenches. In some embodiments of the present disclosure, the first contact structure 444 and the second contact structure 445 contact the terminals of the resistor structure 400, for example, the current flowing through the resistor structure 400 can flow from the first contact structure 444 to the second contact structure 445, or vice versa.

[0045] Similarly, refer to Figure 1 and Figure 4 A benefit of implementing the resistor structure 400 in the passive device region 133 is that the back-end process region 130 can be used to manufacture passive devices (e.g., the resistor structure 400), thereby increasing the available area in the device region 120 for implementing additional active devices and / or passive devices to enhance the functionality and performance of the semiconductor device 100.

[0046] Figure 5 A method 500 of forming a resistor structure 400 in a back-end-of-line process region 130 of a semiconductor device 100 according to some embodiments of the present disclosure is shown. For illustrative purposes, reference will be made to FIG. 6A to FIG. 14A as well as FIG. 6B to FIG. 14B Describe the operation of method 500. According to some embodiments of the present disclosure, FIG. 6A to FIG. 14A is a top-level diagram of the resistor structure 400 at various stages of fabrication, and FIG. 6B to FIG. 14B is a cross-sectional view of the resistor structure 400 at various stages of manufacture. The operations of method 500 may be performed in a different order or not performed, depending on the specific application. It should be noted that method 500 may not produce a complete semiconductor device. Therefore, it should be understood that additional operations may be provided before, during, and after method 500, and only some other processes are briefly described herein. FIG. 6A to FIG. 14A and 6B to Fig. 14B With Figures 1 to 4 The elements in the same annotations as the elements in the description above.

[0047] refer to Figure 5 At operation 510, an interlayer dielectric structure is formed over an electrical component on a substrate. Fig. 6A and Figure 6B , an interlayer dielectric structure 135 is formed above the electrical components on the substrate. For example, referring to Figure 1 and Figure 4, the etch stop layer 432 is part of the first interconnect region 131, and the first interconnect region 131 is disposed above the device region 120. The device region 120 may include electrical components, such as active devices (e.g., planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors), passive devices (e.g., resistors, capacitors, and inductors), or a combination of the foregoing. In some embodiments of the present disclosure, the combination of active devices and passive devices may form one or more electronic circuits, such as a central processing unit, a graphics processing unit, an application-specific integrated circuit, any other suitable electronic circuit, and parts thereof. The device region 120 is disposed on the substrate 110. In addition, according to some embodiments of the present disclosure, when forming Fig. 6A and Figure 6B Before forming the interlayer dielectric structure 135 in the device region 120 , active devices and / or passive devices in the device region 120 and an interconnection structure in the first interconnection region 131 are formed.

[0048] refer to Figure 5 At operation 520, trenches are formed in the interlayer dielectric structure, wherein the trenches are separated from each other by dielectric regions on the interlayer dielectric structure. Fig. 7A and Figure 7B , a trench 410 is formed in the interlayer dielectric structure 135, for example, by a photo pattern and etching process. In some embodiments of the present disclosure, the height H of each trench 410 is 410 (eg, in the y direction) may be substantially equal to or less than the height of the interlayer dielectric structure 135. For example, the height H 410 The width W of each trench may be between about 0.25 μm and about 3 μm, wherein the height of the interlayer dielectric structure may be about 3 μm. 410 (e.g., in the x-direction) can be between about 50 nm and about 250 nm. Fig. 7A and Figure 7B Three trenches 410 are shown in FIG. 4 , but based on the description herein, more or less than three trenches 410 may be implemented, depending on the desired resistance value of the resistor structure 400 .

[0049] refer to Figure 5 At operation 530, a metal layer is formed on the bottom surface and side surfaces of each trench and on the top surface of the dielectric region. Fig. 8A and Figure 8B, a metal layer 441 is formed on the bottom surface and side surface of each groove 410, for example, by a chemical vapor deposition process, an atomic layer deposition process, or any other suitable deposition process. In some embodiments of the present disclosure, the metal layer 441 may be a substantially conformal layer having a thickness between about 5 nm and about 50 nm. According to some embodiments of the present disclosure, the metal layer 441 may include gold, platinum, chromium, titanium, tantalum, copper, silver, cobalt, nickel, iron, lead, aluminum, ruthenium, iridium, molybdenum, tungsten, or any other suitable material. In some embodiments of the present disclosure, the metal layer 441 may include ruthenium oxide, iridium oxide, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum aluminum nitride, or any other suitable material.

[0050] refer to Figure 5 At operation 540, a semiconductor layer is formed on the bottom surface, the side surface, and the top surface of the metal layer. Fig. 8A and Figure 8B , a semiconductor layer 442 is formed on the bottom surface, side surface and top surface of the metal layer 441, for example, by a chemical vapor deposition process, an atomic layer deposition process or any other suitable deposition process. In some embodiments of the present disclosure, the semiconductor layer 442 may be a substantially conformal layer having a thickness between about 2 nm and about 10 nm. The semiconductor layer 442 may include silicon, germanium, silicon germanium, gallium nitride, indium nitride, indium gallium nitride, gallium arsenide, indium arsenide, indium gallium arsenide, indium gallium zinc oxide, copper oxide, indium zinc oxide, gallium zinc oxide or any other suitable material. In some embodiments of the present disclosure, the semiconductor layer 442 may include silicon germanium doped with boron or phosphorus or other doping materials.

[0051] According to some embodiments of the present disclosure, both the semiconductor layer 442 and the metal layer 441 may be substantially conformal layers having different thicknesses, wherein the ratio of the thickness of the semiconductor layer 442 to the thickness of the metal layer 441 may be between about 0.1 and about 0.5. According to some embodiments of the present disclosure, when the ratio is maintained between about 0.1 and about 0.5, the temperature coefficient of resistance of the resistor structure 400 approaches zero. Although the resistor structure 400 has a single-layer semiconductor layer 442 disposed on a single-layer metal layer 441 to form a single metal / semiconductor bilayer, the resistor structure 400 may have multiple metal / semiconductor bilayers (formed by multiple iterations of operations 530 and 540) to adjust the temperature coefficient of resistance to a desired value (e.g., a value close to zero).

[0052] refer to Figure 5 At operation 550, an insulating layer is formed in the trench, and the insulating layer contacts the side surface of the semiconductor layer and the top surface of the semiconductor layer. Fig. 9A and Fig. 9B, an insulating layer 443 is formed in the trench 410, and the insulating layer 443 contacts the side surface of the semiconductor layer 442 and the top surface of the semiconductor layer 442, for example, by a chemical vapor deposition process, an atomic layer deposition process, or any other suitable deposition process. In some embodiments of the present disclosure, the insulating layer 443 may include a dielectric material, such as Al x O y , SiCN, SiCO, and SiN.

[0053] According to some embodiments of the present disclosure, the insulating layer 443 may be photo-patterned and etched. Fig. 10A and Fig. 10B , the insulating layer 443 may be subjected to a photo-patterning and etching process 1010 to expose the interlayer dielectric structure 135 along the periphery of the insulating layer 443. In some embodiments of the present disclosure, the insulating layer 443 may be further subjected to photo-patterning and etching to form trench end cuts (e.g., to prevent electrical shorts within the resistor structure 400). Fig.11A and Fig. 11B , another photo-patterning and etching process may be performed on the insulating layer 443 to remove additional portions of the insulating layer 443 (eg, in the z-direction).

[0054] refer to Figure 5 At operation 560, an interconnect structure is formed in the interlayer dielectric structure. Fig. 12A and Fig. 12B , the formation of the interconnect structure may include: Fig.11A and Fig. 11B Deposition of dielectric materials (e.g., SiN x , SiOC and SiOCN), and a polishing operation (eg, a chemical mechanical polishing operation) is performed. The dielectric material may be the same material as the interlayer dielectric structure 135. Fig.13A and Fig. 13B The formation of the interconnect structure may further include: performing a photo patterning and etching process 1310 to form a contact opening 1320. The contact opening 1320 is formed through the interlayer dielectric structure 135 and the insulating layer 443 so that a portion of the semiconductor layer 442 is exposed. Fig.14A and Fig. 14B , a conductive material (eg, Cu, Al, TiN, TaN, and W) is deposited into the contact opening 1320 and polished (eg, chemical mechanical polishing) to form a first contact structure 444 and a second contact structure 445 .

[0055] The first contact structure 444 contacts a portion of the semiconductor layer 442 that is disposed over a portion of the interlayer dielectric structure 135 at one end of the resistor structure 400. The second contact structure 445 contacts another portion of the semiconductor layer 442 that is disposed over another portion of the interlayer dielectric structure at an opposite end of the resistor structure 400. The first contact structure 444 and the second contact structure 445 may be electrically connected to other interconnect structures, such as Figure 4 The metal line structures 446 and 447 in FIG. Fig.14A and Fig. 14B Four contact structures are shown in FIG. 4 , but the resistor structure 400 may have more or less than four contact structures, depending on the design of the resistor structure 400 .

[0056] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the size of circuit elements, such as active devices (e.g., MOSFETs, finFETs, and GAAFETs) and passive devices (e.g., capacitors, inductors, and resistors). As the number of circuit elements increases, the implementation of these circuit elements becomes increasingly complex.

[0057] The present disclosure describes semiconductor structures and methods for manufacturing semiconductor devices in a back-end processing area (e.g., Figure 1 A resistor structure (eg, Figure 4 A method of manufacturing a resistor structure 400). The resistor structure may include a dielectric layer, a groove, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above an electrical component formed on a substrate. The grooves are disposed in the dielectric layer and separated from each other by dielectric regions of the dielectric layer. The metal layer is disposed on the bottom surface and side surface of each groove and on the top surface of the dielectric region. The semiconductor layer is disposed on the bottom surface, side surface, and top surface of the metal layer. The insulating layer is disposed in a plurality of grooves and in contact with the side surface of the semiconductor layer and the top surface of the semiconductor layer. One of the benefits of implementing a resistor structure in a back-end process region of a semiconductor device is that the back-end process region can be used to manufacture passive devices (e.g., a resistor structure), thereby increasing the available area on the substrate for implementing additional active devices and / or passive devices to enhance the functionality and performance of the semiconductor device.

[0058] Embodiments of the present disclosure include a resistor structure having a dielectric layer, a groove, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above an electrical component formed on a substrate. The grooves are disposed in the dielectric layer and separated from each other by dielectric regions of the dielectric layer. The metal layer is disposed on the bottom surface and side surface of each groove and on the top surface of the dielectric region. The semiconductor layer is disposed on the bottom surface, side surface, and top surface of the metal layer. The insulating layer is disposed in the groove and contacts the side surface of the semiconductor layer and the top surface of the semiconductor layer.

[0059] Embodiments of the present disclosure include a semiconductor structure having a substrate and a metal region. The substrate includes an electrical component formed thereon. The metal region is disposed above the electrical component and includes: a dielectric layer, an interconnect structure disposed in the dielectric layer, and a resistor structure disposed in the dielectric layer and in contact with the interconnect structure. The resistor structure includes a groove, a metal layer, a semiconductor layer, and an insulating layer. The grooves are separated from each other by the dielectric region of the dielectric layer. The metal layer is disposed on the bottom surface and side surface of each groove and on the top surface of the dielectric region. The semiconductor layer is disposed on the bottom surface, side surface, and top surface of the metal layer. The insulating layer is disposed in the groove and in contact with the side surface of the semiconductor layer and the top surface of the semiconductor layer.

[0060] Embodiments of the present disclosure include a method for forming a resistor structure in a back-end process region of a semiconductor device. The method includes: forming a dielectric layer above an electrical component disposed on a substrate; forming trenches in the dielectric layer, the trenches being separated from each other by a dielectric region of the dielectric layer; forming a metal layer on a bottom surface and a side surface of each trench and on a top surface of the dielectric region; forming a semiconductor layer on a bottom surface, a side surface, and a top surface of the metal layer; and forming an insulating layer in the trench, the insulating layer being in contact with a side surface of the semiconductor layer and a top surface of the semiconductor layer.

[0061] It should be understood that the detailed description section (rather than the abstract section of the present disclosure) is intended to be used to interpret the claims. The abstract section of the present disclosure may set forth one or more embodiments, rather than all possible embodiments of the present disclosure contemplated by the inventor(s), and is therefore not intended to limit the appended claims in any way.

[0062] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or realizing the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0063] Example 1 is a resistor structure, comprising: a dielectric layer, disposed above a plurality of electrical components formed on a substrate; a plurality of grooves, disposed in the dielectric layer and separated from each other by dielectric regions of the dielectric layer; a metal layer, disposed on the bottom surface and side surfaces of each of the plurality of grooves and on the top surface of the dielectric region; a semiconductor layer, disposed on the bottom surface, side surface and top surface of the metal layer; and an insulating layer, disposed in the plurality of grooves and in contact with the side surface of the semiconductor layer and the top surface of the semiconductor layer.

[0064] Example 2 is the resistor structure described in Example 1, further including: a first contact structure, contacting a portion of the semiconductor layer, which portion is arranged on a first portion of the dielectric layer opposite to the dielectric region; and a second contact structure, contacting another portion of the semiconductor layer, which other portion is arranged on a second portion of the dielectric layer opposite to another dielectric region separating adjacent grooves among the multiple grooves.

[0065] Example 3 is the resistor structure of Example 1, wherein a width of each of the plurality of trenches is between about 50 nm and about 250 nm.

[0066] Example 4 is the resistor structure of Example 1, wherein a height of each of the plurality of trenches is between about 250 nm and about 3000 nm.

[0067] Example 5 is the resistor structure of Example 1, wherein the metal layer includes gold, platinum, chromium, titanium, tantalum, copper, silver, cobalt, nickel, iron, lead, aluminum, ruthenium, iridium, molybdenum or tungsten.

[0068] Example 6 is the resistor structure described in Example 1, wherein the metal layer includes ruthenium oxide, iridium oxide, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride or tantalum aluminum nitride.

[0069] Example 7 is the resistor structure described in Example 1, wherein the semiconductor layer includes silicon, germanium, silicon germanium, gallium nitride, indium nitride, indium gallium nitride, gallium arsenide, indium arsenide, indium gallium arsenide, indium gallium zinc oxide, copper oxide, indium zinc oxide, or gallium zinc oxide.

[0070] Example 8 is the resistor structure of Example 1, wherein the semiconductor layer includes silicon germanium doped with boron or phosphorus.

[0071] Example 9 is the resistor structure of Example 1, wherein a ratio of a thickness of the semiconductor layer to a thickness of the metal layer is between about 0.1 and about 0.5.

[0072] Example 10 is a semiconductor structure comprising: a substrate having a plurality of electrical components formed on the substrate; and a metal region disposed above the plurality of electrical components, wherein the metal region comprises: a dielectric layer; a plurality of interconnect structures disposed in the dielectric layer; and a resistor structure disposed in the dielectric layer and in contact with the plurality of interconnect structures, wherein the resistor structure comprises: a plurality of grooves separated from each other by the dielectric region of the dielectric layer; a metal layer disposed on the bottom surface and side surfaces of each of the plurality of grooves and on the top surface of the dielectric region; a semiconductor layer disposed on the bottom surface, side surface and top surface of the metal layer; and an insulating layer disposed in the plurality of grooves and in contact with the side surface of the semiconductor layer and the top surface of the semiconductor layer.

[0073] Example 11 is the semiconductor structure of Example 10, wherein at least one electrical component of the plurality of electrical components is electrically connected to the resistor structure.

[0074] Example 12 is a semiconductor structure described in Example 10, wherein the multiple interconnect structures include: a first contact structure, which contacts a portion of the semiconductor layer, which is arranged on a first portion of the dielectric layer opposite to the dielectric region; and a second contact structure, which contacts another portion of the semiconductor layer, which is arranged on a second portion of the dielectric layer opposite to another dielectric region separating adjacent grooves among the multiple grooves.

[0075] Example 13 is the semiconductor structure of Example 10, wherein a width of each of the plurality of trenches is between approximately 50 nm and approximately 250 nm.

[0076] Example 14 is the semiconductor structure of Example 10, wherein a height of each of the plurality of trenches is between approximately 250 nm and approximately 3000 nm.

[0077] Example 15 is the semiconductor structure of Example 10, wherein a ratio of a thickness of the semiconductor layer to a thickness of the metal layer is between about 0.1 and about 0.5.

[0078] Example 16 is a method for forming a semiconductor structure, comprising: forming a dielectric layer over a plurality of electrical components disposed on a substrate; forming a plurality of grooves in the dielectric layer, the plurality of grooves being separated from each other by a dielectric region of the dielectric layer; depositing a metal layer on a bottom surface and side surfaces of each of the plurality of grooves and on a top surface of the dielectric region; depositing a semiconductor layer on a bottom surface, side surface, and top surface of the metal layer; and depositing an insulating layer in the plurality of grooves, the insulating layer being in contact with the side surfaces of the semiconductor layer and the top surface of the semiconductor layer.

[0079] Example 17 is the method of Example 16, further comprising: forming a plurality of interconnect structures in the dielectric layer.

[0080] Example 18 is the method described in Example 17, wherein forming the multiple interconnect structures includes: forming a first contact structure, the first contact structure contacts a portion of the semiconductor layer, the portion being disposed on a first portion of the dielectric layer opposite to the dielectric region; and forming a second contact structure, the second contact structure contacts another portion of the semiconductor layer, the other portion being disposed on a second portion of the dielectric layer opposite to the dielectric region.

[0081] Example 19 is the method described in Example 16, wherein forming the plurality of grooves includes: forming each of the plurality of grooves, the width of each groove being between about 50 nm and about 250 nm; and forming each of the plurality of grooves, the height of each groove being between about 250 nm and about 3000 nm.

[0082] Example 20 is the method described in Example 16, wherein depositing the metal layer and depositing the semiconductor layer include: forming the metal layer having a first thickness; and forming the semiconductor layer having a second thickness different from the first thickness, wherein a ratio of the second thickness to the first thickness is between about 0.1 and about 0.5.

Claims

1. A resistor structure comprising: a dielectric layer disposed over a plurality of electrical components formed on the substrate; a plurality of trenches disposed in the dielectric layer and separated from each other by dielectric regions of the dielectric layer; a metal layer disposed on a bottom surface and a side surface of each of the plurality of trenches and on a top surface of the dielectric region; A semiconductor layer is disposed on the bottom surface, the side surface and the top surface of the metal layer; as well as An insulating layer is disposed in the plurality of trenches and contacts the side surface of the semiconductor layer and the top surface of the semiconductor layer.

2. The resistor structure according to claim 1, further comprising: a first contact structure in contact with a portion of the semiconductor layer, the portion being disposed on a first portion of the dielectric layer opposite the dielectric region; as well as A second contact structure contacts another portion of the semiconductor layer, the other portion being disposed on a second portion of the dielectric layer opposite another dielectric region separating adjacent trenches of the plurality of trenches.

3. The resistor structure according to claim 1, wherein: Each of the plurality of trenches has a width between 50 nm and 250 nm.

4. The resistor structure according to claim 1, wherein: A height of each of the plurality of trenches is between 250 nm and 3000 nm.

5. The resistor structure according to claim 1, wherein: The metal layer includes gold, platinum, chromium, titanium, tantalum, copper, silver, cobalt, nickel, iron, lead, aluminum, ruthenium, iridium, molybdenum or tungsten.

6. The resistor structure according to claim 1, wherein: The metal layer includes ruthenium oxide, iridium oxide, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride or tantalum aluminum nitride.

7. The resistor structure according to claim 1, wherein: The semiconductor layer includes silicon, germanium, silicon germanium, gallium nitride, indium nitride, indium gallium nitride, gallium arsenide, indium arsenide, indium gallium arsenide, indium gallium zinc oxide, copper oxide, indium zinc oxide or gallium zinc oxide.

8. The resistor structure according to claim 1, wherein: The semiconductor layer includes silicon germanium doped with boron or phosphorus.

9. A semiconductor structure comprising: a substrate having a plurality of electrical components formed on said substrate; as well as A metal region is disposed on the plurality of electrical components, wherein the metal region comprises: a dielectric layer; a plurality of interconnect structures disposed in the dielectric layer; and a resistor structure disposed in the dielectric layer and in contact with the plurality of interconnect structures, wherein the resistor structure comprises: a plurality of trenches separated from each other by dielectric regions of the dielectric layer; a metal layer disposed on a bottom surface and a side surface of each of the plurality of trenches and on a top surface of the dielectric region; a semiconductor layer disposed on a bottom surface, a side surface, and a top surface of the metal layer; and An insulating layer is disposed in the plurality of trenches and contacts the side surface of the semiconductor layer and the top surface of the semiconductor layer.

10. A method of forming a semiconductor structure, comprising: forming a dielectric layer over a plurality of electrical components disposed on a substrate; forming a plurality of trenches in the dielectric layer, the plurality of trenches being separated from one another by dielectric regions of the dielectric layer; depositing a metal layer on a bottom surface and side surfaces of each of the plurality of trenches and on a top surface of the dielectric region; depositing a semiconductor layer on a bottom surface, a side surface, and a top surface of the metal layer; as well as An insulating layer is deposited in the plurality of trenches, and the insulating layer contacts a side surface of the semiconductor layer and a top surface of the semiconductor layer.

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