Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a data line, a gate line and a fan-out wire. The data line comprises a data line group arranged along a first direction, each data line group comprising N data lines, in each data line group, the mth data line is electrically connected with the (m+N / 2)th data line; the fan-out wire comprises a fan-out wire group arranged along the first direction, each fan-out wire group comprising N / 2 fan-out wires, and the fan-out wires in the same fan-out wire group are electrically connected with the data lines in the same data line group, and the N / 2 fan-out wires are respectively and electrically connected with the mth data line to the (m-1+N / 2)th data line; each data line in at least one data line group is electrically connected with the corresponding fan-out wire through a first switching part, the number of the first switching parts through which the mth data line is electrically connected with the fan-out wire is the same as the number of the first switching parts through which the (m+N / 2)th data line is electrically connected with the fan-out wire, which can avoid the vertical stripe risk caused by the resistance difference.

Description

Technical Field

[0001] This disclosure relates to an array substrate and a display device. Background Technology

[0002] Display devices employing dual-gate technology reduce costs by halving the number of data lines and doubling the number of gate lines. This halves the number of source driver integrated circuits (ICs) connected to the data lines and doubles the number of gate driver ICs connected to the gate lines. Summary of the Invention

[0003] This disclosure provides an array substrate and a display device.

[0004] This disclosure provides an array substrate, including a display area and a non-display area located on at least one side of the display area. The array substrate includes: a plurality of sub-pixels, a plurality of data lines, a plurality of gate lines located in the display area, and a plurality of fan-out traces located in the non-display area. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, and a gate line pair formed by two gate lines is disposed between two adjacent sub-pixels arranged along the second direction, wherein the first direction and the second direction intersect; the plurality of fan-out traces are configured to be electrically connected to the plurality of data lines. The multiple data lines include multiple data line groups arranged along the first direction, each data line group including N data lines, and in each data line group, the m-th data line is electrically connected to the (m+N / 2)-th data line, where m is a positive integer not greater than N / 2; the multiple fan-out routing lines include multiple fan-out routing line groups arranged along the first direction, each fan-out routing line group including N / 2 fan-out routing lines, and the fan-out routing lines in the same fan-out routing line group are electrically connected to the data lines in the same data line group, and the N / 2 fan-out routing lines are electrically connected to the m-th to (m-1+N / 2)-th data lines respectively; each data line in at least one data line group is electrically connected to the corresponding fan-out routing line through at least one first adapter, and in the at least one data line group, the number of first adapters through which the m-th data line is electrically connected to the fan-out routing line is the same as the number of first adapters through which the (m+N / 2)-th data line is electrically connected to the fan-out routing line.

[0005] For example, according to an embodiment of this disclosure, the first adapter includes at least two first adapter holes, and in the at least one data line group, the number of first adapter holes through which the m-th data line is electrically connected to the fan-out routing line is the same as the number of first adapter holes through which the (m+N / 2)-th data line is electrically connected to the fan-out routing line.

[0006] For example, according to an embodiment of this disclosure, the non-display area includes a first non-display area and a second non-display area located on both sides of the display area in the second direction, respectively. The plurality of fan-out traces and the first adapter are all located in the first non-display area. The array substrate further includes an electrostatic discharge structure, which includes a first electrostatic discharge structure and a second electrostatic discharge structure. The first electrostatic discharge structure is located in the first non-display area, and the second electrostatic discharge structure is located in the second non-display area. The first electrostatic discharge structure is located between the plurality of data lines and the first adapter. The plurality of data lines are electrically connected to the plurality of fan-out traces through the first electrostatic discharge structure and the first adapter. The plurality of data lines are electrically connected to the second electrostatic discharge structure through a plurality of second adapters. The second electrostatic discharge structure is located on the side of the second adapter away from the plurality of data lines. The number of second adapters through which the m-th data line is electrically connected to the second electrostatic discharge structure is the same as the number of second adapters through which the (m+N / 2)-th data line is electrically connected to the second electrostatic discharge structure.

[0007] For example, according to an embodiment of this disclosure, each second adapter includes at least two second adapter holes, and the number of second adapter holes through which the m-th data line is electrically connected to the second electrostatic discharge structure is the same as the number of second adapter holes through which the (m+N / 2)-th data line is electrically connected to the second electrostatic discharge structure.

[0008] For example, according to an embodiment of this disclosure, in the at least one fan-out routing group, two adjacent fan-out routing lines are respectively a first fan-out routing line and a second fan-out routing line, and the first fan-out routing line and the second fan-out routing line are disposed on different layers; a straight line extending along the first direction passes through the first adapter that is electrically connected to each fan-out routing line in the at least one fan-out routing group.

[0009] For example, according to an embodiment of this disclosure, the m-th data line and the (m+N / 2)-th data line are electrically connected through a first connection trace located in the first non-display area. The first connection trace is connected to the first adapter. The first connection trace and the fan-out trace electrically connected thereto are arranged on the same layer.

[0010] For example, according to an embodiment of this disclosure, the m-th data line and the (m+N / 2)-th data line are electrically connected through a second connection trace located in the second non-display area, and the second electrostatic discharge structure is connected to the second adapter through a third connection trace, wherein the third connection trace and the second connection trace are disposed on the same layer.

[0011] For example, according to an embodiment of this disclosure, the first adapter includes at least two conductive layers and a first adapter hole; the at least two conductive layers include three conductive layers, including a first conductive layer, a third conductive layer, and a second conductive layer that is stacked with both the first conductive layer and the third conductive layer, wherein one of the first conductive layer and the third conductive layer is connected to the fan-out routing line and is disposed on the same layer; or, the at least two conductive layers include two conductive layers, including a first conductive layer and a second conductive layer that is stacked with the first conductive layer, wherein the first conductive layer is connected to the fan-out routing line and is disposed on the same layer.

[0012] For example, according to an embodiment of this disclosure, each first adapter electrically connected to each fan-out cable in the at least one fan-out cable group includes two adapter sub-sections arranged along the second direction. The number of first connecting cables is multiple, and at least one first connecting cable passes through the gap between the two adapter sub-sections included in the first adapter that is not connected to it.

[0013] For example, according to an embodiment of this disclosure, each adapter sub-section includes two adapter blocks arranged along the second direction; in each first adapter section, the adapter block closest to the plurality of data lines is disposed on the same layer as the data lines, the adapter block closest to the fan-out routing line is disposed on the same layer as the fan-out routing line connected to the adapter block, and the two adapter blocks located in the middle are connected and disposed on the same layer.

[0014] For example, according to an embodiment of this disclosure, in the at least one fan-out routing group, each fan-out routing line is arranged on the same layer. Each first adapter portion electrically connected to each fan-out routing line in the at least one fan-out routing group includes three conductive layers and a first adapter hole. The three conductive layers include a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer that is stacked with both the first and second sub-conductive layers. The first sub-conductive layer is located between the second sub-conductive layer and the plurality of data lines. The data lines are arranged on the same layer as the first sub-conductive layer. The fan-out routing line is connected to the second conductive layer and is arranged on the same layer.

[0015] For example, according to an embodiment of this disclosure, the m-th data line is electrically connected to the (m+N / 2)-th data line via a first connecting trace. The first connecting trace is connected to the first adapter. The first connecting trace and the fan-out trace electrically connected to it are disposed on the same layer. There are multiple first connecting traces, and the multiple first connecting traces include at least two types of first connecting traces. One type of first connecting trace includes a portion located on the side of the first adapter that is not connected to it that is far away from the multiple data lines, and the other type of first connecting trace includes a portion located on the side of the first adapter that is not connected to it that is close to the multiple data lines.

[0016] For example, according to an embodiment of this disclosure, the second adapter includes three conductive layers and a second adapter hole. The three conductive layers include a fourth sub-conductive layer, a fifth sub-conductive layer, and a sixth sub-conductive layer that is stacked with both the fourth and fifth sub-conductive layers. The fourth sub-conductive layer is located between the fifth sub-conductive layer and the plurality of data lines. The data lines are disposed on the same layer as the fourth sub-conductive layer. The fifth sub-conductive layer is disposed on the same layer as the second connection trace, and both the second connection trace and the third connection trace are connected to the fifth sub-conductive layer.

[0017] For example, according to an embodiment of this disclosure, one of the first fan-out trace and the second fan-out trace is disposed on the same layer as the plurality of data lines, and the other of the first fan-out trace and the second fan-out trace is disposed on the same layer as the plurality of gate lines.

[0018] For example, according to an embodiment of this disclosure, both the second connection trace and the third connection trace are disposed on the same layer as the plurality of gate lines.

[0019] For example, according to an embodiment of this disclosure, the m-th data line and the (m+N / 2)-th data line are electrically connected through a second connection trace located in the second non-display area, and the second electrostatic discharge structure is connected to the second adapter through a third connection trace, wherein the third connection trace and the second connection trace are located on different layers.

[0020] For example, according to an embodiment of this disclosure, the array substrate further includes a detection signal line and a switching component located in the second non-display area. Both the detection signal line and the switching component are located on the side of the second electrostatic discharge structure away from the display area, and the detection signal line is connected to the second electrostatic discharge structure via the switching component.

[0021] For example, according to an embodiment of this disclosure, N is 12, the plurality of gate lines include a first gate line and a second gate line alternately arranged along the second direction, six columns of sub-pixels electrically connected to the first to sixth data lines in the same data line group are electrically connected to the first gate line, and six columns of sub-pixels electrically connected to the seventh to twelfth data lines in the same data line group are electrically connected to the second gate line.

[0022] For example, according to an embodiment of this disclosure, at least one gate line is provided with a plurality of bends, the plurality of bends including a plurality of first bends and a plurality of second bends arranged alternately along the first direction, the orientation of the first bends being opposite to the orientation of the second bends; each sub-pixel includes a transistor, and each bend surrounds a transistor in N sub-pixels electrically connected to a data line group.

[0023] This disclosure provides an array substrate, including a display area and a first non-display area and a second non-display area located on both sides of the display area. The array substrate includes: a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area, the plurality of data lines being arranged along a first direction; a plurality of gate lines located in the display area, the plurality of gate lines being arranged along a second direction, and a gate line pair formed by two gate lines is disposed between two adjacent sub-pixels arranged along the second direction, the first direction intersecting the second direction; and a plurality of fan-out traces located in the first non-display area, the plurality of fan-out traces being configured to be electrically connected to the plurality of data lines. The plurality of data lines include a plurality of data line groups arranged along the first direction, each data line group including N data lines, wherein the m-th data line in each data line group is electrically connected to the (m+N / 2)-th data line, where m is a positive integer not greater than N / 2; the array substrate further includes an electrostatic discharge structure located in the second non-display area, wherein the plurality of data lines are electrically connected to the electrostatic discharge structure through a plurality of adapters, the electrostatic discharge structure being located on the side of the adapters away from the plurality of data lines, and in at least one data line group, the number of adapters through which the m-th data line is electrically connected to the electrostatic discharge structure is the same as the number of adapters through which the (m+N / 2)-th data line is electrically connected to the electrostatic discharge structure.

[0024] For example, according to an embodiment of this disclosure, each adapter includes at least two adapter holes, and in the at least one data line group, the number of adapter holes through which the m-th data line is electrically connected to the electrostatic discharge structure is the same as the number of adapter holes through which the (m+N / 2)-th data line is electrically connected to the electrostatic discharge structure.

[0025] For example, according to an embodiment of this disclosure, the m-th data line and the (m+N / 2)-th data line are electrically connected through a first sub-connection trace located in the second non-display area, and the electrostatic discharge structure is connected to the adapter through a second sub-connection trace. The first sub-connection trace and the second sub-connection trace are arranged on the same layer.

[0026] For example, according to an embodiment of this disclosure, both the first sub-connection trace and the second sub-connection trace are disposed on the same layer as the gate line.

[0027] This disclosure provides a display device including any of the array substrates described above. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0029] Figure 1This is a partial planar structure diagram of an array substrate provided according to an embodiment of the present disclosure.

[0030] Figure 2 for Figure 1 A schematic diagram of the planar structure of some sub-pixels, data lines, and gate lines in the display area of ​​the array substrate shown.

[0031] Figure 3 This is a schematic diagram of a partial planar structure of the non-display area where the fan-out traces of an array substrate are located.

[0032] Figure 4 for Figure 3 A schematic diagram of a partial planar structure of the array substrate shown.

[0033] Figure 5 for Figure 3 and Figure 4 The circuit diagram shown illustrates the electrical connection between the data lines and the fan-out traces in the array substrate.

[0034] Figure 6 for Figure 1 A partial structural diagram of the first non-display area in the array substrate shown.

[0035] Figure 7 for Figure 6 The circuit diagram shown illustrates the electrical connection between the data lines and the fan-out traces in the array substrate.

[0036] Figure 8 and Figure 9 respectively along Figure 6 The partial cross-sectional view shown is taken by lines AA' and BB'.

[0037] Figure 10 This is a schematic diagram showing the positional relationship between the first adapter and the first connecting trace according to another example of an embodiment of this disclosure.

[0038] Figure 11 This is a schematic diagram showing the positional relationship of the first adapter, the first connecting trace, and the fan-out trace according to another example of an embodiment of this disclosure.

[0039] Figure 12 for Figure 1 The second non-display area shown is a partial structural diagram in an example.

[0040] Figure 13 for Figure 12 A partially enlarged view of the array substrate shown.

[0041] Figure 14 for Figure 13 The circuit diagram shown illustrates the electrical connection between the data lines and the second electrostatic discharge structure in the array substrate.

[0042] Figure 15 for Figure 1 A partial structural diagram of the second non-display area in the array substrate shown in another example.

[0043] Figure 16 for Figure 15 The circuit diagram shown illustrates the electrical connection between the data lines and the second electrostatic discharge structure in the array substrate.

[0044] Figure 17 This is a schematic block diagram of a display device provided according to another embodiment of the present disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Features such as “parallel,” “perpendicular,” and “identical” used in embodiments of this disclosure include features in the strict sense of “parallel,” “perpendicular,” and “identical,” as well as cases where “substantially parallel,” “substantially perpendicular,” and “substantially identical” include a certain degree of error, taking into account measurement and errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), indicating a range of acceptable deviations for a particular value as determined by one of ordinary skill in the art. For example, “substantially” can mean within one or more standard deviations, or within 10% or 5% of said value. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component means that the component may be one or more, or can be understood as at least one. “At least one” means one or more, and “more” means at least two. The term "same-layer arrangement" as used in this disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, wherein their materials may be the same or different. The term "integrated arrangement structure" as used in this disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, wherein their materials may be the same or different.

[0047] This disclosure provides an array substrate and a display device. The array substrate includes a display area and a non-display area located on at least one side of the display area. The array substrate includes a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines located in the display area, and a plurality of fan-out traces located in the non-display area. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, and a gate line pair formed by two gate lines is disposed between two adjacent sub-pixels arranged along the second direction, wherein the first direction and the second direction intersect; the plurality of fan-out traces are configured to be electrically connected to the plurality of data lines. The multiple data lines include multiple data line groups arranged along a first direction, each data line group including N data lines, in which the m-th data line is electrically connected to the (m+N / 2)-th data line, where m is a positive integer not greater than N / 2; the multiple fan-out routing lines include multiple fan-out routing line groups arranged along the first direction, each fan-out routing line group including N / 2 fan-out routing lines, and the fan-out routing lines in the same fan-out routing line group are electrically connected to the data lines in the same data line group, and the N / 2 fan-out routing lines are electrically connected one-to-one with the m-th data line to the (m-1+N / 2)-th data line; each data line in at least one data line group is electrically connected to the corresponding fan-out routing line through at least one first adapter, and in at least one data line group, the number of first adapters through which the m-th data line is electrically connected to the fan-out routing line is the same as the number of first adapters through which the (m+N / 2)-th data line is electrically connected to the fan-out routing line.

[0048] By setting the number of first adapters through which different data lines are electrically connected to the fan-out routing to be the same, it is beneficial to reduce the difference in transmission resistance between different data lines, thereby avoiding the risk of vertical lines caused by resistance differences.

[0049] This disclosure provides another array substrate, including a display area and a first non-display area and a second non-display area located on both sides of the display area. The array substrate includes: a plurality of sub-pixels located in the display area, a plurality of gate lines, and a plurality of fan-out traces located in the first non-display area. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, and a gate line pair formed by two gate lines is disposed between two adjacent sub-pixels arranged along the second direction, the first direction and the second direction intersecting; the plurality of fan-out traces are configured to be electrically connected to the plurality of data lines. The multiple data lines include multiple data line groups arranged along a first direction, each data line group including N data lines, in which the m-th data line is electrically connected to the (m+N / 2)-th data line, where m is a positive integer not greater than N / 2; the array substrate also includes an electrostatic discharge structure, which includes a first electrostatic discharge structure and a second electrostatic discharge structure, the first electrostatic discharge structure being located in a first non-display area and between the multiple data lines and the multiple fan-out traces, the second electrostatic discharge structure being located in a second non-display area, the multiple data lines being electrically connected to the second electrostatic discharge structure through multiple adapters, the second electrostatic discharge structure being located on the side of the adapters away from the multiple data lines, in at least one data line group, the number of adapters through which the m-th data line is electrically connected to the second electrostatic discharge structure is the same as the number of adapters through which the (m+N / 2)-th data line is electrically connected to the second electrostatic discharge structure.

[0050] By setting the number of second adapters through which each data line is electrically connected to the second electrostatic discharge structure to be the same, the difference in conduction resistance between the far end of each data line and the second electrostatic discharge structure can be minimized, reducing the risk of specific defects.

[0051] The array substrate and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0052] Figure 1 This is a partial planar structure diagram of an array substrate provided according to an embodiment of the present disclosure.

[0053] like Figure 1 As shown, the array substrate includes a display area 10 and a non-display area 20 located on at least one side of the display area 10. For example, the non-display area 20 may be located on one side of the display area 10, or the non-display area 20 may be located on both sides of the display area 10, or the non-display area 20 may surround the display area 10.

[0054] like Figure 1As shown, the array substrate includes multiple sub-pixels 100, multiple data lines 210, multiple gate lines 220 located in the display area 10, and multiple fan-out traces 300 located in the non-display area 20. For example, the array substrate includes a substrate 01, and the sub-pixels 100, data lines 210, gate lines 220, and fan-out traces 300 are all on the substrate 01. For example, the area where the sub-pixels 100 are located can be the area defined by the intersection of the data lines 210 and the gate lines 220.

[0055] Figure 2 for Figure 1 A schematic diagram of the planar structure of some sub-pixels, data lines, and gate lines in the display area of ​​the array substrate shown.

[0056] For example, such as Figure 2 As shown, each sub-pixel 100 may include a pixel electrode 110 and a common electrode (not shown), and the common electrode may be an electrode shared by multiple sub-pixels 100. For example, each sub-pixel 100 includes a transistor 120, such as a thin-film transistor 120. Transistors can be classified into N-type transistors and P-type transistors according to their characteristics. The transistors provided in this embodiment may be N-type transistors or P-type transistors depending on actual needs. For example, the gate of transistor 120 is electrically connected to gate line 220, one of the source and drain of transistor 120 is electrically connected to data line 210, and the other of the source and drain of transistor 120 is electrically connected to pixel electrode 110. For example, gate line 220 controls the opening or closing of transistor 120, and data line 210 inputs the voltage signal required for displaying the image to the pixel electrode 110 of sub-pixel 100 through transistor 120 to realize the display of the display device including the display substrate.

[0057] For example, the multiple sub-pixels 100 may include sub-pixels of different colors, such as blue sub-pixels that display blue light, green sub-pixels that display green light, and red sub-pixels that display red light. Of course, the multiple sub-pixels may also include white sub-pixels. Figure 1 The schematic diagram shows a plurality of sub-pixels 100 including red sub-pixels, green sub-pixels and blue sub-pixels that are arranged in sequence along a first direction, such as the X direction, such that three adjacent sub-pixels of different colors form a pixel.

[0058] like Figure 1 As shown, multiple data lines 210 are arranged along a first direction, and multiple gate lines 220 are arranged along a second direction, with the first and second directions intersecting. Figure 1 The diagram schematically shows the first direction as the X direction and the second direction as the Y direction. However, this is not a limitation; the first and second directions can be interchanged. For example, the angle between the first and second directions can be 80 to 110 degrees. For example, the first direction can be perpendicular to the second direction.

[0059] like Figure 1 As shown, a pair of gate lines 220 is provided between two adjacent sub-pixels 100 arranged along the second direction. For example, multiple gate lines 220 include a first gate line 221 and a second gate line 222 alternately arranged along the second direction. For example, a pair of gate lines includes a first gate line 221 and a second gate line 222.

[0060] like Figure 1 As shown, the multiple data lines 210 include multiple data line groups 2100 arranged along a first direction. Each data line group 2100 includes N data lines. In each data line group 2100, the m-th data line is electrically connected to the (m+N / 2)-th data line, where m is a positive integer not greater than N / 2. In the array substrate provided in this disclosure, the m-th data line in each data line group is electrically connected to the (m+N / 2)-th data line, which is equivalent to each data line group including only N / 2 data lines, thereby halving the number of data lines. N is an even number.

[0061] For example, such as Figure 1 As shown, multiple sub-pixels 100 can be arranged in an array along a first direction and a second direction. For example, sub-pixels 100 arranged along the Y direction can be a column of sub-pixels, and multiple sub-pixels 100 include multiple columns of sub-pixels. For example, each column of sub-pixels is electrically connected to a data line 210. For example, multiple columns of sub-pixels include multiple sub-pixel column groups, and multiple sub-pixel column groups are electrically connected to multiple data line groups 2100 in a one-to-one correspondence. For example, each sub-pixel column group includes N columns of sub-pixels. In each sub-pixel column group, the data line 210 electrically connected to the m-th column of sub-pixels and the data line 210 electrically connected to the (m+N / 2)-th column of sub-pixels are electrically connected to each other, such as end-to-end connection. The m-th column of sub-pixels and the (m+N / 2)-th column of sub-pixels are electrically connected to the first gate line 221 and the second gate line 222, respectively. This is equivalent to each sub-pixel column group being electrically connected to only N / 2 data lines, which helps to reduce the number of data lines and thus the number of source driver chips, thereby reducing costs. However, this is not the only option. Multiple sub-pixels can also be arranged in other ways, such as triangle arrangement or diamond arrangement, which can be set according to requirements.

[0062] like Figure 1As shown, multiple fan-out traces 300 are configured to be electrically connected to multiple data lines 210. The multiple fan-out traces 300 include multiple fan-out trace groups 3100 arranged along a first direction. Each fan-out trace group 3100 includes N / 2 fan-out traces, and the fan-out traces 300 in the same fan-out trace group 3100 are electrically connected to the data lines 210 in the same data line group 2100. The N / 2 fan-out traces 300 are electrically connected to the m-th data line to the (m-1+N / 2)-th data line respectively. In the array substrate provided in this disclosure, the m-th data line in each data line group is electrically connected to the (m+N / 2)-th data line, and the traces in the fan-out trace group are electrically connected to the m-th to (m-1+N / 2)-th data lines respectively, so that the number of traces in the fan-out trace group corresponding to each data line group is N / 2, which is equivalent to each data line group including only N / 2 data lines. This halves the number of data lines and halves the number of fan-out traces in the fan-out trace group, which helps to reduce the resistance difference caused by the length difference of different fan-out traces.

[0063] In some examples, such as Figure 1 and Figure 2 As shown, N is 12, and m is a positive integer not greater than 6, such as m can be 1, 2, 3, 4, 5, or 6. The six columns of sub-pixels 100 electrically connected to the first to sixth data lines in the same data line group 2100 are electrically connected to the first gate line 221, and the six columns of sub-pixels 100 electrically connected to the seventh to twelfth data lines in the same data line group 2100 are electrically connected to the second gate line 222.

[0064] For example, such as Figure 1 and Figure 2 As shown, 12 adjacent columns of subpixels form a subpixel column group. For example, three adjacent subpixels of different colors arranged along the X direction form a pixel, and a subpixel column group consists of four columns of pixels. For example, Figure 1 The array substrate shown can be applied to FHD (Full High Definition) HADS (High Advanced-Super Dimensional Switching) display devices. FHD refers to Full High Definition, and HADS refers to Advanced Super Dimensional Switching.

[0065] For example, such as Figure 1 and Figure 2 As shown, the column reversal method can be used to process the data including... Figure 1The display device on the array substrate shown is driven. The column inversion method refers to reversing the polarity of the displayed data every predetermined number of sub-pixel columns. With the column inversion method, within a frame, the polarity of the data signal on each data line is always the same (positive or negative). For example... Figure 1 As shown, the voltage polarities stored in the two sub-pixel columns connected to the same data line 210 are the same, and the voltage polarities stored in the two sub-pixel columns connected to the two adjacent data lines 210 are opposite. Therefore, although the m-th and (m+3)-th sub-pixels are configured to display the same color light, the two data lines connected to the m-th and (m+3)-th sub-pixels transmit data signals of opposite polarities. Conversely, when the m-th and (m+6)-th sub-pixels are configured to display the same color light, the data lines electrically connected to these two sub-pixels transmit data signals of the same polarity. Thus, the data lines electrically connected to the m-th and (m+6)-th sub-pixels are connected end-to-end, halving the number of data signal lines while avoiding defects such as head-shaking patterns, fine-pitch effects, and high power consumption in color mixing.

[0066] For example, such as Figure 1 As shown, the number N of data cables 210 in data cable group 2100 is not less than 4. For example, N can be an even number such as 6 or 8, and N can be set according to product requirements.

[0067] By setting the data lines as data line groups, the thin-film transistors of each sub-pixel can be electrically connected to the nearest data line. This prevents a problem where the thin-film transistors of a certain sub-pixel cannot be electrically connected to the nearest data line during the process of connecting the thin-film transistors of adjacent sub-pixels to the corresponding data lines, resulting in a large difference in the length of the connection structure between the thin-film transistors of adjacent sub-pixels and the corresponding data lines. Figure 1 The array substrate shown features low cost, low power consumption, and high aperture ratio.

[0068] Figure 3 This is a schematic diagram of a partial planar structure of the non-display area where the fan-out traces of an array substrate are located. Figure 4 for Figure 3 A schematic diagram of a partial planar structure of the array substrate shown.

[0069] Figure 3 and Figure 4 The array substrate shown has Figure 1 and Figure 2 The display area shown includes sub-pixel 100, data line 210, and gate line 220.

[0070] like Figure 3 and Figure 4As shown, the array substrate also includes an electrostatic discharge (ESD) unit 50. Data lines 210 are electrically connected to fan-out traces 300 through the ESD unit 50, or data lines 210 are electrically connected to fan-out traces 300 through the ESD unit 50 and the adapter 51. Taking the connection of 12 adjacent data lines 210 with 6 adjacent fan-out traces 300 as an example, two adjacent data lines 210 transmit data signals of different polarities, and the m-th data line 210 is electrically connected to the (m+6)-th data line 210 through the connecting trace 51.

[0071] like Figure 3 and Figure 4 As shown, among the multiple fan-out traces 300, two adjacent fan-out traces 31 and 32 are located on different layers. For example, fan-out trace 31 is set on the same layer as data line 210, and fan-out trace 32 is set on the same layer as gate line 220.

[0072] Figure 5 for Figure 3 and Figure 4 The circuit diagram shown illustrates the electrical connection between the data lines and the fan-out traces in the array substrate. Figure 4 The positions of the 12 adjacent data lines S1 to S12 are schematically shown.

[0073] During the research, the inventors of this application discovered that: Figure 3 and Figure 4 As shown, the first data line S1 is directly connected to the fan-out routing line 31; the seventh data line S7 is electrically connected to the same fan-out routing line 31 via two adapters 41; the second data line S2 is electrically connected to the fan-out routing line 32 via one adapter 41; the eighth data line S8 is electrically connected to the same fan-out routing line 32 via one adapter 41; the third data line S3 is directly connected to the fan-out routing line 31; the ninth data line S9 is electrically connected to the same fan-out routing line 31 via two adapters 41; the fourth data line S7... Data line S4 is electrically connected to fan-out routing line 32 via an adapter 41; data line S10 is electrically connected to the same fan-out routing line 32 via an adapter 41; data line S5 is electrically connected to fan-out routing line 31 via two adapters 41; data line S11 is directly connected to the same fan-out routing line 31; data line S6 is electrically connected to fan-out routing line 32 via an adapter 41; and data line S12 is electrically connected to the same fan-out routing line 32 via an adapter 41.

[0074] like Figures 3 to 5As shown, only electrostatic discharge units 50 are provided between the first data line S1, the third data line S3, and the eleventh data line S11 and the corresponding fan-out routing line 300. The two adapters 41 provided between the seventh data line S7, the ninth data line S9, and the fifth data line S5 and the corresponding fan-out routing line 300 are equivalent to two resistors R0 and R1. The adapter 41 provided between the second data line S2, the fourth data line S4, and the sixth data line S6 and the corresponding fan-out routing line 300 is equivalent to one resistor R2. The adapter 41 provided between the eighth data line S8, the tenth data line S10, and the twelfth data line S12 and the corresponding fan-out routing line 300 is equivalent to one resistor R3.

[0075] The resistance of different data lines and their corresponding fan-out traces varies. For example, the data signal required by data line S1 is transmitted directly to the display area without passing through the adapter; however, the data signal required by data line S7, which is connected to data line S1, needs to pass through two additional adapters before entering the display area. The adapter includes at least two stacked conductive layers, which are electrically connected through vias. Compared to the resistance of metal connection traces, the resistance of the adapter is much higher. For example, the resistance of an adapter is usually above 50Ω, while the resistance of a metal connection trace is only 5Ω. Therefore, even if the data signals transmitted from the fan-out trace to data lines S1 and S7 are the same, the signal resistance difference between the sub-pixels electrically connected to data line S1 and those electrically connected to data line S7 can reach at least 100Ω during data signal transmission, significantly increasing the risk of vertical stripes.

[0076] Therefore, of the data signals transmitted from the fan-out traces to the data lines, some data signals are directly transmitted into the display area, while others need to pass through one or two additional adapters before entering the display area. As a result, the resistance differences of different data lines significantly increase the risk of vertical lines.

[0077] Figure 6 for Figure 1 A partial structural diagram of the first non-display area in the array substrate shown. Figure 6 The positions of data lines S1 to S12 are schematically shown. Figure 6 The structure of the first transition portion on the side away from the fan-out trace in the array substrate shown can be combined with... Figure 3 The structure of the first transition section on the side away from the fan-out trace in the array substrate shown has the same characteristics.

[0078] like Figure 1 and Figure 6As shown, each data line 210 in at least one data line group 2100 is electrically connected to the corresponding fan-out routing line 300 through at least one first adapter 410. In at least one data line group 2100, the number of first adapters 410 through which the m-th data line 210 is electrically connected to the fan-out routing line 300 is the same as the number of first adapters 410 through which the (m+N / 2)-th data line 210 is electrically connected to the fan-out routing line 300.

[0079] The array substrate provided in this disclosure, by configuring the interconnected data lines to be electrically connected to the corresponding fan-out traces through the same number of first adapters, helps to reduce the load difference of the signal lines electrically connected to at least two columns of sub-pixels, thereby reducing the risk of vertical stripes caused by resistance differences.

[0080] For example, such as Figure 1 and Figure 6 As shown, the number of first adapters 410 through which different data lines 210 are electrically connected to the corresponding fan-out traces 300 is the same, which helps to reduce the difference in transmission resistance between different data lines and thus avoid the risk of vertical lines caused by resistance differences.

[0081] In some examples, such as Figure 6 As shown, the first adapter 410 includes at least two first adapter holes 4100. In at least one data line group 2100, the number of first adapter holes 4100 through which the m-th data line 210 is electrically connected to the fan-out trace 300 is the same as the number of first adapter holes 4100 through which the (m+N / 2)-th data line 210 is electrically connected to the fan-out trace 300. By setting the data lines connected to each other to be electrically connected to the same fan-out trace through the same number of first adapter holes, it is beneficial to achieve load consistency for signal lines electrically connected to at least two columns of sub-pixels, thereby avoiding the risk of vertical stripes caused by resistance differences.

[0082] For example, such as Figure 6 As shown, each of the first adapter portions 410 includes the same number of first adapter holes 4100.

[0083] In some examples, such as Figure 1 and Figure 6 As shown, the non-display area 20 includes a first non-display area 21 and a second non-display area 22 located on both sides of the display area 10 in the second direction. Multiple fan-out traces 300 and a first adapter 410 are both located in the first non-display area 21. The array substrate also includes an electrostatic discharge structure 500, which includes a first electrostatic discharge structure 510 located in the first non-display area 21. The first electrostatic discharge structure 510 is located between multiple data lines 210, such as those disposed in the display area, and the first adapter 410. The multiple data lines 210 are electrically connected to the multiple fan-out traces 300 through the first electrostatic discharge structure 510 and the first adapter 410.

[0084] Figure 7 for Figure 6 The circuit diagram shown illustrates the electrical connection between the data lines and the fan-out traces in the array substrate.

[0085] For example, such as Figure 6 and Figure 7 As shown, the electrostatic discharge structure 500 also includes a shorting ring (SR) 501. For example, the first electrostatic discharge structure 510 includes multiple sub-electrostatic discharge structures, each of which may include multiple transistors M, such as two transistors M9 and M11 or two transistors M13 and M15. Each sub-electrostatic discharge structure is connected to a data line 210, and all sub-electrostatic discharge structures are connected to the shorting ring 501. When there is a large inrush current on the data line, the transistors in the sub-electrostatic discharge structures can be activated to transfer the large inrush current to the shorting ring for further release. When there is a large inrush current on the shorting ring, the sub-electrostatic discharge structures may also be activated, and the current will be transferred to the data line.

[0086] For example, such as Figure 1 and Figure 6 As shown, a dummy gate region (not shown) can also be provided between the display area 10 and the electrostatic discharge structure 500, so that the load of the GOA (Gate Driven on Array) Reset unit is close to the load of the display area gate line. For example, a common electrode trace (not shown) can also be provided between the dummy gate region and the electrostatic discharge structure 500, which is electrically connected to the common signal line in the display area to provide a planar distribution of VCOM signals. For example, a pad is provided on the side of the fan-out trace 300 away from the display area 10 to bond it to the circuit board.

[0087] In some examples, such as Figure 6 As shown, in at least one fan-out cabling group 3100, two adjacent fan-out cablings 300 are respectively a first fan-out cabling 310 and a second fan-out cabling 320, and the first fan-out cabling 310 and the second fan-out cabling 320 are arranged on different layers. For example, the first fan-out cabling 310 and the second fan-out cabling 320 are arranged alternately.

[0088] In some examples, such as Figure 6 As shown, one of the first sector output line 310 and the second sector output line 320 is arranged on the same layer as multiple data lines 210, and the other of the first sector output line 310 and the second sector output line 320 is arranged on the same layer as multiple gate lines 220. Figure 6 The diagram schematically shows that the first sector output line 310 is arranged on the same layer as the data line, and the second sector output line 320 is arranged on the same layer as the gate line, but it is not limited to this, and the first sector output line and the second sector output line can be interchanged.

[0089] For example, such as Figure 6 As shown, the first data line S1 is electrically connected to the first outgoing line 310 via two first adapters 410; the seventh data line S7 is electrically connected to the same first outgoing line 310 via two first adapters 410; the second data line S2 is electrically connected to the second outgoing line 320 via two first adapters 410; the eighth data line S8 is electrically connected to the same second outgoing line 320 via two first adapters 410; the third data line S3 is electrically connected to the first outgoing line 310 via two first adapters 410; and the ninth data line S9 is electrically connected to the same first outgoing line 310 via two first adapters 410. Four data lines S4 are electrically connected to the second outgoing line 320 through two first adapters 410; the tenth data line S10 is electrically connected to the same second outgoing line 320 through two first adapters 410; the fifth data line S5 is electrically connected to the first outgoing line 310 through two first adapters 410; the eleventh data line S11 is electrically connected to the same first outgoing line 310 through two first adapters 410; the sixth data line S6 is electrically connected to the second outgoing line 320 through two first adapters 410; and the twelfth data line S12 is electrically connected to the same second outgoing line 320 through two first adapters 410.

[0090] For example, such as Figure 1 , Figure 6 and Figure 7 As shown, the same number of first adapter sections 410 are provided between the m-th data line Sm and the S(m+6)-th data line and their corresponding fan-out traces 300. For example, if two first adapter sections 410 are provided for each, the two first adapter sections 410 between the m-th data line Sm and its corresponding fan-out trace 300 are equivalent to two resistors R4 and R5, and the two first adapter sections 410 between the S(m+6)-th data line and its corresponding fan-out trace 300 are equivalent to two resistors R6 and R7. Therefore, the overall resistance of different data lines and their corresponding fan-out traces is basically the same, which helps to reduce the risk of vertical lines occurring.

[0091] In some examples, such as Figure 6 As shown, a straight line extending in a first direction passes through a first adapter 410 electrically connected to each fan-out cable 300 in at least one fan-out cable group 3100. For example, the straight line may pass through the geometric center of the first adapter 410 electrically connected to each fan-out cable 300 in at least one fan-out cable group 3100. For example, the straight line may pass through the edge of the first adapter 410 electrically connected to each fan-out cable 300 in at least one fan-out cable group 3100. For example, the straight line may pass through a first adapter hole 4100 in the first adapter 410 electrically connected to each fan-out cable 300 in at least one fan-out cable group 3100.

[0092] For example, such as Figure 6 As shown, a plurality of first transition portions 410 connected to the fan-out traces 300 of each fan-out trace group 3100 are arranged along a first direction. For example, the edges of the plurality of first transition portions 410 connected to the fan-out traces 300 of each fan-out trace group 3100 that are closest to the display area and parallel to the first direction are substantially on the same straight line, and the edges of the plurality of first transition portions 410 connected to the fan-out traces 300 of each fan-out trace group 3100 that are furthest from the display area and parallel to the first direction are substantially on the same straight line.

[0093] For example, Figure 6 The first adapter 410 shown can be connected to Figure 4 The adapter 41 shown has the same shape and size as the other two. Figure 4 As shown, the arrangement of the adapter 41 connected to data lines S1 to S12 is as provided in this disclosure. Figure 6 The arrangement of the first adapter 410 shown only increases the size of the product by less than 40 micrometers in the second direction, such as less than 35 micrometers or 34 micrometers. The impact on the product's border is small and can be basically ignored.

[0094] In some examples, such as Figure 6 As shown, the m-th data line 210 is electrically connected to the (m+N / 2)-th data line 210 via a first connection trace 610 located in the first non-display area. The first connection trace 610 is connected to the first adapter 410, and the first connection trace 610 and the fan-out trace 300 electrically connected to it are arranged on the same layer. For example, there may be multiple first connection traces 610, some of which may be arranged on the same layer as the data lines 210, while others may be arranged on the same layer as the gate lines 220.

[0095] In some examples, such as Figure 6 As shown, each first adapter portion 410 electrically connected to each fan-out cable 300 in at least one fan-out cable group 3100 includes two adapter sub-ports 4101 arranged along a second direction. For example, the two adapter sub-ports 4101 are electrically connected. For example, a gap is provided between the two adapter sub-ports 4101.

[0096] For example, such as Figure 6 As shown, both the first connection trace 610 and the fan-out trace 300 are electrically connected to the adapter sub-section 4101 on the side closer to the fan-out trace 300 among the two adapter sub-sections 4101. For example, a portion of the adapter sub-section 4101 and the first connection trace 610 and the fan-out trace 300 connected thereto can be an integrated structure.

[0097] In some examples, such as Figure 6As shown, there are multiple first connecting traces 610, with at least one first connecting trace 610 passing through the gap between two transition sub-sections 4101 included in the first adapter portion 410 that is not connected to it. For example, a portion of the multiple first connecting traces 610 is located between the first adapter portion 410 and the fan-out trace 300, while another portion of the multiple first connecting traces 610 passes through the gap between at least one of the two transition sub-sections 4101 included in the first adapter portion 410. This helps to reduce the space occupied by the first adapter portion and the first connecting traces, thereby reducing the impact on the product frame.

[0098] For example, such as Figure 6 As shown, the more of the N first adapter sections 410 connected to the N data lines in the same data line group overlap with the first connecting trace 610, the smaller the distance between the first electrostatic discharge structure 510 and the fan-out trace 300 can be set, and the less impact it has on the frame. For example, the first adapter section 410 connected to the second data line S2 to the first adapter section 410 connected to the eleventh data line S11 all overlap with the first connecting trace 610, which helps to maximize the reduction of the distance between the first electrostatic discharge structure 510 and the fan-out trace 300.

[0099] For example, such as Figure 6 As shown, the distance between two adjacent first transition sections 410 is greater than the line width of the two first connecting lines 610, so that the first connecting lines can pass through the gap between two adjacent first transition sections 410 and connect to the transition block 4102 in the first transition section 410 that is close to the fan-out line 300.

[0100] In some examples, such as Figure 6 As shown, each adapter sub-part 4101 includes two adapter blocks 4102 arranged along the second direction. For example, the two adapter blocks 4102 included in the same adapter sub-part 4101 are spaced apart. For example, the two adapter blocks 4102 included in the same adapter sub-part 4101 can be arranged on the same layer or on different layers. For example, the size of each adapter block 4102 in the X direction is larger than its size in the Y direction, so as to reduce the size in the Y direction while maintaining a good electrical connection relationship and reducing the impact on the frame.

[0101] In some examples, such as Figure 6As shown, in each first adapter section 410, the adapter block 4102 closest to the multiple data lines is arranged on the same layer as the data lines; the adapter block 4102 closest to the fan-out trace 300 and the fan-out trace 300 connected to it are arranged on the same layer; the two adapter blocks 4102 in the middle are connected and arranged on the same layer. For example, a connection structure is provided between the two adapter sub-sections 4101 included in the same first adapter section 410, and this connection structure can be an integral structure with the two adapter blocks 4102 in the middle. For example, the two adapter blocks 4102 in the middle can be arranged on the same layer as the data line 210 or the gate line 220.

[0102] For example, such as Figure 6 As shown, a connection structure is provided between the two adapter sub-parts 4101 included in the same first adapter part 410. The first connection trace 610 can overlap with this connection structure. For example, the connection structure can be arranged on the same layer as the data line 210 or the gate line 220. For example, the dimension of the connection structure in the Y direction is larger than the line width of the first connection trace 610. For example, the dimension of the connection structure in the X direction is smaller than the dimension of the adapter block 4102 in the X direction, so as to reduce the overlap area between the connection structure and the first connection trace.

[0103] Figure 8 and Figure 9 respectively along Figure 6 The partial cross-sectional view shown is taken by lines AA' and BB'.

[0104] In some examples, such as Figure 6 , Figure 8 and Figure 9 As shown, each first adapter portion 410 includes at least two conductive layers and a first adapter hole 4100 located between the two conductive layers that are stacked in the at least two conductive layers.

[0105] In some examples, such as Figure 6 and Figure 8 As shown, at least two conductive layers include three conductive layers. The three conductive layers include a first conductive layer 411, a third conductive layer 413, and a second conductive layer 412 that is stacked with both the first conductive layer 411 and the third conductive layer 413. One of the first conductive layer 411 and the third conductive layer 413 is connected to the fan-out routing line 300 and is disposed on the same layer. Figure 6 and Figure 8 The diagram schematically shows the third conductive part 413 connected to the fan-out trace 300 and disposed on the same layer, but it is not limited to this. In other first transition parts, the first conductive part is connected to the fan-out trace and disposed on the same layer.

[0106] For example, such as Figure 8As shown, the array substrate includes an insulating layer 02 located between the first conductive portion 411 and the third conductive portion 413, and an insulating layer 03 located between the first conductive portion 411 and the second conductive portion 412. The second conductive portion 412 is located on the side of the first conductive portion 411 away from the substrate 01, and the third conductive portion 413 is located between the first conductive portion 411 and the substrate 01.

[0107] For example, such as Figure 8 As shown, the first conductive portion 411 is disposed on the same layer as the data line, the third conductive portion 413 is disposed on the same layer as the gate line, and the second conductive portion 412 is disposed on the same layer as the common electrode of the sub-pixel. Of course, the embodiments disclosed herein are not limited to this, and the first conductive portion and the third conductive portion can be interchanged. For example, the connection structure between the two third conductive portions 413 overlaps with the first connection trace 610, and the first connection trace 610 is located on the side of the third conductive portion 413 away from the substrate 01.

[0108] In some examples, such as Figure 6 and Figure 9 As shown, at least two conductive layers are included, each comprising a first conductive layer 411 and a second conductive layer 412 stacked on top of the first conductive layer 411. The first conductive layer 411 is connected to and co-layered with the fan-out trace 300. For example, the first conductive layer 411 is co-layered with a data line, and the second conductive layer 412 is co-layered with the common electrode of a sub-pixel. For example, the connection structure between the two first conductive layers 411 overlaps with the first connection trace 610, which is located between the first conductive layer 411 and the substrate 01.

[0109] For example, such as Figures 6 to 9 As shown, the adapter block 4102 can be either a first conductive part 411 or a third conductive part 413. For example, the adapter block 4102 closest to the data line can be the first conductive part 411. For example, the adapter block 4102 connected to the first fan-out trace 310 and arranged on the same layer is the first conductive part 411, and the adapter block 4102 connected to the second fan-out trace 320 and arranged on the same layer is the third conductive part 413. For example, the two adapter blocks 4102 located in the middle can be selected as either the first conductive part 411 or the third conductive part 413 as needed.

[0110] For example, such as Figure 6As shown, among the plurality of first adapter portions 410 connected to data lines S1 to S12, the first portion of the first adapter portion 410 does not overlap with the first connecting trace 610, the second portion of the first adapter portion 410 overlaps with one first connecting trace 610, and the third portion of the first adapter portion 410 overlaps with two first connecting traces 610. For example, the first adapter portion 410 connected to data lines S1 and S12 does not overlap with the first connecting trace 610, the first adapter portion 410 connected to data lines S2, S3, S6, S7, S10, and S11 overlaps with one first connecting trace 610, and the first adapter portion 410 connected to data lines S4, S5, S8, and S9 overlaps with two first connecting traces 610. For example, two adjacent first transition sections 410 overlap with two first connecting lines 610, and the first transition lines 610 that overlap with the two adjacent first transition sections 410 are all arranged on the same layer.

[0111] For example, such as Figure 6 As shown, the first connecting trace 610 connecting data lines S1 and S7 is disposed on a different layer from the first connecting trace 610 connecting data lines S12 and S6, and is distributed in a substantially symmetrical manner about the axis of symmetry between data lines S6 and S7. For example, both of the above first connecting traces 610 overlap with the first adapter 410.

[0112] In some examples, such as Figure 2 and Figure 3 As shown, at least one grid line 220 is provided with a plurality of bends 2200. The plurality of bends 2200 include a plurality of first bends 2201 and a plurality of second bends 2202 arranged alternately along a first direction. The orientation of the first bends 2201 is opposite to that of the second bends 2202. For example, the first bends 2201 are oriented in the direction indicated by the arrow in the Y direction, and the second bends 2202 are oriented in the opposite direction to the direction indicated by the arrow in the Y direction. Of course, the first bends and the second bends can be interchanged.

[0113] In some examples, such as Figure 2 and Figure 3 As shown, each bend 2200 surrounds a transistor 120 in N sub-pixels 100 electrically connected to a data line group 2100. For example, each bend 2200 surrounds a transistor 120 in 12 sub-pixels 100 electrically connected to a data line group 2100.

[0114] Figure 10 This is a schematic diagram showing the positional relationship between the first adapter and the first connecting trace according to another example of an embodiment of this disclosure.

[0115] Figure 10 The array substrate shown and Figure 6The difference in the array substrate shown lies in the relative positional relationship between the first connecting trace 610 and the first adapter 410. Figure 10 The array substrate shown provides another wiring method for connecting the first connection trace 610 to the first adapter 410.

[0116] For example, such as Figure 10 As shown, the first connection trace 610 passes through the gap between the two transition sub-sections included in the first adapter portion 410 connected to the second to sixth data lines, while the gap between the two transition sub-sections included in the other first adapter portions 410 is not passed through by the first connection trace 610.

[0117] For example, such as Figure 10 As shown, the following description refers to the direction opposite to the arrow pointing in the X direction as downward. For example, the three adapter sub-sections on the side away from the data lines of the three first adapter sections 410 connected to data lines S4, S5, and S6 are all surrounded by the first connecting trace 610. For example, the first connecting trace 610 connecting data lines S1 and S7 is a bent trace, which passes through the middle of the two first adapter sections 410 connected to data lines S2 and S3 (i.e., between the two adapter sub-sections included in each first adapter section 410), below the first adapter section 410 connected to data line S4, the middle of the first adapter section 410 connected to data line S5, and below the first adapter section 410 connected to data line S6. For example, the first connecting trace 610 connecting data line S2 and data line S8 is a bent trace, which bypasses the middle of the first adapter portion 410 connected to data line S4 (i.e., between the two adapter sub-parts included in each first adapter portion 410), the bottom of the first adapter portion 410 connected to data line S5, the middle of the first adapter portion 410 connected to data line S6, and the bottom of the first adapter portion 410 connected to data line S7.

[0118] For example, such as Figure 10 As shown, the first adapter 410 connected to data lines S1 and S7-S12 does not overlap with the first connecting line 610. The first adapter 410 connected to data lines S2-S4 overlaps with one first connecting line 610. The first adapter 410 connected to data lines S5 and S6 overlaps with two first connecting lines 610.

[0119] Figure 11 This is a schematic diagram showing the positional relationship of the first adapter, the first connecting trace, and the fan-out trace according to another example of an embodiment of this disclosure. Figure 11 The data lines, gate lines, and electrostatic discharge structure in the array substrate shown can be connected to... Figures 1 to 4 as well as Figure 6 The data lines, gate lines, and electrostatic discharge structure shown have the same characteristics, and will not be described again here.

[0120] In some examples, such as Figure 11 As shown, in at least one fan-out cabling group, all fan-out cabling 300 are arranged on the same layer. For example, all fan-out cabling 300 in each fan-out cabling group are arranged on the same layer.

[0121] In some examples, such as Figure 11 As shown, each first adapter portion 410 electrically connected to each fan-out trace 300 in at least one fan-out trace group includes three conductive layers and a first adapter hole 4100 located between two of the three conductive layers. The three conductive layers include a first sub-conductive layer 4111, a second sub-conductive layer 4112, and a third sub-conductive layer 4113 that is stacked with both the first sub-conductive layer 4111 and the second sub-conductive layer 4112. The first sub-conductive layer 4111 is located between the second sub-conductive layer 4112 and multiple data lines. The data lines are disposed on the same layer as the first sub-conductive layer 4111, and the fan-out trace 300 is disposed on the same layer as the second sub-conductive layer 4112, and the fan-out trace 300 is connected to the second sub-conductive layer 4112. For example, the fan-out trace 300 and the second sub-conductive layer 4112 connected thereto can be an integrated structure.

[0122] Figure 11 In the provided array substrate, by setting the fan-out traces as a single-layer structure and each data line being electrically connected to the corresponding fan-out trace through the same number of first adapters, such as one first adapter, it is beneficial to reduce the transmission resistance difference of different data lines, thereby avoiding the risk of vertical lines caused by resistance differences.

[0123] For example, such as Figure 11 As shown, the fan-out trace 300 and the second sub-conductive portion 4112 are both disposed on the same layer as the gate line. For example, the third sub-conductive portion 4113 is disposed on the same layer as the common electrode of the sub-pixel. For example, a straight line extending in the X direction can only pass through a portion of the first transition portion 410.

[0124] In some examples, such as Figure 11 As shown, the first connecting trace 610 is connected to the first adapter 410, and the first connecting trace 610 and the fan-out trace 300 electrically connected to it are arranged on the same layer. For example, the first connecting trace 610, the first adapter 410 and the fan-out trace 300 connected to each other can be an integrated structure.

[0125] In some examples, such as Figure 11As shown, there are multiple first connection traces 610. The multiple first connection traces 610 include at least two types of first connection traces 6101 and 6102. One type of first connection trace 6101 includes a portion located on the side of the first adapter 410 that is not connected to it, away from the multiple data lines. The other type of first connection trace 6102 includes a portion located on the side of the first adapter 410 that is not connected to it, close to the multiple data lines.

[0126] For example, such as Figure 11 As shown, six adjacent first adapter sections 410 electrically connected to the same data cable group are arranged along a first direction, and a portion of the first connection traces 610 are located between these six first adapter sections 410 and the fan-out traces 300; another six adjacent first adapter sections 410 electrically connected to the same data cable group are arranged along a direction having a certain angle with the first direction, and another portion of the first connection traces 610 are located on the side of these other six first adapter sections 410 away from the fan-out traces 300.

[0127] Figure 12 for Figure 1 The second non-display area shown is a partial structural diagram in an example. Figure 13 for Figure 12 A partially enlarged view of the array substrate shown. Figure 14 for Figure 13 The circuit diagram shown illustrates the electrical connection between the data lines and the second electrostatic discharge structure in the array substrate.

[0128] In some examples, such as Figure 1 , Figure 12 and Figure 13 As shown, the electrostatic discharge structure 500 includes a second electrostatic discharge structure 520 located in the second non-display area 22. Multiple data lines 210 are electrically connected to the second electrostatic discharge structure 520 through multiple second adapters 420. The second electrostatic discharge structure 520 is located on the side of the second adapters 420 away from the multiple data lines 210.

[0129] For example, such as Figure 12 and Figure 14As shown, the electrostatic discharge structure 500 also includes a shorting ring (SR) 502. For example, the second electrostatic discharge structure 520 includes multiple sub-electrostatic discharge structures, each of which may include multiple transistors M, such as two transistors M17 and M19 or two transistors M21 and M23. Each sub-electrostatic discharge structure is connected to a data line 210, and all sub-electrostatic discharge structures are connected to the shorting ring 502. When there is a large inrush current on the data line, the transistors in the sub-electrostatic discharge structures can be activated to transfer the large inrush current to the shorting ring for further release. When there is a large inrush current on the shorting ring, the sub-electrostatic discharge structures may also be activated, and the current will be transferred to the data line.

[0130] For example, such as Figure 12 As shown, a common electrode trace (not shown) can also be provided between the second adapter 420 and the display area, which is electrically connected to the common signal line in the display area to provide a planar distribution of VCOM signals.

[0131] In some examples, such as Figure 12 and Figure 13 As shown, the array substrate also includes a detection signal line 710 and a switching component 720 located in the second non-display area. Both the detection signal line 710 and the switching component 720 are located on the side of the second electrostatic discharge structure 520 away from the display area, and the detection signal line 710 is connected to the second electrostatic discharge structure 520 via the switching component 720. For example, the array substrate also includes a detection signal switching line 730 located in the second display area. For example, multiple data lines 210 are grouped according to the signals transmitted for different color sub-pixels. For instance, data lines S1, S4, S7, and S10 are a group of data lines transmitting data signals for red sub-pixels; data lines S2, S5, S8, and S11 are a group of data lines transmitting data signals for green sub-pixels; and data lines S3, S6, S9, and S12 are a group of data lines transmitting data signals for blue sub-pixels.

[0132] For example, such as Figure 12 and Figure 13As shown, when manufacturing a display device including an array substrate, it is necessary to detect whether there are display problems. During the detection stage, a high-level signal can be applied to the detection signal switch line 730 (e.g., a high-level signal is applied when the switch component is an N-type transistor; a low-level signal is applied when the switch component is a P-type transistor), controlling the switch component 720 to be in the open state. The signal corresponding to the red sub-pixel transmitted by the detection signal line 710 (first detection signal line 7101) is transmitted to the data lines S1, S4, S7, and S10 through the control switch component. According to the online method; when the control switch component 720 is in the open state, the signal corresponding to the green sub-pixel transmitted by the detection signal line 710 (second detection signal line 7102) is transmitted through the control switch component to the data lines S2, S5, S8 and S11; when the control switch component 720 is in the open state, the signal corresponding to the blue sub-pixel transmitted by the detection signal line 710 (third detection signal line 7103) is transmitted through the control switch component to the data lines S3, S6, S9 and S12.

[0133] For example, such as Figure 12 and Figure 13 As shown, when the display device including the array substrate is working normally, a low-level signal is applied to the detection signal switch line 730, and the control switch component 720 is in the closed state. At this time, only the data line Sm is connected to the data line S(m+6).

[0134] For example, such as Figure 12 As shown, at least one switching component 720 can be a thin-film transistor (TFT). The gate of the TFT and the detection signal switching line 730 are integrated into a single structure. The TFT includes a first electrode and a second electrode. The first electrode is connected to a second electrostatic discharge structure 520, and the second electrode is connected to a detection signal line 710 via a block-shaped connection portion 740. The second electrode overlaps with other detection signal lines 710 that are not connected to it, and a pad 750 is provided at the overlap position. For example, the pad 750 can be disposed on the same layer as the active layer of the TFT. By providing a pad at the overlap position of the second electrode of the TFT and the detection signal line, the probability of electrostatic breakdown at the overlap position can be reduced, and the step difference between this position and the location of the active layer of the TFT can be improved.

[0135] In some examples, such as Figure 13 As shown, the m-th data line 210 and the (m+N / 2)-th data line 210 are electrically connected through the second connection trace 620 located in the second non-display area. The second electrostatic discharge structure 520 is connected to the second adapter 420 through the third connection trace 630. The third connection trace 630 and the second connection trace 620 are located on different layers.

[0136] For example, such as Figure 13 As shown, the m-th data line 210 and the (m+6)-th data line 210 are electrically connected via a second connection trace 620 located in the second non-display area. For example, one of the second connection trace 620 and the third connection trace 630 is disposed on the same layer as the data lines, and the other is disposed on the same layer as the gate lines.

[0137] For example, such as Figure 12 and Figure 13 As shown, the second adapter 420 includes two adapter blocks 4202. One adapter block 4202 is a first adapter block closer to the data line 210, and the other adapter block 4202 is a second adapter block farther from the data line 210. The first adapter block is disposed on the same layer as the data line 210, and the second adapter block is disposed on the same layer as the gate line 220. For example, the third connection trace 630 is disposed on the same layer as the data line 210 and is connected to the first adapter block. For example, the third connection trace 630 and the first adapter block are integrally formed. For example, the second connection trace 620 is disposed on the same layer as the gate line 220 and is connected to the second adapter block. For example, the second connection trace 620 and the second adapter block are integrally formed.

[0138] During the research, the inventors of this application discovered that: Figures 12 to 14 As shown, the first data line S1, the second data line S2, the third data line S3, the tenth data line S10, the eleventh data line S11, and the twelfth data line S12 are all directly connected to the third connection trace 630; the remaining data lines 210 are all connected to the corresponding third connection trace 630 through two second adapters 420. For example, the two second adapters 420 provided between the seventh data line S7, the eighth data line S8, and the ninth data line S9 and the corresponding third connection trace 630 are equivalent to two resistors R1 and R10, and the two second adapters 420 provided between the fourth data line S4, the fifth data line S5, and the sixth data line S6 and the corresponding third connection trace 630 are equivalent to two resistors R14 and R15.

[0139] The overall resistance of different data lines and their corresponding third connection traces varies. Therefore, the anti-static capability at the distal end of each data line differs. For example, the surge current transmission resistance between different data lines and the second electrostatic discharge structure varies. Figure 13As shown, compared to the first data line S1, the second data line S2, the third data line S3, the tenth data line S10, the eleventh data line S11, and the twelfth data line S12, which are all directly connected to the third connection line 630, the remaining data lines 210 are mostly connected to the corresponding third connection line 630 through two second adapters 420. When a large static electricity is introduced into the display device, the probability of inducing static electricity through different static discharge structures is different. For example, large static electricity tends to concentrate in static discharge structures that are not connected to the second adapter, resulting in static selectivity, which causes poor specificity.

[0140] Figure 15 for Figure 1 A partial structural diagram of the second non-display area in the array substrate shown. Figure 15 The positions of data lines S1 to S12 are schematically shown. Figure 15 The structure of the second transition portion on the side away from the second electrostatic discharge structure in the array substrate shown can be combined with... Figure 12 The structure on the side of the second transition portion away from the second electrostatic discharge structure in the array substrate shown has the same characteristics. Figure 15 The structure of the second transition section in the array substrate shown can be the same as... Figure 12 The second transition section in the array substrate shown has the same structure.

[0141] In some examples, such as Figure 15 As shown, the number of second adapters 420 through which the m-th data line is electrically connected to the second electrostatic discharge structure 520 is the same as the number of second adapters 420 through which the (m+N / 2)-th data line is electrically connected to the second electrostatic discharge structure 520.

[0142] By setting the number of second adapters through which each data line is electrically connected to the second electrostatic discharge structure to be the same, the difference in conduction resistance between the far end of each data line and the second electrostatic discharge structure can be minimized, reducing the risk of specific defects.

[0143] In some examples, such as Figure 15 As shown, each second adapter portion 420 includes at least two second adapter holes 4200. The number of second adapter holes 4200 through which the m-th data line is electrically connected to the second electrostatic discharge structure 520 is the same as the number of second adapter holes 4200 through which the (m+N / 2)-th data line is electrically connected to the second electrostatic discharge structure 520. This makes the conduction resistance of the distal end of each data line to the second electrostatic discharge structure basically equal, further reducing the risk of specific defects.

[0144] In some examples, such as Figure 15As shown, the m-th data line is electrically connected to the (m+N / 2)-th data line via a second connection trace 620 located in the second non-display area. The second electrostatic discharge structure 520 is connected to the second adapter 420 via a third connection trace 630, which is arranged on the same layer as the second connection trace 620. By arranging the second and third connection traces on the same layer, it is beneficial to ensure that the number of second adapters through which each data line is electrically connected to the corresponding third connection trace is the same.

[0145] In some examples, such as Figure 12 and Figure 15 As shown, both the second connecting trace 620 and the third connecting trace 630 are disposed on the same layer as the multiple gate lines 220. For example, both the second connecting trace 620 and the third connecting trace 630 are connected to the second adapter block of the second adapter section 420. For example, the second adapter block and the second connecting trace 620 and the third connecting trace 630 connected thereto are integrally disposed in the structure.

[0146] Figure 16 for Figure 15 The circuit diagram shown illustrates the electrical connection between the data lines and the second electrostatic discharge structure in the array substrate.

[0147] For example, such as Figure 15 and Figure 16 As shown, the same number of second transition sections 420 are provided between the m-th data line Sm and the S(m+6)-th data line and the corresponding second electrostatic discharge structure 520. For example, if each has one second transition section 420, the second transition section 420 between the m-th data line Sm and the corresponding second electrostatic discharge structure 520 is equivalent to a resistor R11, and the second transition section 420 between the S(m+6)-th data line and the corresponding second electrostatic discharge structure 520 is equivalent to a resistor R8. Therefore, the conduction resistance between the distal end of each data line and the second electrostatic discharge structure is essentially equal, further reducing the risk of specific defects.

[0148] In some examples, such as Figure 12 and Figure 15As shown, each second transition portion 420 includes three conductive layers and a second transition hole 4200 located between two of the three conductive layers. The three conductive layers include a fourth sub-conductive layer 4201, a fifth sub-conductive layer 4202, and a sixth sub-conductive layer 4203 that is stacked with both the fourth and fifth sub-conductive layers 4202. The fourth sub-conductive layer 4201 is located between the fifth sub-conductive layer 4202 and multiple data lines 210. The data lines 210 are disposed on the same layer as the fourth sub-conductive layer 4201. The fifth sub-conductive layer 4202 is disposed on the same layer as the second connection trace 620, and both the second connection trace 620 and the third connection trace 630 are connected to the fifth sub-conductive layer 4202. For example, the sixth sub-conductive layer 4203 can be disposed on the same layer as the common electrode of the sub-pixel.

[0149] For example, such as Figure 15 As shown, the connection relationship between the fourth sub-conductive part 4201 and the sixth sub-conductive part 4203 can be referred to Figure 9 The connection relationship between the second conductive part 412 and the first conductive part 411, and the connection relationship between the fifth sub-conductive part 4202 and the sixth sub-conductive part 4203 shown can be referenced. Figure 8 The connection relationship between the third conductive part 413 and the first conductive part 411 is shown.

[0150] Another embodiment of this disclosure provides an array substrate, which can be referred to Figures 1 to 16 The array substrate shown includes a display area 10 and a first non-display area 21 and a second non-display area 22 located on both sides of the display area 10.

[0151] like Figure 1 As shown, the array substrate includes multiple sub-pixels 100 located in the display area 10, multiple data lines 210, multiple gate lines 220, and multiple fan-out traces 300 located in the first non-display area 21. The multiple data lines 210 are arranged along a first direction, and the multiple gate lines 220 are arranged along a second direction. A gate line pair formed by two gate lines is provided between two adjacent sub-pixels 100 arranged along the second direction. The first direction and the second direction intersect. The multiple fan-out traces 300 are configured to be electrically connected to the multiple data lines 210. The multiple data lines 210 include multiple data line groups 2100 arranged along the first direction. Each data line group 2100 includes N data lines. In each data line group 2100, the m-th data line 210 is electrically connected to the (m+N / 2)-th data line 210, where m is a positive integer not greater than N / 2. The sub-pixels, data lines, gate lines, and fan-out traces in the array substrate provided in this embodiment can have the same characteristics as the sub-pixels, data lines, gate lines, and fan-out traces in the above embodiments, and will not be described again here.

[0152] like Figures 1 to 16As shown, the array substrate also includes an electrostatic discharge structure 520 (equivalent to the second electrostatic discharge structure 520 in the above embodiment), located in the second non-display area 22. Multiple data lines 210 are electrically connected to the electrostatic discharge structure 520 through multiple adapters 420 (equivalent to the second adapters 420 in the above embodiment). The electrostatic discharge structure 520 is located on the side of the adapters 420 away from the multiple data lines 210.

[0153] For example, the array substrate also includes a first electrostatic discharge structure 510, located in the first non-display area 21 and between multiple data lines 210 and multiple fan-out traces 300.

[0154] The first electrostatic discharge structure, fan-out trace, and first adapter in the array substrate provided in this embodiment have the same features as the first electrostatic discharge structure, fan-out trace, and first adapter in the above embodiments, and will not be described again here. The second electrostatic discharge structure and adapter in the array substrate provided in this embodiment have the same features as the second electrostatic discharge structure and second adapter in the above embodiments, and will not be described again here.

[0155] like Figure 15 and Figure 16 As shown, in at least one data line group, the number of adapters 420 through which the m-th data line is electrically connected to the second electrostatic discharge structure 520 is the same as the number of adapters 420 through which the (m+N / 2)-th data line is electrically connected to the second electrostatic discharge structure 520. For example, N can be the same as N in the above embodiment. The connection method between the data line and the second electrostatic discharge structure in the array substrate provided in this embodiment is only... Figure 15 The example shown does not include Figure 13 The example shown, and the connection method of the data lines and fan-out traces in the array substrate provided in this embodiment, includes... Figures 4 to 11 The connection method provided in any of the examples.

[0156] By setting the number of adapters through which each data line is electrically connected to the second electrostatic discharge structure to be the same, the difference in conduction resistance between the far end of each data line and the second electrostatic discharge structure can be minimized, reducing the risk of specific defects.

[0157] In some examples, such as Figure 15 As shown, each adapter 420 includes at least two adapter holes 4200 (equivalent to the second adapter hole 4200 in the above embodiment). In at least one data line group, the number of adapter holes 4200 through which the m-th data line 210 is electrically connected to the second electrostatic discharge structure 520 is the same as the number of adapter holes 4200 through which the (m+N / 2)-th data line is electrically connected to the second electrostatic discharge structure 520. This makes the conduction resistance of the distal end of each data line and the second electrostatic discharge structure substantially equal, further reducing the risk of specific defects.

[0158] In some examples, such as Figure 15 As shown, the m-th data line is electrically connected to the (m+N / 2)-th data line via a first sub-connection trace 620 located in the second non-display area (equivalent to the second connection trace 620 in the above embodiment). The second electrostatic discharge structure 520 is connected to the adapter 420 via a second sub-connection trace 630 (equivalent to the third connection trace 630 in the above embodiment). The first sub-connection trace 620 and the second sub-connection trace 630 are arranged on the same layer. By arranging the first and second sub-connection traces on the same layer, it is beneficial to ensure that the number of adapters through which each data line is electrically connected to the second electrostatic discharge structure is the same.

[0159] In some examples, such as Figure 12 and Figure 15 As shown, both the first sub-connection trace 620 and the second sub-connection trace 630 are disposed on the same layer as the gate line 220. The first and second sub-connection traces in this embodiment may have the same characteristics as the second and third connection traces in the above embodiments, and will not be described again here.

[0160] For example, such as Figure 6 and Figure 13 As shown, in one example of this embodiment, the number of first adapters 410 through which the data line Sm is electrically connected to the fan-out routing line 300 is the same as the number of first adapters 410 through which the data line S(m+N / 2) is electrically connected to the same fan-out routing line 300, and the number of second adapters 420 through which the data line Sm is electrically connected to the second electrostatic discharge structure 520 is different from the number of second adapters 420 through which the data line S(m+N / 2) is electrically connected to the same second electrostatic discharge structure 520.

[0161] For example, such as Figure 6 and Figure 15 As shown, in one example of this embodiment, the number of first adapters 410 through which the data line Sm is electrically connected to the fan-out routing line 300 is the same as the number of first adapters 410 through which the data line S(m+N / 2) is electrically connected to the same fan-out routing line 300, and the number of second adapters 420 through which the data line Sm is electrically connected to the second electrostatic discharge structure 520 is the same as the number of second adapters 420 through which the data line S(m+N / 2) is electrically connected to the same second electrostatic discharge structure 520.

[0162] For example, such as Figure 4 and Figure 15As shown, in one example of this embodiment, the number of adapters 41 through which the data line Sm is electrically connected to the fan-out routing line 300 is different from the number of adapters 41 through which the data line S(m+N / 2) is electrically connected to the same fan-out routing line 300, and the number of second adapters 420 through which the data line Sm is electrically connected to the second electrostatic discharge structure 520 is the same as the number of second adapters 420 through which the data line S(m+N / 2) is electrically connected to the same second electrostatic discharge structure 520.

[0163] Figure 17 This is a schematic block diagram of a display device according to another embodiment of the present disclosure. Another embodiment of the present disclosure provides a display device 800 including any of the array substrates 900 described above.

[0164] For example, the display device further includes a counter substrate disposed opposite to the array substrate. For example, the counter substrate may be a color filter substrate. For example, the display device further includes a liquid crystal layer located between the array substrate and the counter substrate.

[0165] For example, the display device can be any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator; this embodiment is not limited to this.

[0166] The following points need to be explained:

[0167] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0168] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0169] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. An array substrate, comprising a display area and a non-display area located at least one side of the display area, the array substrate comprising: a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area, the plurality of data lines arranged along a first direction; a plurality of gate lines located in the display area, the plurality of gate lines arranged along a second direction, and a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels arranged along the second direction, the first direction intersects the second direction; a plurality of fan-out wires located in the non-display area, the plurality of fan-out wires configured to be electrically connected with the plurality of data lines, wherein the plurality of data lines comprises a plurality of data line groups arranged along the first direction, each data line group comprises N data lines, in each data line group, an m th data line is electrically connected with an (m+N / 2) th data line, m is a positive integer not greater than N / 2; the plurality of fan-out wires comprises a plurality of fan-out wire groups arranged along the first direction, each fan-out wire group comprises N / 2 fan-out wires, and the fan-out wires in the same fan-out wire group are electrically connected with the data lines in the same data line group, the N / 2 fan-out wires are respectively electrically connected with the m th data line to the (m-1+N / 2) th data line; each data line in at least one data line group is electrically connected with the corresponding fan-out wire through at least one first adapter, in the at least one data line group, the number of the first adapters through which the m th data line is electrically connected with the fan-out wire is the same as the number of the first adapters through which the (m+N / 2) th data line is electrically connected with the fan-out wire. the first adapter comprises at least two first adapter holes, in the at least one data line group, the number of the first adapter holes through which the m th data line is electrically connected with the fan-out wire is the same as the number of the first adapter holes through which the (m+N / 2) th data line is electrically connected with the fan-out wire; the non-display area comprises a first non-display area and a second non-display area located at two sides of the display area in the second direction respectively, the plurality of fan-out wires and the first adapter are located in the first non-display area; the array substrate further comprises an electrostatic discharge structure, the electrostatic discharge structure comprises a first electrostatic discharge structure and a second electrostatic discharge structure, wherein the first electrostatic discharge structure is located in the first non-display area, the second electrostatic discharge structure is located in the second non-display area, the first electrostatic discharge structure is located between the plurality of data lines and the first adapter, the plurality of data lines are electrically connected with the plurality of fan-out wires through the first electrostatic discharge structure and the first adapter; the plurality of data lines are electrically connected with the second electrostatic discharge structure through a plurality of second adapters, the second electrostatic discharge structure is located on a side of the second adapter away from the plurality of data lines, the number of the second adapters through which the m th data line is electrically connected with the second electrostatic discharge structure is the same as the number of the second adapters through which the (m+N / 2) th data line is electrically connected with the second electrostatic discharge structure. ​ ​ ​ ​ ​ ​ ​ 2. The array substrate according to claim 1, wherein, ​ 3. The array substrate of claim 1, wherein, ​ ​ ​ 4. The array substrate according to claim 3, wherein, Each second adapter part comprises at least two second adapter holes, the number of the second adapter holes through which the mth data line is electrically connected with the second electrostatic discharge structure is the same as the number of the second adapter holes through which the (m+N / 2)th data line is electrically connected with the second electrostatic discharge structure.

5. The array substrate according to claim 3 or 4, wherein, In the at least one fan-out wire group, two adjacent fan-out wires are a first fan-out wire and a second fan-out wire, and the first fan-out wire is arranged on a different layer from the second fan-out wire. A straight line extending along the first direction passes through the first adapter part electrically connected with each fan-out wire in the at least one fan-out wire group.

6. The array substrate according to claim 5, wherein, The mth data line and the (m+N / 2)th data line are electrically connected through a first connection wire located in the first non-display area, the first connection wire is connected with the first adapter part, and the first connection wire and the fan-out wire electrically connected therewith are arranged on the same layer.

7. The array substrate according to claim 3, wherein, The mth data line and the (m+N / 2)th data line are electrically connected through a second connection wire located in the second non-display area, the second electrostatic discharge structure is connected with the second adapter part through a third connection wire, and the third connection wire is arranged on the same layer as the second connection wire.

8. The array substrate of claim 6, wherein, The first adapter part comprises at least two layers of conductive parts and a first adapter hole. The at least two layers of conductive parts comprise three layers of conductive parts, including a first conductive part, a third conductive part, and a second conductive part arranged in a stack with the first conductive part and the third conductive part, one of the first conductive part and the third conductive part is connected with the fan-out wire and arranged on the same layer, or the at least two layers of conductive parts comprise two layers of conductive parts, including a first conductive part and a second conductive part arranged in a stack with the first conductive part, and the first conductive part is connected with the fan-out wire and arranged on the same layer.

9. The array substrate of claim 8, wherein, Each first adapter part electrically connected with each fan-out wire in the at least one fan-out wire group comprises two adapter sub-parts arranged along the second direction, and the number of the first connection wires is plural, and at least one first connection wire passes through the interval between the two adapter sub-parts of the first adapter part not connected therewith.

10. The array substrate of claim 9, wherein, Each adapter sub-part comprises two adapter blocks arranged along the second direction. In each first adapter part, the adapter block closest to the plurality of data lines is arranged on the same layer as the data lines, the adapter block closest to the fan-out wire is arranged on the same layer as the fan-out wire connected therewith, and the two adapter blocks in the middle are connected and arranged on the same layer.

11. The array substrate of claim 1, wherein, In the at least one fan-out wire group, each fan-out wire is arranged on the same layer, each first adapter part electrically connected with each fan-out wire in the at least one fan-out wire group comprises three layers of conductive parts and a first adapter hole, the three layers of conductive parts comprise a first sub-conductive part, a second sub-conductive part, and a third sub-conductive part arranged in a stack with the first sub-conductive part and the second sub-conductive part, the first sub-conductive part is located between the second sub-conductive part and the plurality of data lines, the data lines are arranged on the same layer as the first sub-conductive part, and the fan-out wire is connected with the second sub-conductive part and arranged on the same layer.

12. The array substrate of claim 11, wherein, The mth data line and the (m+N / 2)th data line are electrically connected through a first connecting trace, the first connecting trace is connected with the first adapting part, and the first connecting trace and the fan-out trace electrically connected therewith are arranged in the same layer; The number of the first connecting traces is plural, and the plural first connecting traces include at least two types of first connecting traces, one type of first connecting trace includes a part located on a side of the first adapting part not connected therewith and away from the plural data lines, and the other type of first connecting trace includes a part located on a side of the first adapting part not connected therewith and close to the plural data lines.

13. The array substrate of claim 7, wherein, The second adapting part includes three layers of conductive parts and a second adapting hole, the three layers of conductive parts include a fourth sub-conductive part, a fifth sub-conductive part, and a sixth sub-conductive part arranged in the same layer with the fourth sub-conductive part and the fifth sub-conductive part, the fourth sub-conductive part is located between the fifth sub-conductive part and the plural data lines, the data line is arranged in the same layer with the fourth sub-conductive part, the fifth sub-conductive part is arranged in the same layer with the second connecting trace, and the second connecting trace and the third connecting trace are both connected with the fifth sub-conductive part.

14. The array substrate of claim 5, wherein, One of the first fan-out trace and the second fan-out trace is arranged in the same layer with the plural data lines, and the other of the first fan-out trace and the second fan-out trace is arranged in the same layer with the plural gate lines.

15. The array substrate of claim 7, wherein, The second connecting trace and the third connecting trace are both arranged in the same layer with the plural gate lines.

16. The array substrate of claim 3, wherein, The mth data line and the (m+N / 2)th data line are electrically connected through a second connecting trace located in the second non-display area, the second electrostatic discharge structure is connected with the second adapting part through a third connecting trace, and the third connecting trace and the second connecting trace are located in different layers.

17. The array substrate of claim 3, further comprising: a detection signal line and a switching component located in the second non-display area, wherein the detection signal line and the switching component are both located on a side of the second electrostatic discharge structure away from the display area, and the detection signal line is connected with the second electrostatic discharge structure through the switching component.

18. The array substrate according to any one of claims 1-4, wherein, N is 12, the plural gate lines include first gate lines and second gate lines alternately arranged along the second direction, six columns of sub-pixels electrically connected with the first to sixth data lines in the same data line group are electrically connected with the first gate lines, and six columns of sub-pixels electrically connected with the seventh to twelfth data lines in the same data line group are electrically connected with the second gate lines.

19. The array substrate according to any one of claims 1-4, wherein, At least one gate line is provided with a plurality of bending parts, the plurality of bending parts include a plurality of first bending parts and a plurality of second bending parts alternately arranged along the first direction, and the direction of the first bending parts and the direction of the second bending parts are opposite. Each sub-pixel includes a transistor, and each bending part surrounds the transistors in the N sub-pixels electrically connected with one data line group.

20. An array substrate, comprising a display area and first and second non-display areas located on two sides of the display area respectively, the array substrate comprising: a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area, the plurality of data lines arranged along a first direction; a plurality of gate lines located in the display area, the plurality of gate lines arranged along a second direction, and a pair of gate lines formed by two gate lines arranged between adjacent two sub-pixels along the second direction, the first direction intersecting the second direction; a plurality of fan-out lines located in the first non-display area, the plurality of fan-out lines configured to electrically connect with the plurality of data lines, wherein the plurality of data lines comprises a plurality of data line groups arranged along the first direction, each data line group comprising N data lines, in each data line group, an mth data line is electrically connected with an (m+N / 2)th data line, m is a positive integer not greater than N / 2; the array substrate further comprises an electrostatic discharge structure located in the second non-display area, the plurality of data lines electrically connected with the electrostatic discharge structure through a plurality of transfer portions, the electrostatic discharge structure located on a side of the transfer portions away from the plurality of data lines, in at least one data line group, the number of transfer portions through which an mth data line is electrically connected with the electrostatic discharge structure is the same as the number of transfer portions through which an (m+N / 2)th data line is electrically connected with the electrostatic discharge structure.

21. The array substrate of claim 20, wherein, each transfer portion comprises at least two transfer holes, in the at least one data line group, the number of transfer holes through which an mth data line is electrically connected with the electrostatic discharge structure is the same as the number of transfer holes through which an (m+N / 2)th data line is electrically connected with the electrostatic discharge structure.

22. The array substrate of claim 20 or 21, wherein, the mth data line and the (m+N / 2)th data line are electrically connected through a first sub-connection line located in the second non-display area, the electrostatic discharge structure is connected with the transfer portion through a second sub-connection line, the first sub-connection line and the second sub-connection line are disposed in the same layer.

23. The array substrate of claim 22, wherein, the first sub-connection line and the second sub-connection line are disposed in the same layer as the gate lines.

24. A display device comprising the array substrate of any one of claims 1-23.

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