Layout correction method and device, medium, equipment and program product

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a layout correction method, a layout correction device, a computer readable medium, electronic equipment and a computer program product. The method comprises the following steps: acquiring a correction rule for correcting the layout, wherein the correction rule comprises a mapping relation between a correction position and a correction amount; respectively positioning a local layout corresponding to each correction position on the layout; and determining a target correction value having a mapping relationship with the local layout according to the correction rule, and adjusting the key size of the circuit structure in the local layout according to the target correction value. According to the invention, the processing reliability and the quality stability of the photoetching process can be improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a layout correction method, a layout correction device, a computer-readable medium, an electronic device, and a computer program product. Background Art

[0002] Photolithography is a key technology used in the semiconductor manufacturing process. It involves transferring fine circuit structure patterns into a photoresist layer on a substrate through a photochemical reaction, and then transferring the pattern to the substrate through subsequent processes such as etching.

[0003] The main processes of photolithography technology include exposure and development process and etching process. Exposure and development process refers to the accurate transfer of the pattern pre-fabricated on the mask to the photoresist layer pre-coated on the wafer surface or dielectric layer through the exposure system; while the etching process uses chemical or physical methods to remove the material on the substrate surface that is not masked by the resist layer, thereby forming a pattern on the substrate surface that is completely consistent with the resist layer pattern.

[0004] As the feature size of integrated circuits continues to decrease, the manufacturing of integrated circuits requires higher and higher precision in the photolithography process. Under the influence of various complex factors such as optical proximity effect, random effect, equipment defects, and material defects, the products processed by the photolithography process often have a certain degree of processing error, resulting in problems such as poor process stability and low yield. Summary of the invention

[0005] The present application provides a layout correction method, a layout correction device, a computer-readable medium, an electronic device, and a computer program product, the purpose of which is to improve the processing reliability and quality stability of a photolithography process.

[0006] According to one aspect of an embodiment of the present application, a method for correcting a layout is provided, the method comprising: obtaining a correction rule for correcting the layout, the correction rule comprising a mapping relationship between a correction position and a correction amount; positioning local layouts corresponding to each of the correction positions on the layout; determining a target correction amount having a mapping relationship with the local layout according to the correction rule, and adjusting a critical dimension of a circuit structure in the local layout according to the target correction amount.

[0007] According to one aspect of an embodiment of the present application, a layout correction device is provided, the device comprising:

[0008] An acquisition module is configured to acquire a correction rule for performing correction processing on the layout, wherein the correction rule includes a mapping relationship between a correction position and a correction amount;

[0009] A positioning module, configured to respectively position the local layouts corresponding to the respective correction positions on the layout;

[0010] The adjustment module is configured to determine a target correction amount having a mapping relationship with the local layout according to the correction rule, and adjust a critical dimension of the circuit structure in the local layout according to the target correction amount.

[0011] In some embodiments of the present application, based on the above technical solution, the critical dimension includes line width and / or spacing, the line width is used to represent the radial width of a circuit structure, and the spacing is used to represent the distance between two adjacent circuit structures.

[0012] In some embodiments of the present application, based on the above technical solution, the positioning module further includes:

[0013] A space acquisition module is configured to acquire a concrete space corresponding to the layout, wherein the concrete space is a two-dimensional closed space for concretely displaying the layout;

[0014] A coordinate system establishment module is configured to establish a plane coordinate system using a point in the concrete space as a coordinate origin;

[0015] A region positioning module, configured to respectively locate local space regions corresponding to each of the correction positions in the plane coordinate system;

[0016] The layout determination module is configured to determine the circuit structure of the layout contained in the local space area as the local layout corresponding to the correction position.

[0017] In some embodiments of the present application, based on the above technical solution, the visualization space includes a photolithography mask for projecting the layout onto a substrate, and the plane coordinate system includes a plane rectangular coordinate system established on the photolithography mask.

[0018] In some embodiments of the present application, based on the above technical solution, the visualization space includes a wafer for forming a pattern corresponding to the layout, and the plane coordinate system includes a plane polar coordinate system established on the wafer.

[0019] In some embodiments of the present application, based on the above technical solution, the area positioning module includes:

[0020] a rule traversal module, configured to traverse the correction rules to obtain a first positioning parameter and a second positioning parameter of each correction position, wherein the first positioning parameter is used to represent a position range of the correction position in a first spatial dimension, and the second positioning parameter is used to represent a position range of the correction position in a second spatial dimension;

[0021] The parameter positioning module is configured to locate a local space area consisting of a position range covered by the first positioning parameter and the second positioning parameter in the plane coordinate system.

[0022] In some embodiments of the present application, based on the above technical solution, the plane coordinate system is a plane rectangular coordinate system, the first positioning parameter is the position range on the horizontal axis of the plane rectangular coordinate system, and the second positioning parameter is the position range on the vertical axis of the plane rectangular coordinate system.

[0023] In some embodiments of the present application, based on the above technical solution, the plane coordinate system is a plane polar coordinate system, the first positioning parameter is the position range on the polar diameter of the plane polar coordinate system, and the second positioning parameter is the position range on the polar angle of the plane polar coordinate system.

[0024] In some embodiments of the present application, based on the above technical solution, the acquisition module further includes:

[0025] A parameter acquisition module, configured to acquire static processing parameters for processing a product according to the layout, wherein the static processing parameters include parameters that remain fixed during the product processing;

[0026] The rule determination module is configured to determine a correction rule for correcting the layout according to the static processing parameters.

[0027] In some embodiments of the present application, based on the above technical solution, the static processing parameters include inherent parameters related to the processing equipment and / or processing materials.

[0028] In some embodiments of the present application, based on the above technical solution, the rule determination module is further configured to: simulate processing of the layout according to the static processing parameters and a pre-trained lithography prediction model to obtain a predicted lithography pattern; compare the difference features between the layout and the predicted lithography pattern to obtain a correction rule for correcting the layout.

[0029] In some embodiments of the present application, based on the above technical solution, the device further includes:

[0030] The optical correction module is configured to perform optical proximity effect correction on the layout to obtain a layout with enhanced resolution.

[0031] In some embodiments of the present application, based on the above technical solution, the adjustment module is further configured as: if the critical dimension of the circuit structure in the local layout is smaller than a preset size threshold, the critical dimension is adjusted according to the target correction amount; if the critical dimension of the circuit structure in the local layout is larger than the preset size threshold, the adjustment step of the critical dimension is skipped.

[0032] According to one aspect of an embodiment of the present application, a computer-readable medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the method for correcting a layout in the above technical solution is implemented.

[0033] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the executable instructions to implement a method for correcting a layout as in the above technical solution.

[0034] According to one aspect of an embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method for correcting a layout in the above technical solution is implemented.

[0035] In the technical solution provided in the embodiment of the present application, by obtaining the correction rules for correcting the layout, the local layouts corresponding to the various correction positions can be located on the layout, and then the target correction amount having a mapping relationship with the local layout is determined according to the correction rules, and the critical dimensions of the circuit structure in the local layout are adjusted according to the target correction amount. The embodiment of the present application utilizes the mapping relationship between the correction position and the correction amount, and can accurately correct the error of the lithography process to each spatial position on the layout, and can be applicable to product processing errors caused by various factors such as processing equipment, processing technology and processing materials, broadening the scope of application of error correction and improving the processing reliability and quality stability of the lithography process.

[0036] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 The exemplary system architecture block diagram applying the technical solution of the present application is schematically shown.

[0039] Figure 2 A flow chart of a method for correcting a layout in one embodiment of the present application is shown.

[0040] Figure 3 A flow chart of a method for locating a local layout in one embodiment of the present application is shown.

[0041] Figure 4 A schematic diagram of establishing a plane rectangular coordinate system on a photolithography mask in one embodiment of the present application is shown.

[0042] Figure 5 A schematic diagram of establishing a planar polar coordinate system on a wafer in one embodiment of the present application is shown.

[0043] Figure 6 A schematic diagram of a correction rule mapping table determined based on a plane rectangular coordinate system in an application scenario of an embodiment of the present application is shown.

[0044] Figure 7 A schematic diagram of a correction rule mapping table determined based on a plane polar coordinate system in an application scenario of an embodiment of the present application is shown.

[0045] Figure 8 A schematic diagram of a correction rule mapping table determined based on an OPC process in an application scenario of an embodiment of the present application is shown.

[0046] Fig. 9 The structural block diagram of the layout correction device provided in an embodiment of the present application is schematically shown.

[0047] Fig.10 The structure block diagram of a computer system suitable for implementing an electronic device of an embodiment of the present application is schematically shown. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0049] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0050] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories) or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0051] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0052] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0053] Figure 1 The exemplary system architecture block diagram applying the technical solution of the present application is schematically shown.

[0054] like Figure 1 As shown, the system architecture applying the technical solution of the present application may include a terminal device 110, a network 120 and a server 130. The terminal device 110 may include various computer electronic devices such as smart phones, tablet computers, laptops, and desktop computers. The server 130 may be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The network 120 may be a communication medium of various connection types that can provide a communication link between the terminal device 110 and the server 130, such as a wired communication link or a wireless communication link.

[0055] According to the implementation requirements, the system architecture in the embodiment of the present application can have any number of terminal devices, networks and servers. For example, the server 130 can be a server group composed of multiple server devices. In addition, the technical solution provided in the embodiment of the present application can be applied to the terminal device 110, can also be applied to the server 130, or can be implemented by the terminal device 110 and the server 130 together, and the present application does not make any special restrictions on this.

[0056] For example, the terminal device 110 can download and install control software for driving the execution of the lithography process from the server 130. The terminal device 110 sends control instructions to the lithography machine through the control software, triggering the execution of the corresponding lithography process on the lithography machine. At the same time, the terminal device 110 can obtain the operating parameters of the lithography machine in real time, and monitor and adjust the operating status of the lithography machine according to the operating parameters.

[0057] like Figure 1 As shown, the photolithography process involves multiple devices such as light source, mask, projection lens and substrate.

[0058] The light source provides ultraviolet light or other types of radiation used to expose the photosensitive resist (photoresist) in the photolithography process. The wavelength and intensity of the light source have a direct impact on the exposure effect of the photoresist.

[0059] A mask is a template with a specific pattern, usually made of quartz, chrome, etc. During the photolithography process, the pattern on the mask is transferred to the photoresist layer on the substrate by irradiation with a light source. The pattern on the mask determines the area on the substrate that will be exposed.

[0060] The projection lens is an important component in the lithography machine, which reduces the pattern on the mask and accurately projects it onto the photoresist layer on the substrate. The projection lens requires extremely high precision to ensure accurate transfer of the pattern.

[0061] The substrate is the target material of the photolithography process, usually a round silicon wafer. During the photolithography process, a layer of photoresist is coated on the surface of the silicon wafer, and then the desired circuit pattern is formed through the action of the mask and the light source. However, it is not limited to this. For example, the substrate can include a wafer for making chips, an insulating substrate (such as a glass substrate) for making display panels, a copper clad laminate for making printed circuit boards, and so on.

[0062] The basic process of photolithography is as follows: clean the surface of the silicon wafer to ensure that it is dust-free and pollution-free; evenly coat a layer of photoresist on the surface of the silicon wafer; place the mask above the silicon wafer to ensure that the pattern is aligned; illuminate the mask with a light source to cause a chemical reaction in the photoresist; develop the photoresist to remove the exposed or unexposed photoresist and leave the desired pattern; subsequent steps such as etching can be performed to transfer the pattern to the silicon wafer itself.

[0063] When performing the photolithography process, the lithography machine may have different types of processing errors due to the influence of various internal and external factors such as system equipment, operators, masks, wafer materials, etc. For example, there are many types of influencing factors as follows.

[0064] Characteristics of the equipment itself: including the stability of light source energy, interference from factors such as light interference, and light source position deviation caused by wear of some parts of the lithography machine. These factors may lead to errors in exposure parameters, thereby affecting the product's pattern accuracy, photoresist exposure uniformity, and exposure agent utilization efficiency.

[0065] Operational errors by operators: Inaccurate settings of parameters such as exposure time, light source wavelength, NA (numerical aperture), spot size, etc. by operators will also cause exposure parameter errors. These errors may affect the pattern accuracy of the product, the uniformity of photoresist exposure, and the utilization efficiency of the exposure agent.

[0066] Mask deformation or abnormal proportions: The mask may be deformed during the manufacturing or use process, resulting in abnormal proportions of the pattern on the mask, which will directly affect the alignment of the exposure pattern with the reference pattern.

[0067] Deformation of the wafer itself: The wafer may deform during the processing due to factors such as heat treatment and chemical treatment. This deformation will affect the alignment accuracy between the photolithography layers.

[0068] Distortion of the projection lens system of the lithography machine: If there is distortion in the projection lens system of the lithography machine, the exposure pattern will be distorted, resulting in alignment deviation.

[0069] Uneven movement of the wafer worktable: When the wafer moves inside the lithography machine, if the worktable moves unevenly, the position of the exposure pattern may deviate, resulting in overlay errors.

[0070] Mechanical errors caused by mechanical adjustment: In digital micromirror device (DMD) lithography equipment, mechanical errors caused by mechanical adjustment lead to splicing errors between exposure images, which in turn cause problems such as misalignment and overlap of exposure images.

[0071] These error sources are factors that need to be focused on controlling and correcting in the lithography process to ensure the accuracy of the lithography process and the quality of manufacturing.

[0072] The following is a detailed description of the technical solutions such as the layout correction method, layout correction device, computer-readable medium, electronic device, and computer program product provided by the present application in conjunction with specific implementation methods.

[0073] Figure 2A flowchart showing a method for modifying a layout in an embodiment of the present application is shown. The method can be performed by Figure 1 The terminal device or server shown in the figure can also execute the method together with the terminal device and the server. The present application embodiment takes the method for modifying the layout executed by the terminal device as an example. Figure 2 As shown, the layout correction method may include the following steps S210 to S230.

[0074] S210: Acquire a correction rule for correcting the layout, where the correction rule includes a mapping relationship between a correction position and a correction amount.

[0075] S220: Locating the local layouts corresponding to the respective correction positions on the layout.

[0076] S230: determining a target correction amount having a mapping relationship with the local layout according to the correction rule, and adjusting a critical dimension of the circuit structure in the local layout according to the target correction amount.

[0077] In the layout correction method provided in the embodiment of the present application, by obtaining the correction rules for correcting the layout, the local layouts corresponding to the various correction positions can be located on the layout, and then the target correction amount having a mapping relationship with the local layout is determined according to the correction rules, and the critical dimensions of the circuit structure in the local layout are adjusted according to the target correction amount. The embodiment of the present application utilizes the mapping relationship between the correction position and the correction amount, and can accurately correct the error of the lithography process to each spatial position on the layout, and can be applicable to product processing errors caused by various factors such as processing equipment, processing technology and processing materials, broadening the scope of application of error correction and improving the processing reliability and quality stability of the lithography process.

[0078] The following is a further explanation of how to implement each step in the layout correction method.

[0079] In step S210, a correction rule for correcting the layout is obtained, where the correction rule includes a mapping relationship between a correction position and a correction amount.

[0080] In one embodiment of the present application, a method for obtaining correction rules for correcting a layout may include: obtaining static processing parameters for processing a product according to the layout, the static processing parameters including parameters that remain fixed during the product processing process; and determining correction rules for correcting the layout according to the static processing parameters.

[0081] The embodiment of the present application can pre-collect various types of static processing parameters used in the photolithography process, and arrange and combine them to form a plurality of processing parameter sets, each processing parameter set can correspond to a correction rule, and the plurality of correction rules are stored in a database. When it is necessary to perform a product processing operation, the database can be queried according to the currently used static processing parameters to obtain the corresponding layout correction rules.

[0082] By obtaining static processing parameters, the embodiment of the present application can ensure the consistency and stability of key parameters during product processing, thereby improving processing accuracy and repeatability. At the same time, by determining the correction rules to accurately correct the layout, it can effectively compensate for errors that may occur during the processing, optimize chip performance, improve the yield rate, and ensure the high fidelity and reliability of chip design.

[0083] In one embodiment of the present application, the static processing parameters include intrinsic parameters related to processing equipment and / or processing materials.

[0084] For example, the processing equipment involved in the photolithography process may include the following.

[0085] Photolithography System: A photolithography system is the core equipment of the photolithography step, responsible for transferring the pattern on the mask to the photoresist on the wafer surface through light irradiation. According to the exposure method, photolithography systems include different types such as stepper photolithography systems and scanner photolithography systems.

[0086] Coater and Developer: This type of equipment is used to evenly apply photoresist on the surface of the wafer and perform subsequent soft baking and post-exposure development. The working performance and process quality of the coater and developer directly affect the yield of photolithography.

[0087] Metrology Equipment: used to measure the overlay error (between several photolithography times) and critical dimensions of circuit patterns after photolithography, and to scan and identify pattern defects, monitor process quality and feed back information to the photolithography computing system to improve the process.

[0088] Photolithography Calculation System: As the neural control center of the lithography process, the photolithography calculation system can perform high-precision simulation of the lithography process, materials, and environment based on given partial parameters, predict the results of lithography, and adjust the various setting parameters of the lithography equipment's illumination, focusing, and mask systems based on the measurement parameters fed back by the measurement equipment.

[0089] Photomask or Reticle: A mask is a graphic master used in the photolithography process. It forms a mask pattern structure on a transparent substrate with an opaque light-shielding film. The graphic information on the mask is transferred to the photoresist pattern through the exposure process.

[0090] Cleaning Equipment: Used to clean the surface of silicon wafers during the photolithography process to remove surface contaminants and process residues to ensure good adhesion of the photoresist.

[0091] Thermal Processing Equipment: including pre-bake and post-bake equipment, used to improve the properties of photoresist, enhance the adhesion of photoresist to the silicon wafer surface and the corrosion resistance in subsequent etching and ion implantation processes.

[0092] Etching Equipment: After photolithography is completed, etching equipment is used to selectively etch the substrate portion not protected by photoresist to achieve the construction of semiconductor devices on the substrate surface.

[0093] Ion Implantation Equipment: In some photolithography processes, ion implantation equipment is used to implant dopants into silicon wafers to change their electrical properties.

[0094] The static processing parameters associated with the above processing equipment may include one or more of the following.

[0095] Resolution: Resolution is the minimum feature size that can be achieved by a lithography machine, usually expressed in unit length. It determines the ability of the lithography machine to clearly project the smallest image and is one of the most important technical indicators of the lithography machine.

[0096] Accuracy: Accuracy refers to the accuracy that the lithography machine can achieve during the manufacturing process, including accurate control of the shape, size and position of the pattern. This is crucial to ensuring the performance of the chip and improving the stability and reliability of the chip.

[0097] Wavelength: The wavelength of the light source is one of the determining factors of the process capability of the lithography machine. Different wavelengths of the light source correspond to different types of lithography machines, and the wavelength of the light source affects the process capability of the lithography machine.

[0098] Numerical Aperture (NA): NA is an important indicator of optical lenses. When the wavelength of the light source remains unchanged, it directly determines the actual resolution of the lithography machine, which is equivalent to determining the highest process node that the lithography machine can achieve.

[0099] Exposure energy and focus: These two parameters are the most important parameters in the exposure process. If the energy and focus are not adjusted properly, the required resolution and size of the image cannot be obtained.

[0100] Soft baking temperature and time (Soft Baking): Soft baking is used to remove solvents in photoresist, enhance adhesion, and release stress in the photoresist film. Its temperature and time parameters have an important influence on the performance of photoresist.

[0101] Alignment technology: Alignment technology includes pre-alignment and alignment through alignment marks, which is crucial to ensure the alignment between the pattern and the existing pattern on the silicon wafer.

[0102] The processing materials involved in the photolithography process can include base materials and process materials. Base materials (silicon wafers, etc.) are wafer base materials. Among the process materials, the mask is used for the photolithography process base plate; the photoresist is used to transfer the pattern on the mask to the silicon wafer; the target material and the thin film process precursor are used for thin film deposition; the electronic special gas is used for oxidation / reduction / decontamination; the wet electronic chemicals are used for cleaning / etching; and the polishing material is used to achieve flattening.

[0103] Taking photoresist as an example, static processing parameters related to photoresist may include one or more of the following parameters.

[0104] Physical and chemical properties of photoresist: Each photoresist has different physical and chemical properties, which determine the performance of the photoresist on different brands and models of lithography machines.

[0105] Resolution of photoresist: refers to the minimum size of the pattern that can be reproduced by photoresist, usually measured by critical dimension (CD).

[0106] Contrast of photoresist: refers to the steepness of the transition from the exposed area to the non-exposed area of ​​the photoresist.

[0107] Sensitivity of photoresist: The minimum energy value (or minimum exposure) of a certain wavelength of light required to produce a good pattern on the photoresist, measured in millijoules per square centimeter (mJ / cm 2 ).

[0108] Viscosity of photoresist: a parameter that measures the flow characteristics of photoresist. The evaporation of solvent in photoresist will increase the viscosity.

[0109] Adhesion of photoresist: refers to the adhesion strength between photoresist and wafer.

[0110] Anti-etching of photoresist: The photoresist film must maintain its adhesion and protect the substrate surface during subsequent wet and dry etching.

[0111] Surface tension of photoresist: the attraction between molecules in a liquid that pulls surface molecules toward the main body of the liquid.

[0112] Exposure energy source of photoresist: Photoresist can be divided into types and resolutions for different exposure energy sources such as ultraviolet light wavelengths, electron beams, ion beams, X-rays, etc.

[0113] Types of photoresist: Photoresist can be divided into positive photoresist and negative photoresist. The part of the positive photoresist that is not exposed to light will be retained after development, while the part of the negative photoresist that is exposed to light will be retained after development.

[0114] In one embodiment of the present application, determining a correction rule for correcting a layout based on static processing parameters may further include: simulating processing of the layout based on the static processing parameters and a pre-trained lithography prediction model to obtain a lithography prediction pattern; comparing the difference features between the layout and the lithography prediction pattern to obtain a correction rule for correcting the layout.

[0115] The embodiment of the present application can collect historical data of product processing in advance to form training samples, and use the training samples to train the machine learning model, and after continuously optimizing the model parameters, obtain a lithography prediction model for simulating the processing of the layout. The machine learning model used to train the lithography prediction model may include, for example, a convolutional neural network, a long short-term memory network, or any other neural network model.

[0116] The embodiment of the present application simulates the processing of the layout by combining static processing parameters and a pre-trained lithography prediction model, and can predict the pattern effect after lithography in advance, and then accurately identify the key parameters and pattern details that need to be corrected by comparing the difference characteristics between the original layout and the predicted pattern. The embodiment of the present application not only improves the accuracy and efficiency of the lithography process, but also reduces the experimental cost and time, making the formulation of the correction rules more scientific and accurate, thereby significantly improving the yield and performance of chip manufacturing.

[0117] In step S220, local layouts corresponding to the respective correction positions are located on the layout.

[0118] Figure 3 FIG. 1 shows a flow chart of a method for locating a local layout in one embodiment of the present application. Figure 3 As shown, based on the above embodiment, step S220 may further include the following steps S221 to S224.

[0119] S221: Acquire a visualization space corresponding to the layout, where the visualization space is a two-dimensional closed space used to visualize the layout.

[0120] S222: Establish a plane coordinate system using a point in the concrete space as the coordinate origin.

[0121] S223: Locate local space regions corresponding to the respective correction positions in the plane coordinate system.

[0122] S224: Determine the circuit structure of the layout included in the local spatial area as the local layout corresponding to the correction position.

[0123] The embodiment of the present application effectively converts the abstract layout into an operable two-dimensional closed space by displaying the layout in a concrete space. By establishing a plane coordinate system with a point in the concrete space as the coordinate origin, the local space area corresponding to each correction position can be accurately located in the plane coordinate system. This process not only improves the positioning accuracy of the correction position, but also provides accurate layout data for subsequent correction processing by determining the circuit structure contained in the local space area as the local layout corresponding to the correction position. The embodiment of the present application greatly enhances the accuracy and efficiency of layout correction, making the formulation and application of correction rules more intuitive and accurate, thereby improving the overall quality and reliability of chip manufacturing.

[0124] In one embodiment of the present application, the visualization space includes a photolithography mask for projecting a layout onto a substrate, and the plane coordinate system includes a plane rectangular coordinate system established on the photolithography mask. The substrate is a base material used to carry photoresist and transfer circuit patterns in photolithography technology. For example, the substrate may include a wafer for making chips, an insulating substrate (such as a glass substrate) for making display panels, a copper-clad board for making printed circuit boards, and the like.

[0125] The photolithography mask (also known as a mask, photomask, photolithography mask, etc.) is a key graphic master used in the photolithography process in micro-nano processing technology. It forms a mask graphic structure on a transparent substrate with an opaque light-shielding film, and transfers these graphic information to the product substrate through the exposure process. The main components of the photolithography mask include a glass or quartz substrate and a chromium layer. Its graphic structure can be obtained through platemaking processing. Commonly used processing equipment includes laser direct writing lithography machines, electron beam lithography machines, etc.

[0126] Figure 4 A schematic diagram of establishing a plane rectangular coordinate system on a photolithography mask in one embodiment of the present application is shown.

[0127] like Figure 4 As shown in FIG. 1 , the plane rectangular coordinate system established on the photolithography mask consists of a horizontally placed horizontal axis (X axis) and a vertically placed vertical axis (Y axis), and the X axis and the Y axis are relative to the origin of the coordinate system O. Any position point P on the photolithography mask can be represented by an ordered number pair (x, y), where x represents the vertical distance from point P to the Y axis, and y represents the horizontal distance from point P to the X axis.

[0128] In one embodiment of the present application, the visualization space includes a wafer for forming a pattern corresponding to the layout, and the plane coordinate system includes a plane polar coordinate system established on the wafer.

[0129] Wafers are usually made of high-purity single-crystal silicon, and other semiconductor materials can also be used, such as gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), diamond, aluminum nitride (AlN), etc. Wafers are round and have a variety of standard diameters, such as 6 inches (150mm), 8 inches (200mm), 12 inches (300mm), etc. The larger the size, the more chips can be manufactured on a single wafer.

[0130] Figure 5 A schematic diagram of establishing a planar polar coordinate system on a wafer in one embodiment of the present application is shown.

[0131] like Figure 5As shown in the figure, the plane polar coordinate system established on the wafer is defined by an origin (also called the pole) and a ray (polar axis) starting from the origin to define the position of a point on the plane. Unlike the plane rectangular coordinate system (Cartesian coordinate system) which uses two mutually perpendicular coordinate axes, the polar coordinate system uses a distance value (radius) and an angle value to determine the position of a point. In the plane polar coordinate system, the horizontal rightward direction is usually taken as the positive direction of the polar axis; the straight-line distance from the pole to a point on the plane is represented by the radius r; the angle from the polar axis to the line segment connecting the pole and a point is usually represented by the angle θ, and the angle can be measured in degrees (°) or radians (rad). The position of any position point P on the wafer in the polar coordinate system is represented by an ordered pair (r,θ), where r is the radius and θ is the angle.

[0132] In direct-write lithography processes that do not require the use of a mask for optical projection, a planar coordinate system can be established directly on the substrate.

[0133] Direct-write photolithography machines use a laser beam with variable intensity to perform variable-dose exposure on the resist material on the substrate surface, and after development, the desired relief profile is formed on the resist surface. This equipment uses a computer to control a high-precision laser beam to directly scan and expose the photoresist, and directly transfer the design pattern to the mask. The laser emitted by the laser passes through the optical system to control the light intensity and light flux, and finally the objective lens converges the light spot onto the photoresist surface.

[0134] In one embodiment of the present application, local spatial regions corresponding to respective correction positions are located in a plane coordinate system, including: traversing the correction rules to obtain first positioning parameters and second positioning parameters of respective correction positions, the first positioning parameter being used to represent the position range of the correction position in the first spatial dimension, and the second positioning parameter being used to represent the position range of the correction position in the second spatial dimension; and locating the local spatial region consisting of the position range covered by the first positioning parameter and the second positioning parameter in the plane coordinate system.

[0135] In one embodiment of the present application, when the plane coordinate system is a plane rectangular coordinate system, the first positioning parameter is the position range on the horizontal axis of the plane rectangular coordinate system, and the second positioning parameter is the position range on the vertical axis of the plane rectangular coordinate system.

[0136] Figure 6 A schematic diagram of a correction rule mapping table determined based on a plane rectangular coordinate system in an application scenario of an embodiment of the present application is shown, wherein the first positioning parameter arranged horizontally is the position coordinate in the X-axis direction, and the second positioning parameter arranged vertically is the position coordinate in the Y-axis direction.

[0137] In one embodiment of the present application, when the plane coordinate system is a plane polar coordinate system, the first positioning parameter is the position range on the polar diameter of the plane polar coordinate system, and the second positioning parameter is the position range on the polar angle of the plane polar coordinate system.

[0138] Figure 7 A schematic diagram of a correction rule mapping table determined based on a plane polar coordinate system in an application scenario of an embodiment of the present application is shown, wherein the first positioning parameter arranged horizontally is the radius length in the polar direction, and the second positioning parameter arranged vertically is the rotation angle of the polar axis in the counterclockwise direction.

[0139] In step S230, a target correction amount having a mapping relationship with the local layout is determined according to the correction rule, and a critical dimension of the circuit structure in the local layout is adjusted according to the target correction amount.

[0140] In one embodiment of the present application, the critical dimension includes line width and / or spacing, where the line width is used to represent the radial width of a circuit structure, and the spacing is used to represent the distance between two adjacent circuit structures.

[0141] For example, in an application scenario, the embodiments of the present application can adjust the line width of the circuit structure alone, or can adjust the spacing of the circuit structure alone, or can adjust the line width and spacing of the circuit structure at the same time.

[0142] In one embodiment of the present application, adjusting the critical dimension of the circuit structure in the local layout according to the target correction amount may further include: if the critical dimension of the circuit structure in the local layout is smaller than a preset size threshold, adjusting the critical dimension according to the target correction amount; if the critical dimension of the circuit structure in the local layout is larger than the preset size threshold, skipping the step of adjusting the critical dimension.

[0143] The embodiment of the present application can control whether to perform a correction operation on the critical dimension of the circuit structure by setting a dimension threshold. When the critical dimension of the circuit structure is small, the step of adjusting the critical dimension according to the target correction amount can be performed to improve the process accuracy of product processing according to the layout. When the critical dimension of the circuit structure is large, the existence of the critical dimension error will not excessively affect the chip resolution, so the critical dimension adjustment step can be skipped, and the process efficiency of product processing can be improved on the basis of ensuring the processing accuracy.

[0144] In one embodiment of the present application, before obtaining the correction rule for correcting the layout, the layout may be corrected for optical proximity effect to obtain a layout with enhanced resolution.

[0145] The embodiment of the present application performs layout correction for other error types such as system error, edge-to-edge error and radius error on the basis of correcting the optical proximity effect of the layout, thereby making up for the deficiency of optical correction and improving product processing accuracy.

[0146] The process of Optical Proximity Correction (OPC) is a key step in semiconductor manufacturing to improve lithography accuracy. Its main purpose is to compensate for optical image distortion and ensure that the circuit on the silicon wafer is consistent with the original design. OPC is a RET (Resolution Enhancement Technology) technology that meets the requirements by adjusting the topological structure of the light-transmitting area pattern on the mask, commonly known as retargeting; or adding a small sub-resolution assist feature (SRAF), also known as assist feature (AF), to the mask, so that the imaging result after lithography is close to the circuit design pattern and the line width after etching is equal to the design line width.

[0147] The first step in the OPC workflow is to obtain design data that represents the desired pattern to be etched on the wafer. The design data is processed by OPC software, which can identify potential problems that may cause pattern deformation, such as optical distortion and proximity effect. OPC software applies correction algorithms to the design data to compensate for the predicted distortion. The corrected data is used to generate a photomask, which is a transparent plate on which the corrected pattern is etched. Model-based OPC has been widely used since the 90nm technology node. This approach uses optical models and photoresist chemical reaction models to calculate the pattern after exposure. The key is to establish accurate lithography models, including optical models and photoresist models. These models use approximate models and contain a series of parameters that need to be fitted with experimental data to ensure the accuracy of the model. OPC software corrects the design pattern for optical proximity effects based on pre-determined rules. The correction rules are summarized from a large amount of experimental data or generated by computational methods. Process Window OPC (PWOPC) is an extension of the OPC function. It can analyze the imaging behavior of the graphics corrected by OPC within the entire process window, including line width, line end point shrinkage, and the spacing between end points and lines. PWOPC is performed after the normal OPC is completed. It can find out which graphics have a too small depth of focus (DOF) and are prone to forming bad pixels when process parameters drift. It can also be used to predict alignment problems between graphics caused by process parameter offsets. Through these steps, the OPC process can significantly improve the accuracy of lithography and the quality of chip manufacturing.

[0148] Figure 8 A schematic diagram of a correction rule mapping table determined based on an OPC process in an application scenario of an embodiment of the present application is shown, wherein the first positioning parameter arranged horizontally may be the line width Width in the critical dimension of the circuit structure, and the second positioning parameter arranged vertically may be the spacing space in the critical dimension of the circuit structure.

[0149] Based on the introduction of the above embodiments and application scenarios, it can be known that the present application uses a coordinate system method to define correction values, which can accurately correct the key dimensions of the chip and simultaneously improve the edge placement error (Edge Placement error, EPE) of the graphics. The main benefits are: accurately correcting the line width and spacing at each position on the chip; solving the radius error (Radius error) or side to side error (Side to side error) caused by physical limitations in the chip manufacturing process; shortening the operation time (Run time) of the optical proximity correction (OPC); thereby increasing the chip manufacturing process window (Process window), which is beneficial to improving process stability and chip yield.

[0150] It should be noted that although the steps of the method in the present application are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0151] The following introduces an embodiment of the device of the present application, which can be used to execute the layout correction method in the above-mentioned embodiment of the present application. Fig. 9 The structure block diagram of the layout correction device provided in the embodiment of the present application is schematically shown. Fig. 9 As shown, the layout correction device 900 includes:

[0152] An acquisition module 910 is configured to acquire a correction rule for performing correction processing on the layout, wherein the correction rule includes a mapping relationship between a correction position and a correction amount;

[0153] A positioning module 920 is configured to respectively position the local layout corresponding to each of the correction positions on the layout;

[0154] The adjustment module 930 is configured to determine a target correction amount having a mapping relationship with the local layout according to the correction rule, and adjust a critical dimension of the circuit structure in the local layout according to the target correction amount.

[0155] In some embodiments of the present application, based on the above technical solution, the critical dimension includes line width and / or spacing, the line width is used to represent the radial width of a circuit structure, and the spacing is used to represent the distance between two adjacent circuit structures.

[0156] In some embodiments of the present application, based on the above technical solution, the positioning module 920 further includes:

[0157] A space acquisition module is configured to acquire a concrete space corresponding to the layout, wherein the concrete space is a two-dimensional closed space for concretely displaying the layout;

[0158] A coordinate system establishment module is configured to establish a plane coordinate system using a point in the concrete space as a coordinate origin;

[0159] A region positioning module, configured to respectively locate the local space regions corresponding to each of the correction positions in the plane coordinate system;

[0160] The layout determination module is configured to determine the circuit structure of the layout contained in the local space area as the local layout corresponding to the correction position.

[0161] In some embodiments of the present application, based on the above technical solution, the visualization space includes a photolithography mask for projecting the layout onto a substrate, and the plane coordinate system includes a plane rectangular coordinate system established on the photolithography mask.

[0162] In some embodiments of the present application, based on the above technical solution, the visualization space includes a wafer for forming a pattern corresponding to the layout, and the plane coordinate system includes a plane polar coordinate system established on the wafer, and the coordinate origin of the plane polar coordinate system is the center of the wafer.

[0163] In some embodiments of the present application, based on the above technical solution, the area positioning module includes:

[0164] a rule traversal module, configured to traverse the correction rules to obtain a first positioning parameter and a second positioning parameter of each correction position, wherein the first positioning parameter is used to represent a position range of the correction position in a first spatial dimension, and the second positioning parameter is used to represent a position range of the correction position in a second spatial dimension;

[0165] The parameter positioning module is configured to locate a local space area consisting of a position range covered by the first positioning parameter and the second positioning parameter in the plane coordinate system.

[0166] In some embodiments of the present application, based on the above technical solution, when the plane coordinate system is a plane rectangular coordinate system, the first positioning parameter is the position range on the horizontal axis of the plane rectangular coordinate system, and the second positioning parameter is the position range on the vertical axis of the plane rectangular coordinate system;

[0167] When the plane coordinate system is a plane polar coordinate system, the first positioning parameter is a position range on a polar diameter of the plane polar coordinate system, and the second positioning parameter is a position range on a polar angle of the plane polar coordinate system.

[0168] In some embodiments of the present application, based on the above technical solution, the acquisition module 910 further includes:

[0169] A parameter acquisition module, configured to acquire static processing parameters for processing a product according to the layout, wherein the static processing parameters include parameters that remain fixed during the product processing;

[0170] The rule determination module is configured to determine a correction rule for correcting the layout according to the static processing parameters.

[0171] In some embodiments of the present application, based on the above technical solution, the static processing parameters include inherent parameters related to the processing equipment and / or processing materials.

[0172] In some embodiments of the present application, based on the above technical solution, the rule determination module is further configured to: simulate processing of the layout according to the static processing parameters and a pre-trained lithography prediction model to obtain a predicted lithography pattern; compare the difference features between the layout and the predicted lithography pattern to obtain a correction rule for correcting the layout.

[0173] In some embodiments of the present application, based on the above technical solution, the layout correction device 900 further includes:

[0174] The optical correction module is configured to perform optical proximity effect correction on the layout to obtain a layout with enhanced resolution.

[0175] In some embodiments of the present application, based on the above technical solution, the adjustment module 930 is further configured as follows: if the critical dimension of the circuit structure in the local layout is smaller than a preset size threshold, the critical dimension is adjusted according to the target correction amount; if the critical dimension of the circuit structure in the local layout is larger than the preset size threshold, the adjustment step of the critical dimension is skipped.

[0176] The specific details of the layout correction device provided in each embodiment of the present application have been described in detail in the corresponding method embodiments and will not be repeated here.

[0177] Fig.10 The structure block diagram of a computer system for implementing an electronic device according to an embodiment of the present application is schematically shown.

[0178] It should be noted that Fig.10 The computer system 1000 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0179] like Fig.10As shown, the computer system 1000 includes a central processing unit 1001 (CPU), which can perform various appropriate actions and processes according to the program stored in the read-only memory 1002 (ROM) or the program loaded from the storage part 1008 to the random access memory 1003 (RAM). Various programs and data required for system operation are also stored in the random access memory 1003. The central processing unit 1001, the read-only memory 1002 and the random access memory 1003 are connected to each other through a bus 1004. The input / output interface 1005 (Input / Output interface, i.e., I / O interface) is also connected to the bus 1004.

[0180] The following components are connected to the input / output interface 1005: an input section 1006 including a keyboard, a mouse, etc.; an output section 1007 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN card, a modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the input / output interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage section 1008 as needed.

[0181] In particular, according to an embodiment of the present application, the process described in each method flow chart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer readable medium, and the computer program contains a program code for executing the method shown in the flow chart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 1009, and / or installed from the removable medium 1011. When the computer program is executed by the central processor 1001, various functions defined in the system of the present application are executed.

[0182] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by an instruction execution system, device or device or used in combination with it. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer readable signal media may also be any computer readable medium other than computer readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0183] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0184] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0185] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the implementation methods of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the implementation methods of the present application.

[0186] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary technical means in the art that are not disclosed in the present application.

[0187] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for correcting a layout, characterized in that: include: Acquire a correction rule for correcting the layout, wherein the correction rule includes a mapping relationship between a correction position and a correction amount; Positioning the local layouts corresponding to the respective correction positions on the layout; A target correction amount having a mapping relationship with the local layout is determined according to the correction rule, and a critical dimension of the circuit structure in the local layout is adjusted according to the target correction amount.

2. The method for correcting a layout according to claim 1, characterized in that: The critical dimensions include line width and / or spacing, wherein the line width is used to represent a radial width of a circuit structure, and the spacing is used to represent a distance between two adjacent circuit structures.

3. The method for correcting a layout according to claim 1, characterized in that: Positioning the local layouts corresponding to the respective correction positions on the layout respectively includes: Acquire a concrete space corresponding to the layout, wherein the concrete space is a two-dimensional closed space used to concretely display the layout; Taking a point in the concrete space as the coordinate origin, a plane coordinate system is established; Locating local space regions corresponding to each of the correction positions in the plane coordinate system respectively; The circuit structure of the layout contained in the local spatial area is determined as the local layout corresponding to the correction position.

4. The method for correcting a layout according to claim 3, characterized in that: The visualization space includes a photolithography mask for projecting the layout onto a substrate, and the plane coordinate system includes a plane rectangular coordinate system established on the photolithography mask.

5. The method for correcting a layout according to claim 3, characterized in that: The visualization space includes a wafer for forming a pattern corresponding to the layout, the plane coordinate system includes a plane polar coordinate system established on the wafer, and the coordinate origin is the center of the wafer.

6. The method for correcting a layout according to claim 3, characterized in that: Positioning local space regions corresponding to the respective correction positions in the plane coordinate system respectively includes: Traversing the correction rules, respectively obtaining a first positioning parameter and a second positioning parameter of each of the correction positions, wherein the first positioning parameter is used to represent a position range of the correction position in a first spatial dimension, and the second positioning parameter is used to represent a position range of the correction position in a second spatial dimension; A local space area consisting of a position range covered by the first positioning parameter and the second positioning parameter is located in the plane coordinate system.

7. The method for correcting a layout according to claim 6, characterized in that: The plane coordinate system is a plane rectangular coordinate system, the first positioning parameter is a position range on a horizontal axis of the plane rectangular coordinate system, and the second positioning parameter is a position range on a vertical axis of the plane rectangular coordinate system.

8. The method for correcting a layout according to claim 6, characterized in that: The plane coordinate system is a plane polar coordinate system, the first positioning parameter is a position range on a polar diameter of the plane polar coordinate system, and the second positioning parameter is a position range on a polar angle of the plane polar coordinate system.

9. The method for correcting a layout according to any one of claims 1 to 8, characterized in that: Get the correction rules used to correct the layout, including: Acquiring static processing parameters for processing a product according to the layout, wherein the static processing parameters include parameters that remain fixed during the product processing; A correction rule for correcting the layout is determined according to the static processing parameters.

10. The method for correcting a layout according to claim 9, characterized in that: The static processing parameters include intrinsic parameters related to processing equipment and / or processing materials.

11. The method for correcting a layout according to claim 9, characterized in that: Determining a correction rule for correcting the layout according to the static processing parameters includes: Performing simulation processing on the layout according to the static processing parameters and a pre-trained lithography prediction model to obtain a lithography prediction pattern; The difference features between the layout and the photolithography prediction pattern are compared to obtain a correction rule for correcting the layout.

12. The method for correcting a layout according to any one of claims 1 to 8, characterized in that: Before obtaining the correction rule for correcting the layout, the method further includes: The optical proximity effect is corrected for the layout to obtain a layout with enhanced resolution.

13. The method for correcting a layout according to any one of claims 1 to 8, characterized in that: Adjusting the critical dimension of the circuit structure in the local layout according to the target correction amount includes: If the critical dimension of the circuit structure in the local layout is smaller than a preset dimension threshold, adjusting the critical dimension according to the target correction amount; If the critical dimension of the circuit structure in the local layout is greater than a preset dimension threshold, the step of adjusting the critical dimension is skipped.

14. A layout correction device, characterized in that: include: An acquisition module is configured to acquire a correction rule for performing correction processing on the layout, wherein the correction rule includes a mapping relationship between a correction position and a correction amount; A positioning module, configured to respectively position the local layouts corresponding to the respective correction positions on the layout; The adjustment module is configured to determine a target correction amount having a mapping relationship with the local layout according to the correction rule, and adjust a critical dimension of the circuit structure in the local layout according to the target correction amount.

15. A computer readable medium, characterized in that The computer-readable medium stores a computer program, and when the computer program is executed by a processor, the method for correcting a layout described in any one of claims 1 to 13 is implemented.

16. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the executable instructions to implement the layout correction method as described in any one of claims 1 to 13.

17. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the layout correction method according to any one of claims 1 to 13 is implemented.

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