An ultra-low noise LDO with programmable current limit and fast start-up

Abstract

The present application relates to the technical field of power management in integrated circuits, and particularly relates to an ultra-low noise LDO with programmable current limit and fast start-up, comprising a reference current generating circuit, an RC filter, a first negative feedback loop, a control resistor, a comparison control circuit, a programmable current limit circuit, a sampling tube MP0 and a first switch current source; the first negative feedback loop comprises an error amplifier, a buffer stage and a power tube MP1; before the LDO starts up, the current limit is programmed; after the current limit programming is completed, the LDO starts up, a fast start-up control signal of the LDO is generated through the programmable current limit circuit, an additional charging path is provided for the RC filter circuit through the constant current source, and the fast start-up of the ultra-low noise LDO is realized; when the output voltage of the LDO approaches the preset value, the fast start-up circuit is closed; the LDO current limit of the present application is adjustable, the protection capability of the subsequent stage is improved, and the reliability of the overall system is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of power management in integrated circuits, and in particular to an ultra-low noise LDO with programmable current limit and fast startup. Background Art

[0002] Low-dropout linear regulators (LDOs) are a crucial component in power management technology. Due to their small size, ease of use, and lack of output voltage ripple, LDOs are widely used in battery-powered portable electronic systems and communications equipment. As signal frequencies processed by portable electronic devices continue to increase and power supply voltages continue to decrease, power supply noise is increasingly impacting the performance of these devices. This is particularly true for noise-sensitive RF and analog components, such as phase-locked loops (PLLs) and high-precision A / D converters. Ultra-low-noise LDOs offer exceptionally low output noise. For example, some can achieve output noise levels as low as a few microvolts (μV) or even as low as nanovolts (nV). Therefore, ultra-low-noise LDOs have become a key area of ​​LDO technology development.

[0003] An LDO consists of a bandgap reference, an error amplifier, a power transistor, and feedback resistors. The LDO output voltage noise includes the bandgap reference voltage noise, the error amplifier equivalent input voltage noise, and the feedback resistor thermal noise. To reduce the LDO output voltage noise, a low-pass filter is typically formed using external capacitors and on-chip resistors to achieve lower reference voltage noise. A unity-gain negative feedback structure is also employed to eliminate the impact of feedback resistor thermal noise on the output voltage noise and suppress the amplification of the reference voltage noise and the error amplifier equivalent input voltage noise. In existing technologies, large on-chip resistors and large off-chip capacitors prolong the reference voltage settling time, leading to a conflict between the LDO startup time and output voltage noise. Furthermore, existing high-current LDOs typically have a high current limit that cannot be adjusted. This excessively high current limit reduces the LDO's ability to protect subsequent stages in applications with low output load currents, impacting overall system reliability. Summary of the Invention

[0004] An object of the present invention is to provide an ultra-low-noise LDO with programmable current limit and fast startup. Before the LDO starts, the current limit is programmed by comparing the voltage value of an output voltage feedback port with a reference voltage. The control signal used for current limit programming is then locked, and the current limit is configured. The current limit is determined by the resistance values ​​of two resistors connected to the output voltage feedback port. By selecting different resistor values, the current limit can be flexibly configured according to the usage scenario. After the current limit programming is completed, the LDO starts to start, and an LDO fast startup control signal is generated by reusing one of the current limit configuration comparators. A constant current source is used to provide an additional charging path for an RC filter circuit, thereby achieving fast startup of the ultra-low-noise LDO. When the LDO output voltage approaches a preset value, the fast startup circuit is turned off. The fast startup time is determined by the ratio of the two resistors connected to the output voltage feedback port. The resistor ratio can be reasonably selected according to the preset output voltage value to achieve fast startup of the ultra-low-noise LDO.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] In a first aspect of the present invention, the present invention provides an ultra-low noise LDO with programmable current limit and fast startup, the LDO comprising:

[0007] A reference current generating circuit, an RC filter, a first negative feedback loop, a control resistor, a comparison control circuit, a programmable current limit circuit, a sampling tube MP0, and a first switching current source; the first negative feedback loop includes an error amplifier, a buffer stage, and a power tube MP1; wherein:

[0008] The output of the reference current generating circuit is connected to the inverting input of the error amplifier and the negative terminal of the first switching current source, and also serves as an external port VSET connected to the positive terminal of an external RC filter, the negative terminal of which is grounded. The non-inverting input of the error amplifier is connected to the drain of the power transistor MP1 and the input terminal VOUT of the programmable current limit circuit, and also serves as an external port VOUT connected to the positive terminal of an external control resistor, the control terminal of the control resistor being connected to the output voltage feedback port VO_FB, and the negative terminal of the control resistor being grounded. The output of the error amplifier is connected to the input of the buffer stage and the output of the programmable current limit circuit. The output of the buffer stage is connected to the gates of the sampling transistor MP0 and the power transistor MP1, the sources of the sampling transistors MP0 and MP1 being connected to the input voltage port VIN, the drain of the MP0 transistor being connected to the input terminal VCS of the programmable current limit circuit, the other two inputs of the programmable current limit circuit being connected to the output terminals VLIMIT1 and VLIMIT2 of the comparison control circuit, the input of the comparison control circuit being connected to the output voltage feedback port VO_FB, the other output terminal VS of the comparison control circuit being connected to the control terminal of the first switching current source, and the positive terminal of the first switching current source being connected to the input power supply port VIN.

[0009] Furthermore, the reference current generation circuit is composed of amplifiers AMP1 and AMP2, an NMOS transistor M0, a PMOS transistor M1, and resistors R0, R1, and R2. The non-inverting input of amplifier AMP1 is connected to an internal bandgap reference voltage VREF, the inverting input of amplifier AMP1 is connected to the positive terminal of R0 and the source of M0, the output of amplifier AMP1 is connected to the gate of M0, the negative terminal of resistor R0 is grounded, the drain of M0 is connected to the negative terminal of resistor R1 and the non-inverting input of amplifier AMP2, the inverting input of amplifier AMP2 is connected to the negative terminal of resistor R2 and the source of M1, the positive terminals of resistors R1 and R2 are connected to the input power supply VIN, the output of amplifier AMP2 is connected to the gate of M1, and the drain of M1 serves as the output port VSET.

[0010] Furthermore, the programmable current limit circuit includes a current limit configuration circuit, an LDO output current sampling circuit and a clamping circuit; the current limit configuration circuit changes the voltage of the first control point VA in response to the programmable current limit control signals VLIMIT1 and VLIMT2 output by the comparison control circuit; the LDO output current sampling circuit changes the voltage of the second control point VB in response to the sampling voltage VCS of the sampling tube MP0; the clamping circuit outputs a clamping voltage VEA in response to the first control point VA voltage and the second control point VB voltage to achieve overcurrent protection.

[0011] Furthermore, the programmable current limit circuit includes bias current sources IB1 to IB5, PMOS transistors M2 to M6, resistors R3 to R7, NMOS transistor M7, and amplifier AMP3. The positive terminals of bias current sources IB3, IB4, and IB5 are connected together and to the input voltage VIN. The negative terminal of IB3 is connected to the drain of transistor M2, the drain of transistor M3, and the positive terminal of resistor R3, and is also connected to the inverting input terminal of AMP3. The source of transistor M2 is connected to the negative terminal of IB4, and the gate is connected to the programmable current limit control signal VLIMIT2. The source of transistor M3 is connected to the negative terminal of IB5, and the gate is connected to the programmable current limit control signal VLIMIT1. The positive terminal of resistor R4 is connected to the current sampling signal VCS, and the negative terminal is connected to the source of transistor M4 and the source of transistor M6. The gate of transistor M4 is connected to the drain. The two poles are short-circuited, and the positive terminal of the bias current source IB1 and the gate of the M5 tube are connected. The source of the M5 tube is connected to the negative terminal of the resistor R5, and the drain is connected to the gate of the M6 ​​tube and the positive terminal of the bias current source IB2. The positive terminal of the resistor R5 is connected to the output voltage VOUT. The negative terminals of the bias current sources IB1 and IB2 are connected to the ground. The drain of the M6 ​​tube is connected to the positive terminal of the resistor R6 and the non-inverting input terminal of AMP3, and the negative terminal of R6 is grounded; the output of the amplifier AMP3 is connected to the gate of the M7 tube, the drain of M7 is connected to the negative terminal of the resistor R7, the positive terminal of R7 is connected to the input voltage VIN, and the source of the M7 tube is connected to the output terminal of the error amplifier.

[0012] Furthermore, the resistance of the resistor R6 is smaller than the resistance of the resistor R3.

[0013] Furthermore, the comparison control circuit is composed of comparators COMP1 and COMP2, two-input NAND gates NAND1, NAND2, and NAND3, RS flip-flops FF1 and FF2, a current source IS2, and a switch tube S2. COMP1 and COMP2 are connected to the non-inverting input terminals, and to the negative terminal of the second switching current source, and are also connected to the output voltage feedback port VO_FB. The control terminal of the second switching current source is connected to CK1, and the positive terminal of the second switching current source is connected to the input voltage VIN. The inverting input terminals of COMP1 and COMP2 are connected to the internal reference voltages VREF1 and VREF2, respectively. The output terminal of COMP1 is connected to the first input terminal of NAND1, and the output terminal of COMP2 is connected to the first input terminal of NAND2 and the first input terminal of NAND3. The second input terminal of NAND1 and the second input terminal of NAND2 are connected to the control signal CK2, and the second input terminal of NAND3 is connected to the control signal CK4. The output of NAND3 is the control signal VS of the first switching current source. The output of NAND1 is connected to the R terminal of the RS flip-flop FF1, and the output of NAND2 is connected to the R terminal of the RS flip-flop FF2. The S terminals of FF1 and FF2 are both connected to the control signal CK3. FF1 outputs the programmable current control signal VLIMIT2, and FF2 outputs the programmable current control signal VLIMIT1.

[0014] In a second aspect of the present invention, the present invention further provides an ultra-low noise LDO with programmable current limit and fast startup, specifically comprising:

[0015] When current limit programming begins, the LDO is not enabled, and the output voltage VOUT is pulled down to ground. The comparator control circuit generates a bias current. This bias current generates a voltage across the control resistor through the output voltage feedback terminal VO_FB. This voltage generates current limit control signals VLIMIT1 and VLIMT2 through the comparator control circuit input terminal. The programmable current limit circuit configures the LDO current limit based on VLIMIT1 and VLIMT2.

[0016] After current limit programming is complete, the LDO starts up. The output current ISET of the reference current generation circuit generates a reference voltage at the VSET terminal. The voltage at the VSET terminal rises, and the LDO output voltage VOUT follows suit. Simultaneously, VOUT is divided down by a control resistor and output as a feedback voltage to the voltage feedback terminal VO_FB. The feedback voltage is compared with the reference voltage by the programmable current limit circuit. During the output voltage settling process, if the feedback voltage VO_FB is less than the reference voltage, the comparator output VS controls the first switching current source. The first switching current source and the output current ISET of the reference current generation circuit simultaneously charge the VSET terminal. The voltage at the VSET terminal rises, and the LDO output voltage rapidly rises along with the VSET terminal voltage. When the output voltage VOUT approaches the preset value, the feedback voltage VO_FB exceeds the reference voltage, and the comparator control circuit output VS flips, disabling the first switching current source and ending the LDO's rapid settling process. The output current ISET of the reference current generation circuit continues to charge the RC filter until the voltage at the VSET terminal reaches the preset value. At this point, the LDO completes startup and the output voltage stabilizes at the preset value.

[0017] Beneficial effects of the present invention:

[0018] The ultra-low-noise LDO proposed in the present invention has the characteristics of fast startup and programmable current limit. Before the LDO starts, the current limit is programmed by comparing the output voltage feedback port voltage with a reference voltage. The current limit is determined by the resistance values ​​of two resistors connected to the output voltage feedback port. By selecting different resistor values, the current limit can be flexibly configured according to the usage scenario. During the LDO startup process, an LDO fast startup control signal is generated by multiplexing the current limit configuration comparator. The fast startup time is determined by the ratio of the two resistor values ​​connected to the output voltage feedback port. The resistor ratio can be reasonably selected according to the preset output voltage value to achieve fast startup of the ultra-low-noise LDO. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the structure of an ultra-low noise LDO with programmable current limit and fast startup according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of an ultra-low noise LDO structure with programmable current limit and fast startup according to a preferred embodiment of the present invention;

[0021] Figure 3 A schematic diagram of a reference current generating circuit according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of a programmable current limit circuit according to an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of a comparison control circuit according to an embodiment of the present invention;

[0024] Figure 6 This is a timing diagram of control signals of a comparison control circuit according to an embodiment of the present invention;

[0025] Figure 7 This is a simulation diagram of the programmable current limit of an ultra-low noise LDO according to an embodiment of the present invention;

[0026] Figure 8 This is a simulation diagram of the ultra-low noise LDO startup according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0028] It should be noted that since the embodiments of the present invention focus on signal current or voltage, the description herein assumes that the inputs and outputs of each module / unit / device are current or voltage. Those skilled in the art will appreciate that, in reality, the inputs and outputs of each module / unit / device are signals. To facilitate understanding of the technical means and inventive features of the present invention, the present invention is further described with reference to the accompanying drawings.

[0029] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, a first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0030] In an embodiment of the present invention, an ultra-low noise LDO with programmable current limit and fast startup is specifically implemented by the present invention, and its structural block diagram is as follows: Figure 1 As shown, the ultra-low noise LDO includes a reference current generating circuit, an RC filter, a first negative feedback loop, a control resistor, a comparison control circuit, a programmable current limit circuit, a sampling tube MP0, and a first switching current source; the first negative feedback loop includes an error amplifier, a buffer stage, and a power tube MP1; wherein:

[0031] The output of the reference current generating circuit is connected to the inverting input of the error amplifier and the negative terminal of the first switching current source, and also serves as an external port VSET connected to the positive terminal of an external RC filter, the negative terminal of which is grounded. The non-inverting input of the error amplifier is connected to the drain of the power transistor MP1 and the input terminal VOUT of the programmable current limit circuit, and also serves as an external port VOUT connected to the positive terminal of an external control resistor, the control terminal of the control resistor being connected to the output voltage feedback port VO_FB, and the negative terminal of the control resistor being grounded. The output of the error amplifier is connected to the input of the buffer stage and the output of the programmable current limit circuit. The output of the buffer stage is connected to the gates of the sampling transistor MP0 and the power transistor MP1, the sources of the sampling transistors MP0 and MP1 being connected to the input voltage port VIN, the drain of the MP0 transistor being connected to the input terminal VCS of the programmable current limit circuit, the other two inputs of the programmable current limit circuit being connected to the output terminals VLIMIT1 and VLIMIT2 of the comparison control circuit, the input of the comparison control circuit being connected to the output voltage feedback port VO_FB, the other output terminal VS of the comparison control circuit being connected to the control terminal of the first switching current source, and the positive terminal of the first switching current source being connected to the input power supply port VIN.

[0032] In a preferred embodiment of the present invention, an ultra-low noise LDO with programmable current limit and fast startup is specifically implemented in the present invention, and its structural block diagram is as follows: Figure 2 As shown, the RC filter includes a capacitor CS and a resistor RS; the control resistor includes a resistor RF1 and a resistor RF2; and the first switching current source includes a switch tube S1 and a current source IS1.

[0033] In some embodiments, the control resistor includes external resistors RF1 and RF2, the positive end of the resistor RF2 is connected to the external port VOUT, the negative end of the resistor RF2 is connected to the positive end of the resistor RF1 and serves as the control end of the control resistor connected to the output voltage feedback port VO_FB, and the negative end of the resistor RF1 is grounded.

[0034] In some embodiments of the present invention, the specific implementation process of an ultra-low noise LDO with programmable current limit and fast startup of the present invention can be as follows:

[0035] When current limit programming begins, the LDO is not enabled, and the output voltage VOUT is pulled down to ground. The comparator control circuit generates a bias current. This bias current generates a voltage across the control resistor through the output voltage feedback terminal VO_FB. This voltage generates current limit control signals VLIMIT1 and VLIMT2 through the comparator control circuit input terminal. The programmable current limit circuit configures the LDO current limit based on VLIMIT1 and VLIMT2.

[0036] After current limit programming is complete, the LDO starts up. The output current ISET of the reference current generation circuit generates a reference voltage at the VSET terminal. The voltage at the VSET terminal rises, and the LDO output voltage VOUT follows suit. Simultaneously, VOUT is divided down by a control resistor and output as a feedback voltage to the voltage feedback terminal VO_FB. The feedback voltage is compared with the reference voltage by the programmable current limit circuit. During the output voltage settling process, if the feedback voltage VO_FB is less than the reference voltage, the comparator output VS controls the first switching current source. The first switching current source and the output current ISET of the reference current generation circuit simultaneously charge the VSET terminal. The voltage at the VSET terminal rises, and the LDO output voltage follows the rise of the VSET terminal voltage, starting the LDO. When the output voltage VOUT approaches the preset value, the feedback voltage VO_FB is greater than the reference voltage, and the comparator control circuit output VS toggles, disabling the first switching current source and ending the LDO's fast settling process. The output current ISET of the reference current generation circuit continues to charge the capacitor CS of the RC filter until the voltage at the VSET terminal reaches the preset value. At this point, the LDO completes startup and the output voltage stabilizes at the preset value.

[0037] In the embodiment of the present invention, the preset value is ISET*RS, where RS is the resistance of the RC filter.

[0038] In a preferred embodiment of the present invention, a specific implementation process of an ultra-low noise LDO with programmable current limit and fast startup may also include the following:

[0039] The reference current generation circuit outputs a stable reference current, ISET. This current flows through an external RC filter formed by RS and CS, generating a low-noise reference voltage at VSET. The negative feedback loop formed by the error amplifier, buffer stage, and power transistor MP1 clamps the output voltage, VOUT, to the VSET voltage. Selecting the RS resistor value sets the LDO output voltage, while increasing the CS capacitor value reduces the LDO output voltage noise. Before the LDO starts up, the output voltage, VOUT, is pulled down to ground by an internal bleeder diode. The comparator control circuit generates a bias current. This current flows through the output voltage feedback terminal, VO_FB, generating a voltage across resistors (RF1 / / RF2). This voltage serves as the common input for two comparators with different trip thresholds in the comparator control circuit, generating current limit control signals, VLIMIT1 and VLIMT2. The programmable current limit circuit configures the LDO current limit based on VLIMIT1 and VLIMT2. The LDO current limit operates by mirroring the current in the power transistor through the sampling transistor MP0. In the event of an LDO overcurrent, the error amplifier output, VEA, is clamped to provide overcurrent protection. After current limit programming is complete, the LDO starts up. The output current ISET of the reference current generation circuit generates a voltage at the VSET terminal. Due to the large capacitance of capacitor CS, VSET rises slowly, and the LDO output voltage VOUT follows VSET. Simultaneously, VOUT is divided by resistors RF2 and RF1 and fed back to the output voltage feedback terminal VO_FB. The feedback voltage is compared with the reference voltage by the multiplexed comparator COMP2. During the output voltage settling process, if the feedback voltage VO_FB is less than the reference voltage, the comparator output VS turns on switch S1. Current source IS1 and the output current ISET of the reference current generation circuit simultaneously charge the VSET terminal, causing the voltage at VSET to rise rapidly. The LDO output voltage also rises rapidly with VSET. When the output voltage VOUT approaches the preset value ISET*RS, the feedback voltage VO_FB exceeds the reference voltage, the comparator output VS toggles, and switch S1 turns off, ending the LDO's rapid settling process. The output current ISET of the reference current generation circuit continues to charge capacitor CS until the voltage at VSET reaches the preset value ISET*RS. At this point, the LDO completes startup and the output voltage stabilizes at ISET*RS. By properly configuring resistors RF2 and RF1, the LDO can exit the fast startup phase when the output voltage approaches ISET*RS, thus achieving fast startup while preventing output voltage overshoot.

[0040] It can be understood that COMP1 and COMP2 are used to generate current limit configuration signals VLIMIT1 and VLIMT2 before the LDO is started. After the configuration is completed, the LDO fast startup is achieved by multiplexing COMP2.

[0041] In some embodiments of the present invention, a reference current generating circuit of the present invention is implemented as follows: Figure 3 As shown, the reference current generating circuit includes amplifiers AMP1, AMP2, NMOS transistor M0, PMOS transistor M1 and resistors R0, R1, and R2; the non-inverting input terminal of the amplifier AMP1 is connected to the internal bandgap reference voltage VREF, the inverting input terminal of the amplifier AMP1 is connected to the positive terminal of R0 and the source of M0, the output terminal of the amplifier AMP1 is connected to the gate of the M0 tube, the negative terminal of the resistor R0 is grounded, the drain of the M0 tube is connected to the negative terminal of the resistor R1 and the non-inverting input terminal of the amplifier AMP2, the inverting input terminal of the amplifier AMP2 is connected to the negative terminal of the resistor R2 and the source of the M1 tube, the positive terminals of the resistors R1 and R2 are connected to the input power supply VIN, the output terminal of the amplifier AMP2 is connected to the gate of the M1 tube, and the drain of the M1 tube serves as the output port VSET.

[0042] It should be noted that in this embodiment, the amplifier AMP1, the NMOS transistor M0 and the resistor R0 form a second negative feedback loop, which clamps the voltage at the inverting input terminal of the amplifier AMP1 to VREF, and generates a current flowing through the transistor M0 of:

[0043]

[0044] Resistors R1 and R2, amplifier AMP2, tube M1, and external resistors RS and CS connected to the VSET terminal form a negative feedback circuit, outputting a stable current ISET at the VSET terminal. Assuming that resistor R1 = R2, the output current ISET of the reference current generation circuit is:

[0045]

[0046] After the LDO stabilizes, the output voltage is:

[0047]

[0048] In some embodiments of the present invention, the programmable current limit circuit includes a current limit configuration circuit, an LDO output current sampling circuit, and a clamping circuit; the current limit configuration circuit changes the voltage of a first control point VA in response to programmable current limit control signals VLIMIT1 and VLIMT2 output by a comparison control circuit; the LDO output current sampling circuit changes the voltage of a second control point VB in response to a sampling voltage VCS of a sampling tube MP0; and the clamping circuit outputs a clamping voltage VEA in response to the voltages of the first control point VA and the second control point VB to implement overcurrent protection.

[0049] In a preferred embodiment of the present invention, a programmable current limit circuit of the present invention is implemented as follows: Figure 4As shown, the programmable current limit circuit includes bias current sources IB1~IB5, PMOS tubes M2~M6, resistors R3~R7, NMOS tube M7 and amplifier AMP3; the positive terminals of bias current sources IB3, IB4 and IB5 are connected together and connected to the input voltage VIN, the negative terminal of IB3 is connected to the drain of tube M2, the drain of tube M3 and the positive terminal of resistor R3, and is also connected to the inverting input terminal of AMP3, the source of tube M2 is connected to the negative terminal of IB4, and the gate is connected to the programmable current limit control signal VLIMIT2, the source of tube M3 is connected to the negative terminal of IB5, and the gate is connected to the programmable current limit control signal VLIMIT1; the positive terminal of resistor R4 is connected to the voltage VIN, and the negative terminal of resistor R4 is connected to the voltage VIN. The current sampling signal VCS is connected, and the negative end is connected to the source of the M4 tube and the source of the M6 ​​tube. The gate and drain of the M4 tube are short-circuited, and are connected to the positive end of the bias current source IB1 and the gate of the M5 tube. The source of the M5 tube is connected to the negative end of the resistor R5, and the drain is connected to the gate of the M6 ​​tube and the positive end of the bias current source IB2. The positive end of the resistor R5 is connected to the output voltage VOUT. The negative ends of the bias current sources IB1 and IB2 are connected to the ground. The drain of the M6 ​​tube is connected to the positive end of the resistor R6 and the non-inverting input end of AMP3, and the negative end of R6 is grounded; the output of the amplifier AMP3 is connected to the gate of the M7 tube, the drain of M7 is connected to the negative end of the resistor R7, the positive end of R7 is connected to the input voltage VIN, and the source of the M7 tube is connected to the error amplifier output VEA.

[0050] It should be noted that current sources IB3-IB5, PMOS transistors M2 and M3, and resistor R3 form the current limit configuration circuit. The programmable current limit control signals VLIMIT1 and VLIMT2 output by the comparison control circuit control the on / off of transistors M2 and M3, thereby changing the voltage at point VA. Resistors R4-R6, PMOS transistors M4-M6, and bias current sources IB1 and IB2 form the LDO output current sampling circuit. As the power transistor current increases, the sampling transistor current also gradually increases, and the sampling voltage VCS gradually increases, causing the gate voltage of transistor M6 to decrease, increasing the current in transistor M6 and the voltage at point VB to increase. When the LDO output current increases to the point where the voltage at point VB exceeds the voltage at point VA, the clamping circuit formed by amplifier AMP3, PMOS transistor M7, and resistor R7 clamps the error amplifier output VEA, preventing VEA from further decreasing and preventing the LDO output current from continuing to increase. If the width-to-length ratio of sampling transistor MP0 to power transistor MP1 is 1:k, when the LDO output current reaches the current limit, the voltage at point VB equals the voltage at point VA. Therefore,

[0051]

[0052] Where ILIMIT is the LDO current limit. If IB3 = 2IB4 = 2IB5 = 2I, and the programmable current limit control signals VLIMIT1 and VLIMT2 are both high, the LDO has a minimum overcurrent limit:

[0053]

[0054] When the programmable current limit control signal VLIMIT1 is low and VLIMT2 is high, the LDO overcurrent limit is:

[0055]

[0056] When the programmable current limit control signals VLIMIT1 and VLIMT2 are both low, the LDO has a maximum overcurrent limit:

[0057]

[0058] Since R3 is much larger than R6, the minimum current limit of LDO is about 50% of the maximum current limit, and the intermediate current limit is 75% of the maximum current limit. Figure 5 As shown, the comparison control circuit includes comparators COMP1 and COMP2, two-input NAND gates NAND1, NAND2, and NAND3, RS flip-flops FF1 and FF2, and a second switch current source; COMP1 and COMP2 are connected to the in-phase input terminals, and are connected to the negative terminal of the second switch current source, and are also connected to the output voltage feedback port VO_FB, the control terminal of the second switch current source is connected to CK1, the positive terminal of the second switch current source is connected to the input voltage VIN, the inverting input terminals of COMP1 and COMP2 are connected to the internal reference voltages VREF1 and VREF2 respectively, and the output terminal of COMP1 is connected to the first input terminal of NAND1. The COMP2 output is connected to the first input of NAND2 and the first input of NAND3. The second input of NAND1 and the second input of NAND2 are connected to the control signal CK2. The second input of NAND3 is connected to the control signal CK4. The NAND3 output is the control signal VS of the first switching current source. The NAND1 output is connected to the R terminal of the RS flip-flop FF1, and the NAND2 output is connected to the R terminal of the RS flip-flop FF2. The S terminals of FF1 and FF2 are both connected to the control signal CK3. FF1 outputs the programmable current control signal VLIMIT2, and FF2 outputs the programmable current control signal VLIMIT1. The second switching current source includes a switch tube S2 and a current source IS2.

[0059] In the preferred embodiment of the present invention, in order to realize multi-level programmable Figure 4 Add a branch similar to M2 and M3 in the programmable current limit circuit and use VLIMT3 to control it. Figure 5 The comparison control circuit shown is increased with a comparator COMP3, a two-input NAND gate NAND4, an RS flip-flop FF3, and an output VLIMT3 to achieve 4 levels of programmability; similarly, more levels of programmability can be achieved by continuing to increase.

[0060] In some embodiments of the present invention, the timing relationship of the control signals CK1-CK4 is as follows: Figure 6 Before the current limit programming starts, VREF1 and VREF2 have been established, and VREF1 is greater than VREF2, CK1 is high, the switch tube S2 is disconnected, the VO_FB voltage is 0, CK2 and CK3 are low, the R terminals of the RS flip-flops FF1 and FF2 are high, and the S terminals are low. The RS flip-flop is set, the outputs VLIMIT1 and VLIMT2 are both high, CK4 is low, and the output VS is high. After the current limit programming starts, CK3 becomes high, CK1 becomes low, and the switch tube S2 is turned on. The current source IS2 generates a voltage through the output voltage feedback port VO_FB, whose value is IS2*(RF1 / / RF2). This voltage is compared with two different reference voltages VREF1 and VREF2, and outputs VCOMP1 and VCOMP2. During the period when CK2 is high, the comparator output is transmitted to the R terminal of the RS trigger. When the comparator output is high, the voltage at the R terminal is low, the RS trigger output is reset, and the programmable current limit control signal becomes low. When the comparator output is low, the voltage at the R terminal is high, and the RS trigger is The trigger output remains held, and the programmable current limit control signal remains high. Then, CK2 goes low, and the RS trigger R terminal returns to a high state, locking the RS trigger state. Subsequently, CK1 goes high, turning off switch S2, completing the current limit programming. During the current limit programming process, CK4 goes high, and VS is controlled by VCOMP2. The LDO begins startup, and the voltage at VO_FB is divided by the LDO output voltage. During the LDO startup process, the voltage at VO_FB falls below VREF2, and the comparator output COMP2 goes low. Because CK4 is high at this time, VS is controlled by VCOMP2's high output, turning on switch S1. Current source IS1 charges the VSET terminal, causing the VSET voltage to rise rapidly. The LDO output voltage rises with the VSET voltage. When the output voltage approaches the preset value ISET*RS, the voltage at the output voltage feedback terminal VO_FB exceeds VREF2, causing the comparator COMP2 output to flip, turning VS low, and turning off switch S1, completing the LDO fast startup process. Before the current limit programming is completed, VS is controlled by CK4 output and is also high, and the switch tube S1 is turned on. However, since the LDO startup enable signal has not arrived at this time, the current source IS1 has not generated current. Therefore, during this process, IS1 has no effect on the port VSET, and the VSET terminal voltage is 0.

[0061] Figure 7The present invention is an ultra-low noise LDO programmable current limit simulation diagram. By changing the resistance values ​​of external resistors RF1 and RF2, three programmable levels are achieved. The current limits are 1.44A, 1.1A, and 0.77A respectively. The intermediate current limit is approximately 75% of the maximum current limit, and the minimum current limit is approximately 50% of the maximum current limit.

[0062] Figure 8 The present invention is an ultra-low noise LDO fast startup simulation diagram. By changing the ratio of the external resistors RF1 and RF2, the LDO fast setup time can be set. During the LDO fast setup process, the switch tube S1 controls the signal VS to a high level, and the current source IS1 charges the VSET terminal. The fast setup process ends when VS becomes a low level.

[0063] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for implementing an ultra-low noise LDO with programmable current limit and fast startup, characterized in that: include: When current limit programming begins, the LDO is not enabled, and the output voltage VOUT is pulled down to ground. The comparator control circuit generates a bias current. This bias current generates a voltage across the control resistor through the output voltage feedback terminal VO_FB. This voltage serves as the common input of two comparators COMP1 and COMP2 with different flip-thresholds in the comparator control circuit, generating current limit control signals VLIMIT1 and VLIMT2. The programmable current limit circuit configures the LDO current limit based on VLIMIT1 and VLIMT2. After current limit programming is completed, the LDO starts up. The output current ISET of the reference current generation circuit generates a reference voltage at the VSET terminal. The voltage at the VSET terminal rises, and the LDO output voltage VOUT follows suit. Simultaneously, VOUT is divided down by a control resistor and output as a feedback voltage to the voltage feedback terminal VO_FB. The feedback voltage is compared with the reference voltage by comparator COMP2 in the comparison control circuit. During the output voltage settling process, if the feedback voltage VO_FB is less than the reference voltage, the comparison control circuit output VS activates the first switching current source. The first switching current source and the output current ISET of the reference current generation circuit simultaneously charge the VSET terminal. The voltage at the VSET terminal rises, and the LDO output voltage rapidly rises along with the VSET voltage. When the output voltage VOUT approaches the preset value, the feedback voltage VO_FB exceeds the reference voltage, and the comparison control circuit output VS flips, disabling the first switching current source and ending the LDO's rapid settling process. The output current ISET of the reference current generation circuit continues to charge the RC filter until the voltage at the VSET terminal reaches the preset value. At this point, the LDO completes startup and the output voltage stabilizes at the preset value.

2. The method for implementing an ultra-low noise LDO with programmable current limit and fast startup according to claim 1, wherein: The preset value is ISET*RS, where RS is the resistance of the RC filter.

3. An ultra-low noise LDO with programmable current limit and fast startup, characterized in that: A method for implementing an ultra-low noise LDO with programmable current limit and fast startup as described in any one of claims 1-2, comprising a reference current generating circuit, an RC filter, a first negative feedback loop, a control resistor, a comparison control circuit, a programmable current limit circuit, a sampling tube MP0, and a first switching current source; the first negative feedback loop includes an error amplifier, a buffer stage, and a power tube MP1; wherein: The output of the reference current generating circuit is connected to the inverting input of the error amplifier and the negative terminal of the first switching current source, and also serves as an external port VSET connected to the positive terminal of an external RC filter, the negative terminal of which is grounded. The non-inverting input of the error amplifier is connected to the drain of the power transistor MP1 and the input terminal VOUT of the programmable current limit circuit, and also serves as an external port VOUT connected to the positive terminal of an external control resistor, the control terminal of the control resistor being connected to the output voltage feedback port VO_FB, and the negative terminal of the control resistor being grounded. The output of the error amplifier is connected to the input of the buffer stage and the output of the programmable current limit circuit. The output of the buffer stage is connected to the gates of the sampling transistor MP0 and the power transistor MP1, the sources of the sampling transistors MP0 and MP1 being connected to the input voltage port VIN, the drain of the MP0 transistor being connected to the input terminal VCS of the programmable current limit circuit, the other two inputs of the programmable current limit circuit being connected to the output terminals VLIMIT1 and VLIMIT2 of the comparison control circuit, the input of the comparison control circuit being connected to the output voltage feedback port VO_FB, the other output terminal VS of the comparison control circuit being connected to the control terminal of the first switching current source, and the positive terminal of the first switching current source being connected to the input power supply port VIN.

4. The ultra-low noise LDO with programmable current limit and fast startup according to claim 3, characterized in that: The reference current generating circuit includes amplifiers AMP1 and AMP2, an NMOS transistor M0, a PMOS transistor M1 and resistors R0, R1 and R2; the non-inverting input end of the amplifier AMP1 is connected to an internal bandgap reference voltage VREF, the inverting input end of the amplifier AMP1 is connected to the positive end of R0 and the source of M0, the output end of the amplifier AMP1 is connected to the gate of the transistor M0, the negative end of the resistor R0 is grounded, the drain of the transistor M0 is connected to the negative end of the resistor R1 and the non-inverting input end of the amplifier AMP2, the inverting input end of the amplifier AMP2 is connected to the negative end of the resistor R2 and the source of the transistor M1, the positive ends of the resistors R1 and R2 are connected to the input power supply VIN, the output end of the amplifier AMP2 is connected to the gate of the transistor M1, and the drain of the transistor M1 serves as the output port VSET.

5. The ultra-low noise LDO with programmable current limit and fast startup according to claim 3, characterized in that: The programmable current limit circuit includes a current limit configuration circuit, an LDO output current sampling circuit, and a clamping circuit. The current limit configuration circuit changes the voltage of the first control point VA in response to the programmable current limit control signals VLIMIT1 and VLIMT2 output by the comparison control circuit. The LDO output current sampling circuit changes the voltage of the second control point VB in response to the sampling voltage VCS of the sampling tube MP0. The clamping circuit outputs a clamping voltage VEA in response to the voltages of the first control point VA and the second control point VB to achieve overcurrent protection.

6. The ultra-low noise LDO with programmable current limit and fast startup according to claim 3, characterized in that: The programmable current limit circuit includes bias current sources IB1 to IB5, PMOS tubes M2 to M6, resistors R3 to R7, NMOS tube M7 and amplifier AMP3; the positive terminals of bias current sources IB3, IB4 and IB5 are connected together and connected to the input voltage VIN, the negative terminal of IB3 is connected to the drain of tube M2, the drain of tube M3 and the positive terminal of resistor R3, and is also connected to the inverting input terminal of AMP3, the source of tube M2 is connected to the negative terminal of IB4, and the gate is connected to the programmable current limit control signal VLIMIT2, the source of tube M3 is connected to the negative terminal of IB5, and the gate is connected to the programmable current limit control signal VLIMIT1; the positive terminal of resistor R4 is connected to the current The negative end of the sampling signal VCS is connected to the source of the M4 tube and the source of the M6 ​​tube. The gate and drain of the M4 tube are short-circuited, and are connected to the positive end of the bias current source IB1 and the gate of the M5 tube. The source of the M5 tube is connected to the negative end of the resistor R5, and the drain is connected to the gate of the M6 ​​tube and the positive end of the bias current source IB2. The positive end of the resistor R5 is connected to the output voltage VOUT. The negative ends of the bias current sources IB1 and IB2 are connected to the ground. The drain of the M6 ​​tube is connected to the positive end of the resistor R6 and the non-inverting input end of AMP3, and the negative end of R6 is grounded; the output of the amplifier AMP3 is connected to the gate of the M7 tube, the drain of M7 is connected to the negative end of the resistor R7, the positive end of R7 is connected to the input voltage VIN, and the source of the M7 tube is connected to the output end of the error amplifier.

7. The ultra-low noise LDO with programmable current limit and fast startup according to claim 6, characterized in that: The resistance of the resistor R6 is smaller than the resistance of the resistor R3.

8. The ultra-low noise LDO with programmable current limit and fast startup according to claim 3, characterized in that: The comparison control circuit includes comparators COMP1 and COMP2, two-input NAND gates NAND1, NAND2, and NAND3, RS triggers FF1 and FF2, and a second switch current source; COMP1 and COMP2 are connected to the in-phase input terminal, and are connected to the negative terminal of the second switch current source, and are also connected to the output voltage feedback port VO_FB, the control terminal of the second switch current source is connected to CK1, the positive terminal of the second switch current source is connected to the input voltage VIN, the inverting input terminals of COMP1 and COMP2 are connected to the internal reference voltages VREF1 and VREF2 respectively, and the output terminal of COMP1 is connected to the first input terminal of NAND1. The COMP2 output is connected to the first input terminal of NAND2 and the first input terminal of NAND3, the second input terminal of NAND1 and the second input terminal of NAND2 are connected to the control signal CK2, the second input terminal of NAND3 is connected to the control signal CK4, and the NAND3 output is the control signal VS of the first switching current source. The NAND1 output is connected to the R terminal of the RS trigger FF1, and the NAND2 output is connected to the R terminal of the RS trigger FF2. The S terminals of FF1 and FF2 are both connected to the control signal CK3. The FF1 output is the programmable current control signal VLIMIT2, and the FF2 output is the programmable current control signal VLIMIT1.

9. The ultra-low noise LDO with programmable current limit and fast startup according to claim 3, characterized in that: The control resistor includes external resistors RF1 and RF2, the positive end of the resistor RF2 is connected to the external port VOUT, the negative end of the resistor RF2 is connected to the positive end of the resistor RF1 and serves as the control end of the control resistor connected to the output voltage feedback port VO_FB, and the negative end of the resistor RF1 is grounded.

10. The ultra-low noise LDO with programmable current limit and fast startup according to claim 9, characterized in that: The resistance values ​​of the resistor RF1 and the resistor RF2 are adjustable.

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