Low dropout regulator with bypass mode and negative voltage generation circuit

Abstract

The invention relates to a low dropout regulator with a bypass mode and a negative voltage generation circuit. The low-dropout linear regulator comprises a bypass mode switching circuit, a voltage stabilizing circuit and a control circuit, wherein the bypass mode switching circuit is configured to switch working modes according to power supply voltage; the power tube is configured as an output transistor of the low-dropout voltage stabilizer and is used for outputting stable voltage; wherein the working mode comprises a normal working mode and a bypass mode; when the power supply voltage is lower than the power supply voltage threshold value, the bypass mode switching circuit switches the working mode of the low-dropout linear voltage regulator into the bypass mode, so that the loop of the low-dropout linear voltage regulator fails, and the output end of the low-dropout linear voltage regulator outputs the power supply voltage. According to the invention, when the power supply voltage is reduced and the LDO loop fails, the power supply voltage can be directly adopted for output.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a low voltage dropout linear regulator with a bypass mode and a negative voltage generating circuit. Background Art

[0002] A low dropout regulator (LDO) is a voltage reference generator, usually used to power other functional circuits or modules, such as oscillators, clock buffers, and charge pump modules in SOC systems.

[0003] However, since LDO is a step-down model, when the power supply voltage drops to a certain level, the LDO will no longer work properly due to voltage margin issues, which will result in failure to provide normal power to other circuits or modules. Summary of the invention

[0004] In view of this, embodiments of the present application provide a low voltage dropout linear regulator with a bypass mode and a negative voltage generating circuit to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a low voltage dropout linear regulator with a bypass mode, wherein the low voltage dropout linear regulator with a bypass mode comprises: a bypass mode switching circuit configured to switch the operating mode of the low voltage drop linear regulator according to a power supply voltage; and A power tube configured as an output transistor of the low voltage drop linear regulator for outputting a stable voltage; Wherein, the working mode includes a normal working mode and a bypass mode; When the power supply voltage is lower than the power supply voltage threshold, the bypass mode switching circuit switches the working mode of the low voltage dropout linear regulator to the bypass mode, so that the loop of the low voltage dropout linear regulator is invalid, and the output end of the low voltage dropout linear regulator outputs the power supply voltage; When the power supply voltage is higher than the power supply voltage threshold, the bypass mode switching circuit switches the operating mode of the low-voltage dropout linear regulator to the normal operating mode, so that the low-voltage dropout linear regulator works normally, and the output end of the low-voltage dropout linear regulator outputs the stable voltage output by the power tube.

[0006] In combination with the first aspect, in an optional implementation, The bypass mode switching circuit comprises: A switching control module, configured to generate corresponding start / stop signals and bypass signals according to the power supply voltage; A first switch module is configured to be turned on or off under the control of the bypass signal, so that the output end of the low voltage difference linear regulator switches to output the power supply voltage or the regulated voltage; and The second switch module is configured to be turned on or off under the control of the start-stop signal, so that the power tube is turned off to make the loop of the low-voltage difference linear regulator invalid, or the power tube is turned on to make the low-voltage difference linear regulator work normally.

[0007] In combination with the first aspect, in an optional implementation, The switching control module includes: A voltage dividing module, configured to divide the power supply voltage to obtain a divided voltage; a comparator configured to generate a comparison output signal of a first level when the divided voltage is lower than the second reference voltage; and to generate a comparison output signal of a second level when the divided voltage is higher than the second reference voltage; A first inverter configured to invert the comparison output signal to obtain the bypass signal; and The second inverter is configured to invert the bypass signal to obtain the start / stop signal.

[0008] In combination with the first aspect, in an optional implementation, The voltage dividing module includes a third resistor and a fourth resistor; The first end of the third resistor is configured to obtain the power supply voltage, and the second end of the third resistor is respectively connected to the first input end of the comparator and the first end of the fourth resistor and is configured to provide the divided voltage; A second end of the fourth resistor is connected to the ground.

[0009] In combination with the first aspect, in an optional implementation, The first switch module includes a second switch NMOS tube; The second switch module includes a first switch PMOS tube.

[0010] In combination with the first aspect, in an optional implementation, The comparator includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth PMOS tube, a fifth NMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh NMOS tube, a twelfth PMOS tube, a thirteenth NMOS tube, a fourteenth PMOS tube and a fifteenth NMOS tube; The gate of the first NMOS tube is configured as the first input terminal of the comparator, and the gate of the second NMOS tube is configured as the second input terminal of the comparator and obtains a second reference voltage; The source of the first NMOS tube and the source of the second NMOS tube are respectively connected to the drain of the third NMOS tube, the source of the third NMOS tube is grounded, and the gate of the third NMOS tube is configured to obtain a first low bias voltage; The drain of the first NMOS tube is respectively connected to the gate of the fourth PMOS tube, the drain of the sixth PMOS tube, the gate of the sixth PMOS tube, the gate of the seventh PMOS tube and the drain of the eighth PMOS tube; the drain of the second NMOS tube is respectively connected to the gate of the tenth PMOS tube, the drain of the ninth PMOS tube, the gate of the ninth PMOS tube, the gate of the eighth PMOS tube and the drain of the seventh PMOS tube; the source of the fourth PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the eighth PMOS tube, the source of the ninth PMOS tube and the source of the tenth PMOS tube are respectively configured to obtain the power supply voltage; The drain of the fourth PMOS tube is respectively connected to the drain of the fifth NMOS tube, the gate of the fifth NMOS tube and the gate of the eleventh NMOS tube; the drain of the tenth PMOS tube is respectively connected to the drain of the eleventh NMOS tube, the gate of the twelfth PMOS tube and the gate of the thirteenth NMOS tube; the drain of the twelfth PMOS tube is respectively connected to the drain of the thirteenth NMOS tube, the gate of the fourteenth PMOS tube and the gate of the fifteenth NMOS tube; the source of the twelfth PMOS tube and the source of the fourteenth PMOS tube are respectively configured to obtain the power supply voltage; the source of the fifth NMOS tube, the source of the eleventh NMOS tube, the source of the thirteenth NMOS tube and the source of the fifteenth NMOS tube are respectively connected to the ground terminal; The drain of the fourteenth PMOS tube and the drain of the fifteenth NMOS tube are connected and configured as the output end of the comparator.

[0011] In combination with the first aspect, in an optional implementation manner, the low voltage dropout linear regulator with bypass mode further includes an error amplifier and a feedback circuit; The first input terminal of the error amplifier is configured to obtain a first reference voltage, the second input terminal of the error amplifier is connected to the output terminal of the feedback circuit, and the output terminal of the error amplifier is connected to the gate terminal of the power tube; The input end of the feedback circuit is connected to the output end of the low voltage drop linear regulator.

[0012] In combination with the first aspect, in an optional implementation, The error amplifier includes a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube and a compensation capacitor; The gate of the sixteenth PMOS tube is configured as the first input terminal of the error amplifier EA, and the gate of the seventeenth PMOS tube is configured as the second input terminal of the error amplifier; The drain of the sixteenth PMOS tube is respectively connected to the drain of the nineteenth NMOS tube, the gate of the nineteenth NMOS tube and the gate of the twentieth NMOS tube, the drain of the seventeenth PMOS tube is respectively connected to the drain of the twenty-first NMOS tube, the gate of the twenty-first NMOS tube and the gate of the twenty-second NMOS tube; the drain of the twentieth NMOS tube is connected to the source of the twenty-third NMOS tube, the drain of the twenty-second NMOS tube is connected to the source of the twenty-fourth NMOS tube; the drain of the twenty-third NMOS tube is respectively connected to the drain of the twenty-fifth PMOS tube, the gate of the twenty-fifth PMOS tube and the gate of the twenty-sixth PMOS tube, the drain of the twenty-fourth NMOS tube is connected to the drain of the twenty-sixth PMOS tube and is configured as the output end of the error amplifier; The source of the sixteenth PMOS tube and the source of the seventeenth PMOS tube are respectively connected to the drain of the eighteenth PMOS tube; the source of the eighteenth PMOS tube, the source of the twenty-fifth PMOS tube and the source of the twenty-sixth PMOS tube are respectively configured to obtain power supply voltage connection; the source of the nineteenth NMOS tube, the source of the twentieth NMOS tube, the source of the twenty-first NMOS tube and the source of the twenty-second NMOS tube are respectively connected to the ground terminal; The gate of the twenty-third NMOS tube and the gate of the twenty-fourth NMOS tube are respectively configured to obtain the second low bias voltage, and the gate of the eighteenth PMOS tube M18 is configured to obtain the first high bias voltage; The first end of the compensation capacitor is connected to the drain of the twenty-second NMOS tube and the source of the twenty-fourth NMOS tube respectively, and the second end of the compensation capacitor is connected to the output end of the low voltage difference linear regulator; And / or, the feedback circuit includes a first resistor and a second resistor; The second input end of the error amplifier is connected to the second end of the first resistor and the first end of the second resistor respectively, the first end of the first resistor is connected to the output end of the low voltage difference linear regulator; the second end of the second resistor is connected to the ground.

[0013] In a second aspect, an embodiment of the present application provides a negative voltage generating circuit, wherein the negative voltage generating circuit comprises a charge pump and a low voltage dropout linear regulator with a bypass mode as described in the first aspect; The power supply end of the charge pump is configured to obtain the stable voltage output by the low voltage drop linear regulator in the normal working mode, or the power supply voltage output in the bypass mode; The charge pump is configured to output a stable negative voltage when the power supply terminal obtains the voltage.

[0014] In conjunction with the second aspect, in an optional implementation, The charge pump includes a thirty-sixth PMOS transistor, a thirty-seventh PMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a second capacitor, a third capacitor, a thirty-second PMOS transistor, a thirty-third PMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a fifth resistor and a fourth capacitor; The gate of the thirty-sixth PMOS transistor is configured to obtain the first signal, and the gate of the thirty-ninth NMOS transistor is configured to obtain the first inverted signal; the gate of the thirty-seventh PMOS transistor is configured to obtain the second signal, and the gate of the thirty-eighth NMOS transistor is configured to obtain the second inverted signal; The source of the thirty-sixth PMOS transistor and the source of the thirty-seventh PMOS transistor are respectively connected to the output end of the low voltage difference linear regulator, the source of the thirty-eighth NMOS transistor and the source of the thirty-ninth NMOS transistor are respectively connected to the ground end, the drain of the thirty-sixth PMOS transistor is respectively connected to the drain of the thirty-eighth NMOS transistor and the first end of the second capacitor, the drain of the thirty-seventh PMOS transistor is respectively connected to the drain of the thirty-ninth NMOS transistor and the first end of the third capacitor; the second end of the second capacitor is respectively connected to the drain of the thirty-second PMOS transistor, the drain of the thirty-fourth NMOS transistor, and the drain of the thirty-third PMOS transistor. The gate of the OS transistor is connected to the gate of the thirty-fifth NMOS transistor, and the second end of the third capacitor is respectively connected to the drain of the thirty-third PMOS transistor, the drain of the thirty-fifth NMOS transistor, the gate of the thirty-second PMOS transistor and the gate of the thirty-fourth NMOS transistor; the source of the thirty-second PMOS transistor and the source of the thirty-third PMOS transistor are respectively connected to the ground, the source of the thirty-fourth NMOS transistor and the source of the thirty-fifth NMOS transistor are respectively connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the first end of the fourth capacitor and is configured to output a negative voltage, and the second end of the fourth capacitor is connected to the ground.

[0015] The beneficial effects brought by the technical solution provided by the embodiment of the present application include: through the bypass mode switching circuit, the working mode of the low-dropout linear regulator (LDO) can be switched according to the power supply voltage, so that when the power supply voltage drops to a certain level, that is, below the power supply voltage threshold, the defect that the LDO can no longer work normally is overcome, and it can be switched from the normal working mode of the LDO to the bypass mode, and at this time, the output end of the LDO is controlled to directly output the power supply voltage. Then, the output end of the LDO can output a stable voltage when the LDO is working normally, and can output the power supply voltage when the LDO cannot work normally, so the output will not be turned off due to the failure of the LDO to work normally, that is, the power supply capacity will not be lost, and the power supply voltage can be used to continue to supply power to subsequent functional modules such as the negative pressure generation module, ensuring that the LDO is a relatively stable voltage reference source, so that the voltage output of the LDO is continuous and uninterrupted.

[0016] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of a principle block diagram of a power supply system consistent with at least one embodiment of the present application; Figure 2 A schematic diagram of a principle block diagram of a specific example of a negative pressure generating circuit; Figure 3 A schematic diagram of a principle block diagram of a specific example of a low-dropout linear regulator with a bypass mode in an embodiment of the present application; Figure 4 A circuit diagram of a specific example of a bypass mode switching circuit in an embodiment of the present application; Figure 5 A circuit diagram of a specific example of a comparator in an embodiment of the present application; Figure 6 A circuit diagram of a specific example of a low voltage dropout linear regulator with a bypass mode in an embodiment of the present application; Figure 7 A schematic diagram of a principle block diagram of a specific example of a negative pressure generating circuit in an embodiment of the present application; Figure 8 Schematic diagram of a circuit of a specific example of a charge pump in an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the technical solutions and beneficial effects of the present invention more clearly understandable, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0019] The embodiments of the present application are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, in a certain embodiment, the solution after removing some steps can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.

[0020] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0021] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0022] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0023] In the embodiments of the present application, "plurality" refers to two or more.

[0024] In some embodiments, the terms “at least one”, “one or more”, “a plurality of”, “multiple”, etc. can be used interchangeably.

[0025] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. For the statement of the description object, please refer to the description of the context in the embodiments, and no unnecessary restrictions should be constituted due to the use of prefixes. For example, the value of the description object is not limited by the ordinal number, and can be one or more. Taking "first device" as an example, the value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.

[0026] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.

[0027] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", "above", and "exceed" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0028] In some embodiments, high voltage and low voltage, or high level and low level, or high voltage and low voltage may be relative values ​​and are not limited to absolute values.

[0029] In some embodiments, the transistor may be a single transistor; or a plurality of transistors connected in series and / or in parallel, and have functional poles corresponding to the functional poles of a single transistor, and also have the same working state as the single transistor, such as on state and off state, etc. For example, a single transistor may be a MOSFET (metal oxide semiconductor field effect transistor, MOS for short), and its functional poles may include a gate G, a source S, a drain D, and a substrate B, then the plurality of transistors connected in series and / or in parallel have a gate G, a source S, a drain D, and a substrate B corresponding to the gate G, source S, drain D, and substrate B of a single transistor, and the working state of the MOS. The MOS may include a P-type MOS (PMOS for short) and an N-type MOS (NMOS for short).

[0030] In some embodiments, the LDO circuit may have different names, such as LDO, low voltage dropout voltage regulator circuit, low voltage dropout regulator, low voltage dropout linear voltage regulator circuit, etc., and the names are not limited here.

[0031] Figure 1 A schematic block diagram of a power supply system consistent with at least one embodiment of the present application is shown. As shown in the figure, the power supply system includes a reference voltage generator (voltage reference) and a functional module. The stable voltage vout_ref output by the reference voltage generator is used to supply power to one or more functional modules.

[0032] In an exemplary embodiment, the reference voltage generator may include a low dropout linear regulator (LDO). The LDO has the characteristics of high stability, fast dynamic response, and stable output, and can power the negative voltage generation module, etc., so as to ensure the stability of the negative voltage generated by the negative voltage generation module.

[0033] In an exemplary embodiment, Figure 2 A schematic block diagram of a specific example of a negative voltage generating circuit is shown. As shown in the figure, the negative voltage generating module 200 may include an oscillator, a clock buffer, and a charge pump. In order to ensure that the negative voltage generated by the negative voltage generating module 200 is always maintained at a suitable potential, a reference voltage generator (such as LDO) is first required to provide a relatively stable voltage reference source for the oscillator, the clock buffer, and the charge pump. Then, under the power supply of the stable voltage vout_ref output by the LDO, the clock buffer can generate two opposite clock signals (clk and clkb) according to the oscillation signal output by the oscillator to provide to the charge pump, and finally the charge pump outputs a stable negative voltage vneg.

[0034] However, if the power supply voltage is reduced, and the more advanced the process, the lower the power supply voltage can be used, and LDO is a step-down model, when the power supply voltage is low to a certain level, due to the voltage margin problem, LDO can no longer work normally, that is, LDO turns off the output, and there is no stable voltage vout_ref output, which affects the power supply to functional modules such as oscillators, clock buffers and charge pumps, causing them to fail to work normally.

[0035] To this end, an embodiment of the present application provides a low voltage dropout linear regulator with a bypass mode. Figure 3 A schematic diagram of a principle block diagram of a specific example of a low-voltage dropout linear regulator with a bypass mode in an embodiment of the present application is shown. As shown in the figure, the low-voltage dropout linear regulator with a bypass mode includes: A bypass mode switching circuit 100 is configured to switch the working mode of the low voltage dropout linear regulator according to a power supply voltage vdda; and The power tube MP is configured as an output transistor of the low voltage drop linear regulator to output a stable voltage vout_ref; Wherein, the working mode includes a normal working mode and a bypass mode; When the power supply voltage vdda is lower than the power supply voltage threshold, the bypass mode switching circuit 100 switches the working mode of the low voltage dropout linear regulator to the bypass mode, so that the loop of the low voltage dropout linear regulator is invalid, and the output terminal OUT of the low voltage dropout linear regulator outputs the power supply voltage vdda; When the power supply voltage vdda is higher than the power supply voltage threshold, the bypass mode switching circuit 100 switches the working mode of the low voltage dropout linear regulator to the normal working mode, so that the low voltage dropout linear regulator works normally, and the output terminal OUT of the low voltage dropout linear regulator outputs the stable voltage vout_ref output by the power tube MP.

[0036] In this way, the embodiment of the present application can switch the working mode of the low-dropout linear regulator (LDO) according to the power supply voltage through the bypass mode switching circuit, so that when the power supply voltage drops to a certain level, that is, below the power supply voltage threshold, the defect that the LDO can no longer work normally is overcome, and it can switch from the normal working mode of the LDO to the bypass mode, and at this time, the output end of the LDO is controlled to directly output the power supply voltage. Then, the output end of the LDO can output a stable voltage when the LDO is working normally, and can output the power supply voltage when the LDO cannot work normally, so the output will not be turned off due to the failure of the LDO to work normally, that is, the power supply capacity will not be lost, and the power supply voltage can be used to continue to supply power to subsequent functional modules such as the negative pressure generation module, ensuring that the LDO is a relatively stable voltage reference source, so that the LDO output is continuous and uninterrupted.

[0037] In the embodiment of the present application, the power tube MP may include at least one of the following: MOSFET; BJT (bipolar junction transistor, abbreviated as triode); IGBT (insulated gate bipolar transistor); GTO (gate turn-off thyristor); SCR (silicon controlled thyristor); MCT (MOS controlled thyristor); IGCT (integrated gate commutated thyristor); IEGT (electron injection enhanced gate transistor). The power tube MP may include a control terminal, a first signal terminal, and a second signal terminal. Its working principle is that under the control of the control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off to connect or block the signal transmission between the first signal terminal and the second signal terminal. For example, the first signal terminal may be a source terminal, and correspondingly, the second signal terminal may be a drain terminal; or conversely, the first signal terminal may be a drain terminal, and correspondingly, the second signal terminal may be a source terminal. Exemplarily, the power tube MP may be a PMOS tube.

[0038] The method of implementing the switching of the LDO working mode according to the power supply voltage vdda in the bypass mode switching circuit 100 can be set according to actual needs, for example, it can include at least one of the following: using a switch module to implement switching; using a circuit with signal processing capability to control switching, including a circuit with instruction reading and running capability such as a CPU (Central Processing Unit), a GPU (graphics processing unit), etc., a circuit that implements a certain function through a fixed or reconfigurable logical relationship of a hardware circuit such as an FPGA, or other circuits, to control the switching of the LDO loop to work normally or fail according to the power supply voltage obtained by the circuit; and so on.

[0039] The power supply voltage threshold may be set according to actual requirements, for example, may be determined according to a voltage margin.

[0040] The overall architecture of the low-dropout linear regulator with bypass mode provided in the embodiment of the present application mainly includes two parts: an LDO main loop structure mainly composed of an error amplifier EA, a power tube MP and a feedback circuit 300; and an output switching structure mainly composed of a bypass mode switching circuit 100.

[0041] Figure 4 A circuit diagram of a specific example of a bypass mode switching circuit in an embodiment of the present application is shown. As shown in the figure, in an optional implementation, the bypass mode switching circuit includes: A switching control module 101 is configured to generate a corresponding start / stop signal b and a bypass signal a according to the power supply voltage vdda; A first switch module 102 is configured to be turned on or off under the control of the bypass signal a, so that the output terminal OUT of the low voltage difference linear regulator switches to output the power supply voltage vdda or the regulated voltage vout_ref; and The second switch module 103 is configured to be turned on or off under the control of the start / stop signal b, so that the power tube MP is turned off to make the loop of the low-voltage difference linear regulator invalid, or the power tube MP is turned on to make the low-voltage difference linear regulator work normally.

[0042] In an exemplary embodiment, a comparator may be used to determine whether the power supply voltage vdda decreases. For example, the power supply voltage vdda may be directly compared with a power supply voltage threshold, or the power supply voltage vdda may be divided and then compared with a reference voltage, and so on.

[0043] The corresponding relationship between the bypass signal a and the start-stop signal b can be an in-phase relationship or an anti-phase relationship, which can be determined according to the effective levels of the control signals required by the first switch module 102 and the second switch module 103 respectively controlled by them. For example, if the effective levels of the control signals required by the first switch module 102 (such as an NMOS tube) and the second switch module 103 (such as a PMOS tube) are in opposite phases, that is, one is a high level and the other is a low level, then the bypass signal a and the start-stop signal b can be in an anti-phase relationship.

[0044] In an exemplary embodiment, when the first switch module 102 is turned on under the control of the bypass signal a, the output terminal OUT of the low voltage difference linear regulator can output the power supply voltage vdda. At this time, the second switch module 103 can be turned on under the control of the start-stop signal b, and the power tube MP can be controlled to be disconnected, and the loop of the low voltage difference linear regulator fails.

[0045] On the contrary, when the second switch module 103 is disconnected under the control of the start-stop signal b, the power tube MP can be controlled to be turned on, and the low-voltage difference linear regulator works normally. At this time, the first switch module 102 can be disconnected under the control of the bypass signal a, and the output terminal OUT of the low-voltage difference linear regulator can output a stable voltage vout_ref.

[0046] In this way, the embodiment of the present application switches the voltage value output by the LDO output end according to the power supply voltage control by switching the control module, the first switch module and the second switch module, respectively, under the control of the corresponding start-stop signal and the bypass signal on the first switch module and the second switch module, that is, controls the switching of the LDO working mode, and ensures that no matter whether the LDO can work normally due to the power supply voltage, the LDO output end can have a voltage output, so that the LDO output is continuous and uninterrupted.

[0047] In an optional implementation, the switching control module 101 includes: A voltage dividing module 1011 is configured to divide the power supply voltage vdda to obtain a divided voltage V1; The comparator COM is configured to generate a comparison output signal of a first level when the divided voltage V1 is lower than the second reference voltage Vref2; and to generate a comparison output signal of a second level when the divided voltage V1 is higher than the second reference voltage Vref2; A first inverter U1 is configured to invert the comparison output signal to obtain the bypass signal a; and The second inverter U2 is configured to invert the bypass signal a to obtain the start-stop signal b.

[0048] In the embodiment of the present application, the first level may be a high level or a low level, and correspondingly, the second level may be a low level or a high level.

[0049] In this way, in the embodiment of the present application, the voltage divider module is used to compare the divided voltage obtained after the power supply voltage is divided by the voltage divider module with the second reference voltage, and a bypass signal and a start-stop signal that are mutually inverted are obtained through two cascaded inverters, thereby improving the reliability and stability of the on-off control of the first switch module and the second switch module.

[0050] refer to Figure 4 , shows a specific example of the voltage divider module 1011, but is not limited to this.

[0051] In an optional implementation, the voltage dividing module 1011 includes a third resistor R3 and a fourth resistor R4; The first end of the third resistor R3 is configured to obtain the power supply voltage vdda, and the second end of the third resistor R3 is respectively connected to the first input end of the comparator COM and the first end of the fourth resistor R4 and is configured to provide the divided voltage V1; A second end of the fourth resistor R4 is connected to the ground end vsa.

[0052] In the embodiment of the present application, the third resistor R3 and the fourth resistor R4 can be a single resistor, or a plurality of resistors connected in series and / or in parallel, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.

[0053] In an optional implementation, the first switch module 102 includes a second switch NMOS tube Mc2; The second switch module 103 includes a first switch PMOS transistor Mc1.

[0054] In an exemplary embodiment, when the power supply is normal, the power supply voltage is divided by R3 and R4 and compared with the second reference voltage Vref2, and the comparator COM generates a high level, so the bypass signal a is a low level and the start-stop signal b is a high level, that is, Mc1 and Mc2 are turned off, and the LDO works normally and outputs stably.

[0055] When the power supply voltage decreases, the voltage after being divided by R3 and R4 also decreases, so the comparator COM generates a low level. Similarly, the bypass signal a is high, the start-stop signal b is low, Mc1 is turned on, and the gate end of MP is directly pulled to the power supply voltage. The LDO loop fails and no longer works. At this time, Mc2 is also turned on, and the LDO output end OUT directly outputs the power supply voltage, and then powers the subsequent negative pressure generation module.

[0056] The switch tubes used by the first switch module 102 and the second switch module 103 may also include at least one of the following: BJT (bipolar transistor), SCR (silicon controlled rectifier), GTO (gate turn-off thyristor), IGBT (insulated gate bipolar transistor), MCT (MOS controlled thyristor) and SIT (static induction transistor), etc.

[0057] Figure 5 A circuit diagram of a specific example of a comparator in an embodiment of the present application is shown, but the specific circuit structure of the comparator COM is not limited to Figure 5 As shown in the figure, in an optional implementation, the comparator COM includes a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth PMOS tube M4, a fifth NMOS tube M5, a sixth PMOS tube M6, a seventh PMOS tube M7, an eighth PMOS tube M8, a ninth PMOS tube M9, a tenth PMOS tube M10, an eleventh NMOS tube M11, a twelfth PMOS tube M12, a thirteenth NMOS tube M13, a fourteenth PMOS tube M14 and a fifteenth NMOS tube M15; The gate of the first NMOS transistor M1 is configured as the first input terminal of the comparator COM, and the gate of the second NMOS transistor M2 is configured as the second input terminal of the comparator COM and obtains the second reference voltage Vref2; The source of the first NMOS tube M1 and the source of the second NMOS tube M2 are respectively connected to the drain of the third NMOS tube M3, the source of the third NMOS tube M3 is grounded to the ground terminal vsa, and the gate of the third NMOS tube M3 is configured to obtain the first low bias voltage vbn1; The drain of the first NMOS tube M1 is respectively connected to the gate of the fourth PMOS tube M4, the drain of the sixth PMOS tube M6, the gate of the sixth PMOS tube M7, the gate of the seventh PMOS tube M7 and the drain of the eighth PMOS tube M8; the drain of the second NMOS tube M2 is respectively connected to the gate of the tenth PMOS tube M10, the drain of the ninth PMOS tube M9, the gate of the ninth PMOS tube M9, the gate of the eighth PMOS tube M8 and the drain of the seventh PMOS tube M7; the source of the fourth PMOS tube M4, the source of the sixth PMOS tube M6, the source of the seventh PMOS tube M7, the source of the eighth PMOS tube M8, the source of the ninth PMOS tube M9 and the source of the tenth PMOS tube M10 are respectively configured to obtain the power supply voltage vdda; The drain of the fourth PMOS tube M4 is respectively connected to the drain of the fifth NMOS tube M5, the gate of the fifth NMOS tube M5 and the gate of the eleventh NMOS tube M11; the drain of the tenth PMOS tube M10 is respectively connected to the drain of the eleventh NMOS tube M11, the gate of the twelfth PMOS tube M12 and the gate of the thirteenth NMOS tube M13; the drain of the twelfth PMOS tube M12 is respectively connected to the drain of the thirteenth NMOS tube M13, the gate of the fourteenth PMOS tube M14 and the gate of the fifteenth NMOS tube M15; the source of the twelfth PMOS tube M12 and the source of the fourteenth PMOS tube M14 are respectively configured to obtain the power supply voltage vdda; the source of the fifth NMOS tube M5, the source of the eleventh NMOS tube M11, the source of the thirteenth NMOS tube M13 and the source of the fifteenth NMOS tube M15 are respectively connected to the ground terminal vsa; The drain of the fourteenth PMOS tube M14 and the drain of the fifteenth NMOS tube M15 are connected and configured as the output terminal vout_com of the comparator COM.

[0058] In the embodiment of the present application, the first NMOS transistor M1 and the second NMOS transistor M2 serve as an input pair of transistors of the comparator COM, the gate of M1 can be configured to obtain the divided voltage V1, and the gate of M2 can be configured to obtain the second reference voltage Vref2.

[0059] In an exemplary embodiment, the divided voltage V1 can be input from the positive input terminal of the comparator COM, and the second reference voltage Vref2 can be input from the negative input terminal of the comparator COM. Then, when the divided voltage V1 is higher than the second reference voltage Vref2, the comparator COM can output a high-level comparison output signal, thereby obtaining a low-level bypass signal a and a high-level start-stop signal b. At this time, the first switch module 102 (such as an NMOS tube) can be controlled to be turned off and the second switch module 103 (such as a PMOS tube) can be controlled to be turned off, and the LDO is in a normal working mode.

[0060] When the divided voltage V1 is lower than the second reference voltage Vref2, the comparator COM can output a low-level comparison output signal, thereby obtaining a high-level bypass signal a and a low-level start-stop signal b. At this time, the first switch module 102 (such as an NMOS tube) and the second switch module 103 (such as a PMOS tube) can be controlled to be turned on respectively, and the LDO is in bypass mode.

[0061] In the embodiment of the present application, the twelfth PMOS tube M12 and the thirteenth NMOS tube M13, as well as the fourteenth PMOS tube M14 and the fifteenth NMOS tube M15 can respectively constitute inverters, so that the comparison output signal output by the comparator COM is localized, thereby improving the output stability.

[0062] refer to Figure 3 In an optional implementation, the low dropout linear regulator with bypass mode further includes an error amplifier EA and a feedback circuit 300; The first input terminal of the error amplifier EA is configured to obtain a first reference voltage Vref1, the second input terminal of the error amplifier EA is connected to the output terminal of the feedback circuit 300, and the output terminal of the error amplifier EA is connected to the gate terminal of the power tube MP; The input end of the feedback circuit 300 is connected to the output end of the low voltage drop linear regulator.

[0063] Figure 6 A circuit diagram of a specific example of a low-dropout linear regulator with a bypass mode in an embodiment of the present application is shown, wherein a specific circuit structure of a specific example of an error amplifier EA is shown, but it is not limited thereto. As shown in the figure, in an optional implementation, the error amplifier EA includes a sixteenth PMOS tube M16, a seventeenth PMOS tube M17, an eighteenth PMOS tube M18, a nineteenth NMOS tube M19, a twentieth NMOS tube M20, a twenty-first NMOS tube M21, a twenty-second NMOS tube M22, a twenty-third NMOS tube M23, a twenty-fourth NMOS tube M24, a twenty-fifth PMOS tube M25, a twenty-sixth PMOS tube M26 and a compensation capacitor Cc; The gate of the sixteenth PMOS tube M16 is configured as the first input terminal of the error amplifier EA, and the gate of the seventeenth PMOS tube M17 is configured as the second input terminal of the error amplifier EA; The drain of the sixteenth PMOS tube M16 is respectively connected to the drain of the nineteenth NMOS tube M19, the gate of the nineteenth NMOS tube M19 and the gate of the twentieth NMOS tube M20, the drain of the seventeenth PMOS tube M17 is respectively connected to the drain of the twenty-first NMOS tube M21, the gate of the twenty-first NMOS tube M21 and the gate of the twenty-second NMOS tube M22; the drain of the twentieth NMOS tube M20 is connected to the source of the twenty-third NMOS tube M23, the drain of the twenty-second NMOS tube M22 is connected to the source of the twenty-fourth NMOS tube M24; the drain of the twenty-third NMOS tube M23 is respectively connected to the drain of the twenty-fifth PMOS tube M25, the gate of the twenty-fifth PMOS tube M25 and the gate of the twenty-sixth PMOS tube M26, the drain of the twenty-fourth NMOS tube M24 is connected to the drain of the twenty-sixth PMOS tube M26 and is configured as the output end of the error amplifier EA; The source of the sixteenth PMOS tube M16 and the source of the seventeenth PMOS tube M17 are respectively connected to the drain of the eighteenth PMOS tube M18; the source of the eighteenth PMOS tube M18, the source of the twenty-fifth PMOS tube M25 and the source of the twenty-sixth PMOS tube M26 are respectively configured to obtain the power supply voltage vdda; the source of the nineteenth NMOS tube M19, the source of the twentieth NMOS tube M20, the source of the twenty-first NMOS tube M21 and the source of the twenty-second NMOS tube M22 are respectively connected to the ground terminal vsa; The gate of the twenty-third NMOS tube M23 and the gate of the twenty-fourth NMOS tube M24 are respectively configured to obtain the second low bias voltage vbn2, and the gate of the eighteenth PMOS tube M18 is configured to obtain the first high bias voltage vbp1; A first end of the compensation capacitor Cc is connected to the drain of the twenty-second NMOS transistor M22 and the source of the twenty-fourth NMOS transistor M24 respectively, and a second end of the compensation capacitor Cc is connected to the output end of the low voltage difference linear regulator.

[0064] In the embodiment of the present application, Miller compensation can be achieved through the compensation capacitor Cc, thereby improving output stability.

[0065] In an optional implementation, the feedback circuit 300 includes a first resistor R1 and a second resistor R2; The second input end of the error amplifier EA is respectively connected to the second end of the first resistor R1 and the first end of the second resistor R2. The first end of the first resistor R1 is connected to the output end of the low voltage difference linear regulator. The second end of the second resistor R2 is connected to the ground end vsa.

[0066] In the embodiment of the present application, the first input terminal of the error amplifier EA may be a negative input terminal, and the second input terminal of the error amplifier EA may be a positive input terminal. M16 and M17 may be input pairs of the error amplifier EA, the gate of M16 may obtain the first reference voltage Vref1, the gate of M17 may obtain the feedback signal vfb, and may be connected to the connection node between the first resistor R1 and the second resistor R2. The gate of the power tube MP may be connected to the drain of M24 and the drain of M26, respectively.

[0067] In the embodiment of the present application, the specific circuit structure of the feedback circuit 300 can be set according to actual needs and is not limited to Figure 6 The structure shown.

[0068] The first resistor R1, the second resistor R2, etc. may be a single resistor, or a plurality of resistors connected in series and / or in parallel, or may include a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.

[0069] The first low-bit bias signal vbn1, the second low-bit bias signal vbn2 and the first high-bit bias signal vbp1 can all be provided by external bias circuits, and these bias circuits can be controlled by logic control circuits. These are not the inventive points of the invention, and the bias circuits and logic control circuits are both prior art, and the present invention will not introduce them in detail.

[0070] The embodiment of the present application also provides a negative voltage generating circuit, Figure 7 A schematic diagram of a principle block diagram of a specific example of a negative voltage generating circuit in an embodiment of the present application is shown. As shown in the figure, the negative voltage generating circuit can be powered by the low voltage difference linear regulator with bypass mode in the above embodiment.

[0071] The negative voltage generating circuit includes a charge pump and a low voltage drop linear regulator with a bypass mode as described in the above embodiment; The power supply end of the charge pump is configured to obtain the stable voltage vout_ref output by the low voltage difference linear regulator in the normal working mode, or the power supply voltage vdda output in the bypass mode; The charge pump is configured to output a stable negative voltage vneg under the power supply of the voltage obtained at the power supply end.

[0072] In this way, the charge pump is powered by a low-dropout linear regulator with a bypass mode. Regardless of whether the LDO can work normally due to the reduction of the power supply voltage, the charge pump can provide a stable negative voltage, thereby improving the stability of the charge pump output.

[0073] Figure 8A circuit diagram of a specific example of a charge pump in an embodiment of the present application is shown, but the specific circuit structure of the charge pump is not limited thereto. As shown in the figure, in an optional implementation, the charge pump includes a thirty-sixth PMOS transistor M36, a thirty-seventh PMOS transistor M37, a thirty-eighth NMOS transistor M38, a thirty-ninth NMOS transistor M39, a second capacitor C2, a third capacitor C3, a thirty-second PMOS transistor M32, a thirty-third PMOS transistor M33, a thirty-fourth NMOS transistor M34, a thirty-fifth NMOS transistor M35, a fifth resistor R5, and a fourth capacitor C4; The gate of the thirty-sixth PMOS transistor M36 is configured to obtain the first signal n1, and the gate of the thirty-ninth NMOS transistor M39 is configured to obtain the first inverted signal n1b; the gate of the thirty-seventh PMOS transistor M37 is configured to obtain the second signal n2, and the gate of the thirty-eighth NMOS transistor M38 is configured to obtain the second inverted signal n2b; The source of the thirty-sixth PMOS transistor M36 and the source of the thirty-seventh PMOS transistor M37 are respectively connected to the output terminal OUT of the low voltage difference linear regulator, the source of the thirty-eighth NMOS transistor M38 and the source of the thirty-ninth NMOS transistor M39 are respectively connected to the ground terminal vsa, the drain of the thirty-sixth PMOS transistor M36 is respectively connected to the drain of the thirty-eighth NMOS transistor M38 and the first end of the second capacitor C2, the drain of the thirty-seventh PMOS transistor M37 is respectively connected to the drain of the thirty-ninth NMOS transistor M39 and the first end of the third capacitor C3; the second end of the second capacitor C2 is respectively connected to the drain of the thirty-second PMOS transistor M32, the drain of the thirty-fourth NMOS transistor M34, and the drain of the thirty-third PMOS transistor M35. The gate of M33 is connected to the gate of the thirty-fifth NMOS transistor M35, and the second end of the third capacitor C3 is respectively connected to the drain of the thirty-third PMOS transistor M33, the drain of the thirty-fifth NMOS transistor M35, the gate of the thirty-second PMOS transistor M32 and the gate of the thirty-fourth NMOS transistor M34; the source of the thirty-second PMOS transistor M32 and the source of the thirty-third PMOS transistor M33 are respectively connected to the ground terminal vsa, the source of the thirty-fourth NMOS transistor M34 and the source of the thirty-fifth NMOS transistor M35 are respectively connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the first end of the fourth capacitor C4 and is configured to output a negative voltage vneg, and the second end of the fourth capacitor C4 is connected to the ground terminal vsa.

[0074] In the embodiment of the present application, the charge pump improves the stability of the negative voltage output by supplying power via the stable voltage vout_ref or the power supply voltage vdda.

[0075] refer to Figure 2 , in an optional embodiment, the negative voltage generating circuit further includes an oscillator and a clock buffer; The power supply end of the oscillator and the power supply end of the clock buffer are respectively configured to obtain the stable voltage vout_ref output by the low voltage difference linear regulator in the normal working mode, or the power supply voltage vdda output in the bypass mode; The oscillator is configured to output an oscillation signal; The clock buffer is configured to generate two opposite clock signals according to the oscillation signal, so that the charge pump determines to obtain a first signal, a first inverted signal, a second signal, and a second inverted signal according to the clock signal.

[0076] In this way, the oscillator and the clock buffer are respectively powered by a low voltage drop linear regulator with a bypass mode. Regardless of whether the LDO can work normally due to the reduction of the power supply voltage, the oscillator and the clock buffer can work normally, thereby improving the stability of the output of the negative voltage generating circuit.

[0077] In the embodiment of the present application, the first signal and the second signal can be two opposite clock signals output by the clock buffer, or can be signals localized by an inverter to improve stability. The first inverted signal can be a signal obtained by inverting the first signal, and the second inverted signal can be a signal obtained by inverting the second signal.

[0078] Both the oscillator and the clock buffer can be configured according to actual requirements, and the present invention will not provide detailed descriptions.

[0079] An embodiment of the present application also provides a radio frequency module, which may include the low voltage dropout linear regulator with bypass mode of the above embodiment, or include the negative voltage generating circuit of the above embodiment.

[0080] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A low dropout linear regulator with bypass mode, characterized in that: The low-dropout linear regulator with bypass mode comprises: a bypass mode switching circuit configured to switch the operating mode of the low voltage drop linear regulator according to a power supply voltage; and A power tube configured as an output transistor of the low voltage drop linear regulator for outputting a stable voltage; Wherein, the working mode includes a normal working mode and a bypass mode; When the power supply voltage is lower than the power supply voltage threshold, the bypass mode switching circuit switches the working mode of the low voltage dropout linear regulator to the bypass mode, so that the loop of the low voltage dropout linear regulator is invalid, and the output end of the low voltage dropout linear regulator outputs the power supply voltage; When the power supply voltage is higher than the power supply voltage threshold, the bypass mode switching circuit switches the operating mode of the low-voltage dropout linear regulator to the normal operating mode, so that the low-voltage dropout linear regulator works normally, and the output end of the low-voltage dropout linear regulator outputs the stable voltage output by the power tube.

2. The low voltage dropout linear regulator according to claim 1, characterized in that: The bypass mode switching circuit comprises: A switching control module, configured to generate corresponding start / stop signals and bypass signals according to the power supply voltage; A first switch module is configured to be turned on or off under the control of the bypass signal, so that the output end of the low voltage difference linear regulator switches to output the power supply voltage or the regulated voltage; and The second switch module is configured to be turned on or off under the control of the start-stop signal, so that the power tube is turned off to make the loop of the low-voltage difference linear regulator invalid, or the power tube is turned on to make the low-voltage difference linear regulator work normally.

3. The low voltage dropout linear regulator according to claim 2, characterized in that: The switching control module includes: A voltage dividing module, configured to divide the power supply voltage to obtain a divided voltage; a comparator configured to generate a comparison output signal of a first level when the divided voltage is lower than the second reference voltage; and to generate a comparison output signal of a second level when the divided voltage is higher than the second reference voltage; A first inverter configured to invert the comparison output signal to obtain the bypass signal; and The second inverter is configured to invert the bypass signal to obtain the start / stop signal.

4. The low voltage dropout linear regulator according to claim 3, characterized in that: The voltage dividing module includes a third resistor and a fourth resistor; The first end of the third resistor is configured to obtain the power supply voltage, and the second end of the third resistor is respectively connected to the first input end of the comparator and the first end of the fourth resistor and is configured to provide the divided voltage; A second end of the fourth resistor is connected to the ground.

5. The low voltage dropout linear regulator according to claim 4, characterized in that: The first switch module includes a second switch NMOS tube; The second switch module includes a first switch PMOS tube.

6. The low voltage dropout linear regulator according to claim 5, characterized in that: The comparator includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth PMOS tube, a fifth NMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh NMOS tube, a twelfth PMOS tube, a thirteenth NMOS tube, a fourteenth PMOS tube and a fifteenth NMOS tube; The gate of the first NMOS tube is configured as the first input terminal of the comparator, and the gate of the second NMOS tube is configured as the second input terminal of the comparator and obtains a second reference voltage; The source of the first NMOS tube and the source of the second NMOS tube are respectively connected to the drain of the third NMOS tube, the source of the third NMOS tube is grounded, and the gate of the third NMOS tube is configured to obtain a first low bias voltage; The drain of the first NMOS tube is respectively connected to the gate of the fourth PMOS tube, the drain of the sixth PMOS tube, the gate of the sixth PMOS tube, the gate of the seventh PMOS tube and the drain of the eighth PMOS tube; the drain of the second NMOS tube is respectively connected to the gate of the tenth PMOS tube, the drain of the ninth PMOS tube, the gate of the ninth PMOS tube, the gate of the eighth PMOS tube and the drain of the seventh PMOS tube; the source of the fourth PMOS tube, the source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the eighth PMOS tube, the source of the ninth PMOS tube and the source of the tenth PMOS tube are respectively configured to obtain the power supply voltage; The drain of the fourth PMOS tube is respectively connected to the drain of the fifth NMOS tube, the gate of the fifth NMOS tube and the gate of the eleventh NMOS tube; the drain of the tenth PMOS tube is respectively connected to the drain of the eleventh NMOS tube, the gate of the twelfth PMOS tube and the gate of the thirteenth NMOS tube; the drain of the twelfth PMOS tube is respectively connected to the drain of the thirteenth NMOS tube, the gate of the fourteenth PMOS tube and the gate of the fifteenth NMOS tube; the source of the twelfth PMOS tube and the source of the fourteenth PMOS tube are respectively configured to obtain the power supply voltage; the source of the fifth NMOS tube, the source of the eleventh NMOS tube, the source of the thirteenth NMOS tube and the source of the fifteenth NMOS tube are respectively connected to the ground terminal; The drain of the fourteenth PMOS tube and the drain of the fifteenth NMOS tube are connected and configured as the output end of the comparator.

7. The low voltage dropout linear regulator according to any one of claims 1 to 6, characterized in that: The low-dropout linear regulator with bypass mode also includes an error amplifier and a feedback circuit; The first input terminal of the error amplifier is configured to obtain a first reference voltage, the second input terminal of the error amplifier is connected to the output terminal of the feedback circuit, and the output terminal of the error amplifier is connected to the gate terminal of the power tube; The input end of the feedback circuit is connected to the output end of the low voltage drop linear regulator.

8. The low voltage dropout linear regulator according to claim 7, characterized in that: The error amplifier includes a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube and a compensation capacitor; The gate of the sixteenth PMOS tube is configured as the first input terminal of the error amplifier EA, and the gate of the seventeenth PMOS tube is configured as the second input terminal of the error amplifier; The drain of the sixteenth PMOS tube is respectively connected to the drain of the nineteenth NMOS tube, the gate of the nineteenth NMOS tube and the gate of the twentieth NMOS tube, the drain of the seventeenth PMOS tube is respectively connected to the drain of the twenty-first NMOS tube, the gate of the twenty-first NMOS tube and the gate of the twenty-second NMOS tube; the drain of the twentieth NMOS tube is connected to the source of the twenty-third NMOS tube, the drain of the twenty-second NMOS tube is connected to the source of the twenty-fourth NMOS tube; the drain of the twenty-third NMOS tube is respectively connected to the drain of the twenty-fifth PMOS tube, the gate of the twenty-fifth PMOS tube and the gate of the twenty-sixth PMOS tube, the drain of the twenty-fourth NMOS tube is connected to the drain of the twenty-sixth PMOS tube and is configured as the output end of the error amplifier; The source of the sixteenth PMOS tube and the source of the seventeenth PMOS tube are respectively connected to the drain of the eighteenth PMOS tube; the source of the eighteenth PMOS tube, the source of the twenty-fifth PMOS tube and the source of the twenty-sixth PMOS tube are respectively configured to obtain power supply voltage connection; the source of the nineteenth NMOS tube, the source of the twentieth NMOS tube, the source of the twenty-first NMOS tube and the source of the twenty-second NMOS tube are respectively connected to the ground terminal; The gate of the twenty-third NMOS tube and the gate of the twenty-fourth NMOS tube are respectively configured to obtain the second low bias voltage, and the gate of the eighteenth PMOS tube M18 is configured to obtain the first high bias voltage; The first end of the compensation capacitor is connected to the drain of the twenty-second NMOS tube and the source of the twenty-fourth NMOS tube respectively, and the second end of the compensation capacitor is connected to the output end of the low voltage difference linear regulator; And / or, the feedback circuit includes a first resistor and a second resistor; The second input end of the error amplifier is connected to the second end of the first resistor and the first end of the second resistor respectively, the first end of the first resistor is connected to the output end of the low voltage difference linear regulator; the second end of the second resistor is connected to the ground.

9. A negative pressure generating circuit, characterized in that: The negative voltage generating circuit comprises a charge pump and a low voltage dropout linear regulator with a bypass mode as claimed in any one of claims 1 to 8; The power supply end of the charge pump is configured to obtain the stable voltage output by the low voltage drop linear regulator in the normal working mode, or the power supply voltage output in the bypass mode; The charge pump is configured to output a stable negative voltage when the power supply terminal obtains the voltage.

10. The negative voltage generating circuit according to claim 9, characterized in that: The charge pump includes a thirty-sixth PMOS transistor, a thirty-seventh PMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a second capacitor, a third capacitor, a thirty-second PMOS transistor, a thirty-third PMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a fifth resistor and a fourth capacitor; The gate of the thirty-sixth PMOS transistor is configured to obtain the first signal, and the gate of the thirty-ninth NMOS transistor is configured to obtain the first inverted signal; the gate of the thirty-seventh PMOS transistor is configured to obtain the second signal, and the gate of the thirty-eighth NMOS transistor is configured to obtain the second inverted signal; The source of the thirty-sixth PMOS transistor and the source of the thirty-seventh PMOS transistor are respectively connected to the output end of the low voltage difference linear regulator, the source of the thirty-eighth NMOS transistor and the source of the thirty-ninth NMOS transistor are respectively connected to the ground end, the drain of the thirty-sixth PMOS transistor is respectively connected to the drain of the thirty-eighth NMOS transistor and the first end of the second capacitor, the drain of the thirty-seventh PMOS transistor is respectively connected to the drain of the thirty-ninth NMOS transistor and the first end of the third capacitor; the second end of the second capacitor is respectively connected to the drain of the thirty-second PMOS transistor, the drain of the thirty-fourth NMOS transistor, and the drain of the thirty-third PMOS transistor. The gate of the OS transistor is connected to the gate of the thirty-fifth NMOS transistor, and the second end of the third capacitor is respectively connected to the drain of the thirty-third PMOS transistor, the drain of the thirty-fifth NMOS transistor, the gate of the thirty-second PMOS transistor and the gate of the thirty-fourth NMOS transistor; the source of the thirty-second PMOS transistor and the source of the thirty-third PMOS transistor are respectively connected to the ground, the source of the thirty-fourth NMOS transistor and the source of the thirty-fifth NMOS transistor are respectively connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the first end of the fourth capacitor and is configured to output a negative voltage, and the second end of the fourth capacitor is connected to the ground.

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