Cutting operations using partial cutting instructions

Abstract

Methods and apparatus for performing clipping operations include a plurality of portion clipping instructions based on a portion of a clipping value. Wherein the partial cropping instruction comprises decoding (120) the partial cropping instruction using an instruction decode circuit and obtaining (110) at least a portion of input data associated with a register having a register size. In response to the decoded instruction, clipping (130) the portion of the input data based on the portion of the clipping value; and setting (140) a flag indicating whether further clipping is required. A flag is set when the upper limit value of the portion of the input data equals or exceeds the portion of the clipping value.

Description

Technical Field

[0001] The present invention relates to data processing instructions for clipping the boundaries of a storage device to clip limits, in particular when the processing circuit is arranged to operate on constants of a given constant size. Background Art

[0002] Certain data processing techniques, such as neural network processing and graphics processing, involve the use of operations to process and generate relatively large amounts of data. It is desirable to process the data efficiently when processed by instructions. Summary of the invention

[0003] According to aspects of the present disclosure, methods, computer program products (such as non-transitory computer-readable storage media) and computer programs for controlling a host data processing device and devices configured to perform these methods are provided.

[0004] The first method is a method of executing a partial trim instruction with a portion of a trim value, the method comprising: obtaining at least a portion of input data, the portion of the input data being associated with a register having a register size; decoding the partial trim instruction using an instruction decoding circuit; and in response to the decoded instruction, trimming the portion of the input data based on the portion of the trim value; and when an upper limit value of the portion of the input data is equal to or exceeds the portion of the trim value, setting a flag indicating further trimming.

[0005] By executing trimming instructions on portions of the input data and setting flags to indicate whether further trimming is required, instructions can be cascaded into operations so that the program supports a wide range of input data sizes. This is particularly useful for machine learning implementations, where the size of the tensor used will typically exceed the size of the trimming parameters. This also enables processing input data whose size exceeds the size that the data processing hardware can handle. Therefore, this enables processing input data with larger input data sizes while minimizing the required hardware, thereby reducing the total on-chip space required to implement the method. This reduces the cost, manufacturing complexity, and processing power requirements required to implement the method.

[0006] Optionally, an input portion number associated with the portion of the input data is decoded to determine the selected input portion and the selected clipping portion associated with the clipping value. This enables tracking of clipping portions and associated portions of the input data to ensure that clipping values ​​are accurately generated when performing larger clipping operations.

[0007] The flag value may be read and used to determine whether to clip the portion of the input data based on the flag value. By using the flag value to indicate whether further clipping is required, a more efficient clipping operation may be performed such that if a higher portion comparison has determined that further clipping of the value is not required, no clipping is applied. Similarly, clipping the portion of the input data may include determining whether the portion of the input data is greater than the portion of the clipping value. These features all ensure efficient use of resources such that unnecessary clipping operations are not performed.

[0008] This portion of the clipped value may be an 8-bit shifted constant, which enables the use of hardware capable of processing 8-bit values, thereby reducing manufacturing costs and resource requirements while still providing efficient processing capabilities.

[0009] Optionally, the register includes at least a low boundary component and a high boundary component, and the flag is stored in the low boundary component. The flag can be stored in a sign bit associated with the low boundary of the register. Clipping can be applied only to the high boundary of the register. By dividing the register into a high boundary component and a low boundary component, efficient clipping of input data can be achieved. In addition, storing the flag in the sign bit of the low boundary of the register enables the flag to be stored without additional hardware, because the low boundary of the register will always be greater than or equal to zero.

[0010] Execution of subsequent partial crop instructions may be based on the setting of a flag, and at least one of the subsequent partial crop instructions of the plurality of partial crop instructions may include reading the flag. This enables efficient determination of the cropped input data, as only those values ​​that need to be cropped are cropped based on the flag.

[0011] The second method is a method of compiling an instruction sequence including a plurality of partial pruning instructions (such as the partial pruning instructions described above for the first method), wherein the length of the sequence is determined based on the range of potential input values. This enables efficient generation of pruned input data, wherein the hardware configured to pruned input data is configured to operate on data having a smaller data size.

[0012] Other features and advantages of the present invention will become apparent from the following description of preferred embodiments of the invention given by way of example only with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a flow chart illustrating a method for executing a partial clip instruction according to an example;

[0014] Figure 2 is a flow chart illustrating a method for performing a clipping operation according to an example;

[0015] Figure 3 is a schematic diagram of an apparatus according to an example;

[0016] Figure 4 is a flow chart illustrating a method for executing right shift-multiply and / or right shift-multiply-accumulate instructions according to an example;

[0017] Figure 5 is a schematic diagram of an apparatus for executing right shift-multiply and / or right shift-multiply-accumulate instructions according to an example;

[0018] Figure 6 is a schematic diagram of a data processing system according to an example;

[0019] Figure 7 is a schematic diagram of a neural engine according to an example; and

[0020] Figure 8 is a schematic diagram of a system for distributing data processing tasks according to an example;

[0021] Fig. 9 is a schematic diagram of a simulator implementation according to an example. DETAILED DESCRIPTION

[0022] In common computing, a computer program is typically configured to operate on data stored in registers associated with a processor on which the computer program is executed.

[0023] As part of a computer program, multiple instructions may be issued so that the processor is configured to operate on one or more values ​​stored in a register. The size of the value stored in the register may depend on multiple hardware limitations, including but not limited to the register size. For example, in some examples, the value stored in the register may be limited to a signed 32-bit, and in other examples, the register may have a high component value and a low component value that may store a signed 32-bit value. One of the instructions of the computer program may be a clipping instruction for clipping the register value, so that the clipping instruction is used to specify a boundary range. Examples of other instructions may also be used, such as the right shift multiplication instruction that will be described in further detail below.

[0024] Clipping operations using partial clipping instructions

[0025] As briefly described above, registers can be used to temporarily store one or more values ​​for subsequent processing. The data provided as input may have a data size that exceeds the size that the data processing hardware can handle. In this way, it may be necessary to select a portion of the input data for processing. In addition, this limits the space for program instructions so that each instruction can be represented by a single byte of data that can take a single 8-bit parameter. In such an example, if the input data exceeds the 8-bit size required for the instruction, it may be necessary to divide the input data into some parts for comparison. It should be understood that the input data may have another size (such as 16 or 32 bits). By dividing the input data into some parts for comparison, instructions can be cascaded to enable the program to support operations with a wide range of input data sizes. This is particularly useful for machine learning implementations where the size of the tensor used will generally exceed the range of instruction parameters.

[0026] Figure 1 1 is a flow chart 100 showing a method for executing a partial clipping instruction. At step 110, the partial clipping instruction is received and decoded by data processing hardware. In particular, the partial clipping instruction can be decoded by instruction decoding circuitry associated with the data processing hardware. The instruction decoding circuitry supports a plurality of different instructions including a partial clipping instruction that performs a computational operation to clip input data (or some portion thereof) for a given boundary register based on the low (b.lo) and high (b.hi) signed components of the boundary register, thereby representing the range of the boundary register. The range can therefore be represented as a range [0, m], where m is a non-negative signed 32-bit value. It should be understood that other sizes of "m" (e.g., 16-bit or 32-bit sizes) can be used depending on hardware capabilities. When clipping to the low and high signed components of the boundary register, the clipping value can be represented as:

[0027] b.lo=max(b.lo,0)

[0028] b.hi=min(b.hi,m)

[0029] Equation 1 and Equation 2

[0030] Once the partial crop instruction has been decoded, at step 120, at least a portion of the input data is obtained. For example, the input data may be tensor coordinates or dimensions used as part of a machine learning program, or may be any other suitable data. In some examples, the size of the input data will exceed the size of the data processing hardware (such as the following reference Figures 6 to 8 In such an example, it is necessary to divide the input data into some parts so that the data processing hardware can operate on the parts of the input data.

[0031] As described above, in some examples, the input data may be tensor coordinates or sizes for use in a machine learning program stored in a boundary register or multiple boundary registers having a high signed 32-bit component that represents the range of values ​​of the input data / tensor. The range of values ​​may exceed the processing capabilities of the hardware, and in some examples, the hardware may be configured to operate on shifted 8-bit constants. It should be understood that in other examples, the size of the boundary register may be different from the size of the constant that the hardware is configured to operate on (e.g., 32-bit boundary registers and 16-bit constants; or 64-bit boundary registers and 8-bit constants; other examples will be clear to the skilled person).

[0032] At step 120, in the event that the size of the input data exceeds the size of an immediate value or a constant (such as an 8-bit constant), at least a portion of the input data may be obtained. The input data may be segmented into a plurality of portions and may each be assigned an associated portion number corresponding to the portion number associated with the clipping value.

[0033] In response to decoding of the partial crop instruction, at step 130, a portion of the input data is cropped based on the low and high signed components of the boundary register. Since, as mentioned above, the data processing hardware can only operate on data that is smaller in size than the input data, it is necessary to split the input data into multiple portions so that the size of the input portion is sufficient to be processed by the data processing hardware. For example, the data processing hardware can be configured to operate only on shifted 8-bit constants, so the upper limit value of the range (m) can be represented by four different bytes, namely:

[0034] m=(m3<<24)+(m2<<16)+(m1<<8)+m0

[0035] Equation 3

[0036] Each of these parts of the range can be used to operate on parts of the input data so that the input data can be clipped for the relevant range required by the boundary register (i.e., the range of b.lo and b.hi). Since each of the operations undertaken on these separate parts is related to each other, further efficiency can be obtained by determining whether it is necessary to perform further clipping operations, especially when performing on the high boundary (b.hi) of the boundary register. For example, if the high byte of the input data is less than m3, no further clipping of the subsequent part is required for the higher range. Similarly, if the high byte of the input data is greater than m3, the subsequent part of the input data must be set to m2, and if the high byte of the input data is equal to m3, further clipping will be required for the subsequent part of the input data. An example of this process will be described in further detail below. To indicate whether further clipping is required, at step 140, a flag can be set. Since b.lo is always non-negative (i.e., greater than or equal to 0) after clipping, the sign bit of b.lo can be used to indicate whether further clipping is required. Thus, the signed bit of b.lo may be set to 1 to indicate that further clipping is required, and set to 0 to indicate that no further clipping is required. It should be appreciated that there are other methods and available bits that may be used when setting the flag.

[0037] Figure 2 2 is a flow chart 200 showing a method for performing a clipping operation. At step 210, a partial clipping instruction is executed. The partial clipping instruction (such as for Figure 1 The method 100 described partial crop instruction is executed, and the flag is set as described above. After executing the partial crop instruction, at step 220, it is determined whether to execute further partial crop instructions. In some examples, the determination of whether to execute further partial crop instructions can be based on the flag set in step 140 of method 100. The value of the flag can be read before executing subsequent partial crop instructions, so that if the value of the flag indicates that further cropping is required, further partial cropping instructions can be executed. This can be determined by reading the state of the flag (e.g., the sign bit b.lo of the low boundary of the boundary register). In other examples, such as when the input data has a known size, the highest portion to start cropping can be determined at the compilation stage.

[0038] The partial trimming instructions described for method 100 may be performed on only a portion of the input data. In such an example, the portion of the input data may be assigned an input portion number, and an associated portion of the trimming value (i.e., having a corresponding trimming portion number) may be selected. For example, the portion of the trimming value may be an 8-bit shifted constant, so that the hardware executing the partial trimming instructions may be simplified and memory / processing requirements may be reduced. Further efficiencies may be obtained by pre-compiling the trimming operation so that the compiled trimming operation includes a sequence of partial trimming instructions, and the length of the sequence is based on the range of possible input values. The compiled trimming operation may include multiple partial trimming instructions so that the first partial trimming instruction does not require data associated with a flag (e.g., the sign bit of b.lo), but subsequent partial trimming instructions do require data representing the flag to be present.

[0039] An example of a compiled clipping operation is set forth in the following pseudocode, which represents the method set forth above, i.e., if the higher byte (b.hi) is greater than or equal to the corresponding constant byte (m), the lower limit sign byte (b.lo) is used to signal that further clipping of the lower byte is required. As described above, when b.lo is clipped for non-negative numbers by the first clipping instruction, the sign bit is vacated to maintain the flag. If the higher byte is greater than the corresponding m byte, the lower byte of the register can be set to the maximum value (e.g., 0xFF, where the portion size is 8 bits). This ensures that when the lower byte is clipped, they take the value of the lower byte of m. Then, the clipping operation is performed as a sequence, wherein the first (CLP) in the sequence does not consider the value set to the flag, and the subsequent partial clipping operation (CLP.L) considers the flag when clipping the lower byte. If it is known that the value to be clipped has a smaller range (e.g., 3 bytes to 4 bytes), fewer clipping instructions can be used because the first clipping value can be the highest byte with a non-zero value (see the description of Example 4 below). This method is illustrated in the following examples, which include 32-bit clipping values ​​and four instructions A, B, C, D:

[0040] A.CLP((m>>24)&0xFF),3

[0041] B.CLP.L((m>>16)&0xFF),2

[0042] C.CLP.L((m>>8)&0xFF),1

[0043] D.CLP.L((m>>0)&0xFF),0

[0044] Example 1 :

[0045] b.lo=-0x0000100b.hi=0x12345678m=0x0189ABCD

[0046] After A.: b.lo = 0x80000000 b.hi = 0x01FFFFFF / / This is larger than the above After B.: b.lo = 0x80000000 b.hi = 0x0189FFFF / / Because b

[31] – (the “8” in b.lo) – the signal needs further clipping

[0047] After C.: b.lo = 0x80000000 b.hi = 0x0189ABFF / / Because the b

[31] signal needs to be further trimmed

[0048] After D.: b.lo = 0x00000000 b.hi = 0x0189ABCD / / Because b

[31] is the last byte, it has been cleared

[0049] Example 2 :

[0050] b.lo=-0x0000100b.hi=0x12345678m=0x1234AB00

[0051] After A.: b.lo = 0x80000000 b.hi = 0x12345678 / / This is greater than or equal to the above

[0052] After B.: b.lo = 0x80000000 b.hi = 0x12345678 / / Because b

[31] - ("8" in b.lo) – the signal needs to be further clipped – this is still a greater than or equal situation

[0053] After C.: b.lo = 0x80000000 b.hi = 0x12345678 / / b

[31] is cleared because the corresponding byte of b.hi ("56") is less than the corresponding byte of m ("AB")

[0054] After D.: b.lo = 0x00000000 b.hi = 0x12345678 / / / Because b

[31] has been cleared, there is no need to trim the last byte

[0055] Example 3:

[0056] b.lo=0x00000200b.hi=0x12345678m=0x20000000

[0057] After A.: b.lo = 0x00000200 b.hi = 0x12345678 / / This is less than the above case

[0058] After B.: b.lo = 0x00000200 b.hi = 0x12345678 / / No further cropping required

[0059] After C.: b.lo = 0x00000200 b.hi = 0x12345678 / / No further cropping is required After D.: b.lo = 0x00000200 b.hi = 0x12345678 / / No further cropping is required

[0060] As explained above, the compiler may select fewer trimming instructions. In this case, if the input data range is known to be 16 bits, only two trimming instructions are needed. This method is shown in the following example, which includes a 16-bit trimming value and two instructions E, F:

[0061] E.CLP((m>>8)&0xFF),1

[0062] F.CLP.L((m>>0)&0xFF),0

[0063] Example 4 :

[0064] b.lo=0x00000300 b.hi=0x00001234 m=0x00000567

[0065] After E: b.lo = 0x80000000 b.hi = 0x000005FF / / This is greater than the above, so b

[31] of b.lo is set and the lower byte is FF

[0066] After F: b.lo = 0x00000300 b.hi = 0x00000567 / / The last byte is trimmed and b

[31] of b.lo is cleared

[0067] Figure 3 It is used based on the above Figure 1 and Figure 2 Schematic diagram of an apparatus 300 for performing a trimming operation using a partial trimming instruction described in methods 100 and 200. The apparatus 300 has an input circuit 320 configured to obtain at least a portion of input data, the portion of the input data being associated with a register 310 having a given register size. The register 310 may be the register 310 described above for Figure 1 and Figure 2310a (b.hi) and a low portion 310b (b.lo). The apparatus may also include a storage medium (not shown) such as a solid state drive (SSD) or other semiconductor-based RAM; a ROM such as a CD ROM or a semiconductor ROM; a magnetic recording medium such as a floppy disk or a hard disk; typically an optical storage device; etc. In some examples, the registers may form part of the storage medium.

[0068] The apparatus also includes an instruction decoding circuit 330 configured to receive the instruction 350. The instruction decoding circuit 330 may be configured to receive any number of instructions, not just partial trim instructions and / or trim operations. For example, the instruction decoding circuit 330 may be configured to receive a right shift multiply instruction, as described in further detail below. The instruction decoding circuit 330 receives the instruction and then decodes it for processing by the processing circuit 340. The processing circuit 340 may be configured to perform any number of tasks, and in particular, is configured to perform at least a portion of the trim instruction. The processing circuit 340 is configured to perform the instructions based on the instructions described above for Figure 1 The processing circuitry 100 is further configured to clip the portion of the input data stored in the register corresponding to the portion of the clipping value described in the method 100. The processing circuitry 100 is further configured to set a flag to indicate whether further clipping is required. The flag may be a sign bit of the low portion 310b (b.lo) of the register, since the low boundary of the range is always clipped against the higher of the low boundary or zero (i.e., it will always be non-negative).

[0069] The processing circuit 330 may also be configured to decode the input portion based on the input portion number associated with the portion of the input data and the corresponding crop portion number associated with the corresponding portion of the selected crop value. By decoding the input data portion by portion, it may be determined whether to crop the portion of the input data based on whether a particular portion of the input data is larger than the portion of the crop value. This may then provide information as to whether further cropping may be required.

[0070] As described above, the clipping value may be an 8-bit shifted constant, however, it will be appreciated that clipping values ​​of other sizes may be used depending on the hardware of the processing circuit 330. For example, the processing circuit 330 may be configured to operate on 16-bit constants or 32-bit constants.

[0071] In addition to executing a partial trim instruction, the apparatus 300 may be configured to execute multiple partial trim instructions compiled as trim operations. By executing multiple partial trim instructions, the apparatus 300 is able to trim larger values ​​than initially permitted by the hardware configuration. As described above, this is achieved by setting a flag to indicate whether further trimming is required.

[0072] Floor division using right shift multiplication instruction

[0073] The implementation of the floor division operation can be based on the use of a multiply instruction, as described in further detail below. For example, a floor division that performs a signed 32-bit value divided by a positive 32-bit divisor can be implemented using a 32×8 multiplier. Performing such a calculation can be more efficient in hardware / processor terms than other methods because it can take advantage of hardware efficient implementations, such as right shifts, and minimize the need for more complex hardware.

[0074] Hardware can be limited in performance of calculation based on its processor capability and other hardware constraints (such as register size and / or other constraints). For example, processor and / or memory constraints can limit any calculation to 8-bit input, however, it should be understood that other data lengths (such as 16 and 32 bits) can be used. In such an example, the hardware can be able to multiply a 32-bit integer by an 8-bit constant by utilizing the hardware functionality, and a series of right shift multiplication instructions can be used to implement the division operation. That is, the compiler can use right shift multiplication instructions (such as (n×m)>>shift) to implement downward division for positive values ​​or for negative values, thereby rounding to negative infinity. This enables the use of a processing circuit that is configured to perform operations on a constant that is small and large compared to the constant that can be stored as a constant.

[0075] Figure 4 4 is a flow chart 400 illustrating a method for performing a shift-right multiply instruction ("MULR"), such as the method described above using a floor division operation. At step 410, a shift-right multiply instruction (MULR) and / or a shift-right multiply-accumulate instruction (MLAR) is received and decoded by data processing hardware. In particular, these instructions may be decoded by instruction decoding circuitry associated with the data processing hardware. The instruction decoding circuitry supports a plurality of different instructions, including those instructions that perform calculations to generate shifted multiplied input data based on at least a portion of the input data.

[0076] In some examples, the right shift multiply instruction may include accumulating the multiplied input data with the previously shifted input data. In such examples, the instruction may be referred to as a right shift multiply accumulate instruction ("MLAR").

[0077] Once the instruction has been decoded, at step 420, at least a portion of the signed input data is obtained. The portion of the signed input data is associated with a register having a given register size, for example, the input data may be tensor coordinates or tensor sizes used as part of a machine learning program, or may be any other suitable data. The size of the input data exceeds the size of the data processing hardware (such as described below with reference to Figures 6 to 8 Describes the size of data that the processing hardware can handle.

[0078] As described above, in some examples, the input data may be tensor coordinates or dimensions for use in a machine learning program stored in a boundary register or multiple boundary registers having a signed 32-bit component that represents a range of values ​​for the input data / tensor. The range of values ​​may exceed the processing capabilities of the hardware, which in some examples may be configured to operate on 8-bit constants. It should be understood that in other examples, the size of the boundary register may be different from the size of the constant that the hardware is configured to operate on (e.g., 32-bit boundary registers and 16-bit constants; or 64-bit boundary registers and 8-bit constants; other examples will be clear to the skilled person).

[0079] In some examples, where the size of the input data exceeds the processing capability of the hardware, at least a portion of the input data may be obtained.The input data may be segmented into a plurality of portions, and may each be assigned an associated portion number.

[0080] In response to decoding of the instruction and receipt of the portion of the signed input data, processing circuitry (such as the data processing hardware described above) is controlled to perform data processing on the portion of the signed input data at step 430. The processing circuitry is configured to operate on a constant that is smaller than a register used to store at least a portion of the input data.

[0081] At step 440, a multiplier is selected based on a sign associated with the signed input data. For example, in the case where the sign is negative, a first derived constant is selected as the multiplier, and in the case where the sign is positive, a second derived constant is selected as the multiplier. The derived constant may be based on a constant size that the processing circuit is configured to operate on. In some examples, the first derived constant is equal to the constant that the processing circuit is configured to operate on minus one, and the second derived constant is equal to the constant itself. In other examples, the first derived constant may be equal to the constant-1 modulo the constant size.

[0082] As previously described, the selection of constants can be based on the capabilities of the processing circuit. For example, the constant can be based on the size of the constant (such as an 8-bit constant, a 16-bit constant, or a 32-bit constant) that the processing circuit can operate on. It should be understood that constants of other sizes can also be used and the processing circuit can be able to operate on these other sizes of constants. The selected constant can be derived from one or more inputs of other operations (such as the floor division operation described in further detail below). In such an example, the constant can be derived based on the following:

[0083]

[0084] where the divisor and divisor size are related to the divisor in the floor division operation.

[0085] In some examples, the constant is smaller than the size of the signed input data, and in other examples, as mentioned above, the constant may be limited (such as having a size of 8 bits) based on the processing capabilities of the processing circuitry.

[0086] Once the multiplier is selected, at step 450, the multiplied input is generated. The multiplied input is generated using a portion of the signed input data and the multiplier. The multiplied input can be generated using a processing circuit that may include hardware configured to efficiently perform multiplication operations between inputs of constant size and / or input data portion size. In some examples (such as right shift multiply-accumulate instructions), there is an optional accumulation step 460, in which the results of the previous instructions are accumulated before the shifted multiplied input is generated at step 470 described below. After generating the multiplied input and the optional accumulation, at step 470, the shifted multiplied input data is generated by shifting the input by a constant size. As with steps 450 and 460, the shift operation undertaken at step 470 may also be generated using a processing circuit that may also include hardware configured to efficiently perform a shift operation.

[0087] After generating the shifted multiplied input data, at step 480, the shifted multiplied input data is stored in a storage device. The storage device may form part of a device configured to perform a right shift multiplication operation, and / or may be separate from it. The storage device may be a solid state drive (SSD) or other semiconductor-based RAM; a ROM, such as a CD ROM or a semiconductor ROM; a magnetic recording medium, such as a floppy disk or a hard disk; typically, an optical storage device; etc. In some examples, a register may form part of the storage device.

[0088] The floor division operation may include multiple right shift-multiply and / or right shift-multiply-accumulate instructions, such as the above for Figure 4 The floor division operation may also include one or more right shift multiply-accumulate instructions. Determining the requirement for the floor division operation includes compiling a sequence of these instructions, wherein the sequence of instructions includes at least one of the above-described right shift multiply instructions. The hardware (such as the one described below) may be used. Figures 6 to 8 The floor division operation may include a plurality of instructions configured to perform at least one of the following:

[0089]

[0090] Where n is at least a part of the signed input data, d is a positive divisor, m is a multiplier constant selected based on a constant of a given constant size, N is the number of bits in n such that -(1 << N) ≤ n < (1 << N), and k is the number of bits in d such that (1 << (k - 1)) < d ≤ (1 << k). Then, the constant m is calculated as:

[0091]

[0092] Following the above Equation 5 and Equation 6, the floor division operation can include multiple instances of the right shift multiply instruction and the right shift multiply and accumulate instruction described above. Examples of such operations will be provided below. Figure 4 Description of the right shift multiply instruction and the right shift multiply and accumulate instruction.

[0093] In some examples, such as when the processing circuit is configured to operate on a constant smaller than the size of the multiplier, the multiplier can be divided into multiple parts based on the given constant size. When the results of the constant and the constant minus one are different for a particular part of the signed input data, the right shift multiply instruction can be used in the floor division operation.

[0094] An example of the compiled floor division operation is set forth in the following pseudocode representing the method described above. That is, based on a known divisor (and associated divisor size), input data size, the part of the input data represented as an integer, and a known multiplier, right shift multiply (MULR) and right shift multiply and accumulate (MLAR) operations are used.

[0095] Example 1:

[0096] N (number of bits in n) = 31

[0097] m (multiplier) = 0x12345600

[0098] (m - 1) = 0x123455FF

[0099] k (size of the divisor) = 5

[0100] In the case where the processing circuit is configured to operate on an 8-bit constant, the 32-bit multiplier will be divided into 4 × 8-bit parts, and each part operates on a given part of the input data n. Therefore, based on the above Equation 5 and Equation 6, the floor division operation in this embodiment is represented as:

[0101]

[0102] In this embodiment, m is not derived from the divisor d value, but rather illustrates how an exemplary m value is divided.

[0103] The sequence of instructions is compiled based on each of the 8-bit constants associated with the multipliers. If the 8-bit constants of the multipliers are different, MULR.C / MLAR.C (Equation 6) is used, and if the 8-bit constants are the same, MULR / MLAR is used. Therefore, in this embodiment, the sequence of instructions will be:

[0104] 0:MULR.C#0x00 (0x00 is the lowest byte of m)

[0105] 1:MLAR.C#0x56

[0106] 2:MLAR#0x34

[0107] 3:MLAR#0x12

[0108] 4:ASR#4

[0109] In the above instruction sequence representing the floor division operation, since the two lowest byte sets of m and (m-1) are different, the MULR.C / MLAR.C instructions are used for instructions [0] and [1]. In addition, since N+k=36, the MULR / MLAR instructions only shift the bits by 32 bits, so an additional 4 bits are required, so the ASR#4 instruction is used.

[0110] As described above, the use of MULR and MLAR is based on whether accumulation is required. In this embodiment, a first MULR instruction is executed, followed by a subsequent MLAR instruction, accumulating the results of the previous MULR or MLAR instruction before performing the final shift operation.

[0111] Example 2 :

[0112] N (number of bits in n) = 31

[0113] m(multiplier)=0xaaaaaaab

[0114] (m-1)=0xaaaaaaaa

[0115] k (size of divisor) = 2

[0116] d(divisor)=3

[0117] Based on the above equations 5 and 6, the floor division operation in this embodiment is expressed as:

[0118]

[0119] Using the same processing circuitry as in Embodiment 1 above where the processing circuitry is configured to operate on 8-bit constants, the compiled instruction sequence for the floor division operation would then be:

[0120] 0:MULR.C#0xab (0xab is the lowest byte of m)

[0121] 1:MLAR#0xaa

[0122] 2:MLAR#0xaa

[0123] 3:MLAR#0xaa

[0124] 4:ASR#1

[0125] In the above instruction sequence representing the floor division operation, since the lowest byte set of m and (m-1) is different, the MULR.C / MLAR.C instruction is only utilized for instruction [0]. In addition, since N+k=33, the MULR / MLAR instruction only shifts the bits by 32 bits, so an additional 1 bit shift is required, so the ASR#1 instruction needs to be used.

[0126] As described above, the use of MULR and MLAR is based on whether accumulation is required. In this embodiment, a first MULR instruction is executed, followed by a subsequent MLAR instruction, accumulating the results of the previous MULR or MLAR instruction before performing the final shift operation.

[0127] Example 3 :

[0128] N (number of bits in n) = 31

[0129] m(multiplier)=0xd95dd300

[0130] (m-1)=0xd95dd2ff

[0131] k (size of divisor) = 10

[0132] d(divisor)=603

[0133] Based on the above equations 5 and 6, the floor division operation in this embodiment is expressed as:

[0134]

[0135] Using the same processing circuitry as in Embodiments 1 and 2 above where the processing circuitry is configured to operate on 8-bit constants, the compiled instruction sequence for the floor division operation would then be:

[0136] 0:MULR.C#0x00 (0x00 is the lowest byte of m)

[0137] 1:MLAR.C#0xd3

[0138] 2:MLAR#0x5d

[0139] 3:MLAR#0xd9

[0140] 4:ASR#9

[0141] In the above instruction sequence representing the floor division operation, since the lowest byte set of m and (m-1) is different, the MULR.C / MLAR.C instructions are only utilized for instructions [0] and [1]. In addition, since N+k=41, the MULR / MLAR instructions only shift the bits by 32 bits, so an additional 9 bits are required, so the ASR#9 instruction needs to be used.

[0142] As described above, the use of MULR and MLAR is based on whether accumulation is required. In this embodiment, a first MULR instruction is executed, followed by a subsequent MLAR instruction, accumulating the results of the previous MULR or MLAR instruction before performing the final shift operation.

[0143] Figure 5 It is used based on the above Figure 4 Schematic diagram of an apparatus 500 for performing a floor division operation using a right shift-multiply instruction or a right shift-multiply-accumulate instruction described in conjunction with method 400 and subsequent descriptions. Apparatus 500 has input circuitry 520 configured to obtain at least a portion of signed input data, the portion of signed input data being associated with a register 510 having a given register size. The portion of signed input data may be obtained from a storage medium (not shown) such as a solid state drive (SSD) or other semiconductor-based RAM; a ROM such as a CD ROM or a semiconductor ROM; a magnetic recording medium such as a floppy disk or a hard disk; typically an optical storage device; etc. In some examples, the register may form part of the storage medium.

[0144] The apparatus also includes an instruction decoding circuit 530 configured to receive an instruction 550. The instruction decoding circuit 530 may be configured to receive any number of instructions, not just right shift multiply and / or right shift multiply-accumulate instructions for floor division operations. For example, the instruction decoding circuit 530 may be configured to receive a crop instruction as described in further detail above. The instruction decoding circuit 530 receives the instruction and then decodes it for processing by the processing circuit 540. The processing circuit 540 may be configured to perform any number of tasks, and in particular, is configured to perform at least a floor division operation. The processing circuit 540 is configured to execute a right shift multiply instruction or a right shift multiply-accumulate instruction on a portion of the input data, as described above for the right shift multiply-accumulate instruction. Figure 4The method 400 and subsequent descriptions are described. The processing circuit 540 is configured to operate on a constant of a given constant size that is smaller than the size of the register 510 from which the signed input data is obtained. The processing circuit 540 selects a multiplier based on the sign of the signed input data obtained from the register 510, so that when the sign is positive, a first constant is selected, and if the sign is negative, a second constant is selected. Then, a portion of the signed input data is multiplied by the selected multiplier and shifted by the size of the constant. The processing circuit is then configured to output the shifted multiplied input data to a storage device (not shown) (such as the above-mentioned storage medium) and / or the register 510.

[0145] As described above, processing circuit 530 may be configured to operate on 8-bit constants, however, it will be appreciated that constants of other sizes may be used depending on the hardware of processing circuit 530. For example, processing circuit 530 may be configured to operate on 16-bit constants or 32-bit constants.

[0146] In addition to executing right shift instructions and / or right shift multiply-accumulate instructions, device 500 can be configured to execute multiple right shifts and right shift multiply-accumulate instructions compiled as floor division operations. By executing multiple such instructions, device 500 can efficiently perform floor division operations using a larger value than the initial permission of the hardware configuration. As described above, this is achieved by storing the intermediate results of the right shift and right shift multiply-accumulate instructions in a storage device.

[0147] Overall architecture

[0148] The above method can be implemented on any type of suitable hardware (such as the hardware described below), and can also be used to process many types of data. For example, as explained above, the data generated during the execution of a given task can be a tensor (wherein, as used herein, the term "tensor" will be considered to refer to a multidimensional tensor). A tensor is an array of elements, such as an array of scalar elements of the same type. Various tasks can involve the processing and / or generation of tensors, such as neural network processing and graphics processing.

[0149] The methods herein may use a processor (such as the one referenced above) Figure 3 The processing circuit 320 described above with reference to Figure 5 The processor is implemented as a processing circuit 520 described above, which provides dedicated circuitry that can be used to perform operations that would normally be undertaken by dedicated hardware accelerators (such as neural processing units (NPUs) and graphics processing units (GPUs)). Figure 6 An example of a data processing system 600 including such a processor 630 is schematically shown, which may include the above-mentioned Figure 3 The processing circuit 320 and Figure 5Components described by the processing circuit 520 of . It should be understood that the type of hardware accelerator for which the processor 630 can provide dedicated circuitry is not limited to the type of NPU or GPU, but can be dedicated circuitry for any type of hardware accelerator. GPU shader cores can be well suited to perform certain types of arithmetic operations (such as neural processing operations) because these operations are generally similar to arithmetic operations that may be required when performing graphics processing work (but on different data). In addition, graphics processors typically support advanced concurrent processing (e.g., support a large number of execution threads) and are optimized for data plane (rather than control plane) processing, all of which means that graphics processors can be well suited to perform other types of operations.

[0150] That is, instead of using a completely separate hardware accelerator, such as a machine learning processing unit (such as an NPU) that is independent of the graphics processor, or being able to fully use the GPU's hardware to perform machine learning processing operations, dedicated circuitry can be incorporated into the GPU itself.

[0151] This means that hardware accelerator circuits incorporated into a GPU may be operable to take advantage of some of the GPU's existing resources (e.g., such that at least some of the GPU's functional units and resources may be efficiently shared, for example, between different hardware accelerator circuits) while still allowing improved (more optimized) performance compared to performing all processing in a general purpose implementation.

[0152] As such, processor 630 may be a GPU adapted to include a number of specialized hardware resources, such as those described below.

[0153] In some examples, this can be particularly beneficial when performing machine learning tasks that themselves involve graphics processing work, because in this case, all associated processing can (and preferably) be performed locally on the graphics processor, thus improving data locality and (for example) reducing the need for external communication along interconnects with other hardware units (e.g., NPUs). In this case, at least some of the machine learning processing work can be offloaded to the machine learning processing circuitry, thereby freeing up execution units to perform actual graphics processing operations as needed.

[0154] In other words, in some examples, providing machine learning processing circuitry within a graphics processor means that the machine learning processing circuitry is then preferably operable to perform at least some machine learning processing operations while other functional units of the graphics processor are concurrently performing graphics processing operations. In cases where the machine learning processing involves a portion of the overall graphics processing task, this can therefore improve the overall efficiency (in terms of energy efficiency, throughput, etc.) of the overall graphics processing task.

[0155] exist Figure 6In the embodiment, the processor 630 is arranged to receive a command stream 620 from a host processor 610 (such as a CPU). The command stream includes at least one command in a given sequence, each command is to be executed, and each command can be decomposed into multiple tasks, such as the tasks discussed in the above examples. These tasks can be self-contained operations, such as a given machine learning operation or a graphics processing operation. It should be understood that there may be other types of tasks depending on the command.

[0156] The command stream 620 is sent by the host processor 610 and received by the command processing unit 640, which is arranged to schedule the commands according to the sequence of commands in the command stream 620. The command processing unit 640 is arranged to schedule the commands and decompose each command in the command stream 620 into at least one task. Once the command processing unit 640 has scheduled the commands in the command stream 620 and generated a plurality of tasks for the commands, the command processing unit issues each of the plurality of tasks to at least one computing unit 650a, 650b, each of which is configured to process at least one of the plurality of tasks, as described above with reference to FIG. Figures 1 to 5 In the described example, these tasks may be operations in operation set 120os.

[0157] The processor 630 includes a plurality of computing units 650a, 650b. Each computing unit 650a, 650b may be a shader core of a GPU that is specifically configured to undertake a plurality of different types of operations, however it should be understood that other types of specifically configured processors may be used, such as general purpose processors configured with separate computing units (such as computing units 650a, 650b). Each computing unit 650a, 650b includes a plurality of components, and at least a first processing module 652a, 652b for performing a task of a first task type and a second processing module 654a, 654b for performing a task of a second task type different from the first task type. In some examples, the first processing module 652a, 652b may be a processing module for processing neural processing operations (such as those neural processing operations typically undertaken by a separate NPU). In these cases, the first processing module 652a, 652b is, for example, a neural engine. Similarly, the second processing module 654a, 654b can be a processing module for processing graphics processing operations forming a predefined graphics processing operation set, which enables the implementation of a graphics processing pipeline, which can be referred to as a graphics processor. For example, such graphics processing operations include graphics calculation shader tasks, vertex shader tasks, fragment shader tasks, tessellation shader tasks, and geometry shader tasks. These graphics processing operations can all form a part of a predefined operation set as defined by an application programming interface API. Examples of such APIs include Vulkan, Direct3D, and Metal. Such tasks will generally be undertaken by a separate / external GPU. It should be understood that any number of other graphics processing operations may be able to be processed by the second processing module.

[0158] Thus, the command processing unit 640 issues tasks of a first task type to a first processing module 652a, 652b of a given computing unit 650a, 650b, and issues tasks of a second task type to a second processing module 654a, 354b of a given computing unit 650a, 650b. The command processing unit 640 will issue machine learning / neural processing tasks to a first processing module 652a, 652b of a given computing unit 650a, 650b, where the first processing module 652a, 652b is optimized to handle neural network processing tasks, for example, by including efficient means for managing a large number of multiplication and accumulation operations. Similarly, the command processing unit 640 will issue graphics processing tasks to a second processing module 654a, 654b of a given computing unit 650a, 650b, where the second processing module 652a, 654a is optimized to handle such graphics processing tasks. In some examples, both the first and second can be neural processing tasks issued to the first processing module 652a, 652b as a neural engine. Such neural processing tasks may involve processing, for example, tensors representing feature maps using weights associated with layers of a neural network.

[0159] In addition to including the first processing module 652a, 652b and the second processing module 654a, 654b, each computing unit 650a, 650b also includes a memory in the form of a local cache 656a, 656b for use by the corresponding processing module 652a, 652b, 654a, 654b during task processing. The local cache can be a local memory for holding tensor data, see Figure 3 and Figure 5 The processing circuit 320, 520 processes the coordinates of the tensor data. An example of such a local cache 656a, 656b is an L1 cache. The local cache 656a, 656b can be, for example, a synchronous dynamic random access memory (SDRAM) and / or a static random access memory (SRAM). For example, the local cache 656a, 656b can include a double data rate synchronous dynamic random access memory (DDR-SDRAM). It should be understood that the local cache 656a, 656b can include other types of memory.

[0160] The local cache 656a, 656b is used to store data related to tasks being processed on a given computing unit 650a, 650b by the first processing module 652a, 652b and the second processing module 654a, 654b. It can also be accessed by other processing modules (not shown) that form part of the computing unit 650a, 650b associated with the local cache 656a, 656b. However, in some examples, it may be necessary to provide access data associated with a given task executed on the processing module of another computing unit (not shown) of the processor 630. In such an example, the processor 630 may also include a storage device 660, such as a cache (such as an L2 cache), for providing access to data used to process tasks executed on different computing units 650a, 650b. In some examples, the storage device 660 may be the above referenced Figure 3 and Figure 5 The registers 310, 510 or other storage media (not shown) are described.

[0161] By providing a local cache 656a, 656b, tasks that have been issued to the same compute unit 650a, 650b can access data stored in the local cache 656a, 656b, regardless of whether they form part of the same command in the command stream 620. The command processing unit 640 is responsible for allocating command tasks to a given compute unit 650a, 650b so that it can use available resources (such as the local cache 656a, 656b) most efficiently, thereby reducing the number of read / write transactions required to memory external to the compute unit 650a, 650b (such as the storage device 660 (L2 cache) or higher level memory). One such example is that a task of one command issued to a first processing module 652a of a given compute unit 650a can store its output in the local cache 656a so that it can be accessed by a second task of a different (or the same) command issued to a given processing module 652a, 654a of the same compute unit 650a.

[0162] One or more of the command processing unit 640, the computing units 650a, 650b, and the storage device 660 may be interconnected using a bus. This allows data to be transferred between the various components. The bus may be or include any suitable interface or bus. For example, Advanced Microcontroller Bus Architecture Interface, such as Advanced Extensible Interface (AXI).

[0163] Figure 7 is a schematic diagram of a neural engine 700, which in this example is used as a neural engine according to Figure 6The neural engine 700 includes a command and control module 710. The command and control module 710 receives the command from the command processing unit 640 ( Figure 6 The first storage device receives tasks and also acts as an interface to a storage device external to the neural engine 700 (such as local cache 656a, 656b and / or L2 cache 660), which is arranged to store data to be processed by the neural engine 700, such as data representing tensors or data representing strips of tensors. The first storage device may additionally store other data for configuring the neural engine 700 to perform a particular process and / or data to be used by the neural engine 700 to implement the process (such as neural network weights).

[0164] The command and control module 710 interfaces with a processing unit 720, which is, for example, a traversal synchronization unit (TSU). In this example, each task corresponds to a strip of tensors to be convolved with weights to implement a layer of a neural network. The tensors, for example, represent feature maps for processing using a neural network. A neural network typically includes a series of processing layers, with the output from each layer being used as the input to the next layer. Each layer processes an input feature map, for example by convolving the input feature map with a set of weights to generate an output feature map, which is used as the input feature map for the next layer. The term "feature map" is used generally herein to refer to either an input feature map or an output feature map. The processing performed by a given layer can be considered to correspond to a reference layer. Figures 1 to 5 Describes the operation.

[0165] In this example, processing unit 720 splits the data representing the strip of tensors into a plurality of data blocks, each data block representing a respective portion of the tensor. Processing unit 720 also obtains an operation set including a plurality of operations from a storage device external to neural engine 700, such as L2 cache 660. In this example, the operation is a chain of operations representing a sequence of layers of a neural network. Processing unit 720 assigns the data block as input to one of the operations.

[0166] The processing unit 720 coordinates the interaction of the internal components of the neural engine 700, which include a weight fetch unit 722, an input reader 724, an output writer 726, a direct memory access (DMA) unit 728, a dot product unit (DPU) array 730, a vector engine 732, a transform unit 734, an accumulator buffer 736, and a storage device 738 for processing of data blocks. The processing unit 720 tracks data dependencies across functional units. If all input blocks are available and space is available in the storage device 738 of the neural engine 700, the processing unit 720 in the functional unit initiates processing. The storage device 738 can be considered a shared buffer because the various functional units of the neural engine 700 share access to the storage device 738.

[0167] The weight fetching unit 722 fetches the weights associated with the neural network from the external storage device and stores the weights in the storage device 738. The input reader 724 reads data to be processed by the neural engine 700, such as a block of data representing a portion of a tensor, from the external storage device. The output writer 726 writes data obtained after processing by the neural engine 700 (such as a block of data representing a portion of an output feature map, which is obtained by processing the corresponding portion of the input feature map by the neural network represented by the weight fetched by the weight fetching unit 722) to the external storage device. The weight fetching unit 722, the input reader 724, and the output writer 726 interact with the external storage device (e.g., the local cache 656a, 656b, which may be an L1 cache, such as a load / store cache) via the DMA unit 728.

[0168] The weights and data blocks are processed by the DPU array 730, the vector engine 732, and the transform unit 734 to generate output data, which is written out to an external storage device by the output writer 726. The DPU array 730 is arranged to efficiently calculate the dot product between two operands, such as the dot product between the weight array and the corresponding data block (e.g., representing a portion of a tensor). The vector engine 732 is arranged to perform element-wise operations, such as applying a scaling parameter to scale the output of the dot product calculated by the DPU array 730. Data generated during the processing performed by the DPU array 730 and the vector engine 732 is temporarily stored in the accumulator buffer 736, from which the data can be retrieved by the DPU array 730 or the vector engine 732 for further processing as desired.

[0169] The transform unit 734 is arranged to perform intra-block transforms, such as dimension broadcasting or axis swapping. The transform unit 734 obtains data from the storage device 738 (e.g., after being processed by the DPU array 730 and / or the vector engine 732), and writes the transformed data back to the storage device 738.

[0170] In order to efficiently utilize the available storage device 738 within the neural engine 700, the processing unit 720 determines an available portion of the storage device 738 that is available during the execution of a portion of the first task (e.g., during the processing of a data block associated with the first task by the DPU array 730, the vector engine 732, and / or the transformation unit 734). The processing unit 720 determines a mapping between at least one logical address associated with data generated during the execution of the second task (e.g., by processing the data block associated with the second task by the DPU array 730, the vector engine 732, and / or the transformation unit 734) and at least one physical address of the storage device 738 corresponding to the available portion. The logical address is, for example, a global address in a global coordinate system. Therefore, by changing the physical address corresponding to a given logical address, the processing unit 720 can effectively control the use of the memory 738 without changing the software that defines the operation to be performed, because the same logical address can still be used to refer to a given element of the tensor to be processed. The processing unit 720 identifies at least one physical address corresponding to the at least one logical address based on the mapping, so that the data associated with the logical address is stored in the available portion. The processing unit 720 may perform a mapping process according to any of the examples herein, and may include a clipping operation and a floor division operation to convert tensor coordinates from logical to physical, as described above for Figures 1 to 5 Described.

[0171] Figure 8 A system 800 for distributing processing tasks and, in some examples, generating multiple input data blocks for processing is schematically illustrated.

[0172] System 800 includes a host processor 810, such as a central processing unit or any other type of general purpose processing unit. Host processor 810 issues a command stream including a plurality of commands, each command having a plurality of tasks associated therewith.

[0173] System 800 also includes a processor 830 that can communicate with Figure 6 The processor 630 is similar or identical to the processor 630 of FIG. Figures 1 to 5 At least some of the components described and / or configured to perform the above Figures 1 to 5 The method described. The processor 830 includes at least a plurality of computing units 650a, 650b and a command processing unit 640. Each computing unit may include a plurality of processing modules, each processing module being configured to perform at least one type of operation. The system 800 may also include at least one additional processor (not shown), which may be the same as the processor 830. The processor 830 and the host processor 810 may be combined into a system on chip (SoC) or combined onto a plurality of SoCs to form one or more application processors.

[0174] The system 800 also includes a memory 820 for storing data generated by tasks external to the processor 830 so that other tasks running on other processors can easily access the data. However, it should be understood that due to the distribution of tasks as described above, external memory usage will be less used, so that tasks that need to use data generated by other tasks or need the same data as other tasks will be allocated to the same computing unit 650a, 650b of the processor 830 in order to maximize the use of the local cache 656a, 656b.

[0175] In some examples, the system 800 may include a memory controller (not shown), which may be a dynamic memory controller (DMC). The memory controller is coupled to the memory 820. The memory controller is configured to manage the flow of data into and out of the memory. The memory may include a main memory, or referred to as a "primary memory". The memory may be an external memory because the memory is outside the system 800. For example, the memory 820 may include an "off-chip" memory. The memory may have a larger storage capacity than the local cache of the processor 830 and / or the host processor 810. In some examples, the memory 820 is included in the system 800. For example, the memory 820 may include an "on-chip" memory. The memory 820 may, for example, include a magnetic disk or optical disk and a magnetic disk drive or a solid-state drive (SSD). In some examples, the memory 820 includes a synchronous dynamic random access memory (SDRAM). For example, the memory 820 may include a double data rate synchronous dynamic random access memory (DDR-SDRAM).

[0176] One or more of the host processor 810, processor 830, and memory 820 may be interconnected using a system bus 840. This allows data to be transferred between the various components. The system bus 840 may be or include any suitable interface or bus. For example, a system bus 840 may be used. Advanced Microcontroller Bus Architecture Interface, such as Advanced Extensible Interface (AXI).

[0177] Fig. 9A simulator implementation 900 that can be used is shown. Although the previously described embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware that supports the technology involved, an instruction execution environment according to the embodiments described herein can also be provided, which is implemented by using a computer program. Such computer programs are generally referred to as simulators, to a certain extent because such computer programs provide software-based implementations of hardware architectures. The types of simulator computer programs include emulators, virtual machines, models, and binary converters, which include dynamic binary converters. Typically, the simulator implementation can be run on a host processor 940 that supports the simulator program 920, optionally running a host operating system 930. In some arrangements, multiple simulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide a simulator implementation that was executed at a reasonable speed, but this approach may be reasonable in certain circumstances, such as when it is desired to run another processor local code for compatibility or reuse reasons. For example, the simulator implementation can provide additional functionality that is not supported by the host processor hardware to the instruction execution environment, or provide an instruction execution environment that is generally associated with different hardware architectures. An overview of simulation is given in: "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0178] To the extent that embodiments have been previously described with reference to specific hardware constructs or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructs or features. For example, specific circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. Where one or more of the hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 940), some simulated embodiments may utilize host hardware where appropriate.

[0179] The simulator program 920 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 910, which is the same as the application program interface of the hardware architecture being modeled by the simulator program 920. Therefore, the program instructions of the target code 910 (including the control of memory access based on the above-mentioned range protection function) can be executed from within the instruction execution environment using the simulator program 920, so that there is actually no need to execute the instructions in the target code 910. Figure 3 and Figure 5 The host computer 940 that displays the hardware features of the devices shown in and discussed above can emulate these features.

[0180] References in this article Figures 1 to 9 At least some aspects of the described examples include computer processing performed in a processing system or processor. However, in some examples, the present disclosure also extends to computer programs suitable for putting the present disclosure into practice, in particular computer programs on or in a device. The program may be in the form of non-transient source code, object code, code intermediate source and object code, such as partially compiled form or any other non-transient form suitable for use in the implementation of processing according to the present disclosure. The device may be any entity or device capable of carrying the program. For example, the device may include a storage medium, such as a solid-state drive (SSD) or other semiconductor-based RAM; ROM, for example, a CD ROM or a semiconductor ROM; a magnetic recording medium, for example, a floppy disk or a hard disk; typically, an optical storage device; and the like.

[0181] In the previous description, for the purpose of explanation, many specific details of certain examples are set forth. Reference to "example" or similar language in this specification means that a particular feature, structure or characteristic described in conjunction with the example is included in at least one example, but not necessarily in other examples.

[0182] The above examples are to be understood as illustrative examples of the present disclosure. Additional examples of the present disclosure are contemplated. It should be understood that any feature described for any one example may be used alone or in combination with other features described, and may also be used in combination with one or more features of any other example or in any combination of any other example. In addition, equivalents and modifications not described above may also be employed without departing from the scope of the present disclosure as defined in the appended claims.

Claims

1. A method for executing a partial clipping instruction using a portion of a clipping value, the method comprising: Decoding the partial trimming instruction using an instruction decoding circuit; obtaining at least a portion of input data, the portion of the input data being associated with a register having a register size; as well as In response to the decoded instruction: clipping the portion of the input data based on the portion of the clipping value; as well as When the upper limit value of the portion of the input data equals or exceeds the portion of the clipping value, a flag indicating further clipping needs to be set.

2. The method of executing a partial clipping instruction with a portion of a clipping value according to claim 1, further comprising decoding an input portion number associated with the portion of input data to determine the selected input portion and the selected clipping portion associated with the clipping value.

3. The method of executing a partial clip instruction with a portion of a clip value according to claim 1, further comprising reading a flag value and determining whether to clip the portion of the input data based on the flag value.

4. The method of executing a partial clip instruction with a portion of a clip value of claim 1, wherein clipping the portion of the input data comprises determining whether the portion of the input data is greater than the portion of the clip value.

5. The method of executing a partial trim instruction with a portion of a trim value according to claim 1, wherein the portion of the trim value is an 8-bit shifted constant.

6. The method of executing a partial clipping instruction with a portion of a clipping value according to claim 1, wherein the register comprises at least a lower boundary component and an upper boundary component, and the flag is stored in the lower boundary component, preferably, wherein the flag is stored in a sign bit associated with the lower boundary of the register.

7. A method of performing a trim operation, the method comprising executing a plurality of partial trim instructions according to claim 1, wherein executing a subsequent partial trim instruction is based on the setting of a flag, preferably wherein executing at least one of the subsequent partial trim instructions of the plurality of partial trim instructions comprises reading the flag.

8. A method of compiling a trimming operation, the method comprising compiling an instruction sequence comprising a plurality of partial trimming instructions according to claim 1, wherein the length of the sequence is determined based on a range of potential input values, preferably wherein a first partial trimming instruction of the plurality of partial trimming instructions does not require data associated with a flag, and wherein at least a second partial trimming instruction of the plurality of partial trimming instructions comprises reading the flag.

9. An apparatus for executing a partial clipping instruction using a portion of a clipping value, the apparatus comprising: An instruction decoding circuit, the instruction decoding circuit is used to decode the partial cropping instruction; input circuitry for obtaining at least a portion of input data, the portion of the input data being associated with a register having a register size; and a processing circuit, the processing circuit being configured to perform data processing on the portion of the input data in response to the portion of the trimming instruction decoded by the instruction decoding circuit, wherein the processing circuit is configured to operate on the portion of the input data, and the programming circuit is configured to: clipping the portion of the input data based on the portion of the clipping value; as well as When the upper limit value of the portion of the input data equals or exceeds the portion of the clipping value, a flag indicating further clipping needs to be set.

10. A non-transitory computer readable storage medium comprising a set of computer readable instructions stored thereon, the instructions, when executed by at least one processor, causing the at least one processor to control host data processing operations to provide an instruction execution environment for executing instructions of a target code, the computer program comprising: Decoding the trimming instruction using an instruction decoding circuit; obtaining at least a portion of input data, the portion of the input data being associated with a register having a register size; as well as In response to the decoded instruction: clipping the portion of the input data based on the portion of the clipping value; as well as When the upper limit value of the portion of the input data equals or exceeds the portion of the clipping value, a flag indicating further clipping needs to be set.

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